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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 2004 Embedded Edge, LLC
3 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/module.h>
Sergei Shtylyov35af68b2006-05-16 20:52:06 +040012#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/mtd/mtd.h>
Boris Brezillond4092d72017-08-04 17:29:10 +020014#include <linux/mtd/rawnand.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/mtd/partitions.h>
Manuel Laussb67a1a02011-12-08 10:42:10 +000016#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <asm/io.h>
Manuel Laussb67a1a02011-12-08 10:42:10 +000018#include <asm/mach-au1x00/au1000.h>
19#include <asm/mach-au1x00/au1550nd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
Manuel Laussb67a1a02011-12-08 10:42:10 +000022struct au1550nd_ctx {
Manuel Laussb67a1a02011-12-08 10:42:10 +000023 struct nand_chip chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Manuel Laussb67a1a02011-12-08 10:42:10 +000025 int cs;
26 void __iomem *base;
Boris Brezillonc0739d82018-09-06 14:05:23 +020027 void (*write_byte)(struct nand_chip *, u_char);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028};
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30/**
31 * au_read_byte - read one byte from the chip
Boris Brezillon7e534322018-09-06 14:05:22 +020032 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 *
Brian Norris7854d3f2011-06-23 14:12:08 -070034 * read function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
Boris Brezillon7e534322018-09-06 14:05:22 +020036static u_char au_read_byte(struct nand_chip *this)
Linus Torvalds1da177e2005-04-16 15:20:36 -070037{
Boris Brezillon82fc5092018-09-07 00:38:34 +020038 u_char ret = readb(this->legacy.IO_ADDR_R);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +020039 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -070040 return ret;
41}
42
43/**
44 * au_write_byte - write one byte to the chip
Boris Brezillonc0739d82018-09-06 14:05:23 +020045 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 * @byte: pointer to data byte to write
47 *
Brian Norris7854d3f2011-06-23 14:12:08 -070048 * write function for 8it buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 */
Boris Brezillonc0739d82018-09-06 14:05:23 +020050static void au_write_byte(struct nand_chip *this, u_char byte)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051{
Boris Brezillon82fc5092018-09-07 00:38:34 +020052 writeb(byte, this->legacy.IO_ADDR_W);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +020053 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -070054}
55
56/**
Brian Norris7854d3f2011-06-23 14:12:08 -070057 * au_read_byte16 - read one byte endianness aware from the chip
Boris Brezillon7e534322018-09-06 14:05:22 +020058 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 *
Brian Norris7854d3f2011-06-23 14:12:08 -070060 * read function for 16bit buswidth with endianness conversion
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 */
Boris Brezillon7e534322018-09-06 14:05:22 +020062static u_char au_read_byte16(struct nand_chip *this)
Linus Torvalds1da177e2005-04-16 15:20:36 -070063{
Boris Brezillon82fc5092018-09-07 00:38:34 +020064 u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R));
Manuel Lauss2f73bfb2014-07-23 16:36:26 +020065 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 return ret;
67}
68
69/**
Brian Norris7854d3f2011-06-23 14:12:08 -070070 * au_write_byte16 - write one byte endianness aware to the chip
Boris Brezillonc0739d82018-09-06 14:05:23 +020071 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 * @byte: pointer to data byte to write
73 *
Brian Norris7854d3f2011-06-23 14:12:08 -070074 * write function for 16bit buswidth with endianness conversion
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 */
Boris Brezillonc0739d82018-09-06 14:05:23 +020076static void au_write_byte16(struct nand_chip *this, u_char byte)
Linus Torvalds1da177e2005-04-16 15:20:36 -070077{
Boris Brezillon82fc5092018-09-07 00:38:34 +020078 writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +020079 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -070080}
81
82/**
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 * au_write_buf - write buffer to chip
Boris Brezillonc0739d82018-09-06 14:05:23 +020084 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 * @buf: data buffer
86 * @len: number of bytes to write
87 *
Brian Norris7854d3f2011-06-23 14:12:08 -070088 * write function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 */
Boris Brezillonc0739d82018-09-06 14:05:23 +020090static void au_write_buf(struct nand_chip *this, const u_char *buf, int len)
Linus Torvalds1da177e2005-04-16 15:20:36 -070091{
92 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
David Woodhousee0c7d762006-05-13 18:07:53 +010094 for (i = 0; i < len; i++) {
Boris Brezillon82fc5092018-09-07 00:38:34 +020095 writeb(buf[i], this->legacy.IO_ADDR_W);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +020096 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 }
98}
99
100/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000101 * au_read_buf - read chip data into buffer
Boris Brezillon7e534322018-09-06 14:05:22 +0200102 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 * @buf: buffer to store date
104 * @len: number of bytes to read
105 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700106 * read function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 */
Boris Brezillon7e534322018-09-06 14:05:22 +0200108static void au_read_buf(struct nand_chip *this, u_char *buf, int len)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109{
110 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
David Woodhousee0c7d762006-05-13 18:07:53 +0100112 for (i = 0; i < len; i++) {
Boris Brezillon82fc5092018-09-07 00:38:34 +0200113 buf[i] = readb(this->legacy.IO_ADDR_R);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +0200114 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 }
116}
117
118/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 * au_write_buf16 - write buffer to chip
Boris Brezillonc0739d82018-09-06 14:05:23 +0200120 * @this: NAND chip object
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 * @buf: data buffer
122 * @len: number of bytes to write
123 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700124 * write function for 16bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 */
Boris Brezillonc0739d82018-09-06 14:05:23 +0200126static void au_write_buf16(struct nand_chip *this, const u_char *buf, int len)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127{
128 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 u16 *p = (u16 *) buf;
130 len >>= 1;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000131
David Woodhousee0c7d762006-05-13 18:07:53 +0100132 for (i = 0; i < len; i++) {
Boris Brezillon82fc5092018-09-07 00:38:34 +0200133 writew(p[i], this->legacy.IO_ADDR_W);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +0200134 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137}
138
139/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000140 * au_read_buf16 - read chip data into buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 * @mtd: MTD device structure
142 * @buf: buffer to store date
143 * @len: number of bytes to read
144 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700145 * read function for 16bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146 */
147static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
148{
149 int i;
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100150 struct nand_chip *this = mtd_to_nand(mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 u16 *p = (u16 *) buf;
152 len >>= 1;
153
David Woodhousee0c7d762006-05-13 18:07:53 +0100154 for (i = 0; i < len; i++) {
Boris Brezillon82fc5092018-09-07 00:38:34 +0200155 p[i] = readw(this->legacy.IO_ADDR_R);
Manuel Lauss2f73bfb2014-07-23 16:36:26 +0200156 wmb(); /* drain writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 }
158}
159
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200160/* Select the chip by setting nCE to low */
161#define NAND_CTL_SETNCE 1
162/* Deselect the chip by setting nCE to high */
163#define NAND_CTL_CLRNCE 2
164/* Select the command latch by setting CLE to high */
165#define NAND_CTL_SETCLE 3
166/* Deselect the command latch by setting CLE to low */
167#define NAND_CTL_CLRCLE 4
168/* Select the address latch by setting ALE to high */
169#define NAND_CTL_SETALE 5
170/* Deselect the address latch by setting ALE to low */
171#define NAND_CTL_CLRALE 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
174{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100175 struct nand_chip *this = mtd_to_nand(mtd);
Boris BREZILLONff70f352015-12-10 08:59:51 +0100176 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
177 chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
David Woodhousee0c7d762006-05-13 18:07:53 +0100179 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180
David Woodhousee0c7d762006-05-13 18:07:53 +0100181 case NAND_CTL_SETCLE:
Boris Brezillon82fc5092018-09-07 00:38:34 +0200182 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
David Woodhousee0c7d762006-05-13 18:07:53 +0100183 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184
David Woodhousee0c7d762006-05-13 18:07:53 +0100185 case NAND_CTL_CLRCLE:
Boris Brezillon82fc5092018-09-07 00:38:34 +0200186 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
David Woodhousee0c7d762006-05-13 18:07:53 +0100187 break;
188
189 case NAND_CTL_SETALE:
Boris Brezillon82fc5092018-09-07 00:38:34 +0200190 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
David Woodhousee0c7d762006-05-13 18:07:53 +0100191 break;
192
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000193 case NAND_CTL_CLRALE:
Boris Brezillon82fc5092018-09-07 00:38:34 +0200194 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
David Woodhousee0c7d762006-05-13 18:07:53 +0100195 /* FIXME: Nobody knows why this is necessary,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 * but it works only that way */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000197 udelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 break;
199
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000200 case NAND_CTL_SETNCE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 /* assert (force assert) chip enable */
Manuel Lauss9cf12162014-07-23 16:36:25 +0200202 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 break;
204
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000205 case NAND_CTL_CLRNCE:
David Woodhousee0c7d762006-05-13 18:07:53 +0100206 /* deassert chip enable */
Manuel Lauss9cf12162014-07-23 16:36:25 +0200207 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 break;
209 }
210
Boris Brezillon82fc5092018-09-07 00:38:34 +0200211 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000212
Manuel Lauss2f73bfb2014-07-23 16:36:26 +0200213 wmb(); /* Drain the writebuffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214}
215
Boris Brezillon50a487e2018-09-06 14:05:27 +0200216int au1550_device_ready(struct nand_chip *this)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217{
Manuel Lauss9cf12162014-07-23 16:36:25 +0200218 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219}
220
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400221/**
222 * au1550_select_chip - control -CE line
223 * Forbid driving -CE manually permitting the NAND controller to do this.
224 * Keeping -CE asserted during the whole sector reads interferes with the
225 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
226 * We only have to hold -CE low for the NAND read commands since the flash
227 * chip needs it to be asserted during chip not ready time but the NAND
228 * controller keeps it released.
229 *
Boris Brezillon758b56f2018-09-06 14:05:24 +0200230 * @this: NAND chip object
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400231 * @chip: chipnumber to select, -1 for deselect
232 */
Boris Brezillon758b56f2018-09-06 14:05:24 +0200233static void au1550_select_chip(struct nand_chip *this, int chip)
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400234{
235}
236
237/**
238 * au1550_command - Send command to NAND device
Boris Brezillon5295cf22018-09-06 14:05:28 +0200239 * @this: NAND chip object
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400240 * @command: the command to be sent
241 * @column: the column address for this command, -1 if none
242 * @page_addr: the page address for this command, -1 if none
243 */
Boris Brezillon5295cf22018-09-06 14:05:28 +0200244static void au1550_command(struct nand_chip *this, unsigned command,
245 int column, int page_addr)
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400246{
Boris Brezillon5295cf22018-09-06 14:05:28 +0200247 struct mtd_info *mtd = nand_to_mtd(this);
Boris BREZILLONff70f352015-12-10 08:59:51 +0100248 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
249 chip);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400250 int ce_override = 0, i;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000251 unsigned long flags = 0;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400252
253 /* Begin command latch cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200254 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400255 /*
256 * Write out the command to the device.
257 */
258 if (command == NAND_CMD_SEQIN) {
259 int readcmd;
260
Joern Engel28318772006-05-22 23:18:05 +0200261 if (column >= mtd->writesize) {
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400262 /* OOB area */
Joern Engel28318772006-05-22 23:18:05 +0200263 column -= mtd->writesize;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400264 readcmd = NAND_CMD_READOOB;
265 } else if (column < 256) {
266 /* First 256 bytes --> READ0 */
267 readcmd = NAND_CMD_READ0;
268 } else {
269 column -= 256;
270 readcmd = NAND_CMD_READ1;
271 }
Boris Brezillonc0739d82018-09-06 14:05:23 +0200272 ctx->write_byte(this, readcmd);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400273 }
Boris Brezillonc0739d82018-09-06 14:05:23 +0200274 ctx->write_byte(this, command);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400275
276 /* Set ALE and clear CLE to start address cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200277 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400278
279 if (column != -1 || page_addr != -1) {
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200280 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400281
282 /* Serially input address */
283 if (column != -1) {
284 /* Adjust columns for 16 bit buswidth */
Brian Norris3dad2342014-01-29 14:08:12 -0800285 if (this->options & NAND_BUSWIDTH_16 &&
286 !nand_opcode_8bits(command))
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400287 column >>= 1;
Boris Brezillonc0739d82018-09-06 14:05:23 +0200288 ctx->write_byte(this, column);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400289 }
290 if (page_addr != -1) {
Boris Brezillonc0739d82018-09-06 14:05:23 +0200291 ctx->write_byte(this, (u8)(page_addr & 0xff));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400292
293 if (command == NAND_CMD_READ0 ||
294 command == NAND_CMD_READ1 ||
295 command == NAND_CMD_READOOB) {
296 /*
297 * NAND controller will release -CE after
298 * the last address byte is written, so we'll
299 * have to forcibly assert it. No interrupts
300 * are allowed while we do this as we don't
301 * want the NOR flash or PCMCIA drivers to
302 * steal our precious bytes of data...
303 */
304 ce_override = 1;
305 local_irq_save(flags);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200306 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400307 }
308
Boris Brezillonc0739d82018-09-06 14:05:23 +0200309 ctx->write_byte(this, (u8)(page_addr >> 8));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400310
Masahiro Yamada14157f82017-09-13 11:05:50 +0900311 if (this->options & NAND_ROW_ADDR_3)
Boris Brezillonc0739d82018-09-06 14:05:23 +0200312 ctx->write_byte(this,
Manuel Laussb67a1a02011-12-08 10:42:10 +0000313 ((page_addr >> 16) & 0x0f));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400314 }
315 /* Latch in address */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200316 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400317 }
318
319 /*
320 * Program and erase have their own busy handlers.
321 * Status and sequential in need no delay.
322 */
323 switch (command) {
324
325 case NAND_CMD_PAGEPROG:
326 case NAND_CMD_ERASE1:
327 case NAND_CMD_ERASE2:
328 case NAND_CMD_SEQIN:
329 case NAND_CMD_STATUS:
330 return;
331
332 case NAND_CMD_RESET:
333 break;
334
335 case NAND_CMD_READ0:
336 case NAND_CMD_READ1:
337 case NAND_CMD_READOOB:
338 /* Check if we're really driving -CE low (just in case) */
339 if (unlikely(!ce_override))
340 break;
341
342 /* Apply a short delay always to ensure that we do wait tWB. */
343 ndelay(100);
344 /* Wait for a chip to become ready... */
Boris Brezillon3cece3a2018-09-07 00:38:41 +0200345 for (i = this->legacy.chip_delay;
Boris Brezillon8395b752018-09-07 00:38:37 +0200346 !this->legacy.dev_ready(this) && i > 0; --i)
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400347 udelay(1);
348
349 /* Release -CE and re-enable interrupts. */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200350 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400351 local_irq_restore(flags);
352 return;
353 }
354 /* Apply this short delay always to ensure that we do wait tWB. */
355 ndelay(100);
356
Boris Brezillon8395b752018-09-07 00:38:37 +0200357 while(!this->legacy.dev_ready(this));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400358}
359
Bill Pemberton06f25512012-11-19 13:23:07 -0500360static int find_nand_cs(unsigned long nand_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000362 void __iomem *base =
363 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
364 unsigned long addr, staddr, start, mask, end;
365 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366
Manuel Laussb67a1a02011-12-08 10:42:10 +0000367 for (i = 0; i < 4; i++) {
368 addr = 0x1000 + (i * 0x10); /* CSx */
369 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
370 /* figure out the decoded range of this CS */
371 start = (staddr << 4) & 0xfffc0000;
372 mask = (staddr << 18) & 0xfffc0000;
373 end = (start | (start - 1)) & ~(start ^ mask);
374 if ((nand_base >= start) && (nand_base < end))
375 return i;
376 }
377
378 return -ENODEV;
379}
380
Bill Pemberton06f25512012-11-19 13:23:07 -0500381static int au1550nd_probe(struct platform_device *pdev)
Manuel Laussb67a1a02011-12-08 10:42:10 +0000382{
383 struct au1550nd_platdata *pd;
384 struct au1550nd_ctx *ctx;
385 struct nand_chip *this;
Boris BREZILLONff70f352015-12-10 08:59:51 +0100386 struct mtd_info *mtd;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000387 struct resource *r;
388 int ret, cs;
389
Jingoo Han453810b2013-07-30 17:18:33 +0900390 pd = dev_get_platdata(&pdev->dev);
Manuel Laussb67a1a02011-12-08 10:42:10 +0000391 if (!pd) {
392 dev_err(&pdev->dev, "missing platform data\n");
393 return -ENODEV;
394 }
395
396 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
Jingoo Hance3737f2013-12-26 12:02:30 +0900397 if (!ctx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
Manuel Laussb67a1a02011-12-08 10:42:10 +0000400 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
401 if (!r) {
402 dev_err(&pdev->dev, "no NAND memory resource\n");
403 ret = -ENODEV;
404 goto out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000406 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
407 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
408 ret = -ENOMEM;
409 goto out1;
Pete Popovef6f0d12005-09-23 02:44:58 +0100410 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000411
412 ctx->base = ioremap_nocache(r->start, 0x1000);
413 if (!ctx->base) {
414 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
415 ret = -ENODEV;
416 goto out2;
Pete Popovef6f0d12005-09-23 02:44:58 +0100417 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000418
419 this = &ctx->chip;
Boris BREZILLONff70f352015-12-10 08:59:51 +0100420 mtd = nand_to_mtd(this);
Boris BREZILLONff70f352015-12-10 08:59:51 +0100421 mtd->dev.parent = &pdev->dev;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000422
423 /* figure out which CS# r->start belongs to */
424 cs = find_nand_cs(r->start);
425 if (cs < 0) {
426 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
427 ret = -ENODEV;
428 goto out3;
Pete Popovef6f0d12005-09-23 02:44:58 +0100429 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000430 ctx->cs = cs;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000431
Boris Brezillon8395b752018-09-07 00:38:37 +0200432 this->legacy.dev_ready = au1550_device_ready;
Boris Brezillon7d6c37e2018-11-11 08:55:22 +0100433 this->legacy.select_chip = au1550_select_chip;
Boris Brezillonbf6065c2018-09-07 00:38:36 +0200434 this->legacy.cmdfunc = au1550_command;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400435
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 /* 30 us command delay time */
Boris Brezillon3cece3a2018-09-07 00:38:41 +0200437 this->legacy.chip_delay = 30;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200438 this->ecc.mode = NAND_ECC_SOFT;
Rafał Miłeckic2ec6b32016-04-13 14:06:57 +0200439 this->ecc.algo = NAND_ECC_HAMMING;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440
Manuel Laussb67a1a02011-12-08 10:42:10 +0000441 if (pd->devwidth)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 this->options |= NAND_BUSWIDTH_16;
443
Boris Brezillon716bbba2018-09-07 00:38:35 +0200444 this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000445 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
Boris Brezillon716bbba2018-09-07 00:38:35 +0200446 this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
447 this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Boris Brezillon00ad3782018-09-06 14:05:14 +0200449 ret = nand_scan(this, 1);
Manuel Laussb67a1a02011-12-08 10:42:10 +0000450 if (ret) {
451 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
452 goto out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 }
454
Boris BREZILLONff70f352015-12-10 08:59:51 +0100455 mtd_device_register(mtd, pd->parts, pd->num_parts);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
Wei Yongjuna1d79942013-11-11 14:18:29 +0800457 platform_set_drvdata(pdev, ctx);
458
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 return 0;
460
Manuel Laussb67a1a02011-12-08 10:42:10 +0000461out3:
462 iounmap(ctx->base);
463out2:
464 release_mem_region(r->start, resource_size(r));
465out1:
466 kfree(ctx);
467 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468}
469
Bill Pemberton810b7e02012-11-19 13:26:04 -0500470static int au1550nd_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000472 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
473 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
Boris Brezillon59ac2762018-09-06 14:05:15 +0200475 nand_release(&ctx->chip);
Manuel Laussb67a1a02011-12-08 10:42:10 +0000476 iounmap(ctx->base);
477 release_mem_region(r->start, 0x1000);
478 kfree(ctx);
479 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480}
David Woodhousee0c7d762006-05-13 18:07:53 +0100481
Manuel Laussb67a1a02011-12-08 10:42:10 +0000482static struct platform_driver au1550nd_driver = {
483 .driver = {
484 .name = "au1550-nand",
Manuel Laussb67a1a02011-12-08 10:42:10 +0000485 },
486 .probe = au1550nd_probe,
Bill Pemberton5153b882012-11-19 13:21:24 -0500487 .remove = au1550nd_remove,
Manuel Laussb67a1a02011-12-08 10:42:10 +0000488};
489
490module_platform_driver(au1550nd_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
492MODULE_LICENSE("GPL");
493MODULE_AUTHOR("Embedded Edge, LLC");
494MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");