Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Copyright (C) 2004 Embedded Edge, LLC |
| 3 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 12 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/mtd/mtd.h> |
Boris Brezillon | d4092d7 | 2017-08-04 17:29:10 +0200 | [diff] [blame] | 14 | #include <linux/mtd/rawnand.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/mtd/partitions.h> |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 16 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <asm/io.h> |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 18 | #include <asm/mach-au1x00/au1000.h> |
| 19 | #include <asm/mach-au1x00/au1550nd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 22 | struct au1550nd_ctx { |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 23 | struct nand_chip chip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 25 | int cs; |
| 26 | void __iomem *base; |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 27 | void (*write_byte)(struct nand_chip *, u_char); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | /** |
| 31 | * au_read_byte - read one byte from the chip |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 32 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 34 | * read function for 8bit buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | */ |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 36 | static u_char au_read_byte(struct nand_chip *this) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 38 | u_char ret = readb(this->legacy.IO_ADDR_R); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 39 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | return ret; |
| 41 | } |
| 42 | |
| 43 | /** |
| 44 | * au_write_byte - write one byte to the chip |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 45 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | * @byte: pointer to data byte to write |
| 47 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 48 | * write function for 8it buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | */ |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 50 | static void au_write_byte(struct nand_chip *this, u_char byte) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 52 | writeb(byte, this->legacy.IO_ADDR_W); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 53 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | /** |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 57 | * au_read_byte16 - read one byte endianness aware from the chip |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 58 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 60 | * read function for 16bit buswidth with endianness conversion |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | */ |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 62 | static u_char au_read_byte16(struct nand_chip *this) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 64 | u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R)); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 65 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | return ret; |
| 67 | } |
| 68 | |
| 69 | /** |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 70 | * au_write_byte16 - write one byte endianness aware to the chip |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 71 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | * @byte: pointer to data byte to write |
| 73 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 74 | * write function for 16bit buswidth with endianness conversion |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | */ |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 76 | static void au_write_byte16(struct nand_chip *this, u_char byte) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 78 | writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 79 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | * au_write_buf - write buffer to chip |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 84 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | * @buf: data buffer |
| 86 | * @len: number of bytes to write |
| 87 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 88 | * write function for 8bit buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | */ |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 90 | static void au_write_buf(struct nand_chip *this, const u_char *buf, int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | { |
| 92 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 94 | for (i = 0; i < len; i++) { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 95 | writeb(buf[i], this->legacy.IO_ADDR_W); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 96 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | } |
| 98 | } |
| 99 | |
| 100 | /** |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 101 | * au_read_buf - read chip data into buffer |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 102 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | * @buf: buffer to store date |
| 104 | * @len: number of bytes to read |
| 105 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 106 | * read function for 8bit buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | */ |
Boris Brezillon | 7e53432 | 2018-09-06 14:05:22 +0200 | [diff] [blame] | 108 | static void au_read_buf(struct nand_chip *this, u_char *buf, int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | { |
| 110 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 112 | for (i = 0; i < len; i++) { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 113 | buf[i] = readb(this->legacy.IO_ADDR_R); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 114 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | } |
| 116 | } |
| 117 | |
| 118 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | * au_write_buf16 - write buffer to chip |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 120 | * @this: NAND chip object |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | * @buf: data buffer |
| 122 | * @len: number of bytes to write |
| 123 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 124 | * write function for 16bit buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | */ |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 126 | static void au_write_buf16(struct nand_chip *this, const u_char *buf, int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | { |
| 128 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | u16 *p = (u16 *) buf; |
| 130 | len >>= 1; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 131 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 132 | for (i = 0; i < len; i++) { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 133 | writew(p[i], this->legacy.IO_ADDR_W); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 134 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 136 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /** |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 140 | * au_read_buf16 - read chip data into buffer |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | * @mtd: MTD device structure |
| 142 | * @buf: buffer to store date |
| 143 | * @len: number of bytes to read |
| 144 | * |
Brian Norris | 7854d3f | 2011-06-23 14:12:08 -0700 | [diff] [blame] | 145 | * read function for 16bit buswidth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | */ |
| 147 | static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) |
| 148 | { |
| 149 | int i; |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 150 | struct nand_chip *this = mtd_to_nand(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | u16 *p = (u16 *) buf; |
| 152 | len >>= 1; |
| 153 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 154 | for (i = 0; i < len; i++) { |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 155 | p[i] = readw(this->legacy.IO_ADDR_R); |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 156 | wmb(); /* drain writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | } |
| 158 | } |
| 159 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 160 | /* Select the chip by setting nCE to low */ |
| 161 | #define NAND_CTL_SETNCE 1 |
| 162 | /* Deselect the chip by setting nCE to high */ |
| 163 | #define NAND_CTL_CLRNCE 2 |
| 164 | /* Select the command latch by setting CLE to high */ |
| 165 | #define NAND_CTL_SETCLE 3 |
| 166 | /* Deselect the command latch by setting CLE to low */ |
| 167 | #define NAND_CTL_CLRCLE 4 |
| 168 | /* Select the address latch by setting ALE to high */ |
| 169 | #define NAND_CTL_SETALE 5 |
| 170 | /* Deselect the address latch by setting ALE to low */ |
| 171 | #define NAND_CTL_CLRALE 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | |
| 173 | static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) |
| 174 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 175 | struct nand_chip *this = mtd_to_nand(mtd); |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 176 | struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, |
| 177 | chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 179 | switch (cmd) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 181 | case NAND_CTL_SETCLE: |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 182 | this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD; |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 183 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 185 | case NAND_CTL_CLRCLE: |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 186 | this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 187 | break; |
| 188 | |
| 189 | case NAND_CTL_SETALE: |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 190 | this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 191 | break; |
| 192 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 193 | case NAND_CTL_CLRALE: |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 194 | this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 195 | /* FIXME: Nobody knows why this is necessary, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | * but it works only that way */ |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 197 | udelay(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | break; |
| 199 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 200 | case NAND_CTL_SETNCE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | /* assert (force assert) chip enable */ |
Manuel Lauss | 9cf1216 | 2014-07-23 16:36:25 +0200 | [diff] [blame] | 202 | alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | break; |
| 204 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 205 | case NAND_CTL_CLRNCE: |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 206 | /* deassert chip enable */ |
Manuel Lauss | 9cf1216 | 2014-07-23 16:36:25 +0200 | [diff] [blame] | 207 | alchemy_wrsmem(0, AU1000_MEM_STNDCTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | break; |
| 209 | } |
| 210 | |
Boris Brezillon | 82fc509 | 2018-09-07 00:38:34 +0200 | [diff] [blame] | 211 | this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 212 | |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 213 | wmb(); /* Drain the writebuffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | } |
| 215 | |
Boris Brezillon | 50a487e | 2018-09-06 14:05:27 +0200 | [diff] [blame] | 216 | int au1550_device_ready(struct nand_chip *this) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | { |
Manuel Lauss | 9cf1216 | 2014-07-23 16:36:25 +0200 | [diff] [blame] | 218 | return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | } |
| 220 | |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 221 | /** |
| 222 | * au1550_select_chip - control -CE line |
| 223 | * Forbid driving -CE manually permitting the NAND controller to do this. |
| 224 | * Keeping -CE asserted during the whole sector reads interferes with the |
| 225 | * NOR flash and PCMCIA drivers as it causes contention on the static bus. |
| 226 | * We only have to hold -CE low for the NAND read commands since the flash |
| 227 | * chip needs it to be asserted during chip not ready time but the NAND |
| 228 | * controller keeps it released. |
| 229 | * |
Boris Brezillon | 758b56f | 2018-09-06 14:05:24 +0200 | [diff] [blame] | 230 | * @this: NAND chip object |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 231 | * @chip: chipnumber to select, -1 for deselect |
| 232 | */ |
Boris Brezillon | 758b56f | 2018-09-06 14:05:24 +0200 | [diff] [blame] | 233 | static void au1550_select_chip(struct nand_chip *this, int chip) |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 234 | { |
| 235 | } |
| 236 | |
| 237 | /** |
| 238 | * au1550_command - Send command to NAND device |
Boris Brezillon | 5295cf2 | 2018-09-06 14:05:28 +0200 | [diff] [blame] | 239 | * @this: NAND chip object |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 240 | * @command: the command to be sent |
| 241 | * @column: the column address for this command, -1 if none |
| 242 | * @page_addr: the page address for this command, -1 if none |
| 243 | */ |
Boris Brezillon | 5295cf2 | 2018-09-06 14:05:28 +0200 | [diff] [blame] | 244 | static void au1550_command(struct nand_chip *this, unsigned command, |
| 245 | int column, int page_addr) |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 246 | { |
Boris Brezillon | 5295cf2 | 2018-09-06 14:05:28 +0200 | [diff] [blame] | 247 | struct mtd_info *mtd = nand_to_mtd(this); |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 248 | struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, |
| 249 | chip); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 250 | int ce_override = 0, i; |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 251 | unsigned long flags = 0; |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 252 | |
| 253 | /* Begin command latch cycle */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 254 | au1550_hwcontrol(mtd, NAND_CTL_SETCLE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 255 | /* |
| 256 | * Write out the command to the device. |
| 257 | */ |
| 258 | if (command == NAND_CMD_SEQIN) { |
| 259 | int readcmd; |
| 260 | |
Joern Engel | 2831877 | 2006-05-22 23:18:05 +0200 | [diff] [blame] | 261 | if (column >= mtd->writesize) { |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 262 | /* OOB area */ |
Joern Engel | 2831877 | 2006-05-22 23:18:05 +0200 | [diff] [blame] | 263 | column -= mtd->writesize; |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 264 | readcmd = NAND_CMD_READOOB; |
| 265 | } else if (column < 256) { |
| 266 | /* First 256 bytes --> READ0 */ |
| 267 | readcmd = NAND_CMD_READ0; |
| 268 | } else { |
| 269 | column -= 256; |
| 270 | readcmd = NAND_CMD_READ1; |
| 271 | } |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 272 | ctx->write_byte(this, readcmd); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 273 | } |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 274 | ctx->write_byte(this, command); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 275 | |
| 276 | /* Set ALE and clear CLE to start address cycle */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 277 | au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 278 | |
| 279 | if (column != -1 || page_addr != -1) { |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 280 | au1550_hwcontrol(mtd, NAND_CTL_SETALE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 281 | |
| 282 | /* Serially input address */ |
| 283 | if (column != -1) { |
| 284 | /* Adjust columns for 16 bit buswidth */ |
Brian Norris | 3dad234 | 2014-01-29 14:08:12 -0800 | [diff] [blame] | 285 | if (this->options & NAND_BUSWIDTH_16 && |
| 286 | !nand_opcode_8bits(command)) |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 287 | column >>= 1; |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 288 | ctx->write_byte(this, column); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 289 | } |
| 290 | if (page_addr != -1) { |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 291 | ctx->write_byte(this, (u8)(page_addr & 0xff)); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 292 | |
| 293 | if (command == NAND_CMD_READ0 || |
| 294 | command == NAND_CMD_READ1 || |
| 295 | command == NAND_CMD_READOOB) { |
| 296 | /* |
| 297 | * NAND controller will release -CE after |
| 298 | * the last address byte is written, so we'll |
| 299 | * have to forcibly assert it. No interrupts |
| 300 | * are allowed while we do this as we don't |
| 301 | * want the NOR flash or PCMCIA drivers to |
| 302 | * steal our precious bytes of data... |
| 303 | */ |
| 304 | ce_override = 1; |
| 305 | local_irq_save(flags); |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 306 | au1550_hwcontrol(mtd, NAND_CTL_SETNCE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 307 | } |
| 308 | |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 309 | ctx->write_byte(this, (u8)(page_addr >> 8)); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 310 | |
Masahiro Yamada | 14157f8 | 2017-09-13 11:05:50 +0900 | [diff] [blame] | 311 | if (this->options & NAND_ROW_ADDR_3) |
Boris Brezillon | c0739d8 | 2018-09-06 14:05:23 +0200 | [diff] [blame] | 312 | ctx->write_byte(this, |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 313 | ((page_addr >> 16) & 0x0f)); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 314 | } |
| 315 | /* Latch in address */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 316 | au1550_hwcontrol(mtd, NAND_CTL_CLRALE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | /* |
| 320 | * Program and erase have their own busy handlers. |
| 321 | * Status and sequential in need no delay. |
| 322 | */ |
| 323 | switch (command) { |
| 324 | |
| 325 | case NAND_CMD_PAGEPROG: |
| 326 | case NAND_CMD_ERASE1: |
| 327 | case NAND_CMD_ERASE2: |
| 328 | case NAND_CMD_SEQIN: |
| 329 | case NAND_CMD_STATUS: |
| 330 | return; |
| 331 | |
| 332 | case NAND_CMD_RESET: |
| 333 | break; |
| 334 | |
| 335 | case NAND_CMD_READ0: |
| 336 | case NAND_CMD_READ1: |
| 337 | case NAND_CMD_READOOB: |
| 338 | /* Check if we're really driving -CE low (just in case) */ |
| 339 | if (unlikely(!ce_override)) |
| 340 | break; |
| 341 | |
| 342 | /* Apply a short delay always to ensure that we do wait tWB. */ |
| 343 | ndelay(100); |
| 344 | /* Wait for a chip to become ready... */ |
Boris Brezillon | 3cece3a | 2018-09-07 00:38:41 +0200 | [diff] [blame] | 345 | for (i = this->legacy.chip_delay; |
Boris Brezillon | 8395b75 | 2018-09-07 00:38:37 +0200 | [diff] [blame] | 346 | !this->legacy.dev_ready(this) && i > 0; --i) |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 347 | udelay(1); |
| 348 | |
| 349 | /* Release -CE and re-enable interrupts. */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 350 | au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 351 | local_irq_restore(flags); |
| 352 | return; |
| 353 | } |
| 354 | /* Apply this short delay always to ensure that we do wait tWB. */ |
| 355 | ndelay(100); |
| 356 | |
Boris Brezillon | 8395b75 | 2018-09-07 00:38:37 +0200 | [diff] [blame] | 357 | while(!this->legacy.dev_ready(this)); |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 358 | } |
| 359 | |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 360 | static int find_nand_cs(unsigned long nand_base) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | { |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 362 | void __iomem *base = |
| 363 | (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); |
| 364 | unsigned long addr, staddr, start, mask, end; |
| 365 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 366 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 367 | for (i = 0; i < 4; i++) { |
| 368 | addr = 0x1000 + (i * 0x10); /* CSx */ |
| 369 | staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ |
| 370 | /* figure out the decoded range of this CS */ |
| 371 | start = (staddr << 4) & 0xfffc0000; |
| 372 | mask = (staddr << 18) & 0xfffc0000; |
| 373 | end = (start | (start - 1)) & ~(start ^ mask); |
| 374 | if ((nand_base >= start) && (nand_base < end)) |
| 375 | return i; |
| 376 | } |
| 377 | |
| 378 | return -ENODEV; |
| 379 | } |
| 380 | |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 381 | static int au1550nd_probe(struct platform_device *pdev) |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 382 | { |
| 383 | struct au1550nd_platdata *pd; |
| 384 | struct au1550nd_ctx *ctx; |
| 385 | struct nand_chip *this; |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 386 | struct mtd_info *mtd; |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 387 | struct resource *r; |
| 388 | int ret, cs; |
| 389 | |
Jingoo Han | 453810b | 2013-07-30 17:18:33 +0900 | [diff] [blame] | 390 | pd = dev_get_platdata(&pdev->dev); |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 391 | if (!pd) { |
| 392 | dev_err(&pdev->dev, "missing platform data\n"); |
| 393 | return -ENODEV; |
| 394 | } |
| 395 | |
| 396 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
Jingoo Han | ce3737f | 2013-12-26 12:02:30 +0900 | [diff] [blame] | 397 | if (!ctx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 400 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 401 | if (!r) { |
| 402 | dev_err(&pdev->dev, "no NAND memory resource\n"); |
| 403 | ret = -ENODEV; |
| 404 | goto out1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | } |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 406 | if (request_mem_region(r->start, resource_size(r), "au1550-nand")) { |
| 407 | dev_err(&pdev->dev, "cannot claim NAND memory area\n"); |
| 408 | ret = -ENOMEM; |
| 409 | goto out1; |
Pete Popov | ef6f0d1 | 2005-09-23 02:44:58 +0100 | [diff] [blame] | 410 | } |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 411 | |
| 412 | ctx->base = ioremap_nocache(r->start, 0x1000); |
| 413 | if (!ctx->base) { |
| 414 | dev_err(&pdev->dev, "cannot remap NAND memory area\n"); |
| 415 | ret = -ENODEV; |
| 416 | goto out2; |
Pete Popov | ef6f0d1 | 2005-09-23 02:44:58 +0100 | [diff] [blame] | 417 | } |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 418 | |
| 419 | this = &ctx->chip; |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 420 | mtd = nand_to_mtd(this); |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 421 | mtd->dev.parent = &pdev->dev; |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 422 | |
| 423 | /* figure out which CS# r->start belongs to */ |
| 424 | cs = find_nand_cs(r->start); |
| 425 | if (cs < 0) { |
| 426 | dev_err(&pdev->dev, "cannot detect NAND chipselect\n"); |
| 427 | ret = -ENODEV; |
| 428 | goto out3; |
Pete Popov | ef6f0d1 | 2005-09-23 02:44:58 +0100 | [diff] [blame] | 429 | } |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 430 | ctx->cs = cs; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 431 | |
Boris Brezillon | 8395b75 | 2018-09-07 00:38:37 +0200 | [diff] [blame] | 432 | this->legacy.dev_ready = au1550_device_ready; |
Boris Brezillon | 7d6c37e | 2018-11-11 08:55:22 +0100 | [diff] [blame] | 433 | this->legacy.select_chip = au1550_select_chip; |
Boris Brezillon | bf6065c | 2018-09-07 00:38:36 +0200 | [diff] [blame] | 434 | this->legacy.cmdfunc = au1550_command; |
Sergei Shtylyov | 35af68b | 2006-05-16 20:52:06 +0400 | [diff] [blame] | 435 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | /* 30 us command delay time */ |
Boris Brezillon | 3cece3a | 2018-09-07 00:38:41 +0200 | [diff] [blame] | 437 | this->legacy.chip_delay = 30; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 438 | this->ecc.mode = NAND_ECC_SOFT; |
Rafał Miłecki | c2ec6b3 | 2016-04-13 14:06:57 +0200 | [diff] [blame] | 439 | this->ecc.algo = NAND_ECC_HAMMING; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 441 | if (pd->devwidth) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | this->options |= NAND_BUSWIDTH_16; |
| 443 | |
Boris Brezillon | 716bbba | 2018-09-07 00:38:35 +0200 | [diff] [blame] | 444 | this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte; |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 445 | ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte; |
Boris Brezillon | 716bbba | 2018-09-07 00:38:35 +0200 | [diff] [blame] | 446 | this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; |
| 447 | this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | |
Boris Brezillon | 00ad378 | 2018-09-06 14:05:14 +0200 | [diff] [blame] | 449 | ret = nand_scan(this, 1); |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 450 | if (ret) { |
| 451 | dev_err(&pdev->dev, "NAND scan failed with %d\n", ret); |
| 452 | goto out3; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | } |
| 454 | |
Boris BREZILLON | ff70f35 | 2015-12-10 08:59:51 +0100 | [diff] [blame] | 455 | mtd_device_register(mtd, pd->parts, pd->num_parts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | |
Wei Yongjun | a1d7994 | 2013-11-11 14:18:29 +0800 | [diff] [blame] | 457 | platform_set_drvdata(pdev, ctx); |
| 458 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | return 0; |
| 460 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 461 | out3: |
| 462 | iounmap(ctx->base); |
| 463 | out2: |
| 464 | release_mem_region(r->start, resource_size(r)); |
| 465 | out1: |
| 466 | kfree(ctx); |
| 467 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | } |
| 469 | |
Bill Pemberton | 810b7e0 | 2012-11-19 13:26:04 -0500 | [diff] [blame] | 470 | static int au1550nd_remove(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | { |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 472 | struct au1550nd_ctx *ctx = platform_get_drvdata(pdev); |
| 473 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | |
Boris Brezillon | 59ac276 | 2018-09-06 14:05:15 +0200 | [diff] [blame] | 475 | nand_release(&ctx->chip); |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 476 | iounmap(ctx->base); |
| 477 | release_mem_region(r->start, 0x1000); |
| 478 | kfree(ctx); |
| 479 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | } |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 481 | |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 482 | static struct platform_driver au1550nd_driver = { |
| 483 | .driver = { |
| 484 | .name = "au1550-nand", |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 485 | }, |
| 486 | .probe = au1550nd_probe, |
Bill Pemberton | 5153b88 | 2012-11-19 13:21:24 -0500 | [diff] [blame] | 487 | .remove = au1550nd_remove, |
Manuel Lauss | b67a1a0 | 2011-12-08 10:42:10 +0000 | [diff] [blame] | 488 | }; |
| 489 | |
| 490 | module_platform_driver(au1550nd_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
| 492 | MODULE_LICENSE("GPL"); |
| 493 | MODULE_AUTHOR("Embedded Edge, LLC"); |
| 494 | MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); |