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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Oliver Hartkopp42193e32014-05-15 20:31:56 +02002#ifndef _CAN_PLATFORM_CC770_H
3#define _CAN_PLATFORM_CC770_H
Wolfgang Grandegger2a367c32011-11-30 23:41:18 +00004
5/* CPU Interface Register (0x02) */
6#define CPUIF_CEN 0x01 /* Clock Out Enable */
7#define CPUIF_MUX 0x04 /* Multiplex */
8#define CPUIF_SLP 0x08 /* Sleep */
9#define CPUIF_PWD 0x10 /* Power Down Mode */
10#define CPUIF_DMC 0x20 /* Divide Memory Clock */
11#define CPUIF_DSC 0x40 /* Divide System Clock */
12#define CPUIF_RST 0x80 /* Hardware Reset Status */
13
14/* Clock Out Register (0x1f) */
15#define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */
16#define CLKOUT_SL_MASK 0x30 /* Slew Rate mask */
17#define CLKOUT_SL_SHIFT 4
18
19/* Bus Configuration Register (0x2f) */
20#define BUSCFG_DR0 0x01 /* Disconnect RX0 Input / Select RX input */
21#define BUSCFG_DR1 0x02 /* Disconnect RX1 Input / Silent mode */
22#define BUSCFG_DT1 0x08 /* Disconnect TX1 Output */
23#define BUSCFG_POL 0x20 /* Polarity dominant or recessive */
24#define BUSCFG_CBY 0x40 /* Input Comparator Bypass */
25
26struct cc770_platform_data {
27 u32 osc_freq; /* CAN bus oscillator frequency in Hz */
28
29 u8 cir; /* CPU Interface Register */
30 u8 cor; /* Clock Out Register */
31 u8 bcr; /* Bus Configuration Register */
32};
33
Oliver Hartkopp42193e32014-05-15 20:31:56 +020034#endif /* !_CAN_PLATFORM_CC770_H */