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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * include/linux/fsl_devices.h
4 *
5 * Definitions for any platform device related flags or structures for
6 * Freescale processor devices
7 *
Kumar Gala4c8d3d92005-11-13 16:06:30 -08008 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Ramneek Mehresh58c559e2012-03-20 10:35:50 +053010 * Copyright 2004,2012 Freescale Semiconductor, Inc
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#ifndef _FSL_DEVICE_H_
14#define _FSL_DEVICE_H_
15
Ramneek Mehresh58c559e2012-03-20 10:35:50 +053016#define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
17 PHY CLK to become stable - 10ms*/
Shengzhou Liu5ed33872012-09-24 22:01:35 +080018#define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */
Ramneek Mehresh58c559e2012-03-20 10:35:50 +053019
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/types.h>
21
22/*
23 * Some conventions on how we handle peripherals on Freescale chips
24 *
25 * unique device: a platform_device entry in fsl_plat_devs[] plus
26 * associated device information in its platform_data structure.
27 *
28 * A chip is described by a set of unique devices.
29 *
30 * Each sub-arch has its own master list of unique devices and
31 * enumerates them by enum fsl_devices in a sub-arch specific header
32 *
33 * The platform data structure is broken into two parts. The
34 * first is device specific information that help identify any
35 * unique features of a peripheral. The second is any
36 * information that may be defined by the board or how the device
37 * is connected externally of the chip.
38 *
39 * naming conventions:
40 * - platform data structures: <driver>_platform_data
41 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
43 *
44 */
45
Nikhil Badola38aa4202015-06-15 15:46:37 +053046enum fsl_usb2_controller_ver {
47 FSL_USB_VER_NONE = -1,
48 FSL_USB_VER_OLD = 0,
49 FSL_USB_VER_1_6 = 1,
50 FSL_USB_VER_2_2 = 2,
51 FSL_USB_VER_2_4 = 3,
52 FSL_USB_VER_2_5 = 4,
53};
54
Randy Vinson80cb9ae2006-01-20 13:53:38 -080055enum fsl_usb2_operating_modes {
56 FSL_USB2_MPH_HOST,
57 FSL_USB2_DR_HOST,
58 FSL_USB2_DR_DEVICE,
59 FSL_USB2_DR_OTG,
60};
61
62enum fsl_usb2_phy_modes {
63 FSL_USB2_PHY_NONE,
64 FSL_USB2_PHY_ULPI,
65 FSL_USB2_PHY_UTMI,
66 FSL_USB2_PHY_UTMI_WIDE,
67 FSL_USB2_PHY_SERIAL,
Nikhil Badola6009d952015-06-15 15:48:22 +053068 FSL_USB2_PHY_UTMI_DUAL,
Randy Vinson80cb9ae2006-01-20 13:53:38 -080069};
70
Anatolij Gustschin230f7ed2010-09-28 20:55:21 +020071struct clk;
72struct platform_device;
73
Randy Vinson80cb9ae2006-01-20 13:53:38 -080074struct fsl_usb2_platform_data {
75 /* board specific information */
Nikhil Badola38aa4202015-06-15 15:46:37 +053076 enum fsl_usb2_controller_ver controller_ver;
Li Yang98658532006-10-03 23:10:46 -050077 enum fsl_usb2_operating_modes operating_mode;
78 enum fsl_usb2_phy_modes phy_mode;
79 unsigned int port_enables;
Eric Bénard69cb1ec2010-10-15 14:30:58 +020080 unsigned int workaround;
Anatolij Gustschin230f7ed2010-09-28 20:55:21 +020081
82 int (*init)(struct platform_device *);
83 void (*exit)(struct platform_device *);
84 void __iomem *regs; /* ioremap'd register base */
85 struct clk *clk;
Anatolij Gustschin83722bc2011-04-18 22:02:00 +020086 unsigned power_budget; /* hcd->power_budget */
Anatolij Gustschin230f7ed2010-09-28 20:55:21 +020087 unsigned big_endian_mmio:1;
88 unsigned big_endian_desc:1;
89 unsigned es:1; /* need USBMODE:ES */
90 unsigned le_setup_buf:1;
91 unsigned have_sysif_regs:1;
92 unsigned invert_drvvbus:1;
93 unsigned invert_pwr_fault:1;
Anatolij Gustschin13b7ee2a2011-04-18 22:01:55 +020094
95 unsigned suspended:1;
96 unsigned already_suspended:1;
Ran Wang5f620bb2019-01-17 09:10:55 +000097 unsigned has_fsl_erratum_a007792:1;
98 unsigned has_fsl_erratum_14:1;
99 unsigned has_fsl_erratum_a005275:1;
Changming Huang9d4b8272016-11-29 13:45:38 +0800100 unsigned has_fsl_erratum_a005697:1;
Ran Wang5f620bb2019-01-17 09:10:55 +0000101 unsigned check_phy_clk_valid:1;
Anatolij Gustschin13b7ee2a2011-04-18 22:01:55 +0200102
103 /* register save area for suspend/resume */
104 u32 pm_command;
105 u32 pm_status;
106 u32 pm_intr_enable;
107 u32 pm_frame_index;
108 u32 pm_segment;
109 u32 pm_frame_list;
110 u32 pm_async_next;
111 u32 pm_configured_flag;
112 u32 pm_portsc;
113 u32 pm_usbgenctrl;
Randy Vinson80cb9ae2006-01-20 13:53:38 -0800114};
115
116/* Flags in fsl_usb2_mph_platform_data */
117#define FSL_USB2_PORT0_ENABLED 0x00000001
118#define FSL_USB2_PORT1_ENABLED 0x00000002
119
Eric Bénard69cb1ec2010-10-15 14:30:58 +0200120#define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
121
Anton Vorontsov364fdbc2009-03-31 15:24:36 -0700122struct spi_device;
123
Kumar Galaccf06992006-05-20 15:00:15 -0700124struct fsl_spi_platform_data {
125 u32 initial_spmode; /* initial SPMODE value */
Anton Vorontsov35b4b3c2009-03-31 15:24:37 -0700126 s16 bus_num;
Anton Vorontsov87ec0e92009-10-12 20:49:25 +0400127 unsigned int flags;
Benjamin Herrenschmidt7d6709a2009-11-24 16:06:48 +1100128#define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
129#define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
130#define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
131#define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
132#define SPI_QE (1 << 4) /* SPI unit is in QE block */
Kumar Galaccf06992006-05-20 15:00:15 -0700133 /* board specific information */
134 u16 max_chipselect;
Anton Vorontsov364fdbc2009-03-31 15:24:36 -0700135 void (*cs_control)(struct spi_device *spi, bool on);
Kumar Galaccf06992006-05-20 15:00:15 -0700136 u32 sysclk;
137};
138
Vitaly Bordug80128ff2007-07-09 11:37:35 -0700139struct mpc8xx_pcmcia_ops {
140 void(*hw_ctrl)(int slot, int enable);
141 int(*voltage_set)(int slot, int vcc, int vpp);
142};
143
Scott Woodd49747b2007-10-09 12:37:13 -0500144/* Returns non-zero if the current suspend operation would
145 * lead to a deep sleep (i.e. power removed from the core,
146 * instead of just the clock).
147 */
Anton Vorontsov2e9d5462009-09-23 22:52:38 +0400148#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
Scott Woodd49747b2007-10-09 12:37:13 -0500149int fsl_deep_sleep(void);
Anton Vorontsov2e9d5462009-09-23 22:52:38 +0400150#else
151static inline int fsl_deep_sleep(void) { return 0; }
152#endif
Scott Woodd49747b2007-10-09 12:37:13 -0500153
Li Yang98658532006-10-03 23:10:46 -0500154#endif /* _FSL_DEVICE_H_ */