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Mark Bloch57cbd892018-01-16 14:04:14 +00001/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
4 */
5
6#ifndef _MLX5_ESWITCH_
7#define _MLX5_ESWITCH_
8
9#include <linux/mlx5/driver.h>
10
Or Gerlitz0efc8562018-05-31 11:16:18 +030011#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
12
Mark Bloch57cbd892018-01-16 14:04:14 +000013enum {
14 SRIOV_NONE,
15 SRIOV_LEGACY,
16 SRIOV_OFFLOADS
17};
18
19enum {
20 REP_ETH,
Mark Bloch5e65b022018-01-16 14:13:46 +000021 REP_IB,
Mark Bloch57cbd892018-01-16 14:04:14 +000022 NUM_REP_TYPES,
23};
24
Bodong Wangf121e0e2019-01-29 21:48:31 -060025enum {
26 REP_UNREGISTERED,
27 REP_REGISTERED,
28 REP_LOADED,
29};
30
Mark Bloch57cbd892018-01-16 14:04:14 +000031struct mlx5_eswitch_rep;
32struct mlx5_eswitch_rep_if {
33 int (*load)(struct mlx5_core_dev *dev,
34 struct mlx5_eswitch_rep *rep);
35 void (*unload)(struct mlx5_eswitch_rep *rep);
36 void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);
37 void *priv;
Bodong Wang6f4e0212019-04-18 18:24:15 -050038 atomic_t state;
Mark Bloch57cbd892018-01-16 14:04:14 +000039};
40
41struct mlx5_eswitch_rep {
42 struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES];
43 u16 vport;
44 u8 hw_id[ETH_ALEN];
45 u16 vlan;
46 u32 vlan_refcount;
47};
48
Bodong Wangf8e8fa02019-01-31 17:42:57 -060049void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
50 struct mlx5_eswitch_rep_if *rep_if,
51 u8 rep_type);
52void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
Mark Bloch57cbd892018-01-16 14:04:14 +000053void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
Parav Pandit02f3afd2019-04-05 01:07:19 -050054 u16 vport_num,
Mark Bloch57cbd892018-01-16 14:04:14 +000055 u8 rep_type);
56struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
Parav Pandit02f3afd2019-04-05 01:07:19 -050057 u16 vport_num);
Mark Bloch57cbd892018-01-16 14:04:14 +000058void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
59u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
60struct mlx5_flow_handle *
61mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
Parav Pandit02f3afd2019-04-05 01:07:19 -050062 u16 vport_num, u32 sqn);
Mark Bloch57cbd892018-01-16 14:04:14 +000063#endif