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Kuninori Morimotocfd74012018-11-08 06:39:20 +00001/* SPDX-License-Identifier: GPL-2.0
2 *
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +09003 * SuperH FLCTL nand controller
4 *
5 * Copyright © 2008 Renesas Solutions Corp.
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +09006 */
7
8#ifndef __SH_FLCTL_H__
9#define __SH_FLCTL_H__
10
Bastian Hecht83738d82012-10-19 12:15:35 +020011#include <linux/completion.h>
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090012#include <linux/mtd/mtd.h>
Boris Brezillond4092d72017-08-04 17:29:10 +020013#include <linux/mtd/rawnand.h>
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090014#include <linux/mtd/partitions.h>
Bastian Hechtcfe78192012-03-18 15:13:20 +010015#include <linux/pm_qos.h>
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090016
17/* FLCTL registers */
18#define FLCMNCR(f) (f->reg + 0x0)
19#define FLCMDCR(f) (f->reg + 0x4)
20#define FLCMCDR(f) (f->reg + 0x8)
21#define FLADR(f) (f->reg + 0xC)
22#define FLADR2(f) (f->reg + 0x3C)
23#define FLDATAR(f) (f->reg + 0x10)
24#define FLDTCNTR(f) (f->reg + 0x14)
25#define FLINTDMACR(f) (f->reg + 0x18)
26#define FLBSYTMR(f) (f->reg + 0x1C)
27#define FLBSYCNT(f) (f->reg + 0x20)
28#define FLDTFIFO(f) (f->reg + 0x24)
29#define FLECFIFO(f) (f->reg + 0x28)
30#define FLTRCR(f) (f->reg + 0x2C)
Bastian Hecht3f2e9242012-03-01 10:48:40 +010031#define FLHOLDCR(f) (f->reg + 0x38)
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090032#define FL4ECCRESULT0(f) (f->reg + 0x80)
33#define FL4ECCRESULT1(f) (f->reg + 0x84)
34#define FL4ECCRESULT2(f) (f->reg + 0x88)
35#define FL4ECCRESULT3(f) (f->reg + 0x8C)
36#define FL4ECCCR(f) (f->reg + 0x90)
37#define FL4ECCCNT(f) (f->reg + 0x94)
38#define FLERRADR(f) (f->reg + 0x98)
39
40/* FLCMNCR control bits */
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090041#define _4ECCCNTEN (0x1 << 24)
42#define _4ECCEN (0x1 << 23)
43#define _4ECCCORRECT (0x1 << 22)
Magnus Damm010ab822010-01-27 09:17:21 +000044#define SHBUSSEL (0x1 << 20)
45#define SEL_16BIT (0x1 << 19)
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090046#define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
47#define QTSEL_E (0x1 << 17)
48#define ENDIAN (0x1 << 16) /* 1 = little endian */
49#define FCKSEL_E (0x1 << 15)
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090050#define ACM_SACCES_MODE (0x01 << 10)
51#define NANWF_E (0x1 << 9)
52#define SE_D (0x1 << 8) /* Spare area disable */
53#define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */
54#define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */
55#define TYPESEL_SET (0x1 << 0)
56
Bastian Hechtb6a55882012-03-01 10:48:35 +010057/*
58 * Clock settings using the PULSEx registers from FLCMNCR
59 *
60 * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E
61 * to control the clock divider used between the High-Speed Peripheral Clock
62 * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit
63 * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16
64 * bit version the divider is seperate for the pulse width of high and low
65 * signals.
66 */
67#define PULSE3 (0x1 << 27)
68#define PULSE2 (0x1 << 17)
69#define PULSE1 (0x1 << 15)
70#define PULSE0 (0x1 << 9)
71#define CLK_8B_0_5 PULSE1
72#define CLK_8B_1 0x0
73#define CLK_8B_1_5 (PULSE1 | PULSE2)
74#define CLK_8B_2 PULSE0
75#define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2)
76#define CLK_8B_4 (PULSE0 | PULSE2)
77#define CLK_16B_6L_2H PULSE0
78#define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2)
79#define CLK_16B_12L_4H (PULSE0 | PULSE2)
80
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +090081/* FLCMDCR control bits */
82#define ADRCNT2_E (0x1 << 31) /* 5byte address enable */
83#define ADRMD_E (0x1 << 26) /* Sector address access */
84#define CDSRC_E (0x1 << 25) /* Data buffer selection */
85#define DOSR_E (0x1 << 24) /* Status read check */
86#define SELRW (0x1 << 21) /* 0:read 1:write */
87#define DOADR_E (0x1 << 20) /* Address stage execute */
88#define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */
89#define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */
90#define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */
91#define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */
92#define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */
93#define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */
94
Bastian Hecht3c7ea4e2012-05-14 14:14:41 +020095/* FLINTDMACR control bits */
96#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */
97#define AC1CLR (0x1 << 19) /* ECC FIFO clear */
98#define AC0CLR (0x1 << 18) /* Data FIFO clear */
Bastian Hecht83738d82012-10-19 12:15:35 +020099#define DREQ0EN (0x1 << 16) /* FLDTFIFODMA Request Enable */
Bastian Hecht3c7ea4e2012-05-14 14:14:41 +0200100#define ECERB (0x1 << 9) /* ECC error */
101#define STERB (0x1 << 8) /* Status error */
102#define STERINTE (0x1 << 4) /* Status error enable */
103
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900104/* FLTRCR control bits */
105#define TRSTRT (0x1 << 0) /* translation start */
106#define TREND (0x1 << 1) /* translation end */
107
Bastian Hecht3f2e9242012-03-01 10:48:40 +0100108/*
109 * FLHOLDCR control bits
110 *
111 * HOLDEN: Bus Occupancy Enable (inverted)
112 * Enable this bit when the external bus might be used in between transfers.
113 * If not set and the bus gets used by other modules, a deadlock occurs.
114 */
115#define HOLDEN (0x1 << 0)
116
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900117/* FL4ECCCR control bits */
118#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
119#define _4ECCEND (0x1 << 1) /* 4 symbols end */
120#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
121
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900122#define LOOP_TIMEOUT_MAX 0x00010000
123
Bastian Hecht6667a6d52012-05-14 14:14:46 +0200124enum flctl_ecc_res_t {
125 FL_SUCCESS,
126 FL_REPAIRABLE,
127 FL_ERROR,
128 FL_TIMEOUT
129};
130
Bastian Hecht83738d82012-10-19 12:15:35 +0200131struct dma_chan;
132
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900133struct sh_flctl {
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900134 struct nand_chip chip;
Magnus Dammb79c7ad2010-02-02 13:01:25 +0900135 struct platform_device *pdev;
Bastian Hechtcfe78192012-03-18 15:13:20 +0100136 struct dev_pm_qos_request pm_qos;
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900137 void __iomem *reg;
Arnd Bergmann18733152015-12-08 16:38:12 +0100138 resource_size_t fifo;
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900139
140 uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
141 int read_bytes;
Bastian Hechte8a9d8f2012-10-19 12:15:34 +0200142 unsigned int index;
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900143 int seqin_column; /* column in SEQIN cmd */
144 int seqin_page_addr; /* page_addr in SEQIN cmd */
145 uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
146 int erase1_page_addr; /* page_addr in ERASE1 cmd */
147 uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */
148 uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */
Bastian Hecht0b3f0d12012-03-01 10:48:39 +0100149 uint32_t flcmncr_base; /* base value of FLCMNCR */
Bastian Hecht3c7ea4e2012-05-14 14:14:41 +0200150 uint32_t flintdmacr_base; /* irq enable bits */
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900151
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900152 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
153 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
Bastian Hecht3f2e9242012-03-01 10:48:40 +0100154 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */
Bastian Hechtcfe78192012-03-18 15:13:20 +0100155 unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
Bastian Hecht83738d82012-10-19 12:15:35 +0200156
157 /* DMA related objects */
158 struct dma_chan *chan_fifo0_rx;
159 struct dma_chan *chan_fifo0_tx;
160 struct completion dma_complete;
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900161};
162
163struct sh_flctl_platform_data {
164 struct mtd_partition *parts;
165 int nr_parts;
166 unsigned long flcmncr_val;
167
168 unsigned has_hwecc:1;
Bastian Hecht3f2e9242012-03-01 10:48:40 +0100169 unsigned use_holden:1;
Bastian Hecht83738d82012-10-19 12:15:35 +0200170
171 unsigned int slave_id_fifo0_tx;
172 unsigned int slave_id_fifo0_rx;
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900173};
174
Peter Huewe1cd26202010-05-13 00:06:54 +0200175static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
176{
Boris BREZILLON9c9eef82015-12-10 09:00:23 +0100177 return container_of(mtd_to_nand(mtdinfo), struct sh_flctl, chip);
Peter Huewe1cd26202010-05-13 00:06:54 +0200178}
179
Yoshihiro Shimoda6028aa02008-10-14 21:23:26 +0900180#endif /* __SH_FLCTL_H__ */