blob: 6a91a742ab3da79414c38754fa4f938c1bcd159f [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Alexey Brodkina518d632017-08-15 21:13:55 +03002/*
3 * ARC HSDK Platform support code
4 *
5 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
Alexey Brodkina518d632017-08-15 21:13:55 +03006 */
7
8#include <linux/init.h>
9#include <linux/smp.h>
10#include <asm/arcregs.h>
11#include <asm/io.h>
12#include <asm/mach_desc.h>
13
14#define ARC_CCM_UNUSED_ADDR 0x60000000
15
16static void __init hsdk_init_per_cpu(unsigned int cpu)
17{
18 /*
19 * By default ICCM is mapped to 0x7z while this area is used for
20 * kernel virtual mappings, so move it to currently unused area.
21 */
22 if (cpuinfo_arc700[cpu].iccm.sz)
23 write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
24
25 /*
26 * By default DCCM is mapped to 0x8z while this area is used by kernel,
27 * so move it to currently unused area.
28 */
29 if (cpuinfo_arc700[cpu].dccm.sz)
30 write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
31}
32
33#define ARC_PERIPHERAL_BASE 0xf0000000
34#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
35#define CREG_PAE (CREG_BASE + 0x180)
36#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
37
Eugeniy Paltsev753affb2017-10-11 20:01:42 +030038#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
39#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
40#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
41
Gustavo Pimentelec58ba12018-07-06 11:32:37 +010042#define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000)
43
44static void __init hsdk_enable_gpio_intc_wire(void)
45{
46 /*
47 * Peripherals on CPU Card are wired to cpu intc via intermediate
48 * DW APB GPIO blocks (mainly for debouncing)
49 *
50 * ---------------------
51 * | snps,archs-intc |
52 * ---------------------
53 * |
54 * ----------------------
55 * | snps,archs-idu-intc |
56 * ----------------------
57 * | | | | |
58 * | [eth] [USB] [... other peripherals]
59 * |
60 * -------------------
61 * | snps,dw-apb-intc |
62 * -------------------
63 * | | | |
64 * [Bt] [HAPS] [... other peripherals]
65 *
66 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
67 * with stacked INTCs. In particular problem happens if its master INTC
68 * not yet instantiated. See discussion here -
69 * https://lkml.org/lkml/2015/3/4/755
70 *
71 * So setup the first gpio block as a passive pass thru and hide it from
72 * DT hardware topology - connect intc directly to cpu intc
73 * The GPIO "wire" needs to be init nevertheless (here)
74 *
75 * One side adv is that peripheral interrupt handling avoids one nested
76 * intc ISR hop
77 *
78 * According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
79 * we have the following GPIO input lines used as sources of interrupt:
80 * - GPIO[0] - Bluetooth interrupt of RS9113 module
81 * - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
82 * - GPIO[3] - Audio codec (MAX9880A) interrupt
83 * - GPIO[8-23] - Available on Arduino and PMOD_x headers
84 * For now there's no use of Arduino and PMOD_x headers in Linux
85 * use-case so we only enable lines 0, 2 and 3.
86 *
87 * [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
88 */
89#define GPIO_INTEN (HSDK_GPIO_INTC + 0x30)
90#define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34)
91#define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38)
92#define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c)
93#define GPIO_INT_CONNECTED_MASK 0x0d
94
95 iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
96 iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
97 iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
98 iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
99 iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
100}
101
Alexey Brodkina518d632017-08-15 21:13:55 +0300102static void __init hsdk_init_early(void)
103{
104 /*
105 * PAE remapping for DMA clients does not work due to an RTL bug, so
106 * CREG_PAE register must be programmed to all zeroes, otherwise it
107 * will cause problems with DMA to/from peripherals even if PAE40 is
108 * not used.
109 */
110
111 /* Default is 1, which means "PAE offset = 4GByte" */
112 writel_relaxed(0, (void __iomem *) CREG_PAE);
113
114 /* Really apply settings made above */
115 writel(1, (void __iomem *) CREG_PAE_UPDATE);
Eugeniy Paltsevedb40d72017-09-28 17:33:29 +0300116
117 /*
Eugeniy Paltsev753affb2017-10-11 20:01:42 +0300118 * Switch SDIO external ciu clock divider from default div-by-8 to
119 * minimum possible div-by-2.
120 */
121 iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
Gustavo Pimentelec58ba12018-07-06 11:32:37 +0100122
123 hsdk_enable_gpio_intc_wire();
Alexey Brodkina518d632017-08-15 21:13:55 +0300124}
125
126static const char *hsdk_compat[] __initconst = {
127 "snps,hsdk",
128 NULL,
129};
130
131MACHINE_START(SIMULATION, "hsdk")
132 .dt_compat = hsdk_compat,
133 .init_early = hsdk_init_early,
134 .init_per_cpu = hsdk_init_per_cpu,
135MACHINE_END