Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 2 | /* |
| 3 | * OMAP3 Power Management Routines |
| 4 | * |
| 5 | * Copyright (C) 2006-2008 Nokia Corporation |
| 6 | * Tony Lindgren <tony@atomide.com> |
| 7 | * Jouni Hogander |
| 8 | * |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Rajendra Nayak <rnayak@ti.com> |
| 11 | * |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 12 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 13 | * Richard Woodruff <r-woodruff2@ti.com> |
| 14 | * |
| 15 | * Based on pm.c for omap1 |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
Tony Lindgren | b764a58 | 2018-09-20 12:35:31 -0700 | [diff] [blame] | 18 | #include <linux/cpu_pm.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 19 | #include <linux/pm.h> |
| 20 | #include <linux/suspend.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/err.h> |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 25 | #include <linux/clk.h> |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 26 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 27 | #include <linux/slab.h> |
Tony Lindgren | 45c3eb7 | 2012-11-30 08:41:50 -0800 | [diff] [blame] | 28 | #include <linux/omap-dma.h> |
Tony Lindgren | e639cd5 | 2014-11-20 12:11:25 -0800 | [diff] [blame] | 29 | #include <linux/omap-gpmc.h> |
Tony Lindgren | 4b25408 | 2012-08-30 15:37:24 -0700 | [diff] [blame] | 30 | |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 31 | #include <trace/events/power.h> |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 32 | |
Tony Lindgren | bf027ca | 2012-10-29 13:54:06 -0700 | [diff] [blame] | 33 | #include <asm/fncpy.h> |
Russell King | 2c74a0c | 2011-06-22 17:41:48 +0100 | [diff] [blame] | 34 | #include <asm/suspend.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 35 | #include <asm/system_misc.h> |
Russell King | 2c74a0c | 2011-06-22 17:41:48 +0100 | [diff] [blame] | 36 | |
Paul Walmsley | 1540f214 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 37 | #include "clockdomain.h" |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 38 | #include "powerdomain.h" |
Tony Lindgren | e4c060d | 2012-10-05 13:25:59 -0700 | [diff] [blame] | 39 | #include "soc.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 40 | #include "common.h" |
Paul Walmsley | ff4ae5d | 2012-10-21 01:01:11 -0600 | [diff] [blame] | 41 | #include "cm3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 42 | #include "cm-regbits-34xx.h" |
| 43 | #include "prm-regbits-34xx.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 44 | #include "prm3xxx.h" |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 45 | #include "pm.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 46 | #include "sdrc.h" |
Tony Lindgren | d09220a | 2017-11-27 08:57:26 -0800 | [diff] [blame] | 47 | #include "omap-secure.h" |
Tony Lindgren | bf027ca | 2012-10-29 13:54:06 -0700 | [diff] [blame] | 48 | #include "sram.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 49 | #include "control.h" |
Tony Lindgren | 3b8c4eb | 2014-05-05 17:27:35 -0700 | [diff] [blame] | 50 | #include "vc.h" |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 51 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 52 | /* pm34xx errata defined in pm.h */ |
| 53 | u16 pm34xx_errata; |
| 54 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 55 | struct power_state { |
| 56 | struct powerdomain *pwrdm; |
| 57 | u32 next_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 58 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 59 | u32 saved_state; |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 60 | #endif |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 61 | struct list_head node; |
| 62 | }; |
| 63 | |
| 64 | static LIST_HEAD(pwrst_list); |
| 65 | |
Jean Pihet | 46e130d | 2011-06-29 18:40:23 +0200 | [diff] [blame] | 66 | void (*omap3_do_wfi_sram)(void); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 67 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 68 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
| 69 | static struct powerdomain *core_pwrdm, *per_pwrdm; |
Kalle Jokiniemi | 3a7ec26 | 2009-03-26 15:59:01 +0200 | [diff] [blame] | 70 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 71 | static void omap3_core_save_context(void) |
| 72 | { |
Paul Walmsley | 596efe4 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 73 | omap3_ctrl_save_padconf(); |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Force write last pad into memory, as this can fail in some |
Jean Pihet | 8352129 | 2010-12-18 16:44:46 +0100 | [diff] [blame] | 77 | * cases according to errata 1.157, 1.185 |
Tero Kristo | dccaad8 | 2009-11-17 18:34:53 +0200 | [diff] [blame] | 78 | */ |
| 79 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), |
| 80 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); |
| 81 | |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 82 | /* Save the Interrupt controller context */ |
| 83 | omap_intc_save_context(); |
| 84 | /* Save the GPMC context */ |
| 85 | omap3_gpmc_save_context(); |
| 86 | /* Save the system control module context, padconf already save above*/ |
| 87 | omap3_control_save_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 88 | omap_dma_global_context_save(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void omap3_core_restore_context(void) |
| 92 | { |
| 93 | /* Restore the control module context, padconf restored by h/w */ |
| 94 | omap3_control_restore_context(); |
| 95 | /* Restore the GPMC context */ |
| 96 | omap3_gpmc_restore_context(); |
| 97 | /* Restore the interrupt controller context */ |
| 98 | omap_intc_restore_context(); |
Tero Kristo | f2d1185 | 2008-08-28 13:13:31 +0000 | [diff] [blame] | 99 | omap_dma_global_context_restore(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 100 | } |
| 101 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 102 | /* |
| 103 | * FIXME: This function should be called before entering off-mode after |
| 104 | * OMAP3 secure services have been accessed. Currently it is only called |
| 105 | * once during boot sequence, but this works as we are not using secure |
| 106 | * services. |
| 107 | */ |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 108 | static void omap3_save_secure_ram_context(void) |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 109 | { |
| 110 | u32 ret; |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 111 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 112 | |
| 113 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 114 | /* |
| 115 | * MPU next state must be set to POWER_ON temporarily, |
| 116 | * otherwise the WFI executed inside the ROM code |
| 117 | * will hang the system. |
| 118 | */ |
| 119 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
Tony Lindgren | d09220a | 2017-11-27 08:57:26 -0800 | [diff] [blame] | 120 | ret = omap3_save_secure_ram(omap3_secure_ram_storage, |
| 121 | OMAP3_SAVE_SECURE_RAM_SZ); |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 122 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 123 | /* Following is for error tracking, it should not happen */ |
| 124 | if (ret) { |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 125 | pr_err("save_secure_sram() returns %08x\n", ret); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 126 | while (1) |
| 127 | ; |
| 128 | } |
| 129 | } |
| 130 | } |
| 131 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 132 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 133 | { |
| 134 | int c; |
| 135 | |
Tero Kristo | 9cb6d36 | 2014-04-04 12:31:51 +0300 | [diff] [blame] | 136 | c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | |
| 137 | OMAP3430_ST_IO_CHAIN_MASK); |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 138 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 139 | return c ? IRQ_HANDLED : IRQ_NONE; |
Jon Hunter | 77da2d9 | 2009-06-27 00:07:25 -0500 | [diff] [blame] | 140 | } |
| 141 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 142 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 143 | { |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 144 | int c; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 145 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 146 | /* |
| 147 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, |
| 148 | * these are handled in a separate handler to avoid acking |
| 149 | * IO events before parsing in mux code |
| 150 | */ |
Tero Kristo | 9cb6d36 | 2014-04-04 12:31:51 +0300 | [diff] [blame] | 151 | c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | |
| 152 | OMAP3430_ST_IO_CHAIN_MASK)); |
| 153 | c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); |
| 154 | c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 155 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
Tero Kristo | 9cb6d36 | 2014-04-04 12:31:51 +0300 | [diff] [blame] | 156 | c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); |
| 157 | c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 158 | } |
Paul Walmsley | 8cb0ac9 | 2009-07-22 10:29:02 -0700 | [diff] [blame] | 159 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 160 | return c ? IRQ_HANDLED : IRQ_NONE; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Russell King | cbe2634 | 2011-06-30 08:45:49 +0100 | [diff] [blame] | 163 | static void omap34xx_save_context(u32 *save) |
| 164 | { |
| 165 | u32 val; |
| 166 | |
| 167 | /* Read Auxiliary Control Register */ |
| 168 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); |
| 169 | *save++ = 1; |
| 170 | *save++ = val; |
| 171 | |
| 172 | /* Read L2 AUX ctrl register */ |
| 173 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); |
| 174 | *save++ = 1; |
| 175 | *save++ = val; |
| 176 | } |
| 177 | |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 178 | static int omap34xx_do_sram_idle(unsigned long save_state) |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 179 | { |
Russell King | cbe2634 | 2011-06-30 08:45:49 +0100 | [diff] [blame] | 180 | omap34xx_cpu_suspend(save_state); |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 181 | return 0; |
Rajendra Nayak | 57f277b | 2008-09-26 17:49:34 +0530 | [diff] [blame] | 182 | } |
| 183 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 184 | void omap_sram_idle(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 185 | { |
| 186 | /* Variable to tell what needs to be saved and restored |
| 187 | * in omap_sram_idle*/ |
| 188 | /* save_state = 0 => Nothing to save and restored */ |
| 189 | /* save_state = 1 => Only L1 and logic lost */ |
| 190 | /* save_state = 2 => Only L2 lost */ |
| 191 | /* save_state = 3 => L1, L2 and logic lost */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 192 | int save_state = 0; |
| 193 | int mpu_next_state = PWRDM_POWER_ON; |
| 194 | int per_next_state = PWRDM_POWER_ON; |
| 195 | int core_next_state = PWRDM_POWER_ON; |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 196 | u32 sdrc_pwr = 0; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 197 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 198 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
| 199 | switch (mpu_next_state) { |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 200 | case PWRDM_POWER_ON: |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 201 | case PWRDM_POWER_RET: |
| 202 | /* No need to save context */ |
| 203 | save_state = 0; |
| 204 | break; |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 205 | case PWRDM_POWER_OFF: |
| 206 | save_state = 3; |
| 207 | break; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 208 | default: |
| 209 | /* Invalid state */ |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 210 | pr_err("Invalid mpu state in sram_idle\n"); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 211 | return; |
| 212 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 213 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 214 | /* NEON control */ |
| 215 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 216 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 217 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 218 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 219 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
Tero Kristo | ecf157d | 2008-12-01 13:17:29 +0200 | [diff] [blame] | 220 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 221 | |
Kevin Hilman | e0e29fd | 2012-08-07 11:28:06 -0700 | [diff] [blame] | 222 | pwrdm_pre_transition(NULL); |
Charulatha V | ff2f8e5 | 2011-09-13 18:32:37 +0530 | [diff] [blame] | 223 | |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 224 | /* PER */ |
Tony Lindgren | b764a58 | 2018-09-20 12:35:31 -0700 | [diff] [blame] | 225 | if (per_next_state == PWRDM_POWER_OFF) |
| 226 | cpu_cluster_pm_enter(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 227 | |
| 228 | /* CORE */ |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 229 | if (core_next_state < PWRDM_POWER_ON) { |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 230 | if (core_next_state == PWRDM_POWER_OFF) { |
| 231 | omap3_core_save_context(); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 232 | omap3_cm_save_context(); |
Rajendra Nayak | 2f5939c | 2008-09-26 17:50:07 +0530 | [diff] [blame] | 233 | } |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 234 | } |
Mike Chan | 40742fa | 2010-05-03 16:04:06 -0700 | [diff] [blame] | 235 | |
Tony Lindgren | 3b8c4eb | 2014-05-05 17:27:35 -0700 | [diff] [blame] | 236 | /* Configure PMIC signaling for I2C4 or sys_off_mode */ |
| 237 | omap3_vc_set_pmic_signaling(core_next_state); |
| 238 | |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 239 | omap3_intc_prepare_idle(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 240 | |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 241 | /* |
Paul Walmsley | 3047454 | 2011-10-06 13:43:23 -0600 | [diff] [blame] | 242 | * On EMU/HS devices ROM code restores a SRDC value |
| 243 | * from scratchpad which has automatic self refresh on timeout |
| 244 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
| 245 | * Hence store/restore the SDRC_POWER register here. |
| 246 | */ |
| 247 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
| 248 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || |
| 249 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 250 | core_next_state == PWRDM_POWER_OFF) |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 251 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 252 | |
| 253 | /* |
Russell King | 076f2cc | 2011-06-22 15:42:54 +0100 | [diff] [blame] | 254 | * omap3_arm_context is the location where some ARM context |
| 255 | * get saved. The rest is placed on the stack, and restored |
| 256 | * from there before resuming. |
Rajendra Nayak | 61255ab | 2008-09-26 17:49:56 +0530 | [diff] [blame] | 257 | */ |
Russell King | cbe2634 | 2011-06-30 08:45:49 +0100 | [diff] [blame] | 258 | if (save_state) |
| 259 | omap34xx_save_context(omap3_arm_context); |
Russell King | 076f2cc | 2011-06-22 15:42:54 +0100 | [diff] [blame] | 260 | if (save_state == 1 || save_state == 3) |
Russell King | 2c74a0c | 2011-06-22 17:41:48 +0100 | [diff] [blame] | 261 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
Russell King | 076f2cc | 2011-06-22 15:42:54 +0100 | [diff] [blame] | 262 | else |
| 263 | omap34xx_do_sram_idle(save_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 264 | |
Rajendra Nayak | f265dc4 | 2009-06-09 22:30:41 +0530 | [diff] [blame] | 265 | /* Restore normal SDRC POWER settings */ |
Paul Walmsley | 3047454 | 2011-10-06 13:43:23 -0600 | [diff] [blame] | 266 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
| 267 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || |
| 268 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && |
Tero Kristo | 13a6fe0f | 2008-10-13 13:17:06 +0300 | [diff] [blame] | 269 | core_next_state == PWRDM_POWER_OFF) |
| 270 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); |
| 271 | |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 272 | /* CORE */ |
Dave Gerlach | 1560d15 | 2016-04-13 20:49:48 -0500 | [diff] [blame] | 273 | if (core_next_state < PWRDM_POWER_ON && |
| 274 | pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { |
| 275 | omap3_core_restore_context(); |
| 276 | omap3_cm_restore_context(); |
| 277 | omap3_sram_restore_context(); |
| 278 | omap2_sms_restore_context(); |
| 279 | } else { |
| 280 | /* |
| 281 | * In off-mode resume path above, omap3_core_restore_context |
| 282 | * also handles the INTC autoidle restore done here so limit |
| 283 | * this to non-off mode resume paths so we don't do it twice. |
| 284 | */ |
| 285 | omap3_intc_resume_idle(); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 286 | } |
| 287 | |
Kevin Hilman | e0e29fd | 2012-08-07 11:28:06 -0700 | [diff] [blame] | 288 | pwrdm_post_transition(NULL); |
Kevin Hilman | 658ce97 | 2008-11-04 20:50:52 -0800 | [diff] [blame] | 289 | |
Kevin Hilman | e0e29fd | 2012-08-07 11:28:06 -0700 | [diff] [blame] | 290 | /* PER */ |
Tony Lindgren | b764a58 | 2018-09-20 12:35:31 -0700 | [diff] [blame] | 291 | if (per_next_state == PWRDM_POWER_OFF) |
| 292 | cpu_cluster_pm_exit(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 295 | static void omap3_pm_idle(void) |
| 296 | { |
Nicolas Pitre | 0bcd24b | 2012-01-04 16:27:48 -0500 | [diff] [blame] | 297 | if (omap_irq_pending()) |
Santosh Shilimkar | 6b85638 | 2013-02-11 19:29:45 +0530 | [diff] [blame] | 298 | return; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 299 | |
Jisheng Zhang | 6ca22700 | 2015-09-18 13:41:21 +0800 | [diff] [blame] | 300 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 301 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 302 | omap_sram_idle(); |
| 303 | |
Jisheng Zhang | 6ca22700 | 2015-09-18 13:41:21 +0800 | [diff] [blame] | 304 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 305 | } |
| 306 | |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 307 | #ifdef CONFIG_SUSPEND |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 308 | static int omap3_pm_suspend(void) |
| 309 | { |
| 310 | struct power_state *pwrst; |
| 311 | int state, ret = 0; |
| 312 | |
| 313 | /* Read current next_pwrsts */ |
| 314 | list_for_each_entry(pwrst, &pwrst_list, node) |
| 315 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
| 316 | /* Set ones wanted by suspend */ |
| 317 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 318 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 319 | goto restore; |
| 320 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) |
| 321 | goto restore; |
| 322 | } |
| 323 | |
Tero Kristo | 2bbe3af | 2009-10-23 19:03:48 +0300 | [diff] [blame] | 324 | omap3_intc_suspend(); |
| 325 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 326 | omap_sram_idle(); |
| 327 | |
| 328 | restore: |
| 329 | /* Restore next_pwrsts */ |
| 330 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 331 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
| 332 | if (state > pwrst->next_state) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 333 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
| 334 | pwrst->pwrdm->name, pwrst->next_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 335 | ret = -1; |
| 336 | } |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 337 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 338 | } |
| 339 | if (ret) |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 340 | pr_err("Could not enter target state in pm_suspend\n"); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 341 | else |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 342 | pr_info("Successfully put all powerdomains to target state\n"); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 343 | |
| 344 | return ret; |
| 345 | } |
Dave Gerlach | 2e4b62d | 2014-05-12 13:33:21 -0500 | [diff] [blame] | 346 | #else |
| 347 | #define omap3_pm_suspend NULL |
Kevin Hilman | 10f90ed | 2009-06-24 11:39:18 -0700 | [diff] [blame] | 348 | #endif /* CONFIG_SUSPEND */ |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 349 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 350 | static void __init prcm_setup_regs(void) |
| 351 | { |
Tero Kristo | ba12c24 | 2014-03-04 17:43:04 +0200 | [diff] [blame] | 352 | omap3_ctrl_init(); |
Tero Kristo | b296c81 | 2009-10-23 19:03:49 +0300 | [diff] [blame] | 353 | |
Tero Kristo | c5180a2 | 2014-02-26 17:30:43 +0200 | [diff] [blame] | 354 | omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 355 | } |
| 356 | |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 357 | void omap3_pm_off_mode_enable(int enable) |
| 358 | { |
| 359 | struct power_state *pwrst; |
| 360 | u32 state; |
| 361 | |
| 362 | if (enable) |
| 363 | state = PWRDM_POWER_OFF; |
| 364 | else |
| 365 | state = PWRDM_POWER_RET; |
| 366 | |
| 367 | list_for_each_entry(pwrst, &pwrst_list, node) { |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 368 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
| 369 | pwrst->pwrdm == core_pwrdm && |
| 370 | state == PWRDM_POWER_OFF) { |
| 371 | pwrst->next_state = PWRDM_POWER_RET; |
Ricardo Salveti de Araujo | e16b41b | 2011-01-31 11:35:25 -0200 | [diff] [blame] | 372 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 373 | __func__); |
| 374 | } else { |
| 375 | pwrst->next_state = state; |
| 376 | } |
| 377 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | c40552b | 2009-10-06 14:25:09 -0700 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | |
Tero Kristo | 68d4778 | 2008-11-26 12:26:24 +0200 | [diff] [blame] | 381 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
| 382 | { |
| 383 | struct power_state *pwrst; |
| 384 | |
| 385 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 386 | if (pwrst->pwrdm == pwrdm) |
| 387 | return pwrst->next_state; |
| 388 | } |
| 389 | return -EINVAL; |
| 390 | } |
| 391 | |
| 392 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) |
| 393 | { |
| 394 | struct power_state *pwrst; |
| 395 | |
| 396 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 397 | if (pwrst->pwrdm == pwrdm) { |
| 398 | pwrst->next_state = state; |
| 399 | return 0; |
| 400 | } |
| 401 | } |
| 402 | return -EINVAL; |
| 403 | } |
| 404 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 405 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 406 | { |
| 407 | struct power_state *pwrst; |
| 408 | |
| 409 | if (!pwrdm->pwrsts) |
| 410 | return 0; |
| 411 | |
Ming Lei | d3d381c | 2009-08-22 21:20:26 +0800 | [diff] [blame] | 412 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 413 | if (!pwrst) |
| 414 | return -ENOMEM; |
| 415 | pwrst->pwrdm = pwrdm; |
| 416 | pwrst->next_state = PWRDM_POWER_RET; |
| 417 | list_add(&pwrst->node, &pwrst_list); |
| 418 | |
| 419 | if (pwrdm_has_hdwr_sar(pwrdm)) |
| 420 | pwrdm_enable_hdwr_sar(pwrdm); |
| 421 | |
Santosh Shilimkar | eb6a2c7 | 2010-09-15 01:04:01 +0530 | [diff] [blame] | 422 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | /* |
Jean Pihet | 46e130d | 2011-06-29 18:40:23 +0200 | [diff] [blame] | 426 | * Push functions to SRAM |
| 427 | * |
| 428 | * The minimum set of functions is pushed to SRAM for execution: |
| 429 | * - omap3_do_wfi for erratum i581 WA, |
Jean Pihet | 46e130d | 2011-06-29 18:40:23 +0200 | [diff] [blame] | 430 | */ |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 431 | void omap_push_sram_idle(void) |
| 432 | { |
Jean Pihet | 46e130d | 2011-06-29 18:40:23 +0200 | [diff] [blame] | 433 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
Rajendra Nayak | 3231fc8 | 2008-09-26 17:49:14 +0530 | [diff] [blame] | 434 | } |
| 435 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 436 | static void __init pm_errata_configure(void) |
| 437 | { |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 438 | if (cpu_is_omap3630()) { |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 439 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 440 | /* Enable the l2 cache toggling in sleep logic */ |
| 441 | enable_omap3630_toggle_l2_on_restore(); |
Eduardo Valentin | cc1b602 | 2010-12-20 14:05:09 -0600 | [diff] [blame] | 442 | if (omap_rev() < OMAP3630_REV_ES1_2) |
Paul Walmsley | 856c3c5 | 2012-10-16 00:08:53 -0600 | [diff] [blame] | 443 | pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | |
| 444 | PM_PER_MEMORIES_ERRATUM_i582); |
| 445 | } else if (cpu_is_omap34xx()) { |
| 446 | pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; |
Peter 'p2' De Schrijver | c4236d2 | 2010-12-20 14:05:07 -0600 | [diff] [blame] | 447 | } |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 448 | } |
| 449 | |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 450 | int __init omap3_pm_init(void) |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 451 | { |
| 452 | struct power_state *pwrst, *tmp; |
Paul Walmsley | 856c3c5 | 2012-10-16 00:08:53 -0600 | [diff] [blame] | 453 | struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 454 | int ret; |
| 455 | |
Paul Walmsley | b02b917 | 2011-10-06 17:18:45 -0600 | [diff] [blame] | 456 | if (!omap3_has_io_chain_ctrl()) |
Joe Perches | 3d0cb73 | 2014-09-13 11:31:16 -0700 | [diff] [blame] | 457 | pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); |
Paul Walmsley | b02b917 | 2011-10-06 17:18:45 -0600 | [diff] [blame] | 458 | |
Nishanth Menon | 8cdfd83 | 2010-12-20 14:05:05 -0600 | [diff] [blame] | 459 | pm_errata_configure(); |
| 460 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 461 | /* XXX prcm_setup_regs needs to be before enabling hw |
| 462 | * supervised mode for powerdomains */ |
| 463 | prcm_setup_regs(); |
| 464 | |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 465 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
| 466 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); |
| 467 | |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 468 | if (ret) { |
Tero Kristo | 22f5137 | 2011-12-16 14:36:59 -0700 | [diff] [blame] | 469 | pr_err("pm: Failed to request pm_wkup irq\n"); |
| 470 | goto err1; |
| 471 | } |
| 472 | |
| 473 | /* IO interrupt is shared with mux code */ |
| 474 | ret = request_irq(omap_prcm_event_to_irq("io"), |
| 475 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", |
| 476 | omap3_pm_init); |
| 477 | |
| 478 | if (ret) { |
| 479 | pr_err("pm: Failed to request pm_io irq\n"); |
Mark A. Greer | ce229c5 | 2012-03-17 18:22:47 -0700 | [diff] [blame] | 480 | goto err2; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 481 | } |
| 482 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 483 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 484 | if (ret) { |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 485 | pr_err("Failed to setup powerdomains\n"); |
Mark A. Greer | ce229c5 | 2012-03-17 18:22:47 -0700 | [diff] [blame] | 486 | goto err3; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 487 | } |
| 488 | |
Paul Walmsley | 92206fd | 2012-02-02 02:38:50 -0700 | [diff] [blame] | 489 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 490 | |
| 491 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
| 492 | if (mpu_pwrdm == NULL) { |
Mark A. Greer | 9817985 | 2012-03-17 18:22:48 -0700 | [diff] [blame] | 493 | pr_err("Failed to get mpu_pwrdm\n"); |
Mark A. Greer | ce229c5 | 2012-03-17 18:22:47 -0700 | [diff] [blame] | 494 | ret = -EINVAL; |
| 495 | goto err3; |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 496 | } |
| 497 | |
Rajendra Nayak | fa3c2a4 | 2008-09-26 17:49:22 +0530 | [diff] [blame] | 498 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
| 499 | per_pwrdm = pwrdm_lookup("per_pwrdm"); |
| 500 | core_pwrdm = pwrdm_lookup("core_pwrdm"); |
| 501 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 502 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
| 503 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); |
Paul Walmsley | 856c3c5 | 2012-10-16 00:08:53 -0600 | [diff] [blame] | 504 | per_clkdm = clkdm_lookup("per_clkdm"); |
| 505 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 506 | |
Dave Gerlach | 2e4b62d | 2014-05-12 13:33:21 -0500 | [diff] [blame] | 507 | omap_common_suspend_init(omap3_pm_suspend); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 508 | |
Nicolas Pitre | 0bcd24b | 2012-01-04 16:27:48 -0500 | [diff] [blame] | 509 | arm_pm_idle = omap3_pm_idle; |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 510 | omap3_idle_init(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 511 | |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 512 | /* |
| 513 | * RTA is disabled during initialization as per erratum i608 |
| 514 | * it is safer to disable RTA by the bootloader, but we would like |
| 515 | * to be doubly sure here and prevent any mishaps. |
| 516 | */ |
| 517 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) |
| 518 | omap3630_ctrl_disable_rta(); |
| 519 | |
Paul Walmsley | 856c3c5 | 2012-10-16 00:08:53 -0600 | [diff] [blame] | 520 | /* |
| 521 | * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are |
| 522 | * not correctly reset when the PER powerdomain comes back |
| 523 | * from OFF or OSWR when the CORE powerdomain is kept active. |
| 524 | * See OMAP36xx Erratum i582 "PER Domain reset issue after |
| 525 | * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a |
| 526 | * complete workaround. The kernel must also prevent the PER |
| 527 | * powerdomain from going to OSWR/OFF while the CORE |
| 528 | * powerdomain is not going to OSWR/OFF. And if PER last |
| 529 | * power state was off while CORE last power state was ON, the |
| 530 | * UART3/4 and McBSP2/3 SIDETONE devices need to run a |
| 531 | * self-test using their loopback tests; if that fails, those |
| 532 | * devices are unusable until the PER/CORE can complete a transition |
| 533 | * from ON to OSWR/OFF and then back to ON. |
| 534 | * |
| 535 | * XXX Technically this workaround is only needed if off-mode |
| 536 | * or OSWR is enabled. |
| 537 | */ |
| 538 | if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) |
| 539 | clkdm_add_wkdep(per_clkdm, wkup_clkdm); |
| 540 | |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 541 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 542 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
| 543 | omap3_secure_ram_storage = |
Tony Lindgren | d09220a | 2017-11-27 08:57:26 -0800 | [diff] [blame] | 544 | kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 545 | if (!omap3_secure_ram_storage) |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 546 | pr_err("Memory allocation failed when allocating for secure sram context\n"); |
Tero Kristo | 27d59a4 | 2008-10-13 13:15:00 +0300 | [diff] [blame] | 547 | |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 548 | local_irq_disable(); |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 549 | |
| 550 | omap_dma_global_context_save(); |
Kevin Hilman | 617fcc9 | 2011-01-25 16:40:01 -0800 | [diff] [blame] | 551 | omap3_save_secure_ram_context(); |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 552 | omap_dma_global_context_restore(); |
| 553 | |
| 554 | local_irq_enable(); |
Tero Kristo | 9d97140 | 2008-12-12 11:20:05 +0200 | [diff] [blame] | 555 | } |
| 556 | |
| 557 | omap3_save_scratchpad_contents(); |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 558 | return ret; |
Mark A. Greer | ce229c5 | 2012-03-17 18:22:47 -0700 | [diff] [blame] | 559 | |
| 560 | err3: |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 561 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
| 562 | list_del(&pwrst->node); |
| 563 | kfree(pwrst); |
| 564 | } |
Mark A. Greer | ce229c5 | 2012-03-17 18:22:47 -0700 | [diff] [blame] | 565 | free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
| 566 | err2: |
| 567 | free_irq(omap_prcm_event_to_irq("wkup"), NULL); |
| 568 | err1: |
Kevin Hilman | 8bd2294 | 2009-05-28 10:56:16 -0700 | [diff] [blame] | 569 | return ret; |
| 570 | } |