blob: 54254fc92c2ed93488b672116c27b4d0defe764f [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Kevin Hilman8bd22942009-05-28 10:56:16 -07002/*
3 * OMAP3 Power Management Routines
4 *
5 * Copyright (C) 2006-2008 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Jouni Hogander
8 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05309 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Rajendra Nayak <rnayak@ti.com>
11 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070012 * Copyright (C) 2005 Texas Instruments, Inc.
13 * Richard Woodruff <r-woodruff2@ti.com>
14 *
15 * Based on pm.c for omap1
Kevin Hilman8bd22942009-05-28 10:56:16 -070016 */
17
Tony Lindgrenb764a582018-09-20 12:35:31 -070018#include <linux/cpu_pm.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070019#include <linux/pm.h>
20#include <linux/suspend.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/err.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070025#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020026#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Tony Lindgren45c3eb72012-11-30 08:41:50 -080028#include <linux/omap-dma.h>
Tony Lindgrene639cd52014-11-20 12:11:25 -080029#include <linux/omap-gpmc.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070030
Jean Pihet5e7c58d2011-03-03 11:25:43 +010031#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070032
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070033#include <asm/fncpy.h>
Russell King2c74a0c2011-06-22 17:41:48 +010034#include <asm/suspend.h>
David Howells9f97da72012-03-28 18:30:01 +010035#include <asm/system_misc.h>
Russell King2c74a0c2011-06-22 17:41:48 +010036
Paul Walmsley1540f2142010-12-21 21:05:15 -070037#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070038#include "powerdomain.h"
Tony Lindgrene4c060d2012-10-05 13:25:59 -070039#include "soc.h"
Tony Lindgren4e653312011-11-10 22:45:17 +010040#include "common.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060041#include "cm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070042#include "cm-regbits-34xx.h"
43#include "prm-regbits-34xx.h"
Paul Walmsley139563a2012-10-21 01:01:10 -060044#include "prm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070045#include "pm.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030046#include "sdrc.h"
Tony Lindgrend09220a2017-11-27 08:57:26 -080047#include "omap-secure.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070048#include "sram.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060049#include "control.h"
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -070050#include "vc.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030051
Nishanth Menon8cdfd832010-12-20 14:05:05 -060052/* pm34xx errata defined in pm.h */
53u16 pm34xx_errata;
54
Kevin Hilman8bd22942009-05-28 10:56:16 -070055struct power_state {
56 struct powerdomain *pwrdm;
57 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070058#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070059 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070060#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070061 struct list_head node;
62};
63
64static LIST_HEAD(pwrst_list);
65
Jean Pihet46e130d2011-06-29 18:40:23 +020066void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030067
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053068static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
69static struct powerdomain *core_pwrdm, *per_pwrdm;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020070
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053071static void omap3_core_save_context(void)
72{
Paul Walmsley596efe42010-12-21 21:05:16 -070073 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +020074
75 /*
76 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +010077 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +020078 */
79 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
80 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
81
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053082 /* Save the Interrupt controller context */
83 omap_intc_save_context();
84 /* Save the GPMC context */
85 omap3_gpmc_save_context();
86 /* Save the system control module context, padconf already save above*/
87 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +000088 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053089}
90
91static void omap3_core_restore_context(void)
92{
93 /* Restore the control module context, padconf restored by h/w */
94 omap3_control_restore_context();
95 /* Restore the GPMC context */
96 omap3_gpmc_restore_context();
97 /* Restore the interrupt controller context */
98 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +000099 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530100}
101
Tero Kristo9d971402008-12-12 11:20:05 +0200102/*
103 * FIXME: This function should be called before entering off-mode after
104 * OMAP3 secure services have been accessed. Currently it is only called
105 * once during boot sequence, but this works as we are not using secure
106 * services.
107 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800108static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300109{
110 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800111 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300112
113 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300114 /*
115 * MPU next state must be set to POWER_ON temporarily,
116 * otherwise the WFI executed inside the ROM code
117 * will hang the system.
118 */
119 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
Tony Lindgrend09220a2017-11-27 08:57:26 -0800120 ret = omap3_save_secure_ram(omap3_secure_ram_storage,
121 OMAP3_SAVE_SECURE_RAM_SZ);
Kevin Hilman617fcc92011-01-25 16:40:01 -0800122 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300123 /* Following is for error tracking, it should not happen */
124 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700125 pr_err("save_secure_sram() returns %08x\n", ret);
Tero Kristo27d59a42008-10-13 13:15:00 +0300126 while (1)
127 ;
128 }
129 }
130}
131
Tero Kristo22f51372011-12-16 14:36:59 -0700132static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700133{
134 int c;
135
Tero Kristo9cb6d362014-04-04 12:31:51 +0300136 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
137 OMAP3430_ST_IO_CHAIN_MASK);
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700138
Tero Kristo22f51372011-12-16 14:36:59 -0700139 return c ? IRQ_HANDLED : IRQ_NONE;
Jon Hunter77da2d92009-06-27 00:07:25 -0500140}
141
Tero Kristo22f51372011-12-16 14:36:59 -0700142static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700143{
Tero Kristo22f51372011-12-16 14:36:59 -0700144 int c;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700145
Tero Kristo22f51372011-12-16 14:36:59 -0700146 /*
147 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
148 * these are handled in a separate handler to avoid acking
149 * IO events before parsing in mux code
150 */
Tero Kristo9cb6d362014-04-04 12:31:51 +0300151 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
152 OMAP3430_ST_IO_CHAIN_MASK));
153 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
154 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
Tero Kristo22f51372011-12-16 14:36:59 -0700155 if (omap_rev() > OMAP3430_REV_ES1_0) {
Tero Kristo9cb6d362014-04-04 12:31:51 +0300156 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
157 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
Tero Kristo22f51372011-12-16 14:36:59 -0700158 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700159
Tero Kristo22f51372011-12-16 14:36:59 -0700160 return c ? IRQ_HANDLED : IRQ_NONE;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700161}
162
Russell Kingcbe26342011-06-30 08:45:49 +0100163static void omap34xx_save_context(u32 *save)
164{
165 u32 val;
166
167 /* Read Auxiliary Control Register */
168 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
169 *save++ = 1;
170 *save++ = val;
171
172 /* Read L2 AUX ctrl register */
173 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
174 *save++ = 1;
175 *save++ = val;
176}
177
Russell King29cb3cd2011-07-02 09:54:01 +0100178static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530179{
Russell Kingcbe26342011-06-30 08:45:49 +0100180 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100181 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530182}
183
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530184void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700185{
186 /* Variable to tell what needs to be saved and restored
187 * in omap_sram_idle*/
188 /* save_state = 0 => Nothing to save and restored */
189 /* save_state = 1 => Only L1 and logic lost */
190 /* save_state = 2 => Only L2 lost */
191 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530192 int save_state = 0;
193 int mpu_next_state = PWRDM_POWER_ON;
194 int per_next_state = PWRDM_POWER_ON;
195 int core_next_state = PWRDM_POWER_ON;
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300196 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700197
Kevin Hilman8bd22942009-05-28 10:56:16 -0700198 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
199 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530200 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700201 case PWRDM_POWER_RET:
202 /* No need to save context */
203 save_state = 0;
204 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530205 case PWRDM_POWER_OFF:
206 save_state = 3;
207 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700208 default:
209 /* Invalid state */
Mark A. Greer98179852012-03-17 18:22:48 -0700210 pr_err("Invalid mpu state in sram_idle\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700211 return;
212 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300213
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530214 /* NEON control */
215 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200216 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530217
Mike Chan40742fa2010-05-03 16:04:06 -0700218 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800219 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200220 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Mike Chan40742fa2010-05-03 16:04:06 -0700221
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700222 pwrdm_pre_transition(NULL);
Charulatha Vff2f8e52011-09-13 18:32:37 +0530223
Mike Chan40742fa2010-05-03 16:04:06 -0700224 /* PER */
Tony Lindgrenb764a582018-09-20 12:35:31 -0700225 if (per_next_state == PWRDM_POWER_OFF)
226 cpu_cluster_pm_enter();
Kevin Hilman658ce972008-11-04 20:50:52 -0800227
228 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530229 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530230 if (core_next_state == PWRDM_POWER_OFF) {
231 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700232 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530233 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530234 }
Mike Chan40742fa2010-05-03 16:04:06 -0700235
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -0700236 /* Configure PMIC signaling for I2C4 or sys_off_mode */
237 omap3_vc_set_pmic_signaling(core_next_state);
238
Tero Kristof18cc2f2009-10-23 19:03:50 +0300239 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700240
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530241 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600242 * On EMU/HS devices ROM code restores a SRDC value
243 * from scratchpad which has automatic self refresh on timeout
244 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
245 * Hence store/restore the SDRC_POWER register here.
246 */
247 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
248 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
249 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530250 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300251 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300252
253 /*
Russell King076f2cc2011-06-22 15:42:54 +0100254 * omap3_arm_context is the location where some ARM context
255 * get saved. The rest is placed on the stack, and restored
256 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530257 */
Russell Kingcbe26342011-06-30 08:45:49 +0100258 if (save_state)
259 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100260 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100261 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100262 else
263 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700264
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530265 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600266 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
267 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
268 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300269 core_next_state == PWRDM_POWER_OFF)
270 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
271
Kevin Hilman658ce972008-11-04 20:50:52 -0800272 /* CORE */
Dave Gerlach1560d152016-04-13 20:49:48 -0500273 if (core_next_state < PWRDM_POWER_ON &&
274 pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
275 omap3_core_restore_context();
276 omap3_cm_restore_context();
277 omap3_sram_restore_context();
278 omap2_sms_restore_context();
279 } else {
280 /*
281 * In off-mode resume path above, omap3_core_restore_context
282 * also handles the INTC autoidle restore done here so limit
283 * this to non-off mode resume paths so we don't do it twice.
284 */
285 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800286 }
287
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700288 pwrdm_post_transition(NULL);
Kevin Hilman658ce972008-11-04 20:50:52 -0800289
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700290 /* PER */
Tony Lindgrenb764a582018-09-20 12:35:31 -0700291 if (per_next_state == PWRDM_POWER_OFF)
292 cpu_cluster_pm_exit();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700293}
294
Kevin Hilman8bd22942009-05-28 10:56:16 -0700295static void omap3_pm_idle(void)
296{
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500297 if (omap_irq_pending())
Santosh Shilimkar6b856382013-02-11 19:29:45 +0530298 return;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700299
Jisheng Zhang6ca227002015-09-18 13:41:21 +0800300 trace_cpu_idle_rcuidle(1, smp_processor_id());
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100301
Kevin Hilman8bd22942009-05-28 10:56:16 -0700302 omap_sram_idle();
303
Jisheng Zhang6ca227002015-09-18 13:41:21 +0800304 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Kevin Hilman8bd22942009-05-28 10:56:16 -0700305}
306
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700307#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700308static int omap3_pm_suspend(void)
309{
310 struct power_state *pwrst;
311 int state, ret = 0;
312
313 /* Read current next_pwrsts */
314 list_for_each_entry(pwrst, &pwrst_list, node)
315 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
316 /* Set ones wanted by suspend */
317 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530318 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700319 goto restore;
320 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
321 goto restore;
322 }
323
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300324 omap3_intc_suspend();
325
Kevin Hilman8bd22942009-05-28 10:56:16 -0700326 omap_sram_idle();
327
328restore:
329 /* Restore next_pwrsts */
330 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700331 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
332 if (state > pwrst->next_state) {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600333 pr_info("Powerdomain (%s) didn't enter target state %d\n",
334 pwrst->pwrdm->name, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700335 ret = -1;
336 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530337 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700338 }
339 if (ret)
Mark A. Greer98179852012-03-17 18:22:48 -0700340 pr_err("Could not enter target state in pm_suspend\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700341 else
Mark A. Greer98179852012-03-17 18:22:48 -0700342 pr_info("Successfully put all powerdomains to target state\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700343
344 return ret;
345}
Dave Gerlach2e4b62d2014-05-12 13:33:21 -0500346#else
347#define omap3_pm_suspend NULL
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700348#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700349
Kevin Hilman8111b222009-04-28 15:27:44 -0700350static void __init prcm_setup_regs(void)
351{
Tero Kristoba12c242014-03-04 17:43:04 +0200352 omap3_ctrl_init();
Tero Kristob296c812009-10-23 19:03:49 +0300353
Tero Kristoc5180a22014-02-26 17:30:43 +0200354 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
Kevin Hilman8bd22942009-05-28 10:56:16 -0700355}
356
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700357void omap3_pm_off_mode_enable(int enable)
358{
359 struct power_state *pwrst;
360 u32 state;
361
362 if (enable)
363 state = PWRDM_POWER_OFF;
364 else
365 state = PWRDM_POWER_RET;
366
367 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600368 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
369 pwrst->pwrdm == core_pwrdm &&
370 state == PWRDM_POWER_OFF) {
371 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200372 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600373 __func__);
374 } else {
375 pwrst->next_state = state;
376 }
377 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700378 }
379}
380
Tero Kristo68d47782008-11-26 12:26:24 +0200381int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
382{
383 struct power_state *pwrst;
384
385 list_for_each_entry(pwrst, &pwrst_list, node) {
386 if (pwrst->pwrdm == pwrdm)
387 return pwrst->next_state;
388 }
389 return -EINVAL;
390}
391
392int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
393{
394 struct power_state *pwrst;
395
396 list_for_each_entry(pwrst, &pwrst_list, node) {
397 if (pwrst->pwrdm == pwrdm) {
398 pwrst->next_state = state;
399 return 0;
400 }
401 }
402 return -EINVAL;
403}
404
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300405static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700406{
407 struct power_state *pwrst;
408
409 if (!pwrdm->pwrsts)
410 return 0;
411
Ming Leid3d381c2009-08-22 21:20:26 +0800412 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700413 if (!pwrst)
414 return -ENOMEM;
415 pwrst->pwrdm = pwrdm;
416 pwrst->next_state = PWRDM_POWER_RET;
417 list_add(&pwrst->node, &pwrst_list);
418
419 if (pwrdm_has_hdwr_sar(pwrdm))
420 pwrdm_enable_hdwr_sar(pwrdm);
421
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530422 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700423}
424
425/*
Jean Pihet46e130d2011-06-29 18:40:23 +0200426 * Push functions to SRAM
427 *
428 * The minimum set of functions is pushed to SRAM for execution:
429 * - omap3_do_wfi for erratum i581 WA,
Jean Pihet46e130d2011-06-29 18:40:23 +0200430 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530431void omap_push_sram_idle(void)
432{
Jean Pihet46e130d2011-06-29 18:40:23 +0200433 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530434}
435
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600436static void __init pm_errata_configure(void)
437{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600438 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600439 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600440 /* Enable the l2 cache toggling in sleep logic */
441 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600442 if (omap_rev() < OMAP3630_REV_ES1_2)
Paul Walmsley856c3c52012-10-16 00:08:53 -0600443 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
444 PM_PER_MEMORIES_ERRATUM_i582);
445 } else if (cpu_is_omap34xx()) {
446 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600447 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600448}
449
Shawn Guobbd707a2012-04-26 16:06:50 +0800450int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700451{
452 struct power_state *pwrst, *tmp;
Paul Walmsley856c3c52012-10-16 00:08:53 -0600453 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700454 int ret;
455
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600456 if (!omap3_has_io_chain_ctrl())
Joe Perches3d0cb732014-09-13 11:31:16 -0700457 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600458
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600459 pm_errata_configure();
460
Kevin Hilman8bd22942009-05-28 10:56:16 -0700461 /* XXX prcm_setup_regs needs to be before enabling hw
462 * supervised mode for powerdomains */
463 prcm_setup_regs();
464
Tero Kristo22f51372011-12-16 14:36:59 -0700465 ret = request_irq(omap_prcm_event_to_irq("wkup"),
466 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
467
Kevin Hilman8bd22942009-05-28 10:56:16 -0700468 if (ret) {
Tero Kristo22f51372011-12-16 14:36:59 -0700469 pr_err("pm: Failed to request pm_wkup irq\n");
470 goto err1;
471 }
472
473 /* IO interrupt is shared with mux code */
474 ret = request_irq(omap_prcm_event_to_irq("io"),
475 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
476 omap3_pm_init);
477
478 if (ret) {
479 pr_err("pm: Failed to request pm_io irq\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700480 goto err2;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700481 }
482
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300483 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700484 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700485 pr_err("Failed to setup powerdomains\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700486 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700487 }
488
Paul Walmsley92206fd2012-02-02 02:38:50 -0700489 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700490
491 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
492 if (mpu_pwrdm == NULL) {
Mark A. Greer98179852012-03-17 18:22:48 -0700493 pr_err("Failed to get mpu_pwrdm\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700494 ret = -EINVAL;
495 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700496 }
497
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530498 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
499 per_pwrdm = pwrdm_lookup("per_pwrdm");
500 core_pwrdm = pwrdm_lookup("core_pwrdm");
501
Paul Walmsley55ed9692010-01-26 20:12:59 -0700502 neon_clkdm = clkdm_lookup("neon_clkdm");
503 mpu_clkdm = clkdm_lookup("mpu_clkdm");
Paul Walmsley856c3c52012-10-16 00:08:53 -0600504 per_clkdm = clkdm_lookup("per_clkdm");
505 wkup_clkdm = clkdm_lookup("wkup_clkdm");
Paul Walmsley55ed9692010-01-26 20:12:59 -0700506
Dave Gerlach2e4b62d2014-05-12 13:33:21 -0500507 omap_common_suspend_init(omap3_pm_suspend);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700508
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500509 arm_pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300510 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700511
Nishanth Menon458e9992010-12-20 14:05:06 -0600512 /*
513 * RTA is disabled during initialization as per erratum i608
514 * it is safer to disable RTA by the bootloader, but we would like
515 * to be doubly sure here and prevent any mishaps.
516 */
517 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
518 omap3630_ctrl_disable_rta();
519
Paul Walmsley856c3c52012-10-16 00:08:53 -0600520 /*
521 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
522 * not correctly reset when the PER powerdomain comes back
523 * from OFF or OSWR when the CORE powerdomain is kept active.
524 * See OMAP36xx Erratum i582 "PER Domain reset issue after
525 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
526 * complete workaround. The kernel must also prevent the PER
527 * powerdomain from going to OSWR/OFF while the CORE
528 * powerdomain is not going to OSWR/OFF. And if PER last
529 * power state was off while CORE last power state was ON, the
530 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
531 * self-test using their loopback tests; if that fails, those
532 * devices are unusable until the PER/CORE can complete a transition
533 * from ON to OSWR/OFF and then back to ON.
534 *
535 * XXX Technically this workaround is only needed if off-mode
536 * or OSWR is enabled.
537 */
538 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
539 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
540
Paul Walmsley55ed9692010-01-26 20:12:59 -0700541 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300542 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
543 omap3_secure_ram_storage =
Tony Lindgrend09220a2017-11-27 08:57:26 -0800544 kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
Tero Kristo27d59a42008-10-13 13:15:00 +0300545 if (!omap3_secure_ram_storage)
Paul Walmsley7852ec02012-07-26 00:54:26 -0600546 pr_err("Memory allocation failed when allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300547
Tero Kristo9d971402008-12-12 11:20:05 +0200548 local_irq_disable();
Tero Kristo9d971402008-12-12 11:20:05 +0200549
550 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800551 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200552 omap_dma_global_context_restore();
553
554 local_irq_enable();
Tero Kristo9d971402008-12-12 11:20:05 +0200555 }
556
557 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700558 return ret;
Mark A. Greerce229c52012-03-17 18:22:47 -0700559
560err3:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700561 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
562 list_del(&pwrst->node);
563 kfree(pwrst);
564 }
Mark A. Greerce229c52012-03-17 18:22:47 -0700565 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
566err2:
567 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
568err1:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700569 return ret;
570}