blob: 0395c00b7772ad3f87706881b2267ffbabba997d [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Thierry Reding6b6b6042013-11-15 16:06:05 +01002/*
3 * Copyright (C) 2013 NVIDIA Corporation
Thierry Reding6b6b6042013-11-15 16:06:05 +01004 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/of_gpio.h>
Jon Hunter0751bb52016-06-29 10:17:55 +010012#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/pinctrl/pinmux.h>
Thierry Reding82b81b32017-10-12 17:32:52 +020015#include <linux/pm_runtime.h>
Thierry Reding6b6b6042013-11-15 16:06:05 +010016#include <linux/platform_device.h>
17#include <linux/reset.h>
18#include <linux/regulator/consumer.h>
Thierry Reding2fff79d32014-04-25 16:42:32 +020019#include <linux/workqueue.h>
Thierry Reding6b6b6042013-11-15 16:06:05 +010020
21#include <drm/drm_dp_helper.h>
22#include <drm/drm_panel.h>
23
24#include "dpaux.h"
25#include "drm.h"
Thierry Redingeba7c452017-08-15 15:41:13 +020026#include "trace.h"
Thierry Reding6b6b6042013-11-15 16:06:05 +010027
28static DEFINE_MUTEX(dpaux_lock);
29static LIST_HEAD(dpaux_list);
30
31struct tegra_dpaux {
32 struct drm_dp_aux aux;
33 struct device *dev;
34
35 void __iomem *regs;
36 int irq;
37
38 struct tegra_output *output;
39
40 struct reset_control *rst;
41 struct clk *clk_parent;
42 struct clk *clk;
43
44 struct regulator *vdd;
45
46 struct completion complete;
Thierry Reding2fff79d32014-04-25 16:42:32 +020047 struct work_struct work;
Thierry Reding6b6b6042013-11-15 16:06:05 +010048 struct list_head list;
Jon Hunter0751bb52016-06-29 10:17:55 +010049
50#ifdef CONFIG_GENERIC_PINCONF
51 struct pinctrl_dev *pinctrl;
52 struct pinctrl_desc desc;
53#endif
Thierry Reding6b6b6042013-11-15 16:06:05 +010054};
55
56static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
57{
58 return container_of(aux, struct tegra_dpaux, aux);
59}
60
Thierry Reding2fff79d32014-04-25 16:42:32 +020061static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
62{
63 return container_of(work, struct tegra_dpaux, work);
64}
65
Thierry Reding8a8005e2015-06-02 13:13:01 +020066static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
Thierry Redinge8ddfdc2017-08-15 15:41:06 +020067 unsigned int offset)
Thierry Reding6b6b6042013-11-15 16:06:05 +010068{
Thierry Redingeba7c452017-08-15 15:41:13 +020069 u32 value = readl(dpaux->regs + (offset << 2));
70
71 trace_dpaux_readl(dpaux->dev, offset, value);
72
73 return value;
Thierry Reding6b6b6042013-11-15 16:06:05 +010074}
75
76static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
Thierry Redinge8ddfdc2017-08-15 15:41:06 +020077 u32 value, unsigned int offset)
Thierry Reding6b6b6042013-11-15 16:06:05 +010078{
Thierry Redingeba7c452017-08-15 15:41:13 +020079 trace_dpaux_writel(dpaux->dev, offset, value);
Thierry Reding6b6b6042013-11-15 16:06:05 +010080 writel(value, dpaux->regs + (offset << 2));
81}
82
83static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
84 size_t size)
85{
Thierry Reding6b6b6042013-11-15 16:06:05 +010086 size_t i, j;
87
Thierry Reding3c1dae02015-06-11 18:33:48 +020088 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
89 size_t num = min_t(size_t, size - i * 4, 4);
Thierry Reding8a8005e2015-06-02 13:13:01 +020090 u32 value = 0;
Thierry Reding6b6b6042013-11-15 16:06:05 +010091
92 for (j = 0; j < num; j++)
Thierry Reding3c1dae02015-06-11 18:33:48 +020093 value |= buffer[i * 4 + j] << (j * 8);
Thierry Reding6b6b6042013-11-15 16:06:05 +010094
Thierry Reding3c1dae02015-06-11 18:33:48 +020095 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
Thierry Reding6b6b6042013-11-15 16:06:05 +010096 }
97}
98
99static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
100 size_t size)
101{
Thierry Reding6b6b6042013-11-15 16:06:05 +0100102 size_t i, j;
103
Thierry Reding3c1dae02015-06-11 18:33:48 +0200104 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
105 size_t num = min_t(size_t, size - i * 4, 4);
Thierry Reding8a8005e2015-06-02 13:13:01 +0200106 u32 value;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100107
Thierry Reding3c1dae02015-06-11 18:33:48 +0200108 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
Thierry Reding6b6b6042013-11-15 16:06:05 +0100109
110 for (j = 0; j < num; j++)
Thierry Reding3c1dae02015-06-11 18:33:48 +0200111 buffer[i * 4 + j] = value >> (j * 8);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100112 }
113}
114
115static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
116 struct drm_dp_aux_msg *msg)
117{
Thierry Reding6b6b6042013-11-15 16:06:05 +0100118 unsigned long timeout = msecs_to_jiffies(250);
119 struct tegra_dpaux *dpaux = to_dpaux(aux);
120 unsigned long status;
121 ssize_t ret = 0;
Thierry Reding1ca20302014-04-07 10:37:44 +0200122 u32 value;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100123
Thierry Reding1ca20302014-04-07 10:37:44 +0200124 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
125 if (msg->size > 16)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100126 return -EINVAL;
127
Thierry Reding1ca20302014-04-07 10:37:44 +0200128 /*
129 * Allow zero-sized messages only for I2C, in which case they specify
130 * address-only transactions.
131 */
132 if (msg->size < 1) {
133 switch (msg->request & ~DP_AUX_I2C_MOT) {
Ville Syrjäläf9934062015-08-27 17:23:29 +0300134 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
Thierry Reding1ca20302014-04-07 10:37:44 +0200135 case DP_AUX_I2C_WRITE:
136 case DP_AUX_I2C_READ:
137 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
138 break;
139
140 default:
141 return -EINVAL;
142 }
143 } else {
144 /* For non-zero-sized messages, set the CMDLEN field. */
145 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
146 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100147
148 switch (msg->request & ~DP_AUX_I2C_MOT) {
149 case DP_AUX_I2C_WRITE:
150 if (msg->request & DP_AUX_I2C_MOT)
Thierry Reding1ca20302014-04-07 10:37:44 +0200151 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100152 else
Thierry Reding1ca20302014-04-07 10:37:44 +0200153 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100154
155 break;
156
157 case DP_AUX_I2C_READ:
158 if (msg->request & DP_AUX_I2C_MOT)
Thierry Reding1ca20302014-04-07 10:37:44 +0200159 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100160 else
Thierry Reding1ca20302014-04-07 10:37:44 +0200161 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100162
163 break;
164
Ville Syrjälä2b712be2015-08-27 17:23:26 +0300165 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
Thierry Reding6b6b6042013-11-15 16:06:05 +0100166 if (msg->request & DP_AUX_I2C_MOT)
Thierry Reding1ca20302014-04-07 10:37:44 +0200167 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100168 else
Thierry Reding1ca20302014-04-07 10:37:44 +0200169 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100170
171 break;
172
173 case DP_AUX_NATIVE_WRITE:
Thierry Reding1ca20302014-04-07 10:37:44 +0200174 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100175 break;
176
177 case DP_AUX_NATIVE_READ:
Thierry Reding1ca20302014-04-07 10:37:44 +0200178 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100179 break;
180
181 default:
182 return -EINVAL;
183 }
184
Thierry Reding1ca20302014-04-07 10:37:44 +0200185 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100186 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
187
188 if ((msg->request & DP_AUX_I2C_READ) == 0) {
189 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
190 ret = msg->size;
191 }
192
193 /* start transaction */
194 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
195 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
197
198 status = wait_for_completion_timeout(&dpaux->complete, timeout);
199 if (!status)
200 return -ETIMEDOUT;
201
202 /* read status and clear errors */
203 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
204 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
205
206 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
207 return -ETIMEDOUT;
208
209 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
210 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
211 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
212 return -EIO;
213
214 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
215 case 0x00:
216 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
217 break;
218
219 case 0x01:
220 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
221 break;
222
223 case 0x02:
224 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
225 break;
226
227 case 0x04:
228 msg->reply = DP_AUX_I2C_REPLY_NACK;
229 break;
230
231 case 0x08:
232 msg->reply = DP_AUX_I2C_REPLY_DEFER;
233 break;
234 }
235
Thierry Reding1ca20302014-04-07 10:37:44 +0200236 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
Thierry Reding6b6b6042013-11-15 16:06:05 +0100237 if (msg->request & DP_AUX_I2C_READ) {
238 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
239
240 if (WARN_ON(count != msg->size))
241 count = min_t(size_t, count, msg->size);
242
243 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
244 ret = count;
245 }
246 }
247
248 return ret;
249}
250
Thierry Reding2fff79d32014-04-25 16:42:32 +0200251static void tegra_dpaux_hotplug(struct work_struct *work)
252{
253 struct tegra_dpaux *dpaux = work_to_dpaux(work);
254
255 if (dpaux->output)
256 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
257}
258
Thierry Reding6b6b6042013-11-15 16:06:05 +0100259static irqreturn_t tegra_dpaux_irq(int irq, void *data)
260{
261 struct tegra_dpaux *dpaux = data;
262 irqreturn_t ret = IRQ_HANDLED;
Thierry Reding8a8005e2015-06-02 13:13:01 +0200263 u32 value;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100264
265 /* clear interrupts */
266 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
267 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
268
Thierry Reding2fff79d32014-04-25 16:42:32 +0200269 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
270 schedule_work(&dpaux->work);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100271
272 if (value & DPAUX_INTR_IRQ_EVENT) {
273 /* TODO: handle this */
274 }
275
276 if (value & DPAUX_INTR_AUX_DONE)
277 complete(&dpaux->complete);
278
279 return ret;
280}
281
Jon Hunter0751bb52016-06-29 10:17:55 +0100282enum tegra_dpaux_functions {
283 DPAUX_PADCTL_FUNC_AUX,
284 DPAUX_PADCTL_FUNC_I2C,
285 DPAUX_PADCTL_FUNC_OFF,
286};
287
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100288static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
289{
290 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
291
292 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
293
294 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
295}
296
297static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
298{
299 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
300
301 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
302
303 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
304}
305
306static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
307{
308 u32 value;
309
310 switch (function) {
Jon Hunter0751bb52016-06-29 10:17:55 +0100311 case DPAUX_PADCTL_FUNC_AUX:
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100312 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
313 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
314 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
315 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
316 DPAUX_HYBRID_PADCTL_MODE_AUX;
317 break;
318
Jon Hunter0751bb52016-06-29 10:17:55 +0100319 case DPAUX_PADCTL_FUNC_I2C:
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100320 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
321 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
Thierry Reding72ba4cf52017-12-14 13:25:37 +0100322 DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
323 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
324 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100325 DPAUX_HYBRID_PADCTL_MODE_I2C;
326 break;
327
Jon Hunter0751bb52016-06-29 10:17:55 +0100328 case DPAUX_PADCTL_FUNC_OFF:
329 tegra_dpaux_pad_power_down(dpaux);
330 return 0;
331
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100332 default:
333 return -ENOTSUPP;
334 }
335
336 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
337 tegra_dpaux_pad_power_up(dpaux);
338
339 return 0;
340}
341
Jon Hunter0751bb52016-06-29 10:17:55 +0100342#ifdef CONFIG_GENERIC_PINCONF
343static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
344 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
345 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
346};
347
348static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
349
350static const char * const tegra_dpaux_groups[] = {
351 "dpaux-io",
352};
353
354static const char * const tegra_dpaux_functions[] = {
355 "aux",
356 "i2c",
357 "off",
358};
359
360static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
361{
362 return ARRAY_SIZE(tegra_dpaux_groups);
363}
364
365static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
366 unsigned int group)
367{
368 return tegra_dpaux_groups[group];
369}
370
371static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
372 unsigned group, const unsigned **pins,
373 unsigned *num_pins)
374{
375 *pins = tegra_dpaux_pin_numbers;
376 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
377
378 return 0;
379}
380
381static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
382 .get_groups_count = tegra_dpaux_get_groups_count,
383 .get_group_name = tegra_dpaux_get_group_name,
384 .get_group_pins = tegra_dpaux_get_group_pins,
385 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
386 .dt_free_map = pinconf_generic_dt_free_map,
387};
388
389static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
390{
391 return ARRAY_SIZE(tegra_dpaux_functions);
392}
393
394static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
395 unsigned int function)
396{
397 return tegra_dpaux_functions[function];
398}
399
400static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
401 unsigned int function,
402 const char * const **groups,
403 unsigned * const num_groups)
404{
405 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
406 *groups = tegra_dpaux_groups;
407
408 return 0;
409}
410
411static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
412 unsigned int function, unsigned int group)
413{
414 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
415
416 return tegra_dpaux_pad_config(dpaux, function);
417}
418
419static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
420 .get_functions_count = tegra_dpaux_get_functions_count,
421 .get_function_name = tegra_dpaux_get_function_name,
422 .get_function_groups = tegra_dpaux_get_function_groups,
423 .set_mux = tegra_dpaux_set_mux,
424};
425#endif
426
Thierry Reding6b6b6042013-11-15 16:06:05 +0100427static int tegra_dpaux_probe(struct platform_device *pdev)
428{
429 struct tegra_dpaux *dpaux;
430 struct resource *regs;
Thierry Reding8a8005e2015-06-02 13:13:01 +0200431 u32 value;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100432 int err;
433
434 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
435 if (!dpaux)
436 return -ENOMEM;
437
Thierry Reding2fff79d32014-04-25 16:42:32 +0200438 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100439 init_completion(&dpaux->complete);
440 INIT_LIST_HEAD(&dpaux->list);
441 dpaux->dev = &pdev->dev;
442
443 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
445 if (IS_ERR(dpaux->regs))
446 return PTR_ERR(dpaux->regs);
447
448 dpaux->irq = platform_get_irq(pdev, 0);
449 if (dpaux->irq < 0) {
450 dev_err(&pdev->dev, "failed to get IRQ\n");
451 return -ENXIO;
452 }
453
Jon Hunter9b990442016-06-29 10:17:51 +0100454 if (!pdev->dev.pm_domain) {
455 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
456 if (IS_ERR(dpaux->rst)) {
457 dev_err(&pdev->dev,
458 "failed to get reset control: %ld\n",
459 PTR_ERR(dpaux->rst));
460 return PTR_ERR(dpaux->rst);
461 }
Thierry Reding08f580e2015-04-27 14:50:30 +0200462 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100463
464 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
Thierry Reding08f580e2015-04-27 14:50:30 +0200465 if (IS_ERR(dpaux->clk)) {
466 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
467 PTR_ERR(dpaux->clk));
Thierry Reding6b6b6042013-11-15 16:06:05 +0100468 return PTR_ERR(dpaux->clk);
Thierry Reding08f580e2015-04-27 14:50:30 +0200469 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100470
Thierry Reding6b6b6042013-11-15 16:06:05 +0100471 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
Thierry Reding08f580e2015-04-27 14:50:30 +0200472 if (IS_ERR(dpaux->clk_parent)) {
473 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
474 PTR_ERR(dpaux->clk_parent));
Thierry Reding82b81b32017-10-12 17:32:52 +0200475 return PTR_ERR(dpaux->clk_parent);
Thierry Reding08f580e2015-04-27 14:50:30 +0200476 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100477
478 err = clk_set_rate(dpaux->clk_parent, 270000000);
479 if (err < 0) {
480 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
481 err);
Thierry Reding82b81b32017-10-12 17:32:52 +0200482 return err;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100483 }
484
485 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
Thierry Reding08f580e2015-04-27 14:50:30 +0200486 if (IS_ERR(dpaux->vdd)) {
487 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
488 PTR_ERR(dpaux->vdd));
Thierry Reding82b81b32017-10-12 17:32:52 +0200489 return PTR_ERR(dpaux->vdd);
Thierry Reding08f580e2015-04-27 14:50:30 +0200490 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100491
Thierry Reding82b81b32017-10-12 17:32:52 +0200492 platform_set_drvdata(pdev, dpaux);
493 pm_runtime_enable(&pdev->dev);
494 pm_runtime_get_sync(&pdev->dev);
495
Thierry Reding6b6b6042013-11-15 16:06:05 +0100496 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
497 dev_name(dpaux->dev), dpaux);
498 if (err < 0) {
499 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
500 dpaux->irq, err);
Thierry Reding82b81b32017-10-12 17:32:52 +0200501 return err;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100502 }
503
Thierry Reding9e532b32015-07-03 14:56:46 +0200504 disable_irq(dpaux->irq);
505
Thierry Reding6b6b6042013-11-15 16:06:05 +0100506 dpaux->aux.transfer = tegra_dpaux_transfer;
507 dpaux->aux.dev = &pdev->dev;
508
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000509 err = drm_dp_aux_register(&dpaux->aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100510 if (err < 0)
Thierry Reding82b81b32017-10-12 17:32:52 +0200511 return err;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100512
Thierry Reding32271662015-04-27 15:16:26 +0200513 /*
514 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
515 * so power them up and configure them in I2C mode.
516 *
517 * The DPAUX code paths reconfigure the pads in AUX mode, but there
518 * is no possibility to perform the I2C mode configuration in the
519 * HDMI path.
520 */
Dmitry Osipenko47022002018-09-21 14:42:41 +0300521 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100522 if (err < 0)
523 return err;
Thierry Reding32271662015-04-27 15:16:26 +0200524
Jon Hunter0751bb52016-06-29 10:17:55 +0100525#ifdef CONFIG_GENERIC_PINCONF
526 dpaux->desc.name = dev_name(&pdev->dev);
527 dpaux->desc.pins = tegra_dpaux_pins;
528 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
529 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
530 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
531 dpaux->desc.owner = THIS_MODULE;
532
533 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
Christophe Jaillet9376cad2016-10-28 11:09:45 +0200534 if (IS_ERR(dpaux->pinctrl)) {
Jon Hunter0751bb52016-06-29 10:17:55 +0100535 dev_err(&pdev->dev, "failed to register pincontrol\n");
Christophe Jaillet9376cad2016-10-28 11:09:45 +0200536 return PTR_ERR(dpaux->pinctrl);
Jon Hunter0751bb52016-06-29 10:17:55 +0100537 }
538#endif
Thierry Reding6b6b6042013-11-15 16:06:05 +0100539 /* enable and clear all interrupts */
540 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
541 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
542 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
543 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
544
545 mutex_lock(&dpaux_lock);
546 list_add_tail(&dpaux->list, &dpaux_list);
547 mutex_unlock(&dpaux_lock);
548
Thierry Reding6b6b6042013-11-15 16:06:05 +0100549 return 0;
550}
551
552static int tegra_dpaux_remove(struct platform_device *pdev)
553{
554 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
Thierry Reding32271662015-04-27 15:16:26 +0200555
Thierry Reding82b81b32017-10-12 17:32:52 +0200556 cancel_work_sync(&dpaux->work);
557
Thierry Reding32271662015-04-27 15:16:26 +0200558 /* make sure pads are powered down when not in use */
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100559 tegra_dpaux_pad_power_down(dpaux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100560
Thierry Reding82b81b32017-10-12 17:32:52 +0200561 pm_runtime_put(&pdev->dev);
562 pm_runtime_disable(&pdev->dev);
563
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000564 drm_dp_aux_unregister(&dpaux->aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100565
566 mutex_lock(&dpaux_lock);
567 list_del(&dpaux->list);
568 mutex_unlock(&dpaux_lock);
569
Thierry Reding6b6b6042013-11-15 16:06:05 +0100570 return 0;
571}
572
Thierry Reding82b81b32017-10-12 17:32:52 +0200573#ifdef CONFIG_PM
574static int tegra_dpaux_suspend(struct device *dev)
575{
576 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
577 int err = 0;
578
579 if (dpaux->rst) {
580 err = reset_control_assert(dpaux->rst);
581 if (err < 0) {
582 dev_err(dev, "failed to assert reset: %d\n", err);
583 return err;
584 }
585 }
586
587 usleep_range(1000, 2000);
588
589 clk_disable_unprepare(dpaux->clk_parent);
590 clk_disable_unprepare(dpaux->clk);
591
592 return err;
593}
594
595static int tegra_dpaux_resume(struct device *dev)
596{
597 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
598 int err;
599
600 err = clk_prepare_enable(dpaux->clk);
601 if (err < 0) {
602 dev_err(dev, "failed to enable clock: %d\n", err);
603 return err;
604 }
605
606 err = clk_prepare_enable(dpaux->clk_parent);
607 if (err < 0) {
608 dev_err(dev, "failed to enable parent clock: %d\n", err);
609 goto disable_clk;
610 }
611
612 usleep_range(1000, 2000);
613
614 if (dpaux->rst) {
615 err = reset_control_deassert(dpaux->rst);
616 if (err < 0) {
617 dev_err(dev, "failed to deassert reset: %d\n", err);
618 goto disable_parent;
619 }
620
621 usleep_range(1000, 2000);
622 }
623
624 return 0;
625
626disable_parent:
627 clk_disable_unprepare(dpaux->clk_parent);
628disable_clk:
629 clk_disable_unprepare(dpaux->clk);
630 return err;
631}
632#endif
633
634static const struct dev_pm_ops tegra_dpaux_pm_ops = {
635 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
636};
637
Thierry Reding6b6b6042013-11-15 16:06:05 +0100638static const struct of_device_id tegra_dpaux_of_match[] = {
Thierry Reding30f11cf2018-09-21 12:27:45 +0200639 { .compatible = "nvidia,tegra194-dpaux", },
Thierry Reding7b2c2842017-10-12 17:34:11 +0200640 { .compatible = "nvidia,tegra186-dpaux", },
Thierry Reding32271662015-04-27 15:16:26 +0200641 { .compatible = "nvidia,tegra210-dpaux", },
Thierry Reding6b6b6042013-11-15 16:06:05 +0100642 { .compatible = "nvidia,tegra124-dpaux", },
643 { },
644};
Stephen Warrenef707282014-06-18 16:21:55 -0600645MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100646
647struct platform_driver tegra_dpaux_driver = {
648 .driver = {
649 .name = "tegra-dpaux",
650 .of_match_table = tegra_dpaux_of_match,
Thierry Reding82b81b32017-10-12 17:32:52 +0200651 .pm = &tegra_dpaux_pm_ops,
Thierry Reding6b6b6042013-11-15 16:06:05 +0100652 },
653 .probe = tegra_dpaux_probe,
654 .remove = tegra_dpaux_remove,
655};
656
Thierry Reding9542c232015-07-08 13:39:09 +0200657struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100658{
659 struct tegra_dpaux *dpaux;
660
661 mutex_lock(&dpaux_lock);
662
663 list_for_each_entry(dpaux, &dpaux_list, list)
664 if (np == dpaux->dev->of_node) {
665 mutex_unlock(&dpaux_lock);
Thierry Reding9542c232015-07-08 13:39:09 +0200666 return &dpaux->aux;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100667 }
668
669 mutex_unlock(&dpaux_lock);
670
671 return NULL;
672}
673
Thierry Reding9542c232015-07-08 13:39:09 +0200674int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100675{
Thierry Reding9542c232015-07-08 13:39:09 +0200676 struct tegra_dpaux *dpaux = to_dpaux(aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100677 unsigned long timeout;
678 int err;
679
Thierry Reding7c463382014-04-25 16:44:48 +0200680 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100681 dpaux->output = output;
682
683 err = regulator_enable(dpaux->vdd);
684 if (err < 0)
685 return err;
686
687 timeout = jiffies + msecs_to_jiffies(250);
688
689 while (time_before(jiffies, timeout)) {
690 enum drm_connector_status status;
691
Thierry Reding9542c232015-07-08 13:39:09 +0200692 status = drm_dp_aux_detect(aux);
Thierry Reding9e532b32015-07-03 14:56:46 +0200693 if (status == connector_status_connected) {
694 enable_irq(dpaux->irq);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100695 return 0;
Thierry Reding9e532b32015-07-03 14:56:46 +0200696 }
Thierry Reding6b6b6042013-11-15 16:06:05 +0100697
698 usleep_range(1000, 2000);
699 }
700
701 return -ETIMEDOUT;
702}
703
Thierry Reding9542c232015-07-08 13:39:09 +0200704int drm_dp_aux_detach(struct drm_dp_aux *aux)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100705{
Thierry Reding9542c232015-07-08 13:39:09 +0200706 struct tegra_dpaux *dpaux = to_dpaux(aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100707 unsigned long timeout;
708 int err;
709
Thierry Reding9e532b32015-07-03 14:56:46 +0200710 disable_irq(dpaux->irq);
711
Thierry Reding6b6b6042013-11-15 16:06:05 +0100712 err = regulator_disable(dpaux->vdd);
713 if (err < 0)
714 return err;
715
716 timeout = jiffies + msecs_to_jiffies(250);
717
718 while (time_before(jiffies, timeout)) {
719 enum drm_connector_status status;
720
Thierry Reding9542c232015-07-08 13:39:09 +0200721 status = drm_dp_aux_detect(aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100722 if (status == connector_status_disconnected) {
723 dpaux->output = NULL;
724 return 0;
725 }
726
727 usleep_range(1000, 2000);
728 }
729
730 return -ETIMEDOUT;
731}
732
Thierry Reding9542c232015-07-08 13:39:09 +0200733enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100734{
Thierry Reding9542c232015-07-08 13:39:09 +0200735 struct tegra_dpaux *dpaux = to_dpaux(aux);
Thierry Reding8a8005e2015-06-02 13:13:01 +0200736 u32 value;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100737
738 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
739
740 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
741 return connector_status_connected;
742
743 return connector_status_disconnected;
744}
745
Thierry Reding9542c232015-07-08 13:39:09 +0200746int drm_dp_aux_enable(struct drm_dp_aux *aux)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100747{
Thierry Reding9542c232015-07-08 13:39:09 +0200748 struct tegra_dpaux *dpaux = to_dpaux(aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100749
Jon Hunter0751bb52016-06-29 10:17:55 +0100750 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100751}
752
Thierry Reding9542c232015-07-08 13:39:09 +0200753int drm_dp_aux_disable(struct drm_dp_aux *aux)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100754{
Thierry Reding9542c232015-07-08 13:39:09 +0200755 struct tegra_dpaux *dpaux = to_dpaux(aux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100756
Jon Hunter9d0e09c2016-06-29 10:17:49 +0100757 tegra_dpaux_pad_power_down(dpaux);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100758
759 return 0;
760}
761
Thierry Reding9542c232015-07-08 13:39:09 +0200762int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100763{
764 int err;
765
Thierry Reding9542c232015-07-08 13:39:09 +0200766 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
Thierry Reding6b6b6042013-11-15 16:06:05 +0100767 encoding);
768 if (err < 0)
769 return err;
770
771 return 0;
772}
773
Thierry Reding9542c232015-07-08 13:39:09 +0200774int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
775 u8 pattern)
Thierry Reding6b6b6042013-11-15 16:06:05 +0100776{
777 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
778 u8 status[DP_LINK_STATUS_SIZE], values[4];
779 unsigned int i;
780 int err;
781
Thierry Reding9542c232015-07-08 13:39:09 +0200782 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100783 if (err < 0)
784 return err;
785
786 if (tp == DP_TRAINING_PATTERN_DISABLE)
787 return 0;
788
789 for (i = 0; i < link->num_lanes; i++)
790 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
Sonika Jindaleeb82a52014-08-08 16:23:45 +0530791 DP_TRAIN_PRE_EMPH_LEVEL_0 |
Thierry Reding6b6b6042013-11-15 16:06:05 +0100792 DP_TRAIN_MAX_SWING_REACHED |
Sonika Jindaleeb82a52014-08-08 16:23:45 +0530793 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100794
Thierry Reding9542c232015-07-08 13:39:09 +0200795 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
Thierry Reding6b6b6042013-11-15 16:06:05 +0100796 link->num_lanes);
797 if (err < 0)
798 return err;
799
800 usleep_range(500, 1000);
801
Thierry Reding9542c232015-07-08 13:39:09 +0200802 err = drm_dp_dpcd_read_link_status(aux, status);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100803 if (err < 0)
804 return err;
805
806 switch (tp) {
807 case DP_TRAINING_PATTERN_1:
808 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
809 return -EAGAIN;
810
811 break;
812
813 case DP_TRAINING_PATTERN_2:
814 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
815 return -EAGAIN;
816
817 break;
818
819 default:
Thierry Reding9542c232015-07-08 13:39:09 +0200820 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100821 return -EINVAL;
822 }
823
Thierry Reding9542c232015-07-08 13:39:09 +0200824 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
Thierry Reding6b6b6042013-11-15 16:06:05 +0100825 if (err < 0)
826 return err;
827
828 return 0;
829}