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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Shenwei Wange324c4d2015-08-24 14:04:15 -05002/*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
Shenwei Wange324c4d2015-08-24 14:04:15 -05004 */
5
6#include <linux/of_address.h>
7#include <linux/of_irq.h>
8#include <linux/slab.h>
9#include <linux/irqchip.h>
10#include <linux/syscore_ops.h>
11
12#define IMR_NUM 4
13#define GPC_MAX_IRQS (IMR_NUM * 32)
14
15#define GPC_IMR1_CORE0 0x30
16#define GPC_IMR1_CORE1 0x40
Andrey Smirnoved01edc2018-12-05 23:31:25 -080017#define GPC_IMR1_CORE2 0x1c0
18#define GPC_IMR1_CORE3 0x1d0
19
Shenwei Wange324c4d2015-08-24 14:04:15 -050020
21struct gpcv2_irqchip_data {
22 struct raw_spinlock rlock;
23 void __iomem *gpc_base;
24 u32 wakeup_sources[IMR_NUM];
25 u32 saved_irq_mask[IMR_NUM];
26 u32 cpu2wakeup;
27};
28
29static struct gpcv2_irqchip_data *imx_gpcv2_instance;
30
Andrey Smirnovbd654fb2018-12-05 23:31:22 -080031static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
32{
33 return cd->gpc_base + cd->cpu2wakeup + i * 4;
34}
35
Shenwei Wange324c4d2015-08-24 14:04:15 -050036static int gpcv2_wakeup_source_save(void)
37{
38 struct gpcv2_irqchip_data *cd;
39 void __iomem *reg;
40 int i;
41
42 cd = imx_gpcv2_instance;
43 if (!cd)
44 return 0;
45
46 for (i = 0; i < IMR_NUM; i++) {
Andrey Smirnovbd654fb2018-12-05 23:31:22 -080047 reg = gpcv2_idx_to_reg(cd, i);
Shenwei Wange324c4d2015-08-24 14:04:15 -050048 cd->saved_irq_mask[i] = readl_relaxed(reg);
49 writel_relaxed(cd->wakeup_sources[i], reg);
50 }
51
52 return 0;
53}
54
55static void gpcv2_wakeup_source_restore(void)
56{
57 struct gpcv2_irqchip_data *cd;
Shenwei Wange324c4d2015-08-24 14:04:15 -050058 int i;
59
60 cd = imx_gpcv2_instance;
61 if (!cd)
62 return;
63
Andrey Smirnovbd654fb2018-12-05 23:31:22 -080064 for (i = 0; i < IMR_NUM; i++)
65 writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
Shenwei Wange324c4d2015-08-24 14:04:15 -050066}
67
68static struct syscore_ops imx_gpcv2_syscore_ops = {
69 .suspend = gpcv2_wakeup_source_save,
70 .resume = gpcv2_wakeup_source_restore,
71};
72
73static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
74{
75 struct gpcv2_irqchip_data *cd = d->chip_data;
76 unsigned int idx = d->hwirq / 32;
77 unsigned long flags;
Shenwei Wange324c4d2015-08-24 14:04:15 -050078 u32 mask, val;
79
80 raw_spin_lock_irqsave(&cd->rlock, flags);
Andrey Smirnovf2dace52018-12-05 23:31:23 -080081 mask = BIT(d->hwirq % 32);
Shenwei Wange324c4d2015-08-24 14:04:15 -050082 val = cd->wakeup_sources[idx];
83
84 cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
85 raw_spin_unlock_irqrestore(&cd->rlock, flags);
86
87 /*
88 * Do *not* call into the parent, as the GIC doesn't have any
89 * wake-up facility...
90 */
91
92 return 0;
93}
94
95static void imx_gpcv2_irq_unmask(struct irq_data *d)
96{
97 struct gpcv2_irqchip_data *cd = d->chip_data;
98 void __iomem *reg;
99 u32 val;
100
101 raw_spin_lock(&cd->rlock);
Andrey Smirnovbd654fb2018-12-05 23:31:22 -0800102 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500103 val = readl_relaxed(reg);
Andrey Smirnovf2dace52018-12-05 23:31:23 -0800104 val &= ~BIT(d->hwirq % 32);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500105 writel_relaxed(val, reg);
106 raw_spin_unlock(&cd->rlock);
107
108 irq_chip_unmask_parent(d);
109}
110
111static void imx_gpcv2_irq_mask(struct irq_data *d)
112{
113 struct gpcv2_irqchip_data *cd = d->chip_data;
114 void __iomem *reg;
115 u32 val;
116
117 raw_spin_lock(&cd->rlock);
Andrey Smirnovbd654fb2018-12-05 23:31:22 -0800118 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500119 val = readl_relaxed(reg);
Andrey Smirnovf2dace52018-12-05 23:31:23 -0800120 val |= BIT(d->hwirq % 32);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500121 writel_relaxed(val, reg);
122 raw_spin_unlock(&cd->rlock);
123
124 irq_chip_mask_parent(d);
125}
126
127static struct irq_chip gpcv2_irqchip_data_chip = {
128 .name = "GPCv2",
129 .irq_eoi = irq_chip_eoi_parent,
130 .irq_mask = imx_gpcv2_irq_mask,
131 .irq_unmask = imx_gpcv2_irq_unmask,
132 .irq_set_wake = imx_gpcv2_irq_set_wake,
133 .irq_retrigger = irq_chip_retrigger_hierarchy,
134#ifdef CONFIG_SMP
135 .irq_set_affinity = irq_chip_set_affinity_parent,
136#endif
137};
138
Marc Zyngierf833f572015-10-13 12:51:33 +0100139static int imx_gpcv2_domain_translate(struct irq_domain *d,
140 struct irq_fwspec *fwspec,
141 unsigned long *hwirq,
142 unsigned int *type)
Shenwei Wange324c4d2015-08-24 14:04:15 -0500143{
Marc Zyngierf833f572015-10-13 12:51:33 +0100144 if (is_of_node(fwspec->fwnode)) {
145 if (fwspec->param_count != 3)
146 return -EINVAL;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500147
Marc Zyngierf833f572015-10-13 12:51:33 +0100148 /* No PPI should point to this domain */
149 if (fwspec->param[0] != 0)
150 return -EINVAL;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500151
Marc Zyngierf833f572015-10-13 12:51:33 +0100152 *hwirq = fwspec->param[1];
153 *type = fwspec->param[2];
154 return 0;
155 }
Shenwei Wange324c4d2015-08-24 14:04:15 -0500156
Marc Zyngierf833f572015-10-13 12:51:33 +0100157 return -EINVAL;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500158}
159
160static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
161 unsigned int irq, unsigned int nr_irqs,
162 void *data)
163{
Marc Zyngierf833f572015-10-13 12:51:33 +0100164 struct irq_fwspec *fwspec = data;
165 struct irq_fwspec parent_fwspec;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500166 irq_hw_number_t hwirq;
Marc Zyngierf833f572015-10-13 12:51:33 +0100167 unsigned int type;
168 int err;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500169 int i;
170
Marc Zyngierf833f572015-10-13 12:51:33 +0100171 err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
172 if (err)
173 return err;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500174
Shenwei Wange324c4d2015-08-24 14:04:15 -0500175 if (hwirq >= GPC_MAX_IRQS)
176 return -EINVAL;
177
178 for (i = 0; i < nr_irqs; i++) {
179 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
180 &gpcv2_irqchip_data_chip, domain->host_data);
181 }
182
Marc Zyngierf833f572015-10-13 12:51:33 +0100183 parent_fwspec = *fwspec;
184 parent_fwspec.fwnode = domain->parent->fwnode;
185 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
186 &parent_fwspec);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500187}
188
Tobias Klauserdcbbefc2017-06-02 10:20:54 +0200189static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +0100190 .translate = imx_gpcv2_domain_translate,
191 .alloc = imx_gpcv2_domain_alloc,
192 .free = irq_domain_free_irqs_common,
Shenwei Wange324c4d2015-08-24 14:04:15 -0500193};
194
Andrey Smirnoved01edc2018-12-05 23:31:25 -0800195static const struct of_device_id gpcv2_of_match[] = {
196 { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
197 { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
198 { /* END */ }
199};
200
Shenwei Wange324c4d2015-08-24 14:04:15 -0500201static int __init imx_gpcv2_irqchip_init(struct device_node *node,
202 struct device_node *parent)
203{
204 struct irq_domain *parent_domain, *domain;
205 struct gpcv2_irqchip_data *cd;
Andrey Smirnoved01edc2018-12-05 23:31:25 -0800206 const struct of_device_id *id;
207 unsigned long core_num;
Shenwei Wange324c4d2015-08-24 14:04:15 -0500208 int i;
209
210 if (!parent) {
Rob Herringe81f54c2017-07-18 16:43:10 -0500211 pr_err("%pOF: no parent, giving up\n", node);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500212 return -ENODEV;
213 }
214
Andrey Smirnoved01edc2018-12-05 23:31:25 -0800215 id = of_match_node(gpcv2_of_match, node);
216 if (!id) {
217 pr_err("%pOF: unknown compatibility string\n", node);
218 return -ENODEV;
219 }
220
221 core_num = (unsigned long)id->data;
222
Shenwei Wange324c4d2015-08-24 14:04:15 -0500223 parent_domain = irq_find_host(parent);
224 if (!parent_domain) {
Rob Herringe81f54c2017-07-18 16:43:10 -0500225 pr_err("%pOF: unable to get parent domain\n", node);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500226 return -ENXIO;
227 }
228
229 cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
230 if (!cd) {
Andrey Smirnovfb7348a2018-12-05 23:31:24 -0800231 pr_err("%pOF: kzalloc failed!\n", node);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500232 return -ENOMEM;
233 }
234
Tyler Baker75eb5e12017-04-13 15:27:31 -0700235 raw_spin_lock_init(&cd->rlock);
236
Shenwei Wange324c4d2015-08-24 14:04:15 -0500237 cd->gpc_base = of_iomap(node, 0);
238 if (!cd->gpc_base) {
Andrey Smirnovfb7348a2018-12-05 23:31:24 -0800239 pr_err("%pOF: unable to map gpc registers\n", node);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500240 kfree(cd);
241 return -ENOMEM;
242 }
243
244 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
245 node, &gpcv2_irqchip_data_domain_ops, cd);
246 if (!domain) {
247 iounmap(cd->gpc_base);
248 kfree(cd);
249 return -ENOMEM;
250 }
251 irq_set_default_host(domain);
252
253 /* Initially mask all interrupts */
254 for (i = 0; i < IMR_NUM; i++) {
Andrey Smirnoved01edc2018-12-05 23:31:25 -0800255 void __iomem *reg = cd->gpc_base + i * 4;
256
257 switch (core_num) {
258 case 4:
259 writel_relaxed(~0, reg + GPC_IMR1_CORE2);
260 writel_relaxed(~0, reg + GPC_IMR1_CORE3);
Marc Zyngier893b0af2018-12-15 09:10:46 +0000261 /* fall through */
262 case 2:
Andrey Smirnoved01edc2018-12-05 23:31:25 -0800263 writel_relaxed(~0, reg + GPC_IMR1_CORE0);
264 writel_relaxed(~0, reg + GPC_IMR1_CORE1);
265 }
Shenwei Wange324c4d2015-08-24 14:04:15 -0500266 cd->wakeup_sources[i] = ~0;
267 }
268
269 /* Let CORE0 as the default CPU to wake up by GPC */
270 cd->cpu2wakeup = GPC_IMR1_CORE0;
271
272 /*
273 * Due to hardware design failure, need to make sure GPR
274 * interrupt(#32) is unmasked during RUN mode to avoid entering
275 * DSM by mistake.
276 */
277 writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
278
279 imx_gpcv2_instance = cd;
280 register_syscore_ops(&imx_gpcv2_syscore_ops);
281
Andrey Smirnov9d4b5bd2017-04-11 09:48:09 -0700282 /*
283 * Clear the OF_POPULATED flag set in of_irq_init so that
284 * later the GPC power domain driver will not be skipped.
285 */
286 of_node_clear_flag(node, OF_POPULATED);
Shenwei Wange324c4d2015-08-24 14:04:15 -0500287 return 0;
288}
289
Lucas Stach8ca66b72018-12-14 13:15:28 +0100290IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
291IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);