blob: dc067ed0b72d4c0bbf22b3af9a872100c50855a9 [file] [log] [blame]
Oded Gabbayb7facba2014-07-16 15:55:29 +03001/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef KFD_IOCTL_H_INCLUDED
24#define KFD_IOCTL_H_INCLUDED
25
Mikko Rapeli472b46c2017-08-06 18:44:27 +020026#include <drm/drm.h>
Oded Gabbayb7facba2014-07-16 15:55:29 +030027#include <linux/ioctl.h>
28
29#define KFD_IOCTL_MAJOR_VERSION 1
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +020030#define KFD_IOCTL_MINOR_VERSION 1
Oded Gabbayb7facba2014-07-16 15:55:29 +030031
32struct kfd_ioctl_get_version_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +020033 __u32 major_version; /* from KFD */
34 __u32 minor_version; /* from KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030035};
36
37/* For kfd_ioctl_create_queue_args.queue_type. */
38#define KFD_IOC_QUEUE_TYPE_COMPUTE 0
39#define KFD_IOC_QUEUE_TYPE_SDMA 1
40#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
41
42#define KFD_MAX_QUEUE_PERCENTAGE 100
43#define KFD_MAX_QUEUE_PRIORITY 15
44
45struct kfd_ioctl_create_queue_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +020046 __u64 ring_base_address; /* to KFD */
47 __u64 write_pointer_address; /* from KFD */
48 __u64 read_pointer_address; /* from KFD */
49 __u64 doorbell_offset; /* from KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030050
Mikko Rapeli472b46c2017-08-06 18:44:27 +020051 __u32 ring_size; /* to KFD */
52 __u32 gpu_id; /* to KFD */
53 __u32 queue_type; /* to KFD */
54 __u32 queue_percentage; /* to KFD */
55 __u32 queue_priority; /* to KFD */
56 __u32 queue_id; /* from KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030057
Mikko Rapeli472b46c2017-08-06 18:44:27 +020058 __u64 eop_buffer_address; /* to KFD */
59 __u64 eop_buffer_size; /* to KFD */
60 __u64 ctx_save_restore_address; /* to KFD */
Felix Kuehling373d7082017-11-14 16:41:19 -050061 __u32 ctx_save_restore_size; /* to KFD */
62 __u32 ctl_stack_size; /* to KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030063};
64
65struct kfd_ioctl_destroy_queue_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +020066 __u32 queue_id; /* to KFD */
67 __u32 pad;
Oded Gabbayb7facba2014-07-16 15:55:29 +030068};
69
70struct kfd_ioctl_update_queue_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +020071 __u64 ring_base_address; /* to KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030072
Mikko Rapeli472b46c2017-08-06 18:44:27 +020073 __u32 queue_id; /* to KFD */
74 __u32 ring_size; /* to KFD */
75 __u32 queue_percentage; /* to KFD */
76 __u32 queue_priority; /* to KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +030077};
78
Felix Kuehlinga7fe68a2018-07-14 19:05:58 -040079struct kfd_ioctl_set_cu_mask_args {
80 __u32 queue_id; /* to KFD */
81 __u32 num_cu_mask; /* to KFD */
82 __u64 cu_mask_ptr; /* to KFD */
83};
84
Jay Cornwall5df099e2017-05-02 17:39:37 -050085struct kfd_ioctl_get_queue_wave_state_args {
Dmitry V. Levin8e7f9172018-11-01 14:03:28 +030086 __u64 ctl_stack_address; /* to KFD */
87 __u32 ctl_stack_used_size; /* from KFD */
88 __u32 save_area_used_size; /* from KFD */
89 __u32 queue_id; /* to KFD */
90 __u32 pad;
Jay Cornwall5df099e2017-05-02 17:39:37 -050091};
92
Oded Gabbayb7facba2014-07-16 15:55:29 +030093/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
94#define KFD_IOC_CACHE_POLICY_COHERENT 0
95#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
96
97struct kfd_ioctl_set_memory_policy_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +020098 __u64 alternate_aperture_base; /* to KFD */
99 __u64 alternate_aperture_size; /* to KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +0300100
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200101 __u32 gpu_id; /* to KFD */
102 __u32 default_policy; /* to KFD */
103 __u32 alternate_policy; /* to KFD */
104 __u32 pad;
Oded Gabbayb7facba2014-07-16 15:55:29 +0300105};
106
107/*
108 * All counters are monotonic. They are used for profiling of compute jobs.
109 * The profiling is done by userspace.
110 *
111 * In case of GPU reset, the counter should not be affected.
112 */
113
114struct kfd_ioctl_get_clock_counters_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200115 __u64 gpu_clock_counter; /* from KFD */
116 __u64 cpu_clock_counter; /* from KFD */
117 __u64 system_clock_counter; /* from KFD */
118 __u64 system_clock_freq; /* from KFD */
Oded Gabbayb7facba2014-07-16 15:55:29 +0300119
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200120 __u32 gpu_id; /* to KFD */
121 __u32 pad;
Oded Gabbayb7facba2014-07-16 15:55:29 +0300122};
123
Oded Gabbayb7facba2014-07-16 15:55:29 +0300124struct kfd_process_device_apertures {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200125 __u64 lds_base; /* from KFD */
126 __u64 lds_limit; /* from KFD */
127 __u64 scratch_base; /* from KFD */
128 __u64 scratch_limit; /* from KFD */
129 __u64 gpuvm_base; /* from KFD */
130 __u64 gpuvm_limit; /* from KFD */
131 __u32 gpu_id; /* from KFD */
132 __u32 pad;
Oded Gabbayb7facba2014-07-16 15:55:29 +0300133};
134
Felix Kuehlingc7bcbfa2018-03-15 17:27:46 -0400135/*
136 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
137 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
138 * unlimited number of GPUs.
139 */
140#define NUM_OF_SUPPORTED_GPUS 7
Oded Gabbayb7facba2014-07-16 15:55:29 +0300141struct kfd_ioctl_get_process_apertures_args {
142 struct kfd_process_device_apertures
143 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
144
145 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200146 __u32 num_of_nodes;
147 __u32 pad;
Oded Gabbayb7facba2014-07-16 15:55:29 +0300148};
149
Felix Kuehlingc7bcbfa2018-03-15 17:27:46 -0400150struct kfd_ioctl_get_process_apertures_new_args {
151 /* User allocated. Pointer to struct kfd_process_device_apertures
152 * filled in by Kernel
153 */
154 __u64 kfd_process_device_apertures_ptr;
155 /* to KFD - indicates amount of memory present in
156 * kfd_process_device_apertures_ptr
157 * from KFD - Number of entries filled by KFD.
158 */
159 __u32 num_of_nodes;
160 __u32 pad;
161};
162
Yair Shacharaef11002014-12-07 17:05:22 +0200163#define MAX_ALLOWED_NUM_POINTS 100
164#define MAX_ALLOWED_AW_BUFF_SIZE 4096
165#define MAX_ALLOWED_WAC_BUFF_SIZE 128
166
167struct kfd_ioctl_dbg_register_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200168 __u32 gpu_id; /* to KFD */
169 __u32 pad;
Yair Shacharaef11002014-12-07 17:05:22 +0200170};
171
172struct kfd_ioctl_dbg_unregister_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200173 __u32 gpu_id; /* to KFD */
174 __u32 pad;
Yair Shacharaef11002014-12-07 17:05:22 +0200175};
176
177struct kfd_ioctl_dbg_address_watch_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200178 __u64 content_ptr; /* a pointer to the actual content */
179 __u32 gpu_id; /* to KFD */
180 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
Yair Shacharaef11002014-12-07 17:05:22 +0200181};
182
183struct kfd_ioctl_dbg_wave_control_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200184 __u64 content_ptr; /* a pointer to the actual content */
185 __u32 gpu_id; /* to KFD */
186 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
Yair Shacharaef11002014-12-07 17:05:22 +0200187};
188
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200189/* Matching HSA_EVENTTYPE */
190#define KFD_IOC_EVENT_SIGNAL 0
191#define KFD_IOC_EVENT_NODECHANGE 1
192#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
193#define KFD_IOC_EVENT_HW_EXCEPTION 3
194#define KFD_IOC_EVENT_SYSTEM_EVENT 4
195#define KFD_IOC_EVENT_DEBUG_EVENT 5
196#define KFD_IOC_EVENT_PROFILE_EVENT 6
197#define KFD_IOC_EVENT_QUEUE_EVENT 7
198#define KFD_IOC_EVENT_MEMORY 8
199
200#define KFD_IOC_WAIT_RESULT_COMPLETE 0
201#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
202#define KFD_IOC_WAIT_RESULT_FAIL 2
203
Oded Gabbay7e86a3652017-10-27 19:35:30 -0400204#define KFD_SIGNAL_EVENT_LIMIT 4096
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200205
Shaoyun Liu0c119ab2018-07-11 22:32:53 -0400206/* For kfd_event_data.hw_exception_data.reset_type. */
207#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
208#define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
209
210/* For kfd_event_data.hw_exception_data.reset_cause. */
211#define KFD_HW_EXCEPTION_GPU_HANG 0
212#define KFD_HW_EXCEPTION_ECC 1
213
Eric Huang9b54d202019-01-11 14:38:51 -0500214/* For kfd_hsa_memory_exception_data.ErrorType */
215#define KFD_MEM_ERR_NO_RAS 0
216#define KFD_MEM_ERR_SRAM_ECC 1
217#define KFD_MEM_ERR_POISON_CONSUMED 2
218#define KFD_MEM_ERR_GPU_HANG 3
Shaoyun Liu0c119ab2018-07-11 22:32:53 -0400219
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200220struct kfd_ioctl_create_event_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200221 __u64 event_page_offset; /* from KFD */
222 __u32 event_trigger_data; /* from KFD - signal events only */
223 __u32 event_type; /* to KFD */
224 __u32 auto_reset; /* to KFD */
225 __u32 node_id; /* to KFD - only valid for certain
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200226 event types */
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200227 __u32 event_id; /* from KFD */
228 __u32 event_slot_index; /* from KFD */
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200229};
230
231struct kfd_ioctl_destroy_event_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200232 __u32 event_id; /* to KFD */
233 __u32 pad;
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200234};
235
236struct kfd_ioctl_set_event_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200237 __u32 event_id; /* to KFD */
238 __u32 pad;
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200239};
240
241struct kfd_ioctl_reset_event_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200242 __u32 event_id; /* to KFD */
243 __u32 pad;
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200244};
245
246struct kfd_memory_exception_failure {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200247 __u32 NotPresent; /* Page not present or supervisor privilege */
248 __u32 ReadOnly; /* Write access to a read-only page */
249 __u32 NoExecute; /* Execute access to a page marked NX */
shaoyunl2640c3f2018-07-11 22:32:50 -0400250 __u32 imprecise; /* Can't determine the exact fault address */
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200251};
252
253/* memory exception data*/
254struct kfd_hsa_memory_exception_data {
255 struct kfd_memory_exception_failure failure;
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200256 __u64 va;
257 __u32 gpu_id;
Eric Huang9b54d202019-01-11 14:38:51 -0500258 __u32 ErrorType; /* 0 = no RAS error,
259 * 1 = ECC_SRAM,
260 * 2 = Link_SYNFLOOD (poison),
261 * 3 = GPU hang (not attributable to a specific cause),
262 * other values reserved
263 */
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200264};
265
Shaoyun Liu0c119ab2018-07-11 22:32:53 -0400266/* hw exception data */
267struct kfd_hsa_hw_exception_data {
Dmitry V. Levinaba118382018-11-01 14:03:08 +0300268 __u32 reset_type;
269 __u32 reset_cause;
270 __u32 memory_lost;
271 __u32 gpu_id;
Shaoyun Liu0c119ab2018-07-11 22:32:53 -0400272};
273
274/* Event data */
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200275struct kfd_event_data {
276 union {
277 struct kfd_hsa_memory_exception_data memory_exception_data;
Shaoyun Liu0c119ab2018-07-11 22:32:53 -0400278 struct kfd_hsa_hw_exception_data hw_exception_data;
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200279 }; /* From KFD */
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200280 __u64 kfd_event_data_ext; /* pointer to an extension structure
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200281 for future exception types */
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200282 __u32 event_id; /* to KFD */
283 __u32 pad;
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200284};
285
286struct kfd_ioctl_wait_events_args {
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200287 __u64 events_ptr; /* pointed to struct
Yair Shacharaef11002014-12-07 17:05:22 +0200288 kfd_event_data array, to KFD */
Mikko Rapeli472b46c2017-08-06 18:44:27 +0200289 __u32 num_events; /* to KFD */
290 __u32 wait_for_all; /* to KFD */
291 __u32 timeout; /* to KFD */
292 __u32 wait_result; /* from KFD */
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200293};
294
Moses Reuben6a1c9512017-08-15 23:00:20 -0400295struct kfd_ioctl_set_scratch_backing_va_args {
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300296 __u64 va_addr; /* to KFD */
297 __u32 gpu_id; /* to KFD */
298 __u32 pad;
Moses Reuben6a1c9512017-08-15 23:00:20 -0400299};
300
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400301struct kfd_ioctl_get_tile_config_args {
302 /* to KFD: pointer to tile array */
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300303 __u64 tile_config_ptr;
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400304 /* to KFD: pointer to macro tile array */
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300305 __u64 macro_tile_config_ptr;
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400306 /* to KFD: array size allocated by user mode
307 * from KFD: array size filled by kernel
308 */
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300309 __u32 num_tile_configs;
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400310 /* to KFD: array size allocated by user mode
311 * from KFD: array size filled by kernel
312 */
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300313 __u32 num_macro_tile_configs;
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400314
Dmitry V. Levinb4d08522017-11-13 03:35:27 +0300315 __u32 gpu_id; /* to KFD */
316 __u32 gb_addr_config; /* from KFD */
317 __u32 num_banks; /* from KFD */
318 __u32 num_ranks; /* from KFD */
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400319 /* struct size can be extended later if needed
320 * without breaking ABI compatibility
321 */
322};
323
Felix Kuehlingd7b9bd22017-11-14 16:41:20 -0500324struct kfd_ioctl_set_trap_handler_args {
Felix Kuehlinga1102442018-02-06 20:32:46 -0500325 __u64 tba_addr; /* to KFD */
326 __u64 tma_addr; /* to KFD */
327 __u32 gpu_id; /* to KFD */
328 __u32 pad;
Felix Kuehlingd7b9bd22017-11-14 16:41:20 -0500329};
330
Felix Kuehling5ec7e022018-03-15 17:27:51 -0400331struct kfd_ioctl_acquire_vm_args {
332 __u32 drm_fd; /* to KFD */
333 __u32 gpu_id; /* to KFD */
334};
335
336/* Allocation flags: memory types */
337#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
338#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
339#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
340#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
341/* Allocation flags: attributes/access options */
342#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
343#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
344#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
345#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
346#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
347#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
348
349/* Allocate memory for later SVM (shared virtual memory) mapping.
350 *
351 * @va_addr: virtual address of the memory to be allocated
352 * all later mappings on all GPUs will use this address
353 * @size: size in bytes
354 * @handle: buffer handle returned to user mode, used to refer to
355 * this allocation for mapping, unmapping and freeing
356 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
357 * for userptrs this is overloaded to specify the CPU address
358 * @gpu_id: device identifier
359 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
360 */
361struct kfd_ioctl_alloc_memory_of_gpu_args {
362 __u64 va_addr; /* to KFD */
363 __u64 size; /* to KFD */
364 __u64 handle; /* from KFD */
365 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */
366 __u32 gpu_id; /* to KFD */
367 __u32 flags;
368};
369
370/* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
371 *
372 * @handle: memory handle returned by alloc
373 */
374struct kfd_ioctl_free_memory_of_gpu_args {
375 __u64 handle; /* to KFD */
376};
377
378/* Map memory to one or more GPUs
379 *
380 * @handle: memory handle returned by alloc
381 * @device_ids_array_ptr: array of gpu_ids (__u32 per device)
382 * @n_devices: number of devices in the array
383 * @n_success: number of devices mapped successfully
384 *
385 * @n_success returns information to the caller how many devices from
386 * the start of the array have mapped the buffer successfully. It can
387 * be passed into a subsequent retry call to skip those devices. For
388 * the first call the caller should initialize it to 0.
389 *
390 * If the ioctl completes with return code 0 (success), n_success ==
391 * n_devices.
392 */
393struct kfd_ioctl_map_memory_to_gpu_args {
394 __u64 handle; /* to KFD */
395 __u64 device_ids_array_ptr; /* to KFD */
396 __u32 n_devices; /* to KFD */
397 __u32 n_success; /* to/from KFD */
398};
399
400/* Unmap memory from one or more GPUs
401 *
402 * same arguments as for mapping
403 */
404struct kfd_ioctl_unmap_memory_from_gpu_args {
405 __u64 handle; /* to KFD */
406 __u64 device_ids_array_ptr; /* to KFD */
407 __u32 n_devices; /* to KFD */
408 __u32 n_success; /* to/from KFD */
409};
410
Felix Kuehling1dde0ea2018-11-20 21:00:29 -0500411struct kfd_ioctl_get_dmabuf_info_args {
412 __u64 size; /* from KFD */
413 __u64 metadata_ptr; /* to KFD */
414 __u32 metadata_size; /* to KFD (space allocated by user)
415 * from KFD (actual metadata size)
416 */
417 __u32 gpu_id; /* from KFD */
418 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
419 __u32 dmabuf_fd; /* to KFD */
420};
421
422struct kfd_ioctl_import_dmabuf_args {
423 __u64 va_addr; /* to KFD */
424 __u64 handle; /* from KFD */
425 __u32 gpu_id; /* to KFD */
426 __u32 dmabuf_fd; /* to KFD */
427};
428
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200429#define AMDKFD_IOCTL_BASE 'K'
430#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
431#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
432#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
433#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300434
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200435#define AMDKFD_IOC_GET_VERSION \
436 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300437
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200438#define AMDKFD_IOC_CREATE_QUEUE \
439 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300440
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200441#define AMDKFD_IOC_DESTROY_QUEUE \
442 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300443
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200444#define AMDKFD_IOC_SET_MEMORY_POLICY \
445 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300446
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200447#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
448 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300449
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200450#define AMDKFD_IOC_GET_PROCESS_APERTURES \
451 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
Oded Gabbayb7facba2014-07-16 15:55:29 +0300452
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200453#define AMDKFD_IOC_UPDATE_QUEUE \
454 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
455
Andrew Lewycky29a5d3e2014-12-07 17:05:11 +0200456#define AMDKFD_IOC_CREATE_EVENT \
457 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
458
459#define AMDKFD_IOC_DESTROY_EVENT \
460 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
461
462#define AMDKFD_IOC_SET_EVENT \
463 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
464
465#define AMDKFD_IOC_RESET_EVENT \
466 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
467
468#define AMDKFD_IOC_WAIT_EVENTS \
469 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
470
Yair Shacharaef11002014-12-07 17:05:22 +0200471#define AMDKFD_IOC_DBG_REGISTER \
472 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
473
474#define AMDKFD_IOC_DBG_UNREGISTER \
475 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
476
477#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
478 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
479
480#define AMDKFD_IOC_DBG_WAVE_CONTROL \
481 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
482
Moses Reuben6a1c9512017-08-15 23:00:20 -0400483#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
484 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
485
Yong Zhao5d71dbc2017-08-15 23:00:22 -0400486#define AMDKFD_IOC_GET_TILE_CONFIG \
487 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
488
Felix Kuehlingd7b9bd22017-11-14 16:41:20 -0500489#define AMDKFD_IOC_SET_TRAP_HANDLER \
490 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
491
Felix Kuehlingc7bcbfa2018-03-15 17:27:46 -0400492#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
493 AMDKFD_IOWR(0x14, \
494 struct kfd_ioctl_get_process_apertures_new_args)
495
Felix Kuehling5ec7e022018-03-15 17:27:51 -0400496#define AMDKFD_IOC_ACQUIRE_VM \
497 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
498
499#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
500 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
501
502#define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
503 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
504
505#define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
506 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
507
508#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
509 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
510
Felix Kuehlinga7fe68a2018-07-14 19:05:58 -0400511#define AMDKFD_IOC_SET_CU_MASK \
512 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
513
Jay Cornwall5df099e2017-05-02 17:39:37 -0500514#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
515 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
516
Felix Kuehling1dde0ea2018-11-20 21:00:29 -0500517#define AMDKFD_IOC_GET_DMABUF_INFO \
518 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
519
520#define AMDKFD_IOC_IMPORT_DMABUF \
521 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
522
Oded Gabbayb81c55d2014-12-29 15:24:25 +0200523#define AMDKFD_COMMAND_START 0x01
Felix Kuehling1dde0ea2018-11-20 21:00:29 -0500524#define AMDKFD_COMMAND_END 0x1E
Oded Gabbayb7facba2014-07-16 15:55:29 +0300525
526#endif