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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
David Woodhousea1452a32010-08-08 20:58:20 +01002 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
3 * Steven J. Hill <sjhill@realitydiluted.com>
4 * Thomas Gleixner <tglx@linutronix.de>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020010 * Info:
11 * Contains standard defines and IDs for NAND flash devices
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020013 * Changelog:
14 * See git changelog.
Linus Torvalds1da177e2005-04-16 15:20:36 -070015 */
Boris Brezillond4092d72017-08-04 17:29:10 +020016#ifndef __LINUX_MTD_RAWNAND_H
17#define __LINUX_MTD_RAWNAND_H
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/wait.h>
20#include <linux/spinlock.h>
21#include <linux/mtd/mtd.h>
Alessandro Rubini30631cb2009-09-20 23:28:14 +020022#include <linux/mtd/flashchip.h>
Alessandro Rubinic62d81b2009-09-20 23:28:04 +020023#include <linux/mtd/bbm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
25struct mtd_info;
David Woodhouse5e81e882010-02-26 18:32:56 +000026struct nand_flash_dev;
Brian Norris5844fee2015-01-23 00:22:27 -080027struct device_node;
28
Linus Torvalds1da177e2005-04-16 15:20:36 -070029/* Scan and identify a NAND device */
Sascha Hauer79022592016-09-07 14:21:42 +020030int nand_scan(struct mtd_info *mtd, int max_chips);
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020031/*
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
34 */
Sascha Hauer79022592016-09-07 14:21:42 +020035int nand_scan_ident(struct mtd_info *mtd, int max_chips,
David Woodhouse5e81e882010-02-26 18:32:56 +000036 struct nand_flash_dev *table);
Sascha Hauer79022592016-09-07 14:21:42 +020037int nand_scan_tail(struct mtd_info *mtd);
David Woodhouse3b85c322006-09-25 17:06:53 +010038
Richard Weinbergerd44154f2016-09-21 11:44:41 +020039/* Unregister the MTD device and free resources held by the NAND device */
Sascha Hauer79022592016-09-07 14:21:42 +020040void nand_release(struct mtd_info *mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
David Woodhouseb77d95c2006-09-25 21:58:50 +010042/* Internal helper for board drivers which need to override command function */
Sascha Hauer79022592016-09-07 14:21:42 +020043void nand_wait_ready(struct mtd_info *mtd);
David Woodhouseb77d95c2006-09-25 21:58:50 +010044
Brian Norris7854d3f2011-06-23 14:12:08 -070045/* locks all blocks present in the device */
Sascha Hauer79022592016-09-07 14:21:42 +020046int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
Vimal Singh7d70f332010-02-08 15:50:49 +053047
Brian Norris7854d3f2011-06-23 14:12:08 -070048/* unlocks specified locked blocks */
Sascha Hauer79022592016-09-07 14:21:42 +020049int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
Vimal Singh7d70f332010-02-08 15:50:49 +053050
Linus Torvalds1da177e2005-04-16 15:20:36 -070051/* The maximum number of NAND chips in an array */
52#define NAND_MAX_CHIPS 8
53
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020054/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 * Constants for hardware specific CLE/ALE/NCE function
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020056 *
57 * These are bits which can be or'ed to set/clear multiple
58 * bits in one go.
59 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070060/* Select the chip by setting nCE to low */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020061#define NAND_NCE 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -070062/* Select the command latch by setting CLE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020063#define NAND_CLE 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -070064/* Select the address latch by setting ALE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020065#define NAND_ALE 0x04
66
67#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69#define NAND_CTRL_CHANGE 0x80
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71/*
72 * Standard NAND flash commands
73 */
74#define NAND_CMD_READ0 0
75#define NAND_CMD_READ1 1
Thomas Gleixner7bc33122006-06-20 20:05:05 +020076#define NAND_CMD_RNDOUT 5
Linus Torvalds1da177e2005-04-16 15:20:36 -070077#define NAND_CMD_PAGEPROG 0x10
78#define NAND_CMD_READOOB 0x50
79#define NAND_CMD_ERASE1 0x60
80#define NAND_CMD_STATUS 0x70
Linus Torvalds1da177e2005-04-16 15:20:36 -070081#define NAND_CMD_SEQIN 0x80
Thomas Gleixner7bc33122006-06-20 20:05:05 +020082#define NAND_CMD_RNDIN 0x85
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#define NAND_CMD_READID 0x90
84#define NAND_CMD_ERASE2 0xd0
Florian Fainellicaa4b6f2010-08-30 18:32:14 +020085#define NAND_CMD_PARAM 0xec
Huang Shijie7db03ec2012-09-13 14:57:52 +080086#define NAND_CMD_GET_FEATURES 0xee
87#define NAND_CMD_SET_FEATURES 0xef
Linus Torvalds1da177e2005-04-16 15:20:36 -070088#define NAND_CMD_RESET 0xff
89
Vimal Singh7d70f332010-02-08 15:50:49 +053090#define NAND_CMD_LOCK 0x2a
91#define NAND_CMD_UNLOCK1 0x23
92#define NAND_CMD_UNLOCK2 0x24
93
Linus Torvalds1da177e2005-04-16 15:20:36 -070094/* Extended commands for large page devices */
95#define NAND_CMD_READSTART 0x30
Thomas Gleixner7bc33122006-06-20 20:05:05 +020096#define NAND_CMD_RNDOUTSTART 0xE0
Linus Torvalds1da177e2005-04-16 15:20:36 -070097#define NAND_CMD_CACHEDPROG 0x15
98
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020099#define NAND_CMD_NONE -1
100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101/* Status bits */
102#define NAND_STATUS_FAIL 0x01
103#define NAND_STATUS_FAIL_N1 0x02
104#define NAND_STATUS_TRUE_READY 0x20
105#define NAND_STATUS_READY 0x40
106#define NAND_STATUS_WP 0x80
107
Boris Brezillon104e4422017-03-16 09:35:58 +0100108#define NAND_DATA_IFACE_CHECK_ONLY -1
109
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000110/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 * Constants for ECC_MODES
112 */
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200113typedef enum {
114 NAND_ECC_NONE,
115 NAND_ECC_SOFT,
116 NAND_ECC_HW,
117 NAND_ECC_HW_SYNDROME,
Sneha Narnakaje6e0cb132009-09-18 12:51:47 -0700118 NAND_ECC_HW_OOB_FIRST,
Thomas Petazzoni785818f2017-04-29 11:06:43 +0200119 NAND_ECC_ON_DIE,
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200120} nand_ecc_modes_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121
Rafał Miłeckib0fcd8a2016-03-23 11:19:00 +0100122enum nand_ecc_algo {
123 NAND_ECC_UNKNOWN,
124 NAND_ECC_HAMMING,
125 NAND_ECC_BCH,
126};
127
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128/*
129 * Constants for Hardware ECC
David A. Marlin068e3c02005-01-24 03:07:46 +0000130 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131/* Reset Hardware ECC for read */
132#define NAND_ECC_READ 0
133/* Reset Hardware ECC for write */
134#define NAND_ECC_WRITE 1
Brian Norris7854d3f2011-06-23 14:12:08 -0700135/* Enable Hardware ECC before syndrome is read back from flash */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136#define NAND_ECC_READSYN 2
137
Boris BREZILLON40cbe6e2015-12-30 20:32:04 +0100138/*
139 * Enable generic NAND 'page erased' check. This check is only done when
140 * ecc.correct() returns -EBADMSG.
141 * Set this flag if your implementation does not fix bitflips in erased
142 * pages and you want to rely on the default implementation.
143 */
144#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
Boris Brezillonba78ee02016-06-08 17:04:22 +0200145#define NAND_ECC_MAXIMIZE BIT(1)
Marc Gonzalez3371d662016-11-15 10:56:20 +0100146/*
147 * If your controller already sends the required NAND commands when
148 * reading or writing a page, then the framework is not supposed to
149 * send READ0 and SEQIN/PAGEPROG respectively.
150 */
151#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
Boris BREZILLON40cbe6e2015-12-30 20:32:04 +0100152
David A. Marlin068e3c02005-01-24 03:07:46 +0000153/* Bit mask for flags passed to do_nand_read_ecc */
154#define NAND_GET_DEVICE 0x80
155
156
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200157/*
158 * Option constants for bizarre disfunctionality and real
159 * features.
160 */
Brian Norris7854d3f2011-06-23 14:12:08 -0700161/* Buswidth is 16 bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162#define NAND_BUSWIDTH_16 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163/* Chip has cache program function */
164#define NAND_CACHEPRG 0x00000008
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200165/*
Brian Norris5bc7c332013-03-13 09:51:31 -0700166 * Chip requires ready check on read (for auto-incremented sequential read).
167 * True only for small page devices; large page devices do not support
168 * autoincrement.
169 */
170#define NAND_NEED_READRDY 0x00000100
171
Thomas Gleixner29072b92006-09-28 15:38:36 +0200172/* Chip does not allow subpage writes */
173#define NAND_NO_SUBPAGE_WRITE 0x00000200
174
Maxim Levitsky93edbad2010-02-22 20:39:40 +0200175/* Device is one of 'new' xD cards that expose fake nand command set */
176#define NAND_BROKEN_XD 0x00000400
177
178/* Device behaves just like nand, but is readonly */
179#define NAND_ROM 0x00000800
180
Jeff Westfahla5ff4f12012-08-13 16:35:30 -0500181/* Device supports subpage reads */
182#define NAND_SUBPAGE_READ 0x00001000
183
Boris BREZILLONc03d9962015-12-02 12:01:05 +0100184/*
185 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
186 * patterns.
187 */
188#define NAND_NEED_SCRAMBLING 0x00002000
189
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190/* Options valid for Samsung large page devices */
Artem Bityutskiy3239a6c2013-03-04 14:56:18 +0200191#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192
193/* Macros to identify the above */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
Jeff Westfahla5ff4f12012-08-13 16:35:30 -0500195#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
Marc Gonzalez3371d662016-11-15 10:56:20 +0100196#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198/* Non chip related options */
Thomas Gleixner0040bf32005-02-09 12:20:00 +0000199/* This option skips the bbt scan during initialization. */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700200#define NAND_SKIP_BBTSCAN 0x00010000
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200201/*
202 * This option is defined if the board driver allocates its own buffers
203 * (e.g. because it needs them DMA-coherent).
204 */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700205#define NAND_OWN_BUFFERS 0x00020000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000206/* Chip may not exist, so silence any errors in scan */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700207#define NAND_SCAN_SILENT_NODEV 0x00040000
Matthieu CASTET64b37b22012-11-06 11:51:44 +0100208/*
209 * Autodetect nand buswidth with readid/onfi.
210 * This suppose the driver will configure the hardware in 8 bits mode
211 * when calling nand_scan_ident, and update its configuration
212 * before calling nand_scan_tail.
213 */
214#define NAND_BUSWIDTH_AUTO 0x00080000
Scott Wood5f867db2015-06-26 19:43:58 -0500215/*
216 * This option could be defined by controller drivers to protect against
217 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
218 */
219#define NAND_USE_BOUNCE_BUFFER 0x00100000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000220
Boris Brezillon6ea40a32016-10-01 10:24:03 +0200221/*
222 * In case your controller is implementing ->cmd_ctrl() and is relying on the
223 * default ->cmdfunc() implementation, you may want to let the core handle the
224 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
225 * requested.
226 * If your controller already takes care of this delay, you don't need to set
227 * this flag.
228 */
229#define NAND_WAIT_TCCS 0x00200000
230
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231/* Options set by nand scan */
Thomas Gleixnera36ed292006-05-23 11:37:03 +0200232/* Nand scan has allocated controller struct */
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200233#define NAND_CONTROLLER_ALLOC 0x80000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234
Thomas Gleixner29072b92006-09-28 15:38:36 +0200235/* Cell info constants */
236#define NAND_CI_CHIPNR_MSK 0x03
237#define NAND_CI_CELLTYPE_MSK 0x0C
Huang Shijie7db906b2013-09-25 14:58:11 +0800238#define NAND_CI_CELLTYPE_SHIFT 2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240/* Keep gcc happy */
241struct nand_chip;
242
Huang Shijie5b40db62013-05-17 11:17:28 +0800243/* ONFI features */
244#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
245#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
246
Huang Shijie3e701922012-09-13 14:57:53 +0800247/* ONFI timing mode, used in both asynchronous and synchronous mode */
248#define ONFI_TIMING_MODE_0 (1 << 0)
249#define ONFI_TIMING_MODE_1 (1 << 1)
250#define ONFI_TIMING_MODE_2 (1 << 2)
251#define ONFI_TIMING_MODE_3 (1 << 3)
252#define ONFI_TIMING_MODE_4 (1 << 4)
253#define ONFI_TIMING_MODE_5 (1 << 5)
254#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
255
Huang Shijie7db03ec2012-09-13 14:57:52 +0800256/* ONFI feature address */
257#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
258
Brian Norris8429bb32013-12-03 15:51:09 -0800259/* Vendor-specific feature address (Micron) */
260#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
Thomas Petazzoni9748e1d2017-04-29 11:06:45 +0200261#define ONFI_FEATURE_ON_DIE_ECC 0x90
262#define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
Brian Norris8429bb32013-12-03 15:51:09 -0800263
Huang Shijie7db03ec2012-09-13 14:57:52 +0800264/* ONFI subfeature parameters length */
265#define ONFI_SUBFEATURE_PARAM_LEN 4
266
David Mosbergerd914c932013-05-29 15:30:13 +0300267/* ONFI optional commands SET/GET FEATURES supported? */
268#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
269
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200270struct nand_onfi_params {
271 /* rev info and features block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200272 /* 'O' 'N' 'F' 'I' */
273 u8 sig[4];
274 __le16 revision;
275 __le16 features;
276 __le16 opt_cmd;
Huang Shijie5138a982013-05-17 11:17:27 +0800277 u8 reserved0[2];
278 __le16 ext_param_page_length; /* since ONFI 2.1 */
279 u8 num_of_param_pages; /* since ONFI 2.1 */
280 u8 reserved1[17];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200281
282 /* manufacturer information block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200283 char manufacturer[12];
284 char model[20];
285 u8 jedec_id;
286 __le16 date_code;
287 u8 reserved2[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200288
289 /* memory organization block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200290 __le32 byte_per_page;
291 __le16 spare_bytes_per_page;
292 __le32 data_bytes_per_ppage;
293 __le16 spare_bytes_per_ppage;
294 __le32 pages_per_block;
295 __le32 blocks_per_lun;
296 u8 lun_count;
297 u8 addr_cycles;
298 u8 bits_per_cell;
299 __le16 bb_per_lun;
300 __le16 block_endurance;
301 u8 guaranteed_good_blocks;
302 __le16 guaranteed_block_endurance;
303 u8 programs_per_page;
304 u8 ppage_attr;
305 u8 ecc_bits;
306 u8 interleaved_bits;
307 u8 interleaved_ops;
308 u8 reserved3[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200309
310 /* electrical parameter block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200311 u8 io_pin_capacitance_max;
312 __le16 async_timing_mode;
313 __le16 program_cache_timing_mode;
314 __le16 t_prog;
315 __le16 t_bers;
316 __le16 t_r;
317 __le16 t_ccs;
318 __le16 src_sync_timing_mode;
Boris BREZILLONde64aa92015-11-23 11:23:07 +0100319 u8 src_ssync_features;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200320 __le16 clk_pin_capacitance_typ;
321 __le16 io_pin_capacitance_typ;
322 __le16 input_pin_capacitance_typ;
323 u8 input_pin_capacitance_max;
Brian Norrisa55e85c2013-12-02 11:12:22 -0800324 u8 driver_strength_support;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200325 __le16 t_int_r;
Brian Norris74e98be2015-12-01 11:08:32 -0800326 __le16 t_adl;
Boris BREZILLONde64aa92015-11-23 11:23:07 +0100327 u8 reserved4[8];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200328
329 /* vendor */
Brian Norris6f0065b2013-12-03 12:02:20 -0800330 __le16 vendor_revision;
331 u8 vendor[88];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200332
333 __le16 crc;
Brian Norrise2e6b7b2013-12-05 12:06:54 -0800334} __packed;
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200335
336#define ONFI_CRC_BASE 0x4F4E
337
Huang Shijie5138a982013-05-17 11:17:27 +0800338/* Extended ECC information Block Definition (since ONFI 2.1) */
339struct onfi_ext_ecc_info {
340 u8 ecc_bits;
341 u8 codeword_size;
342 __le16 bb_per_lun;
343 __le16 block_endurance;
344 u8 reserved[2];
345} __packed;
346
347#define ONFI_SECTION_TYPE_0 0 /* Unused section. */
348#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
349#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
350struct onfi_ext_section {
351 u8 type;
352 u8 length;
353} __packed;
354
355#define ONFI_EXT_SECTION_MAX 8
356
357/* Extended Parameter Page Definition (since ONFI 2.1) */
358struct onfi_ext_param_page {
359 __le16 crc;
360 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
361 u8 reserved0[10];
362 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
363
364 /*
365 * The actual size of the Extended Parameter Page is in
366 * @ext_param_page_length of nand_onfi_params{}.
367 * The following are the variable length sections.
368 * So we do not add any fields below. Please see the ONFI spec.
369 */
370} __packed;
371
Huang Shijieafbfff02014-02-21 13:39:37 +0800372struct jedec_ecc_info {
373 u8 ecc_bits;
374 u8 codeword_size;
375 __le16 bb_per_lun;
376 __le16 block_endurance;
377 u8 reserved[2];
378} __packed;
379
Huang Shijie7852f892014-02-21 13:39:39 +0800380/* JEDEC features */
381#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
382
Huang Shijieafbfff02014-02-21 13:39:37 +0800383struct nand_jedec_params {
384 /* rev info and features block */
385 /* 'J' 'E' 'S' 'D' */
386 u8 sig[4];
387 __le16 revision;
388 __le16 features;
389 u8 opt_cmd[3];
390 __le16 sec_cmd;
391 u8 num_of_param_pages;
392 u8 reserved0[18];
393
394 /* manufacturer information block */
395 char manufacturer[12];
396 char model[20];
397 u8 jedec_id[6];
398 u8 reserved1[10];
399
400 /* memory organization block */
401 __le32 byte_per_page;
402 __le16 spare_bytes_per_page;
403 u8 reserved2[6];
404 __le32 pages_per_block;
405 __le32 blocks_per_lun;
406 u8 lun_count;
407 u8 addr_cycles;
408 u8 bits_per_cell;
409 u8 programs_per_page;
410 u8 multi_plane_addr;
411 u8 multi_plane_op_attr;
412 u8 reserved3[38];
413
414 /* electrical parameter block */
415 __le16 async_sdr_speed_grade;
416 __le16 toggle_ddr_speed_grade;
417 __le16 sync_ddr_speed_grade;
418 u8 async_sdr_features;
419 u8 toggle_ddr_features;
420 u8 sync_ddr_features;
421 __le16 t_prog;
422 __le16 t_bers;
423 __le16 t_r;
424 __le16 t_r_multi_plane;
425 __le16 t_ccs;
426 __le16 io_pin_capacitance_typ;
427 __le16 input_pin_capacitance_typ;
428 __le16 clk_pin_capacitance_typ;
429 u8 driver_strength_support;
Brian Norris74e98be2015-12-01 11:08:32 -0800430 __le16 t_adl;
Huang Shijieafbfff02014-02-21 13:39:37 +0800431 u8 reserved4[36];
432
433 /* ECC and endurance block */
434 u8 guaranteed_good_blocks;
435 __le16 guaranteed_block_endurance;
436 struct jedec_ecc_info ecc_info[4];
437 u8 reserved5[29];
438
439 /* reserved */
440 u8 reserved6[148];
441
442 /* vendor */
443 __le16 vendor_rev_num;
444 u8 reserved7[88];
445
446 /* CRC for Parameter Page */
447 __le16 crc;
448} __packed;
449
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450/**
Boris Brezillon7f501f02016-05-24 19:20:05 +0200451 * struct nand_id - NAND id structure
452 * @data: buffer containing the id bytes. Currently 8 bytes large, but can
453 * be extended if required.
454 * @len: ID length.
455 */
456struct nand_id {
457 u8 data[8];
458 int len;
459};
460
461/**
Randy Dunlap844d3b42006-06-28 21:48:27 -0700462 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000463 * @lock: protection lock
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 * @active: the mtd device which holds the controller currently
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200465 * @wq: wait queue to sleep on if a NAND operation is in
466 * progress used instead of the per chip wait queue
467 * when a hw controller is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 */
469struct nand_hw_control {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200470 spinlock_t lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471 struct nand_chip *active;
Thomas Gleixner0dfc6242005-05-31 20:39:20 +0100472 wait_queue_head_t wq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473};
474
Marc Gonzalezd45bc582016-07-27 11:23:52 +0200475static inline void nand_hw_control_init(struct nand_hw_control *nfc)
476{
477 nfc->active = NULL;
478 spin_lock_init(&nfc->lock);
479 init_waitqueue_head(&nfc->wq);
480}
481
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482/**
Masahiro Yamada2c8f8af2017-06-07 20:52:10 +0900483 * struct nand_ecc_step_info - ECC step information of ECC engine
484 * @stepsize: data bytes per ECC step
485 * @strengths: array of supported strengths
486 * @nstrengths: number of supported strengths
487 */
488struct nand_ecc_step_info {
489 int stepsize;
490 const int *strengths;
491 int nstrengths;
492};
493
494/**
495 * struct nand_ecc_caps - capability of ECC engine
496 * @stepinfos: array of ECC step information
497 * @nstepinfos: number of ECC step information
498 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
499 */
500struct nand_ecc_caps {
501 const struct nand_ecc_step_info *stepinfos;
502 int nstepinfos;
503 int (*calc_ecc_bytes)(int step_size, int strength);
504};
505
Masahiro Yamadaa03c6012017-06-07 20:52:11 +0900506/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
507#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
508static const int __name##_strengths[] = { __VA_ARGS__ }; \
509static const struct nand_ecc_step_info __name##_stepinfo = { \
510 .stepsize = __step, \
511 .strengths = __name##_strengths, \
512 .nstrengths = ARRAY_SIZE(__name##_strengths), \
513}; \
514static const struct nand_ecc_caps __name = { \
515 .stepinfos = &__name##_stepinfo, \
516 .nstepinfos = 1, \
517 .calc_ecc_bytes = __calc, \
518}
519
Masahiro Yamada2c8f8af2017-06-07 20:52:10 +0900520/**
Brian Norris7854d3f2011-06-23 14:12:08 -0700521 * struct nand_ecc_ctrl - Control structure for ECC
522 * @mode: ECC mode
Rafał Miłeckib0fcd8a2016-03-23 11:19:00 +0100523 * @algo: ECC algorithm
Brian Norris7854d3f2011-06-23 14:12:08 -0700524 * @steps: number of ECC steps per page
525 * @size: data bytes per ECC step
526 * @bytes: ECC bytes per step
Mike Dunn1d0b95b2012-03-11 14:21:10 -0700527 * @strength: max number of correctible bits per ECC step
Brian Norris7854d3f2011-06-23 14:12:08 -0700528 * @total: total number of ECC bytes per page
529 * @prepad: padding information for syndrome based ECC generators
530 * @postpad: padding information for syndrome based ECC generators
Boris BREZILLON40cbe6e2015-12-30 20:32:04 +0100531 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
Brian Norris7854d3f2011-06-23 14:12:08 -0700532 * @priv: pointer to private ECC control data
533 * @hwctl: function to control hardware ECC generator. Must only
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200534 * be provided if an hardware ECC is available
Brian Norris7854d3f2011-06-23 14:12:08 -0700535 * @calculate: function for ECC calculation or readback from ECC hardware
Boris BREZILLON6e941192015-12-30 20:32:03 +0100536 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
537 * Should return a positive number representing the number of
538 * corrected bitflips, -EBADMSG if the number of bitflips exceed
539 * ECC strength, or any other error code if the error is not
540 * directly related to correction.
541 * If -EBADMSG is returned the input buffers should be left
542 * untouched.
Boris BREZILLON62d956d2014-10-20 10:46:14 +0200543 * @read_page_raw: function to read a raw page without ECC. This function
544 * should hide the specific layout used by the ECC
545 * controller and always return contiguous in-band and
546 * out-of-band data even if they're not stored
547 * contiguously on the NAND chip (e.g.
548 * NAND_ECC_HW_SYNDROME interleaves in-band and
549 * out-of-band data).
550 * @write_page_raw: function to write a raw page without ECC. This function
551 * should hide the specific layout used by the ECC
552 * controller and consider the passed data as contiguous
553 * in-band and out-of-band data. ECC controller is
554 * responsible for doing the appropriate transformations
555 * to adapt to its specific layout (e.g.
556 * NAND_ECC_HW_SYNDROME interleaves in-band and
557 * out-of-band data).
Brian Norris7854d3f2011-06-23 14:12:08 -0700558 * @read_page: function to read a page according to the ECC generator
Mike Dunn5ca7f412012-09-11 08:59:03 -0700559 * requirements; returns maximum number of bitflips corrected in
Masahiro Yamada07604682017-03-30 15:45:47 +0900560 * any single ECC step, -EIO hw error
Mike Dunn5ca7f412012-09-11 08:59:03 -0700561 * @read_subpage: function to read parts of the page covered by ECC;
562 * returns same as read_page()
Gupta, Pekon837a6ba2013-03-15 17:55:53 +0530563 * @write_subpage: function to write parts of the page covered by ECC.
Brian Norris7854d3f2011-06-23 14:12:08 -0700564 * @write_page: function to write a page according to the ECC generator
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200565 * requirements.
Brian Norris9ce244b2011-08-30 18:45:37 -0700566 * @write_oob_raw: function to write chip OOB data without ECC
Brian Norrisc46f6482011-08-30 18:45:38 -0700567 * @read_oob_raw: function to read chip OOB data without ECC
Randy Dunlap844d3b42006-06-28 21:48:27 -0700568 * @read_oob: function to read chip OOB data
569 * @write_oob: function to write chip OOB data
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200570 */
571struct nand_ecc_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200572 nand_ecc_modes_t mode;
Rafał Miłeckib0fcd8a2016-03-23 11:19:00 +0100573 enum nand_ecc_algo algo;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200574 int steps;
575 int size;
576 int bytes;
577 int total;
Mike Dunn1d0b95b2012-03-11 14:21:10 -0700578 int strength;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200579 int prepad;
580 int postpad;
Boris BREZILLON40cbe6e2015-12-30 20:32:04 +0100581 unsigned int options;
Ivan Djelic193bd402011-03-11 11:05:33 +0100582 void *priv;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200583 void (*hwctl)(struct mtd_info *mtd, int mode);
584 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
585 uint8_t *ecc_code);
586 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
587 uint8_t *calc_ecc);
588 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700589 uint8_t *buf, int oob_required, int page);
Josh Wufdbad98d2012-06-25 18:07:45 +0800590 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200591 const uint8_t *buf, int oob_required, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200592 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700593 uint8_t *buf, int oob_required, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200594 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
Huang Shijiee004deb2014-01-03 11:01:40 +0800595 uint32_t offs, uint32_t len, uint8_t *buf, int page);
Gupta, Pekon837a6ba2013-03-15 17:55:53 +0530596 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
597 uint32_t offset, uint32_t data_len,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200598 const uint8_t *data_buf, int oob_required, int page);
Josh Wufdbad98d2012-06-25 18:07:45 +0800599 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200600 const uint8_t *buf, int oob_required, int page);
Brian Norris9ce244b2011-08-30 18:45:37 -0700601 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
602 int page);
Brian Norrisc46f6482011-08-30 18:45:38 -0700603 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +0300604 int page);
605 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200606 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
607 int page);
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200608};
609
Marc Gonzalez3371d662016-11-15 10:56:20 +0100610static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
611{
612 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
613}
614
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200615/**
616 * struct nand_buffers - buffer structure for read/write
Huang Shijief02ea4e2014-01-13 14:27:12 +0800617 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
618 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
619 * @databuf: buffer pointer for data, size is (page size + oobsize).
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200620 *
621 * Do not change the order of buffers. databuf and oobrbuf must be in
622 * consecutive order.
623 */
624struct nand_buffers {
Huang Shijief02ea4e2014-01-13 14:27:12 +0800625 uint8_t *ecccalc;
626 uint8_t *ecccode;
627 uint8_t *databuf;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200628};
629
630/**
Sascha Hauereee64b72016-09-15 10:32:46 +0200631 * struct nand_sdr_timings - SDR NAND chip timings
632 *
633 * This struct defines the timing requirements of a SDR NAND chip.
634 * These information can be found in every NAND datasheets and the timings
635 * meaning are described in the ONFI specifications:
636 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
637 * Parameters)
638 *
639 * All these timings are expressed in picoseconds.
640 *
Boris Brezillon204e7ec2016-10-01 10:24:02 +0200641 * @tBERS_max: Block erase time
642 * @tCCS_min: Change column setup time
643 * @tPROG_max: Page program time
644 * @tR_max: Page read time
Sascha Hauereee64b72016-09-15 10:32:46 +0200645 * @tALH_min: ALE hold time
646 * @tADL_min: ALE to data loading time
647 * @tALS_min: ALE setup time
648 * @tAR_min: ALE to RE# delay
649 * @tCEA_max: CE# access time
Randy Dunlap61babe92016-11-21 18:32:08 -0800650 * @tCEH_min: CE# high hold time
Sascha Hauereee64b72016-09-15 10:32:46 +0200651 * @tCH_min: CE# hold time
652 * @tCHZ_max: CE# high to output hi-Z
653 * @tCLH_min: CLE hold time
654 * @tCLR_min: CLE to RE# delay
655 * @tCLS_min: CLE setup time
656 * @tCOH_min: CE# high to output hold
657 * @tCS_min: CE# setup time
658 * @tDH_min: Data hold time
659 * @tDS_min: Data setup time
660 * @tFEAT_max: Busy time for Set Features and Get Features
661 * @tIR_min: Output hi-Z to RE# low
662 * @tITC_max: Interface and Timing Mode Change time
663 * @tRC_min: RE# cycle time
664 * @tREA_max: RE# access time
665 * @tREH_min: RE# high hold time
666 * @tRHOH_min: RE# high to output hold
667 * @tRHW_min: RE# high to WE# low
668 * @tRHZ_max: RE# high to output hi-Z
669 * @tRLOH_min: RE# low to output hold
670 * @tRP_min: RE# pulse width
671 * @tRR_min: Ready to RE# low (data only)
672 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
673 * rising edge of R/B#.
674 * @tWB_max: WE# high to SR[6] low
675 * @tWC_min: WE# cycle time
676 * @tWH_min: WE# high hold time
677 * @tWHR_min: WE# high to RE# low
678 * @tWP_min: WE# pulse width
679 * @tWW_min: WP# transition to WE# low
680 */
681struct nand_sdr_timings {
Boris Brezillon204e7ec2016-10-01 10:24:02 +0200682 u32 tBERS_max;
683 u32 tCCS_min;
684 u32 tPROG_max;
685 u32 tR_max;
Sascha Hauereee64b72016-09-15 10:32:46 +0200686 u32 tALH_min;
687 u32 tADL_min;
688 u32 tALS_min;
689 u32 tAR_min;
690 u32 tCEA_max;
691 u32 tCEH_min;
692 u32 tCH_min;
693 u32 tCHZ_max;
694 u32 tCLH_min;
695 u32 tCLR_min;
696 u32 tCLS_min;
697 u32 tCOH_min;
698 u32 tCS_min;
699 u32 tDH_min;
700 u32 tDS_min;
701 u32 tFEAT_max;
702 u32 tIR_min;
703 u32 tITC_max;
704 u32 tRC_min;
705 u32 tREA_max;
706 u32 tREH_min;
707 u32 tRHOH_min;
708 u32 tRHW_min;
709 u32 tRHZ_max;
710 u32 tRLOH_min;
711 u32 tRP_min;
712 u32 tRR_min;
713 u64 tRST_max;
714 u32 tWB_max;
715 u32 tWC_min;
716 u32 tWH_min;
717 u32 tWHR_min;
718 u32 tWP_min;
719 u32 tWW_min;
720};
721
722/**
723 * enum nand_data_interface_type - NAND interface timing type
724 * @NAND_SDR_IFACE: Single Data Rate interface
725 */
726enum nand_data_interface_type {
727 NAND_SDR_IFACE,
728};
729
730/**
731 * struct nand_data_interface - NAND interface timing
732 * @type: type of the timing
733 * @timings: The timing, type according to @type
734 */
735struct nand_data_interface {
736 enum nand_data_interface_type type;
737 union {
738 struct nand_sdr_timings sdr;
739 } timings;
740};
741
742/**
743 * nand_get_sdr_timings - get SDR timing from data interface
744 * @conf: The data interface
745 */
746static inline const struct nand_sdr_timings *
747nand_get_sdr_timings(const struct nand_data_interface *conf)
748{
749 if (conf->type != NAND_SDR_IFACE)
750 return ERR_PTR(-EINVAL);
751
752 return &conf->timings.sdr;
753}
754
755/**
Boris Brezillonabbe26d2016-06-08 09:32:55 +0200756 * struct nand_manufacturer_ops - NAND Manufacturer operations
757 * @detect: detect the NAND memory organization and capabilities
758 * @init: initialize all vendor specific fields (like the ->read_retry()
759 * implementation) if any.
760 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
761 * is here to let vendor specific code release those resources.
762 */
763struct nand_manufacturer_ops {
764 void (*detect)(struct nand_chip *chip);
765 int (*init)(struct nand_chip *chip);
766 void (*cleanup)(struct nand_chip *chip);
767};
768
769/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 * struct nand_chip - NAND Private Flash Chip Data
Boris BREZILLONed4f85c2015-12-01 12:03:06 +0100771 * @mtd: MTD device registered to the MTD framework
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200772 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
773 * flash device
774 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
775 * flash device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 * @read_byte: [REPLACEABLE] read one byte from the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777 * @read_word: [REPLACEABLE] read one word from the chip
Uwe Kleine-König05f78352013-12-05 22:22:04 +0100778 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
779 * low 8 I/O lines
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
781 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 * @select_chip: [REPLACEABLE] select chip nr
Brian Norrisce157512013-04-11 01:34:59 -0700783 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
784 * @block_markbad: [REPLACEABLE] mark a block bad
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300785 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200786 * ALE/CLE/nCE. Also used to write command and address
Brian Norris7854d3f2011-06-23 14:12:08 -0700787 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200788 * device ready/busy line. If set to NULL no access to
789 * ready/busy is available and the ready/busy information
790 * is read from the chip status register.
791 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
792 * commands to the chip.
793 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
794 * ready.
Brian Norrisba84fb52014-01-03 15:13:33 -0800795 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
796 * setting the read-retry mode. Mostly needed for MLC NAND.
Brian Norris7854d3f2011-06-23 14:12:08 -0700797 * @ecc: [BOARDSPECIFIC] ECC control structure
Randy Dunlap844d3b42006-06-28 21:48:27 -0700798 * @buffers: buffer structure for read/write
Masahiro Yamada477544c2017-03-30 17:15:05 +0900799 * @buf_align: minimum buffer alignment required by a platform
Randy Dunlap844d3b42006-06-28 21:48:27 -0700800 * @hwcontrol: platform-specific hardware control structure
Brian Norris49c50b92014-05-06 16:02:19 -0700801 * @erase: [REPLACEABLE] erase function
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 * @scan_bbt: [REPLACEABLE] function to scan bad block table
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300803 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200804 * data from array to read regs (tR).
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200805 * @state: [INTERN] the current state of the NAND device
Brian Norrise9195ed2011-08-30 18:45:43 -0700806 * @oob_poi: "poison value buffer," used for laying out OOB data
807 * before writing
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200808 * @page_shift: [INTERN] number of address bits in a page (column
809 * address bits).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
811 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
812 * @chip_shift: [INTERN] number of address bits in one chip
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200813 * @options: [BOARDSPECIFIC] various chip options. They can partly
814 * be set to inform nand_scan about special functionality.
815 * See the defines for further explanation.
Brian Norris5fb15492011-05-31 16:31:21 -0700816 * @bbt_options: [INTERN] bad block specific options. All options used
817 * here must come from bbm.h. By default, these options
818 * will be copied to the appropriate nand_bbt_descr's.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200819 * @badblockpos: [INTERN] position of the bad block marker in the oob
820 * area.
Brian Norris661a0832012-01-13 18:11:50 -0800821 * @badblockbits: [INTERN] minimum number of set bits in a good block's
822 * bad block marker position; i.e., BBM == 11110111b is
823 * not bad when badblockbits == 7
Huang Shijie7db906b2013-09-25 14:58:11 +0800824 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
Huang Shijie4cfeca22013-05-17 11:17:25 +0800825 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
826 * Minimum amount of bit errors per @ecc_step_ds guaranteed
827 * to be correctable. If unknown, set to zero.
828 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
Mauro Carvalho Chehabb6f6c292017-05-13 07:40:36 -0300829 * also from the datasheet. It is the recommended ECC step
Huang Shijie4cfeca22013-05-17 11:17:25 +0800830 * size, if known; if unknown, set to zero.
Boris BREZILLON57a94e22014-09-22 20:11:50 +0200831 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
Boris Brezillond8e725d2016-09-15 10:32:50 +0200832 * set to the actually used ONFI mode if the chip is
833 * ONFI compliant or deduced from the datasheet if
834 * the NAND chip is not ONFI compliant.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 * @numchips: [INTERN] number of physical chips
836 * @chipsize: [INTERN] the size of one chip for multichip arrays
837 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200838 * @pagebuf: [INTERN] holds the pagenumber which is currently in
839 * data_buf.
Mike Dunnedbc45402012-04-25 12:06:11 -0700840 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
841 * currently in data_buf.
Thomas Gleixner29072b92006-09-28 15:38:36 +0200842 * @subpagesize: [INTERN] holds the subpagesize
Boris Brezillon7f501f02016-05-24 19:20:05 +0200843 * @id: [INTERN] holds NAND ID
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200844 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
845 * non 0 if ONFI supported.
Huang Shijied94abba2014-02-21 13:39:38 +0800846 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
847 * non 0 if JEDEC supported.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200848 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
849 * supported, 0 otherwise.
Huang Shijied94abba2014-02-21 13:39:38 +0800850 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
851 * supported, 0 otherwise.
Zach Brownceb374e2017-01-10 13:30:19 -0600852 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
853 * this nand device will encounter their life times.
854 * @blocks_per_die: [INTERN] The number of PEBs in a die
Randy Dunlap61babe92016-11-21 18:32:08 -0800855 * @data_interface: [INTERN] NAND interface timing information
Brian Norrisba84fb52014-01-03 15:13:33 -0800856 * @read_retries: [INTERN] the number of read retry modes supported
Robert P. J. Day9ef525a2012-10-25 09:43:10 -0400857 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
858 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
Boris Brezillon104e4422017-03-16 09:35:58 +0100859 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
860 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
861 * means the configuration should not be applied but
862 * only checked.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 * @bbt: [INTERN] bad block table pointer
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200864 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
865 * lookup.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200867 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
868 * bad block scan.
869 * @controller: [REPLACEABLE] a pointer to a hardware controller
Brian Norris7854d3f2011-06-23 14:12:08 -0700870 * structure which is shared among multiple independent
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200871 * devices.
Brian Norris32c8db82011-08-23 17:17:35 -0700872 * @priv: [OPTIONAL] pointer to private chip data
Boris Brezillonabbe26d2016-06-08 09:32:55 +0200873 * @manufacturer: [INTERN] Contains manufacturer information
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 */
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000875
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876struct nand_chip {
Boris BREZILLONed4f85c2015-12-01 12:03:06 +0100877 struct mtd_info mtd;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200878 void __iomem *IO_ADDR_R;
879 void __iomem *IO_ADDR_W;
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000880
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200881 uint8_t (*read_byte)(struct mtd_info *mtd);
882 u16 (*read_word)(struct mtd_info *mtd);
Uwe Kleine-König05f78352013-12-05 22:22:04 +0100883 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200884 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
885 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200886 void (*select_chip)(struct mtd_info *mtd, int chip);
Archit Taneja9f3e0422016-02-03 14:29:49 +0530887 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200888 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
889 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200890 int (*dev_ready)(struct mtd_info *mtd);
891 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
892 int page_addr);
893 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
Brian Norris49c50b92014-05-06 16:02:19 -0700894 int (*erase)(struct mtd_info *mtd, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200895 int (*scan_bbt)(struct mtd_info *mtd);
Huang Shijie7db03ec2012-09-13 14:57:52 +0800896 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
897 int feature_addr, uint8_t *subfeature_para);
898 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
899 int feature_addr, uint8_t *subfeature_para);
Brian Norrisba84fb52014-01-03 15:13:33 -0800900 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
Boris Brezillon104e4422017-03-16 09:35:58 +0100901 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
902 const struct nand_data_interface *conf);
Boris Brezillond8e725d2016-09-15 10:32:50 +0200903
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200904
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200905 int chip_delay;
906 unsigned int options;
Brian Norris5fb15492011-05-31 16:31:21 -0700907 unsigned int bbt_options;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200908
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200909 int page_shift;
910 int phys_erase_shift;
911 int bbt_erase_shift;
912 int chip_shift;
913 int numchips;
914 uint64_t chipsize;
915 int pagemask;
916 int pagebuf;
Mike Dunnedbc45402012-04-25 12:06:11 -0700917 unsigned int pagebuf_bitflips;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200918 int subpagesize;
Huang Shijie7db906b2013-09-25 14:58:11 +0800919 uint8_t bits_per_cell;
Huang Shijie4cfeca22013-05-17 11:17:25 +0800920 uint16_t ecc_strength_ds;
921 uint16_t ecc_step_ds;
Boris BREZILLON57a94e22014-09-22 20:11:50 +0200922 int onfi_timing_mode_default;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200923 int badblockpos;
924 int badblockbits;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200925
Boris Brezillon7f501f02016-05-24 19:20:05 +0200926 struct nand_id id;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200927 int onfi_version;
Huang Shijied94abba2014-02-21 13:39:38 +0800928 int jedec_version;
929 union {
930 struct nand_onfi_params onfi_params;
931 struct nand_jedec_params jedec_params;
932 };
Zach Brownceb374e2017-01-10 13:30:19 -0600933 u16 max_bb_per_die;
934 u32 blocks_per_die;
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200935
Boris Brezillond8e725d2016-09-15 10:32:50 +0200936 struct nand_data_interface *data_interface;
937
Brian Norrisba84fb52014-01-03 15:13:33 -0800938 int read_retries;
939
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200940 flstate_t state;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200941
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200942 uint8_t *oob_poi;
943 struct nand_hw_control *controller;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200944
945 struct nand_ecc_ctrl ecc;
David Woodhouse4bf63fc2006-09-25 17:08:04 +0100946 struct nand_buffers *buffers;
Masahiro Yamada477544c2017-03-30 17:15:05 +0900947 unsigned long buf_align;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200948 struct nand_hw_control hwcontrol;
949
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200950 uint8_t *bbt;
951 struct nand_bbt_descr *bbt_td;
952 struct nand_bbt_descr *bbt_md;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200953
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200954 struct nand_bbt_descr *badblock_pattern;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200955
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200956 void *priv;
Boris Brezillonabbe26d2016-06-08 09:32:55 +0200957
958 struct {
959 const struct nand_manufacturer *desc;
960 void *priv;
961 } manufacturer;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962};
963
Boris Brezillon41b207a2016-02-03 19:06:15 +0100964extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
965extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
966
Brian Norris28b8b26b2015-10-30 20:33:20 -0700967static inline void nand_set_flash_node(struct nand_chip *chip,
968 struct device_node *np)
969{
Boris BREZILLON29574ed2015-12-10 09:00:38 +0100970 mtd_set_of_node(&chip->mtd, np);
Brian Norris28b8b26b2015-10-30 20:33:20 -0700971}
972
973static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
974{
Boris BREZILLON29574ed2015-12-10 09:00:38 +0100975 return mtd_get_of_node(&chip->mtd);
Brian Norris28b8b26b2015-10-30 20:33:20 -0700976}
977
Boris BREZILLON9eba47d2015-11-16 14:37:35 +0100978static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
979{
Boris BREZILLON2d3b77b2015-12-10 09:00:33 +0100980 return container_of(mtd, struct nand_chip, mtd);
Boris BREZILLON9eba47d2015-11-16 14:37:35 +0100981}
982
Boris BREZILLONffd014f2015-12-01 12:03:07 +0100983static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
984{
985 return &chip->mtd;
986}
987
Boris BREZILLONd39ddbd2015-12-10 09:00:39 +0100988static inline void *nand_get_controller_data(struct nand_chip *chip)
989{
990 return chip->priv;
991}
992
993static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
994{
995 chip->priv = priv;
996}
997
Boris Brezillonabbe26d2016-06-08 09:32:55 +0200998static inline void nand_set_manufacturer_data(struct nand_chip *chip,
999 void *priv)
1000{
1001 chip->manufacturer.priv = priv;
1002}
1003
1004static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1005{
1006 return chip->manufacturer.priv;
1007}
1008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009/*
1010 * NAND Flash Manufacturer ID Codes
1011 */
1012#define NAND_MFR_TOSHIBA 0x98
Rafał Miłecki1c7fe6b2016-06-09 20:10:11 +02001013#define NAND_MFR_ESMT 0xc8
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014#define NAND_MFR_SAMSUNG 0xec
1015#define NAND_MFR_FUJITSU 0x04
1016#define NAND_MFR_NATIONAL 0x8f
1017#define NAND_MFR_RENESAS 0x07
1018#define NAND_MFR_STMICRO 0x20
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +02001019#define NAND_MFR_HYNIX 0xad
sshahrom@micron.com8c60e542007-03-21 18:48:02 -07001020#define NAND_MFR_MICRON 0x2c
Steven J. Hill30eb0db2007-07-18 23:29:46 -05001021#define NAND_MFR_AMD 0x01
Brian Norrisc1257b42011-11-02 13:34:42 -07001022#define NAND_MFR_MACRONIX 0xc2
Brian Norrisb1ccfab2012-05-22 07:30:47 -07001023#define NAND_MFR_EON 0x92
Huang Shijie3f97c6f2013-12-26 15:37:45 +08001024#define NAND_MFR_SANDISK 0x45
Huang Shijie4968a412014-01-03 16:50:39 +08001025#define NAND_MFR_INTEL 0x89
Brian Norris641519c2014-11-04 11:32:45 -08001026#define NAND_MFR_ATO 0x9b
Andrey Jr. Melnikova4077ce2016-12-08 19:57:08 +03001027#define NAND_MFR_WINBOND 0xef
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028
Artem Bityutskiy53552d22013-03-14 09:57:23 +02001029/* The maximum expected count of bytes in the NAND ID sequence */
1030#define NAND_MAX_ID_LEN 8
1031
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +02001032/*
1033 * A helper for defining older NAND chips where the second ID byte fully
1034 * defined the chip, including the geometry (chip size, eraseblock size, page
Artem Bityutskiy5bfa9b72013-03-19 10:29:26 +02001035 * size). All these chips have 512 bytes NAND page size.
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +02001036 */
Artem Bityutskiy5bfa9b72013-03-19 10:29:26 +02001037#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1038 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1039 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +02001040
1041/*
1042 * A helper for defining newer chips which report their page size and
1043 * eraseblock size via the extended ID bytes.
1044 *
1045 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1046 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1047 * device ID now only represented a particular total chip size (and voltage,
1048 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1049 * using the same device ID.
1050 */
Artem Bityutskiy8e12b472013-03-04 16:26:56 +02001051#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1052 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +02001053 .options = (opts) }
1054
Huang Shijie2dc0bdd2013-05-17 11:17:31 +08001055#define NAND_ECC_INFO(_strength, _step) \
1056 { .strength_ds = (_strength), .step_ds = (_step) }
1057#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1058#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1059
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060/**
1061 * struct nand_flash_dev - NAND Flash Device ID Structure
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001062 * @name: a human-readable name of the NAND chip
1063 * @dev_id: the device ID (the second byte of the full chip ID array)
Artem Bityutskiy8e12b472013-03-04 16:26:56 +02001064 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1065 * memory address as @id[0])
1066 * @dev_id: device ID part of the full chip ID array (refers the same memory
1067 * address as @id[1])
1068 * @id: full device ID array
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001069 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1070 * well as the eraseblock size) is determined from the extended NAND
1071 * chip ID array)
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001072 * @chipsize: total chip size in MiB
Artem Bityutskiyecb42fe2013-03-13 13:45:00 +02001073 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001074 * @options: stores various chip bit options
Huang Shijief22d5f62013-03-15 11:00:59 +08001075 * @id_len: The valid length of the @id.
1076 * @oobsize: OOB size
Randy Dunlap7b7d8982014-07-27 14:31:53 -07001077 * @ecc: ECC correctability and step information from the datasheet.
Huang Shijie2dc0bdd2013-05-17 11:17:31 +08001078 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1079 * @ecc_strength_ds in nand_chip{}.
1080 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1081 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1082 * For example, the "4bit ECC for each 512Byte" can be set with
1083 * NAND_ECC_INFO(4, 512).
Boris BREZILLON57a94e22014-09-22 20:11:50 +02001084 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1085 * reset. Should be deduced from timings described
1086 * in the datasheet.
1087 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 */
1089struct nand_flash_dev {
1090 char *name;
Artem Bityutskiy8e12b472013-03-04 16:26:56 +02001091 union {
1092 struct {
1093 uint8_t mfr_id;
1094 uint8_t dev_id;
1095 };
Artem Bityutskiy53552d22013-03-14 09:57:23 +02001096 uint8_t id[NAND_MAX_ID_LEN];
Artem Bityutskiy8e12b472013-03-04 16:26:56 +02001097 };
Artem Bityutskiyecb42fe2013-03-13 13:45:00 +02001098 unsigned int pagesize;
1099 unsigned int chipsize;
1100 unsigned int erasesize;
1101 unsigned int options;
Huang Shijief22d5f62013-03-15 11:00:59 +08001102 uint16_t id_len;
1103 uint16_t oobsize;
Huang Shijie2dc0bdd2013-05-17 11:17:31 +08001104 struct {
1105 uint16_t strength_ds;
1106 uint16_t step_ds;
1107 } ecc;
Boris BREZILLON57a94e22014-09-22 20:11:50 +02001108 int onfi_timing_mode_default;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109};
1110
1111/**
Boris Brezillon8cfb9ab2017-01-07 15:15:57 +01001112 * struct nand_manufacturer - NAND Flash Manufacturer structure
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 * @name: Manufacturer name
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +02001114 * @id: manufacturer ID code of device.
Boris Brezillonabbe26d2016-06-08 09:32:55 +02001115 * @ops: manufacturer operations
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116*/
Boris Brezillon8cfb9ab2017-01-07 15:15:57 +01001117struct nand_manufacturer {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 int id;
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +02001119 char *name;
Boris Brezillonabbe26d2016-06-08 09:32:55 +02001120 const struct nand_manufacturer_ops *ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121};
1122
Boris Brezillonbcc678c2017-01-07 15:48:25 +01001123const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1124
1125static inline const char *
1126nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1127{
1128 return manufacturer ? manufacturer->name : "Unknown";
1129}
1130
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131extern struct nand_flash_dev nand_flash_ids[];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132
Boris Brezillon9b2d61f2016-06-08 10:34:57 +02001133extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
Boris Brezillonc51d0ac2016-06-08 10:22:19 +02001134extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
Boris Brezillon01389b62016-06-08 10:30:18 +02001135extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
Boris Brezillon10d4e752016-06-08 10:38:57 +02001136extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
Boris Brezillon229204d2016-06-08 10:42:23 +02001137extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
Boris Brezillon3b5206f2016-06-08 10:43:26 +02001138extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
Boris Brezillonc51d0ac2016-06-08 10:22:19 +02001139
Sascha Hauer79022592016-09-07 14:21:42 +02001140int nand_default_bbt(struct mtd_info *mtd);
1141int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1142int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1143int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1144int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1145 int allowbbt);
1146int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1147 size_t *retlen, uint8_t *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Thomas Gleixner41796c22006-05-23 11:38:59 +02001149/**
1150 * struct platform_nand_chip - chip level device structure
Thomas Gleixner41796c22006-05-23 11:38:59 +02001151 * @nr_chips: max. number of chips to scan for
Randy Dunlap844d3b42006-06-28 21:48:27 -07001152 * @chip_offset: chip number offset
Thomas Gleixner8be834f2006-05-27 20:05:26 +02001153 * @nr_partitions: number of partitions pointed to by partitions (or zero)
Thomas Gleixner41796c22006-05-23 11:38:59 +02001154 * @partitions: mtd partition list
1155 * @chip_delay: R/B delay value in us
1156 * @options: Option flags, e.g. 16bit buswidth
Brian Norrisa40f7342011-05-31 16:31:22 -07001157 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
Vitaly Wool972edcb2007-05-06 18:46:57 +04001158 * @part_probe_types: NULL-terminated array of probe types
Thomas Gleixner41796c22006-05-23 11:38:59 +02001159 */
1160struct platform_nand_chip {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001161 int nr_chips;
1162 int chip_offset;
1163 int nr_partitions;
1164 struct mtd_partition *partitions;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001165 int chip_delay;
1166 unsigned int options;
Brian Norrisa40f7342011-05-31 16:31:22 -07001167 unsigned int bbt_options;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001168 const char **part_probe_types;
Thomas Gleixner41796c22006-05-23 11:38:59 +02001169};
1170
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -07001171/* Keep gcc happy */
1172struct platform_device;
1173
Thomas Gleixner41796c22006-05-23 11:38:59 +02001174/**
1175 * struct platform_nand_ctrl - controller level device structure
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -07001176 * @probe: platform specific function to probe/setup hardware
1177 * @remove: platform specific function to remove/teardown hardware
Thomas Gleixner41796c22006-05-23 11:38:59 +02001178 * @hwcontrol: platform specific hardware control structure
1179 * @dev_ready: platform specific function to read ready/busy pin
1180 * @select_chip: platform specific chip select function
Vitaly Wool972edcb2007-05-06 18:46:57 +04001181 * @cmd_ctrl: platform specific function for controlling
1182 * ALE/CLE/nCE. Also used to write command and address
Alexander Clouterd6fed9e2009-05-11 19:28:01 +01001183 * @write_buf: platform specific function for write buffer
1184 * @read_buf: platform specific function for read buffer
Randy Dunlap25806d32012-08-18 17:41:35 -07001185 * @read_byte: platform specific function to read one byte from chip
Randy Dunlap844d3b42006-06-28 21:48:27 -07001186 * @priv: private data to transport driver specific settings
Thomas Gleixner41796c22006-05-23 11:38:59 +02001187 *
1188 * All fields are optional and depend on the hardware driver requirements
1189 */
1190struct platform_nand_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001191 int (*probe)(struct platform_device *pdev);
1192 void (*remove)(struct platform_device *pdev);
1193 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1194 int (*dev_ready)(struct mtd_info *mtd);
1195 void (*select_chip)(struct mtd_info *mtd, int chip);
1196 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1197 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1198 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
John Crispinb4f7aa82012-04-30 19:30:47 +02001199 unsigned char (*read_byte)(struct mtd_info *mtd);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001200 void *priv;
Thomas Gleixner41796c22006-05-23 11:38:59 +02001201};
1202
Vitaly Wool972edcb2007-05-06 18:46:57 +04001203/**
1204 * struct platform_nand_data - container structure for platform-specific data
1205 * @chip: chip level chip structure
1206 * @ctrl: controller level device structure
1207 */
1208struct platform_nand_data {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +02001209 struct platform_nand_chip chip;
1210 struct platform_nand_ctrl ctrl;
Vitaly Wool972edcb2007-05-06 18:46:57 +04001211};
1212
Huang Shijie5b40db62013-05-17 11:17:28 +08001213/* return the supported features. */
1214static inline int onfi_feature(struct nand_chip *chip)
1215{
1216 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1217}
1218
Huang Shijie3e701922012-09-13 14:57:53 +08001219/* return the supported asynchronous timing mode. */
1220static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1221{
1222 if (!chip->onfi_version)
1223 return ONFI_TIMING_MODE_UNKNOWN;
1224 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1225}
1226
1227/* return the supported synchronous timing mode. */
1228static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1229{
1230 if (!chip->onfi_version)
1231 return ONFI_TIMING_MODE_UNKNOWN;
1232 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1233}
1234
Sascha Hauerb88730a2016-09-15 10:32:48 +02001235int onfi_init_data_interface(struct nand_chip *chip,
1236 struct nand_data_interface *iface,
1237 enum nand_data_interface_type type,
1238 int timing_mode);
1239
Huang Shijie1d0ed692013-09-25 14:58:10 +08001240/*
1241 * Check if it is a SLC nand.
1242 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1243 * We do not distinguish the MLC and TLC now.
1244 */
1245static inline bool nand_is_slc(struct nand_chip *chip)
1246{
Huang Shijie7db906b2013-09-25 14:58:11 +08001247 return chip->bits_per_cell == 1;
Huang Shijie1d0ed692013-09-25 14:58:10 +08001248}
Brian Norris3dad2342014-01-29 14:08:12 -08001249
1250/**
1251 * Check if the opcode's address should be sent only on the lower 8 bits
1252 * @command: opcode to check
1253 */
1254static inline int nand_opcode_8bits(unsigned int command)
1255{
David Mosbergere34fcb02014-03-21 16:05:10 -06001256 switch (command) {
1257 case NAND_CMD_READID:
1258 case NAND_CMD_PARAM:
1259 case NAND_CMD_GET_FEATURES:
1260 case NAND_CMD_SET_FEATURES:
1261 return 1;
1262 default:
1263 break;
1264 }
1265 return 0;
Brian Norris3dad2342014-01-29 14:08:12 -08001266}
1267
Huang Shijie7852f892014-02-21 13:39:39 +08001268/* return the supported JEDEC features. */
1269static inline int jedec_feature(struct nand_chip *chip)
1270{
1271 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1272 : 0;
1273}
Boris BREZILLONbb5fd0b2014-07-11 09:49:41 +02001274
Boris BREZILLON974647e2014-07-11 09:49:42 +02001275/* get timing characteristics from ONFI timing mode. */
1276const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
Sascha Hauer6e1f9702016-09-15 10:32:49 +02001277/* get data interface from ONFI timing mode 0, used after reset. */
1278const struct nand_data_interface *nand_get_default_data_interface(void);
Boris BREZILLON730a43f2015-09-03 18:03:38 +02001279
1280int nand_check_erased_ecc_chunk(void *data, int datalen,
1281 void *ecc, int ecclen,
1282 void *extraoob, int extraooblen,
1283 int threshold);
Boris Brezillon9d02fc22015-08-26 16:08:12 +02001284
Masahiro Yamada2c8f8af2017-06-07 20:52:10 +09001285int nand_check_ecc_caps(struct nand_chip *chip,
1286 const struct nand_ecc_caps *caps, int oobavail);
1287
1288int nand_match_ecc_req(struct nand_chip *chip,
1289 const struct nand_ecc_caps *caps, int oobavail);
1290
1291int nand_maximize_ecc(struct nand_chip *chip,
1292 const struct nand_ecc_caps *caps, int oobavail);
1293
Boris Brezillon9d02fc22015-08-26 16:08:12 +02001294/* Default write_oob implementation */
1295int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1296
1297/* Default write_oob syndrome implementation */
1298int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1299 int page);
1300
1301/* Default read_oob implementation */
1302int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1303
1304/* Default read_oob syndrome implementation */
1305int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1306 int page);
Sascha Hauer2f94abf2016-09-15 10:32:45 +02001307
Boris Brezillon4a78cc62017-05-26 17:10:15 +02001308/* Stub used by drivers that do not support GET/SET FEATURES operations */
1309int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd,
1310 struct nand_chip *chip, int addr,
1311 u8 *subfeature_param);
1312
Thomas Petazzonicc0f51e2017-04-29 11:06:44 +02001313/* Default read_page_raw implementation */
1314int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1315 uint8_t *buf, int oob_required, int page);
1316
1317/* Default write_page_raw implementation */
1318int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1319 const uint8_t *buf, int oob_required, int page);
1320
Sascha Hauer2f94abf2016-09-15 10:32:45 +02001321/* Reset and initialize a NAND device */
Boris Brezillon73f907f2016-10-24 16:46:20 +02001322int nand_reset(struct nand_chip *chip, int chipnr);
Sascha Hauer2f94abf2016-09-15 10:32:45 +02001323
Richard Weinbergerd44154f2016-09-21 11:44:41 +02001324/* Free resources held by the NAND device */
1325void nand_cleanup(struct nand_chip *chip);
1326
Boris Brezillonabbe26d2016-06-08 09:32:55 +02001327/* Default extended ID decoding function */
1328void nand_decode_ext_id(struct nand_chip *chip);
Boris Brezillond4092d72017-08-04 17:29:10 +02001329#endif /* __LINUX_MTD_RAWNAND_H */