blob: 1840350452084d64601a2dff44c63af8376565c0 [file] [log] [blame]
Roland Stigge2944a442012-06-07 12:22:15 +02001/*
2 * NXP LPC32XX NAND SLC driver
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright © 2011 NXP Semiconductors
9 * Copyright © 2012 Roland Stigge
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/delay.h>
31#include <linux/io.h>
32#include <linux/mm.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmaengine.h>
35#include <linux/mtd/nand_ecc.h>
36#include <linux/gpio.h>
37#include <linux/of.h>
38#include <linux/of_mtd.h>
39#include <linux/of_gpio.h>
Roland Stiggede20c222012-08-16 15:15:34 +020040#include <linux/mtd/lpc32xx_slc.h>
Roland Stigge2944a442012-06-07 12:22:15 +020041
42#define LPC32XX_MODNAME "lpc32xx-nand"
43
44/**********************************************************************
45* SLC NAND controller register offsets
46**********************************************************************/
47
48#define SLC_DATA(x) (x + 0x000)
49#define SLC_ADDR(x) (x + 0x004)
50#define SLC_CMD(x) (x + 0x008)
51#define SLC_STOP(x) (x + 0x00C)
52#define SLC_CTRL(x) (x + 0x010)
53#define SLC_CFG(x) (x + 0x014)
54#define SLC_STAT(x) (x + 0x018)
55#define SLC_INT_STAT(x) (x + 0x01C)
56#define SLC_IEN(x) (x + 0x020)
57#define SLC_ISR(x) (x + 0x024)
58#define SLC_ICR(x) (x + 0x028)
59#define SLC_TAC(x) (x + 0x02C)
60#define SLC_TC(x) (x + 0x030)
61#define SLC_ECC(x) (x + 0x034)
62#define SLC_DMA_DATA(x) (x + 0x038)
63
64/**********************************************************************
65* slc_ctrl register definitions
66**********************************************************************/
67#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
68#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
69#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
70
71/**********************************************************************
72* slc_cfg register definitions
73**********************************************************************/
74#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
75#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
76#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
77#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
78#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
79#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
80
81/**********************************************************************
82* slc_stat register definitions
83**********************************************************************/
84#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
85#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
86#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
87
88/**********************************************************************
89* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
90**********************************************************************/
91#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
92#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
93
94/**********************************************************************
95* slc_tac register definitions
96**********************************************************************/
97/* Clock setting for RDY write sample wait time in 2*n clocks */
98#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
99/* Write pulse width in clock cycles, 1 to 16 clocks */
100#define SLCTAC_WWIDTH(n) (((n) & 0xF) << 24)
101/* Write hold time of control and data signals, 1 to 16 clocks */
102#define SLCTAC_WHOLD(n) (((n) & 0xF) << 20)
103/* Write setup time of control and data signals, 1 to 16 clocks */
104#define SLCTAC_WSETUP(n) (((n) & 0xF) << 16)
105/* Clock setting for RDY read sample wait time in 2*n clocks */
106#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
107/* Read pulse width in clock cycles, 1 to 16 clocks */
108#define SLCTAC_RWIDTH(n) (((n) & 0xF) << 8)
109/* Read hold time of control and data signals, 1 to 16 clocks */
110#define SLCTAC_RHOLD(n) (((n) & 0xF) << 4)
111/* Read setup time of control and data signals, 1 to 16 clocks */
112#define SLCTAC_RSETUP(n) (((n) & 0xF) << 0)
113
114/**********************************************************************
115* slc_ecc register definitions
116**********************************************************************/
117/* ECC line party fetch macro */
118#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
119#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
120
121/*
122 * DMA requires storage space for the DMA local buffer and the hardware ECC
123 * storage area. The DMA local buffer is only used if DMA mapping fails
124 * during runtime.
125 */
126#define LPC32XX_DMA_DATA_SIZE 4096
127#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
128
129/* Number of bytes used for ECC stored in NAND per 256 bytes */
130#define LPC32XX_SLC_DEV_ECC_BYTES 3
131
132/*
133 * If the NAND base clock frequency can't be fetched, this frequency will be
134 * used instead as the base. This rate is used to setup the timing registers
135 * used for NAND accesses.
136 */
137#define LPC32XX_DEF_BUS_RATE 133250000
138
139/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
140#define LPC32XX_DMA_TIMEOUT 100
141
142/*
143 * NAND ECC Layout for small page NAND devices
144 * Note: For large and huge page devices, the default layouts are used
145 */
146static struct nand_ecclayout lpc32xx_nand_oob_16 = {
147 .eccbytes = 6,
148 .eccpos = {10, 11, 12, 13, 14, 15},
149 .oobfree = {
150 { .offset = 0, .length = 4 },
151 { .offset = 6, .length = 4 },
152 },
153};
154
155static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
156static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
157
158/*
159 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
160 * Note: Large page devices used the default layout
161 */
162static struct nand_bbt_descr bbt_smallpage_main_descr = {
163 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
164 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
165 .offs = 0,
166 .len = 4,
167 .veroffs = 6,
168 .maxblocks = 4,
169 .pattern = bbt_pattern
170};
171
172static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
173 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
174 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
175 .offs = 0,
176 .len = 4,
177 .veroffs = 6,
178 .maxblocks = 4,
179 .pattern = mirror_pattern
180};
181
182/*
183 * NAND platform configuration structure
184 */
185struct lpc32xx_nand_cfg_slc {
186 uint32_t wdr_clks;
187 uint32_t wwidth;
188 uint32_t whold;
189 uint32_t wsetup;
190 uint32_t rdr_clks;
191 uint32_t rwidth;
192 uint32_t rhold;
193 uint32_t rsetup;
194 bool use_bbt;
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200195 int wp_gpio;
Roland Stigge2944a442012-06-07 12:22:15 +0200196 struct mtd_partition *parts;
197 unsigned num_parts;
198};
199
200struct lpc32xx_nand_host {
201 struct nand_chip nand_chip;
Roland Stiggede20c222012-08-16 15:15:34 +0200202 struct lpc32xx_slc_platform_data *pdata;
Roland Stigge2944a442012-06-07 12:22:15 +0200203 struct clk *clk;
204 struct mtd_info mtd;
205 void __iomem *io_base;
206 struct lpc32xx_nand_cfg_slc *ncfg;
207
208 struct completion comp;
209 struct dma_chan *dma_chan;
210 uint32_t dma_buf_len;
211 struct dma_slave_config dma_slave_config;
212 struct scatterlist sgl;
213
214 /*
215 * DMA and CPU addresses of ECC work area and data buffer
216 */
217 uint32_t *ecc_buf;
218 uint8_t *data_buf;
219 dma_addr_t io_base_dma;
220};
221
222static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
223{
224 uint32_t clkrate, tmp;
225
226 /* Reset SLC controller */
227 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
228 udelay(1000);
229
230 /* Basic setup */
231 writel(0, SLC_CFG(host->io_base));
232 writel(0, SLC_IEN(host->io_base));
233 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
234 SLC_ICR(host->io_base));
235
236 /* Get base clock for SLC block */
237 clkrate = clk_get_rate(host->clk);
238 if (clkrate == 0)
239 clkrate = LPC32XX_DEF_BUS_RATE;
240
241 /* Compute clock setup values */
242 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
243 SLCTAC_WWIDTH(1 + (clkrate / host->ncfg->wwidth)) |
244 SLCTAC_WHOLD(1 + (clkrate / host->ncfg->whold)) |
245 SLCTAC_WSETUP(1 + (clkrate / host->ncfg->wsetup)) |
246 SLCTAC_RDR(host->ncfg->rdr_clks) |
247 SLCTAC_RWIDTH(1 + (clkrate / host->ncfg->rwidth)) |
248 SLCTAC_RHOLD(1 + (clkrate / host->ncfg->rhold)) |
249 SLCTAC_RSETUP(1 + (clkrate / host->ncfg->rsetup));
250 writel(tmp, SLC_TAC(host->io_base));
251}
252
253/*
254 * Hardware specific access to control lines
255 */
256static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
257 unsigned int ctrl)
258{
259 uint32_t tmp;
260 struct nand_chip *chip = mtd->priv;
261 struct lpc32xx_nand_host *host = chip->priv;
262
263 /* Does CE state need to be changed? */
264 tmp = readl(SLC_CFG(host->io_base));
265 if (ctrl & NAND_NCE)
266 tmp |= SLCCFG_CE_LOW;
267 else
268 tmp &= ~SLCCFG_CE_LOW;
269 writel(tmp, SLC_CFG(host->io_base));
270
271 if (cmd != NAND_CMD_NONE) {
272 if (ctrl & NAND_CLE)
273 writel(cmd, SLC_CMD(host->io_base));
274 else
275 writel(cmd, SLC_ADDR(host->io_base));
276 }
277}
278
279/*
280 * Read the Device Ready pin
281 */
282static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
283{
284 struct nand_chip *chip = mtd->priv;
285 struct lpc32xx_nand_host *host = chip->priv;
286 int rdy = 0;
287
288 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
289 rdy = 1;
290
291 return rdy;
292}
293
294/*
295 * Enable NAND write protect
296 */
297static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
298{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200299 if (gpio_is_valid(host->ncfg->wp_gpio))
300 gpio_set_value(host->ncfg->wp_gpio, 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200301}
302
303/*
304 * Disable NAND write protect
305 */
306static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
307{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200308 if (gpio_is_valid(host->ncfg->wp_gpio))
309 gpio_set_value(host->ncfg->wp_gpio, 1);
Roland Stigge2944a442012-06-07 12:22:15 +0200310}
311
312/*
313 * Prepares SLC for transfers with H/W ECC enabled
314 */
315static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
316{
317 /* Hardware ECC is enabled automatically in hardware as needed */
318}
319
320/*
321 * Calculates the ECC for the data
322 */
323static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
324 const unsigned char *buf,
325 unsigned char *code)
326{
327 /*
328 * ECC is calculated automatically in hardware during syndrome read
329 * and write operations, so it doesn't need to be calculated here.
330 */
331 return 0;
332}
333
334/*
335 * Read a single byte from NAND device
336 */
337static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
338{
339 struct nand_chip *chip = mtd->priv;
340 struct lpc32xx_nand_host *host = chip->priv;
341
342 return (uint8_t)readl(SLC_DATA(host->io_base));
343}
344
345/*
346 * Simple device read without ECC
347 */
348static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
349{
350 struct nand_chip *chip = mtd->priv;
351 struct lpc32xx_nand_host *host = chip->priv;
352
353 /* Direct device read with no ECC */
354 while (len-- > 0)
355 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
356}
357
358/*
359 * Simple device write without ECC
360 */
361static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
362{
363 struct nand_chip *chip = mtd->priv;
364 struct lpc32xx_nand_host *host = chip->priv;
365
366 /* Direct device write with no ECC */
367 while (len-- > 0)
368 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
369}
370
371/*
372 * Verify data in buffer to data on device
373 */
374static int lpc32xx_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
375{
376 struct nand_chip *chip = mtd->priv;
377 struct lpc32xx_nand_host *host = chip->priv;
378 int i;
379
380 /* DATA register must be read as 32 bits or it will fail */
381 for (i = 0; i < len; i++) {
382 if (buf[i] != (uint8_t)readl(SLC_DATA(host->io_base)))
383 return -EFAULT;
384 }
385
386 return 0;
387}
388
389/*
390 * Read the OOB data from the device without ECC using FIFO method
391 */
392static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
393 struct nand_chip *chip, int page)
394{
395 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
396 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
397
398 return 0;
399}
400
401/*
402 * Write the OOB data to the device without ECC using FIFO method
403 */
404static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
405 struct nand_chip *chip, int page)
406{
407 int status;
408
409 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
410 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
411
412 /* Send command to program the OOB data */
413 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
414
415 status = chip->waitfunc(mtd, chip);
416
417 return status & NAND_STATUS_FAIL ? -EIO : 0;
418}
419
420/*
421 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
422 */
423static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
424{
425 int i;
426
427 for (i = 0; i < (count * 3); i += 3) {
428 uint32_t ce = ecc[i / 3];
429 ce = ~(ce << 2) & 0xFFFFFF;
430 spare[i + 2] = (uint8_t)(ce & 0xFF);
431 ce >>= 8;
432 spare[i + 1] = (uint8_t)(ce & 0xFF);
433 ce >>= 8;
434 spare[i] = (uint8_t)(ce & 0xFF);
435 }
436}
437
438static void lpc32xx_dma_complete_func(void *completion)
439{
440 complete(completion);
441}
442
443static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
444 void *mem, int len, enum dma_transfer_direction dir)
445{
446 struct nand_chip *chip = mtd->priv;
447 struct lpc32xx_nand_host *host = chip->priv;
448 struct dma_async_tx_descriptor *desc;
449 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
450 int res;
451
452 host->dma_slave_config.direction = dir;
453 host->dma_slave_config.src_addr = dma;
454 host->dma_slave_config.dst_addr = dma;
455 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
456 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
457 host->dma_slave_config.src_maxburst = 4;
458 host->dma_slave_config.dst_maxburst = 4;
459 /* DMA controller does flow control: */
460 host->dma_slave_config.device_fc = false;
461 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
462 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
463 return -ENXIO;
464 }
465
466 sg_init_one(&host->sgl, mem, len);
467
468 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
469 DMA_BIDIRECTIONAL);
470 if (res != 1) {
471 dev_err(mtd->dev.parent, "Failed to map sg list\n");
472 return -ENXIO;
473 }
474 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
475 flags);
476 if (!desc) {
477 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
478 goto out1;
479 }
480
481 init_completion(&host->comp);
482 desc->callback = lpc32xx_dma_complete_func;
483 desc->callback_param = &host->comp;
484
485 dmaengine_submit(desc);
486 dma_async_issue_pending(host->dma_chan);
487
488 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
489
490 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
491 DMA_BIDIRECTIONAL);
492
493 return 0;
494out1:
495 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
496 DMA_BIDIRECTIONAL);
497 return -ENXIO;
498}
499
500/*
501 * DMA read/write transfers with ECC support
502 */
503static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
504 int read)
505{
506 struct nand_chip *chip = mtd->priv;
507 struct lpc32xx_nand_host *host = chip->priv;
508 int i, status = 0;
509 unsigned long timeout;
510 int res;
511 enum dma_transfer_direction dir =
512 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
513 uint8_t *dma_buf;
514 bool dma_mapped;
515
516 if ((void *)buf <= high_memory) {
517 dma_buf = buf;
518 dma_mapped = true;
519 } else {
520 dma_buf = host->data_buf;
521 dma_mapped = false;
522 if (!read)
523 memcpy(host->data_buf, buf, mtd->writesize);
524 }
525
526 if (read) {
527 writel(readl(SLC_CFG(host->io_base)) |
528 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
529 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
530 } else {
531 writel((readl(SLC_CFG(host->io_base)) |
532 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
533 ~SLCCFG_DMA_DIR,
534 SLC_CFG(host->io_base));
535 }
536
537 /* Clear initial ECC */
538 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
539
540 /* Transfer size is data area only */
541 writel(mtd->writesize, SLC_TC(host->io_base));
542
543 /* Start transfer in the NAND controller */
544 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
545 SLC_CTRL(host->io_base));
546
547 for (i = 0; i < chip->ecc.steps; i++) {
548 /* Data */
549 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
550 dma_buf + i * chip->ecc.size,
551 mtd->writesize / chip->ecc.steps, dir);
552 if (res)
553 return res;
554
555 /* Always _read_ ECC */
556 if (i == chip->ecc.steps - 1)
557 break;
558 if (!read) /* ECC availability delayed on write */
559 udelay(10);
560 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
561 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
562 if (res)
563 return res;
564 }
565
566 /*
567 * According to NXP, the DMA can be finished here, but the NAND
568 * controller may still have buffered data. After porting to using the
569 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
570 * appears to be always true, according to tests. Keeping the check for
571 * safety reasons for now.
572 */
573 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
574 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
575 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
576 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
577 time_before(jiffies, timeout))
578 cpu_relax();
579 if (!time_before(jiffies, timeout)) {
580 dev_err(mtd->dev.parent, "FIFO held data too long\n");
581 status = -EIO;
582 }
583 }
584
585 /* Read last calculated ECC value */
586 if (!read)
587 udelay(10);
588 host->ecc_buf[chip->ecc.steps - 1] =
589 readl(SLC_ECC(host->io_base));
590
591 /* Flush DMA */
592 dmaengine_terminate_all(host->dma_chan);
593
594 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
595 readl(SLC_TC(host->io_base))) {
596 /* Something is left in the FIFO, something is wrong */
597 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
598 status = -EIO;
599 }
600
601 /* Stop DMA & HW ECC */
602 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
603 SLC_CTRL(host->io_base));
604 writel(readl(SLC_CFG(host->io_base)) &
605 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
606 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
607
608 if (!dma_mapped && read)
609 memcpy(buf, host->data_buf, mtd->writesize);
610
611 return status;
612}
613
614/*
615 * Read the data and OOB data from the device, use ECC correction with the
616 * data, disable ECC for the OOB data
617 */
618static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
619 struct nand_chip *chip, uint8_t *buf,
620 int oob_required, int page)
621{
622 struct lpc32xx_nand_host *host = chip->priv;
623 int stat, i, status;
624 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
625
626 /* Issue read command */
627 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
628
629 /* Read data and oob, calculate ECC */
630 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
631
632 /* Get OOB data */
633 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
634
635 /* Convert to stored ECC format */
636 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
637
638 /* Pointer to ECC data retrieved from NAND spare area */
639 oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0];
640
641 for (i = 0; i < chip->ecc.steps; i++) {
642 stat = chip->ecc.correct(mtd, buf, oobecc,
643 &tmpecc[i * chip->ecc.bytes]);
644 if (stat < 0)
645 mtd->ecc_stats.failed++;
646 else
647 mtd->ecc_stats.corrected += stat;
648
649 buf += chip->ecc.size;
650 oobecc += chip->ecc.bytes;
651 }
652
653 return status;
654}
655
656/*
657 * Read the data and OOB data from the device, no ECC correction with the
658 * data or OOB data
659 */
660static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
661 struct nand_chip *chip,
662 uint8_t *buf, int oob_required,
663 int page)
664{
665 /* Issue read command */
666 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
667
668 /* Raw reads can just use the FIFO interface */
669 chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
670 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
671
672 return 0;
673}
674
675/*
676 * Write the data and OOB data to the device, use ECC with the data,
677 * disable ECC for the OOB data
678 */
679static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
680 struct nand_chip *chip,
681 const uint8_t *buf, int oob_required)
682{
683 struct lpc32xx_nand_host *host = chip->priv;
684 uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
685 int error;
686
687 /* Write data, calculate ECC on outbound data */
688 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
689 if (error)
690 return error;
691
692 /*
693 * The calculated ECC needs some manual work done to it before
694 * committing it to NAND. Process the calculated ECC and place
695 * the resultant values directly into the OOB buffer. */
696 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
697
698 /* Write ECC data to device */
699 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
700 return 0;
701}
702
703/*
704 * Write the data and OOB data to the device, no ECC correction with the
705 * data or OOB data
706 */
707static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
708 struct nand_chip *chip,
709 const uint8_t *buf,
710 int oob_required)
711{
712 /* Raw writes can just use the FIFO interface */
713 chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
714 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
715 return 0;
716}
717
Roland Stigge2944a442012-06-07 12:22:15 +0200718static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
719{
720 struct mtd_info *mtd = &host->mtd;
721 dma_cap_mask_t mask;
722
Roland Stiggede20c222012-08-16 15:15:34 +0200723 if (!host->pdata || !host->pdata->dma_filter) {
724 dev_err(mtd->dev.parent, "no DMA platform data\n");
725 return -ENOENT;
726 }
727
Roland Stigge2944a442012-06-07 12:22:15 +0200728 dma_cap_zero(mask);
729 dma_cap_set(DMA_SLAVE, mask);
Roland Stiggede20c222012-08-16 15:15:34 +0200730 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
731 "nand-slc");
Roland Stigge2944a442012-06-07 12:22:15 +0200732 if (!host->dma_chan) {
733 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
734 return -EBUSY;
735 }
736
737 return 0;
738}
739
740#ifdef CONFIG_OF
741static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
742{
743 struct lpc32xx_nand_cfg_slc *pdata;
744 struct device_node *np = dev->of_node;
745
746 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
747 if (!pdata) {
748 dev_err(dev, "could not allocate memory for platform data\n");
749 return NULL;
750 }
751
752 of_property_read_u32(np, "nxp,wdr-clks", &pdata->wdr_clks);
753 of_property_read_u32(np, "nxp,wwidth", &pdata->wwidth);
754 of_property_read_u32(np, "nxp,whold", &pdata->whold);
755 of_property_read_u32(np, "nxp,wsetup", &pdata->wsetup);
756 of_property_read_u32(np, "nxp,rdr-clks", &pdata->rdr_clks);
757 of_property_read_u32(np, "nxp,rwidth", &pdata->rwidth);
758 of_property_read_u32(np, "nxp,rhold", &pdata->rhold);
759 of_property_read_u32(np, "nxp,rsetup", &pdata->rsetup);
760
761 if (!pdata->wdr_clks || !pdata->wwidth || !pdata->whold ||
762 !pdata->wsetup || !pdata->rdr_clks || !pdata->rwidth ||
763 !pdata->rhold || !pdata->rsetup) {
764 dev_err(dev, "chip parameters not specified correctly\n");
765 return NULL;
766 }
767
768 pdata->use_bbt = of_get_nand_on_flash_bbt(np);
Roland Stigge21535ab2012-06-27 17:51:14 +0200769 pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200770
771 return pdata;
772}
773#else
774static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
775{
776 return NULL;
777}
778#endif
779
780/*
781 * Probe for NAND controller
782 */
783static int __devinit lpc32xx_nand_probe(struct platform_device *pdev)
784{
785 struct lpc32xx_nand_host *host;
786 struct mtd_info *mtd;
787 struct nand_chip *chip;
788 struct resource *rc;
789 struct mtd_part_parser_data ppdata = {};
790 int res;
791
792 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
793 if (rc == NULL) {
794 dev_err(&pdev->dev, "No memory resource found for device\n");
795 return -EBUSY;
796 }
797
798 /* Allocate memory for the device structure (and zero it) */
799 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
800 if (!host) {
801 dev_err(&pdev->dev, "failed to allocate device structure\n");
802 return -ENOMEM;
803 }
804 host->io_base_dma = rc->start;
805
806 host->io_base = devm_request_and_ioremap(&pdev->dev, rc);
807 if (host->io_base == NULL) {
808 dev_err(&pdev->dev, "ioremap failed\n");
809 return -ENOMEM;
810 }
811
812 if (pdev->dev.of_node)
813 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
814 else
815 host->ncfg = pdev->dev.platform_data;
816 if (!host->ncfg) {
817 dev_err(&pdev->dev, "Missing platform data\n");
818 return -ENOENT;
819 }
Roland Stigged5842ab2012-06-27 17:51:15 +0200820 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
821 return -EPROBE_DEFER;
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200822 if (gpio_is_valid(host->ncfg->wp_gpio) &&
823 gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
Roland Stigge2944a442012-06-07 12:22:15 +0200824 dev_err(&pdev->dev, "GPIO not available\n");
825 return -EBUSY;
826 }
827 lpc32xx_wp_disable(host);
828
Roland Stiggede20c222012-08-16 15:15:34 +0200829 host->pdata = pdev->dev.platform_data;
830
Roland Stigge2944a442012-06-07 12:22:15 +0200831 mtd = &host->mtd;
832 chip = &host->nand_chip;
833 chip->priv = host;
834 mtd->priv = chip;
835 mtd->owner = THIS_MODULE;
836 mtd->dev.parent = &pdev->dev;
837
838 /* Get NAND clock */
839 host->clk = clk_get(&pdev->dev, NULL);
840 if (IS_ERR(host->clk)) {
841 dev_err(&pdev->dev, "Clock failure\n");
842 res = -ENOENT;
843 goto err_exit1;
844 }
845 clk_enable(host->clk);
846
847 /* Set NAND IO addresses and command/ready functions */
848 chip->IO_ADDR_R = SLC_DATA(host->io_base);
849 chip->IO_ADDR_W = SLC_DATA(host->io_base);
850 chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
851 chip->dev_ready = lpc32xx_nand_device_ready;
852 chip->chip_delay = 20; /* 20us command delay time */
853
854 /* Init NAND controller */
855 lpc32xx_nand_setup(host);
856
857 platform_set_drvdata(pdev, host);
858
859 /* NAND callbacks for LPC32xx SLC hardware */
860 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
861 chip->read_byte = lpc32xx_nand_read_byte;
862 chip->read_buf = lpc32xx_nand_read_buf;
863 chip->write_buf = lpc32xx_nand_write_buf;
864 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
865 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
866 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
867 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
868 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
869 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
870 chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
871 chip->ecc.correct = nand_correct_data;
872 chip->ecc.strength = 1;
873 chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
874 chip->verify_buf = lpc32xx_verify_buf;
875
876 /* bitflip_threshold's default is defined as ecc_strength anyway.
877 * Unfortunately, it is set only later at add_mtd_device(). Meanwhile
878 * being 0, it causes bad block table scanning errors in
879 * nand_scan_tail(), so preparing it here already. */
880 mtd->bitflip_threshold = chip->ecc.strength;
881
882 /*
883 * Allocate a large enough buffer for a single huge page plus
884 * extra space for the spare area and ECC storage area
885 */
886 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
887 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
888 GFP_KERNEL);
889 if (host->data_buf == NULL) {
890 dev_err(&pdev->dev, "Error allocating memory\n");
891 res = -ENOMEM;
892 goto err_exit2;
893 }
894
895 res = lpc32xx_nand_dma_setup(host);
896 if (res) {
897 res = -EIO;
898 goto err_exit2;
899 }
900
901 /* Find NAND device */
902 if (nand_scan_ident(mtd, 1, NULL)) {
903 res = -ENXIO;
904 goto err_exit3;
905 }
906
907 /* OOB and ECC CPU and DMA work areas */
908 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
909
910 /*
911 * Small page FLASH has a unique OOB layout, but large and huge
912 * page FLASH use the standard layout. Small page FLASH uses a
913 * custom BBT marker layout.
914 */
915 if (mtd->writesize <= 512)
916 chip->ecc.layout = &lpc32xx_nand_oob_16;
917
918 /* These sizes remain the same regardless of page size */
919 chip->ecc.size = 256;
920 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
921 chip->ecc.prepad = chip->ecc.postpad = 0;
922
923 /* Avoid extra scan if using BBT, setup BBT support */
924 if (host->ncfg->use_bbt) {
925 chip->options |= NAND_SKIP_BBTSCAN;
926 chip->bbt_options |= NAND_BBT_USE_FLASH;
927
928 /*
929 * Use a custom BBT marker setup for small page FLASH that
930 * won't interfere with the ECC layout. Large and huge page
931 * FLASH use the standard layout.
932 */
933 if (mtd->writesize <= 512) {
934 chip->bbt_td = &bbt_smallpage_main_descr;
935 chip->bbt_md = &bbt_smallpage_mirror_descr;
936 }
937 }
938
939 /*
940 * Fills out all the uninitialized function pointers with the defaults
941 */
942 if (nand_scan_tail(mtd)) {
943 res = -ENXIO;
944 goto err_exit3;
945 }
946
947 /* Standard layout in FLASH for bad block tables */
948 if (host->ncfg->use_bbt) {
949 if (nand_default_bbt(mtd) < 0)
950 dev_err(&pdev->dev,
951 "Error initializing default bad block tables\n");
952 }
953
954 mtd->name = "nxp_lpc3220_slc";
955 ppdata.of_node = pdev->dev.of_node;
956 res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
957 host->ncfg->num_parts);
958 if (!res)
959 return res;
960
961 nand_release(mtd);
962
963err_exit3:
964 dma_release_channel(host->dma_chan);
965err_exit2:
966 clk_disable(host->clk);
967 clk_put(host->clk);
968 platform_set_drvdata(pdev, NULL);
969err_exit1:
970 lpc32xx_wp_enable(host);
971 gpio_free(host->ncfg->wp_gpio);
972
973 return res;
974}
975
976/*
977 * Remove NAND device.
978 */
979static int __devexit lpc32xx_nand_remove(struct platform_device *pdev)
980{
981 uint32_t tmp;
982 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
983 struct mtd_info *mtd = &host->mtd;
984
985 nand_release(mtd);
986 dma_release_channel(host->dma_chan);
987
988 /* Force CE high */
989 tmp = readl(SLC_CTRL(host->io_base));
990 tmp &= ~SLCCFG_CE_LOW;
991 writel(tmp, SLC_CTRL(host->io_base));
992
993 clk_disable(host->clk);
994 clk_put(host->clk);
995 platform_set_drvdata(pdev, NULL);
996 lpc32xx_wp_enable(host);
997 gpio_free(host->ncfg->wp_gpio);
998
999 return 0;
1000}
1001
1002#ifdef CONFIG_PM
1003static int lpc32xx_nand_resume(struct platform_device *pdev)
1004{
1005 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1006
1007 /* Re-enable NAND clock */
1008 clk_enable(host->clk);
1009
1010 /* Fresh init of NAND controller */
1011 lpc32xx_nand_setup(host);
1012
1013 /* Disable write protect */
1014 lpc32xx_wp_disable(host);
1015
1016 return 0;
1017}
1018
1019static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
1020{
1021 uint32_t tmp;
1022 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1023
1024 /* Force CE high */
1025 tmp = readl(SLC_CTRL(host->io_base));
1026 tmp &= ~SLCCFG_CE_LOW;
1027 writel(tmp, SLC_CTRL(host->io_base));
1028
1029 /* Enable write protect for safety */
1030 lpc32xx_wp_enable(host);
1031
1032 /* Disable clock */
1033 clk_disable(host->clk);
1034
1035 return 0;
1036}
1037
1038#else
1039#define lpc32xx_nand_resume NULL
1040#define lpc32xx_nand_suspend NULL
1041#endif
1042
1043#if defined(CONFIG_OF)
1044static const struct of_device_id lpc32xx_nand_match[] = {
1045 { .compatible = "nxp,lpc3220-slc" },
1046 { /* sentinel */ },
1047};
1048MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1049#endif
1050
1051static struct platform_driver lpc32xx_nand_driver = {
1052 .probe = lpc32xx_nand_probe,
1053 .remove = __devexit_p(lpc32xx_nand_remove),
1054 .resume = lpc32xx_nand_resume,
1055 .suspend = lpc32xx_nand_suspend,
1056 .driver = {
1057 .name = LPC32XX_MODNAME,
1058 .owner = THIS_MODULE,
1059 .of_match_table = of_match_ptr(lpc32xx_nand_match),
1060 },
1061};
1062
1063module_platform_driver(lpc32xx_nand_driver);
1064
1065MODULE_LICENSE("GPL");
1066MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1067MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1068MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");