Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 1 | /* |
| 2 | * dmx.h |
| 3 | * |
| 4 | * Copyright (C) 2000 Marcus Metzler <marcus@convergence.de> |
| 5 | * & Ralph Metzler <ralph@convergence.de> |
| 6 | * for convergence integrated media GmbH |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU Lesser General Public License |
| 10 | * as published by the Free Software Foundation; either version 2.1 |
| 11 | * of the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU Lesser General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #ifndef _UAPI_DVBDMX_H_ |
| 25 | #define _UAPI_DVBDMX_H_ |
| 26 | |
| 27 | #include <linux/types.h> |
| 28 | #include <asm/ioctl.h> |
| 29 | #ifndef __KERNEL__ |
| 30 | #include <time.h> |
| 31 | #endif |
| 32 | |
| 33 | #define CONFIG_AMLOGIC_DVB_COMPAT |
| 34 | #define DMX_FILTER_SIZE 16 |
| 35 | |
| 36 | enum dmx_output |
| 37 | { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 38 | DMX_OUT_DECODER, /* Streaming directly to decoder. */ |
| 39 | DMX_OUT_TAP, /* Output going to a memory buffer */ |
| 40 | /* (to be retrieved via the read command).*/ |
| 41 | DMX_OUT_TS_TAP, /* Output multiplexed into a new TS */ |
| 42 | /* (to be retrieved by reading from the */ |
| 43 | /* logical DVR device). */ |
| 44 | DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */ |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | typedef enum dmx_output dmx_output_t; |
| 48 | |
| 49 | typedef enum dmx_input |
| 50 | { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 51 | DMX_IN_FRONTEND, /* Input from a front-end device. */ |
| 52 | DMX_IN_DVR /* Input from the logical DVR device. */ |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 53 | } dmx_input_t; |
| 54 | |
| 55 | |
| 56 | typedef enum dmx_ts_pes |
| 57 | { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 58 | DMX_PES_AUDIO0, |
| 59 | DMX_PES_VIDEO0, |
| 60 | DMX_PES_TELETEXT0, |
| 61 | DMX_PES_SUBTITLE0, |
| 62 | DMX_PES_PCR0, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 63 | |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 64 | DMX_PES_AUDIO1, |
| 65 | DMX_PES_VIDEO1, |
| 66 | DMX_PES_TELETEXT1, |
| 67 | DMX_PES_SUBTITLE1, |
| 68 | DMX_PES_PCR1, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 69 | |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 70 | DMX_PES_AUDIO2, |
| 71 | DMX_PES_VIDEO2, |
| 72 | DMX_PES_TELETEXT2, |
| 73 | DMX_PES_SUBTITLE2, |
| 74 | DMX_PES_PCR2, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 75 | |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 76 | DMX_PES_AUDIO3, |
| 77 | DMX_PES_VIDEO3, |
| 78 | DMX_PES_TELETEXT3, |
| 79 | DMX_PES_SUBTITLE3, |
| 80 | DMX_PES_PCR3, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 81 | |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 82 | DMX_PES_OTHER |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 83 | } dmx_pes_type_t; |
| 84 | |
| 85 | #define DMX_PES_AUDIO DMX_PES_AUDIO0 |
| 86 | #define DMX_PES_VIDEO DMX_PES_VIDEO0 |
| 87 | #define DMX_PES_TELETEXT DMX_PES_TELETEXT0 |
| 88 | #define DMX_PES_SUBTITLE DMX_PES_SUBTITLE0 |
| 89 | #define DMX_PES_PCR DMX_PES_PCR0 |
| 90 | |
| 91 | |
| 92 | typedef struct dmx_filter |
| 93 | { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 94 | __u8 filter[DMX_FILTER_SIZE]; |
| 95 | __u8 mask[DMX_FILTER_SIZE]; |
| 96 | __u8 mode[DMX_FILTER_SIZE]; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 97 | } dmx_filter_t; |
| 98 | |
| 99 | |
| 100 | struct dmx_sct_filter_params |
| 101 | { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 102 | __u16 pid; |
| 103 | dmx_filter_t filter; |
| 104 | __u32 timeout; |
| 105 | __u32 flags; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 106 | #define DMX_CHECK_CRC 1 |
| 107 | #define DMX_ONESHOT 2 |
| 108 | #define DMX_IMMEDIATE_START 4 |
| 109 | #define DMX_KERNEL_CLIENT 0x8000 |
| 110 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
| 111 | #define DMX_USE_SWFILTER 0x100 |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 112 | |
| 113 | /*bit 8~15 for mem sec_level*/ |
| 114 | #define DMX_MEM_SEC_LEVEL1 (1 << 10) |
| 115 | #define DMX_MEM_SEC_LEVEL2 (1 << 11) |
| 116 | #define DMX_MEM_SEC_LEVEL3 (1 << 12) |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 117 | #endif |
| 118 | }; |
| 119 | |
| 120 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
| 121 | |
| 122 | enum dmx_input_source { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 123 | INPUT_DEMOD, |
| 124 | INPUT_LOCAL, |
| 125 | INPUT_LOCAL_SEC |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | /** |
| 129 | * struct dmx_non_sec_es_header - non-sec Elementary Stream (ES) Header |
| 130 | * |
| 131 | * @pts_dts_flag:[1:0], 01:pts valid, 10:dts valid |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 132 | * @pts: pts value |
| 133 | * @dts: dts value |
| 134 | * @len: data len |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 135 | */ |
| 136 | struct dmx_non_sec_es_header { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 137 | __u8 pts_dts_flag; |
| 138 | __u64 pts; |
| 139 | __u64 dts; |
| 140 | __u32 len; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * struct dmx_sec_es_data - sec Elementary Stream (ES) |
| 145 | * |
| 146 | * @pts_dts_flag:[1:0], 01:pts valid, 10:dts valid |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 147 | * @pts: pts value |
| 148 | * @dts: dts value |
| 149 | * @buf_start: buf start addr |
| 150 | * @buf_end: buf end addr |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 151 | * @data_start: data start addr |
| 152 | * @data_end: data end addr |
| 153 | */ |
| 154 | struct dmx_sec_es_data { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 155 | __u8 pts_dts_flag; |
| 156 | __u64 pts; |
| 157 | __u64 dts; |
| 158 | __u32 buf_start; |
| 159 | __u32 buf_end; |
| 160 | __u32 data_start; |
| 161 | __u32 data_end; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 162 | }; |
| 163 | |
hualing chen | f986740 | 2020-09-23 17:06:20 +0800 | [diff] [blame] | 164 | struct dmx_sec_ts_data { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 165 | __u32 buf_start; |
| 166 | __u32 buf_end; |
| 167 | __u32 data_start; |
| 168 | __u32 data_end; |
hualing chen | f986740 | 2020-09-23 17:06:20 +0800 | [diff] [blame] | 169 | }; |
| 170 | |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 171 | enum dmx_audio_format { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 172 | AUDIO_UNKNOWN = 0, /* unknown media */ |
| 173 | AUDIO_MPX = 1, /* mpeg audio MP2/MP3 */ |
| 174 | AUDIO_AC3 = 2, /* Dolby AC3/EAC3 */ |
| 175 | AUDIO_AAC_ADTS = 3, /* AAC-ADTS */ |
| 176 | AUDIO_AAC_LOAS = 4, /* AAC-LOAS */ |
| 177 | AUDIO_DTS = 5, /* DTS */ |
| 178 | AUDIO_MAX |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | struct dmx_mem_info { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 182 | __u32 dmx_total_size; |
| 183 | __u32 dmx_buf_phy_start; |
| 184 | __u32 dmx_free_size; |
| 185 | __u32 dvb_core_total_size; |
| 186 | __u32 dvb_core_free_size; |
| 187 | __u32 wp_offset; |
| 188 | __u64 newest_pts; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 189 | }; |
| 190 | |
hualing chen | f986740 | 2020-09-23 17:06:20 +0800 | [diff] [blame] | 191 | struct dmx_sec_mem { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 192 | __u32 buff; |
| 193 | __u32 size; |
hualing chen | f986740 | 2020-09-23 17:06:20 +0800 | [diff] [blame] | 194 | }; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 195 | #endif |
| 196 | |
| 197 | /** |
| 198 | * struct dmx_pes_filter_params - Specifies Packetized Elementary Stream (PES) |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 199 | * filter parameters. |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 200 | * |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 201 | * @pid: PID to be filtered. |
| 202 | * @input: Demux input, as specified by &enum dmx_input. |
| 203 | * @output: Demux output, as specified by &enum dmx_output. |
| 204 | * @pes_type: Type of the pes filter, as specified by &enum dmx_pes_type. |
| 205 | * @flags: Demux PES flags. |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 206 | */ |
| 207 | struct dmx_pes_filter_params { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 208 | __u16 pid; |
| 209 | dmx_input_t input; |
| 210 | dmx_output_t output; |
| 211 | dmx_pes_type_t pes_type; |
| 212 | __u32 flags; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 213 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
| 214 | /*bit 8~15 for mem sec_level*/ |
| 215 | #define DMX_MEM_SEC_LEVEL1 (1 << 10) |
| 216 | #define DMX_MEM_SEC_LEVEL2 (1 << 11) |
| 217 | #define DMX_MEM_SEC_LEVEL3 (1 << 12) |
| 218 | |
| 219 | /*bit 16~23 for output */ |
| 220 | #define DMX_ES_OUTPUT (1 << 16) |
| 221 | /*set raw mode, it will send the struct dmx_sec_es_data, not es data*/ |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 222 | #define DMX_OUTPUT_RAW_MODE (1 << 17) |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 223 | |
| 224 | /*24~31 one byte for audio type, dmx_audio_format_t*/ |
| 225 | #define DMX_AUDIO_FORMAT_BIT 24 |
| 226 | |
| 227 | #endif |
| 228 | }; |
| 229 | |
| 230 | typedef struct dmx_caps { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 231 | __u32 caps; |
| 232 | int num_decoders; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 233 | } dmx_caps_t; |
| 234 | |
| 235 | typedef enum dmx_source { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 236 | DMX_SOURCE_FRONT0 = 0, |
| 237 | DMX_SOURCE_FRONT1, |
| 238 | DMX_SOURCE_FRONT2, |
| 239 | DMX_SOURCE_FRONT3, |
| 240 | DMX_SOURCE_DVR0 = 16, |
| 241 | DMX_SOURCE_DVR1, |
| 242 | DMX_SOURCE_DVR2, |
| 243 | DMX_SOURCE_DVR3, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 244 | |
| 245 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 246 | DMX_SOURCE_FRONT0_OFFSET = 100, |
| 247 | DMX_SOURCE_FRONT1_OFFSET, |
| 248 | DMX_SOURCE_FRONT2_OFFSET |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 249 | #endif |
| 250 | } dmx_source_t; |
| 251 | |
| 252 | struct dmx_stc { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 253 | unsigned int num; /* input : which STC? 0..N */ |
| 254 | unsigned int base; /* output: divisor for stc to get 90 kHz clock */ |
| 255 | __u64 stc; /* output: stc in 'base'*90 kHz units */ |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
| 259 | enum { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 260 | DMA_0 = 0, |
| 261 | DMA_1, |
| 262 | DMA_2, |
| 263 | DMA_3, |
| 264 | DMA_4, |
| 265 | DMA_5, |
| 266 | DMA_6, |
| 267 | DMA_7, |
| 268 | FRONTEND_TS0 = 32, |
| 269 | FRONTEND_TS1, |
| 270 | FRONTEND_TS2, |
| 271 | FRONTEND_TS3, |
| 272 | FRONTEND_TS4, |
| 273 | FRONTEND_TS5, |
| 274 | FRONTEND_TS6, |
| 275 | FRONTEND_TS7, |
| 276 | DMA_0_1 = 64, |
| 277 | DMA_1_1, |
| 278 | DMA_2_1, |
| 279 | DMA_3_1, |
| 280 | DMA_4_1, |
| 281 | DMA_5_1, |
| 282 | DMA_6_1, |
| 283 | DMA_7_1, |
| 284 | FRONTEND_TS0_1 = 96, |
| 285 | FRONTEND_TS1_1, |
| 286 | FRONTEND_TS2_1, |
| 287 | FRONTEND_TS3_1, |
| 288 | FRONTEND_TS4_1, |
| 289 | FRONTEND_TS5_1, |
| 290 | FRONTEND_TS6_1, |
| 291 | FRONTEND_TS7_1, |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 292 | }; |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 293 | |
| 294 | /*define filter mem_info type*/ |
| 295 | enum { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 296 | DMX_VIDEO_TYPE = 0, |
| 297 | DMX_AUDIO_TYPE, |
| 298 | DMX_SUBTITLE_TYPE, |
| 299 | DMX_TELETEXT_TYPE, |
| 300 | DMX_SECTION_TYPE, |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | struct filter_mem_info { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 304 | __u32 type; |
| 305 | __u32 pid; |
| 306 | struct dmx_mem_info filter_info; |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 307 | }; |
| 308 | |
| 309 | struct dmx_filter_mem_info { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 310 | __u32 filter_num; |
| 311 | struct filter_mem_info info[40]; |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 312 | }; |
| 313 | |
| 314 | struct dvr_mem_info { |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 315 | __u32 wp_offset; |
Yahui Han | ce15e9c | 2020-12-08 18:08:32 +0800 | [diff] [blame] | 316 | }; |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 317 | #endif |
| 318 | |
| 319 | #define DMX_START _IO('o', 41) |
| 320 | #define DMX_STOP _IO('o', 42) |
| 321 | #define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params) |
| 322 | #define DMX_SET_PES_FILTER _IOW('o', 44, struct dmx_pes_filter_params) |
| 323 | #define DMX_SET_BUFFER_SIZE _IO('o', 45) |
| 324 | #define DMX_GET_PES_PIDS _IOR('o', 47, __u16[5]) |
| 325 | #define DMX_GET_CAPS _IOR('o', 48, dmx_caps_t) |
| 326 | #define DMX_SET_SOURCE _IOW('o', 49, dmx_source_t) |
| 327 | #define DMX_GET_STC _IOWR('o', 50, struct dmx_stc) |
| 328 | #define DMX_ADD_PID _IOW('o', 51, __u16) |
| 329 | #define DMX_REMOVE_PID _IOW('o', 52, __u16) |
| 330 | #ifdef CONFIG_AMLOGIC_DVB_COMPAT |
| 331 | #define DMX_SET_INPUT _IO('o', 80) |
| 332 | #define DMX_GET_MEM_INFO _IOR('o', 81, struct dmx_mem_info) |
| 333 | #define DMX_SET_HW_SOURCE _IO('o', 82) |
| 334 | #define DMX_GET_HW_SOURCE _IOR('o', 83, int) |
hualing chen | f986740 | 2020-09-23 17:06:20 +0800 | [diff] [blame] | 335 | #define DMX_GET_FILTER_MEM_INFO _IOR('o', 84, struct dmx_filter_mem_info) |
| 336 | /*just for dvr sec mem, please call before DMX_SET_PES_FILTER*/ |
hualing chen | 002e5b9 | 2022-02-23 17:51:21 +0800 | [diff] [blame] | 337 | #define DMX_SET_SEC_MEM _IOW('o', 85, struct dmx_sec_mem) |
| 338 | #define DMX_GET_DVR_MEM _IOR('o', 86, struct dvr_mem_info) |
Kihun Lee | 50e7d5b | 2021-08-05 07:59:03 +0800 | [diff] [blame] | 339 | #define DMX_REMAP_PID _IOR('o', 87, __u16[2]) |
Chuanzhi Wang | 670fc04 | 2020-08-12 11:11:04 +0800 | [diff] [blame] | 340 | #endif |
| 341 | |
| 342 | #endif /* _UAPI_DVBDMX_H_ */ |