blob: 8ceed08725318f801ef8000ee03c460184cec410 [file] [log] [blame]
chen.wang1d5483452024-02-28 06:18:16 +00001/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019-2022 Amlogic Inc.
4 */
Ao Xu0733c432018-11-02 17:35:02 +08005#ifndef _MESON_DRM_H
6#define _MESON_DRM_H
Yalong Liubdcf9122018-01-19 18:35:02 +08007
Ao Xu0733c432018-11-02 17:35:02 +08008#include <drm/drm.h>
9
10/* Use flags */
11#define MESON_USE_NONE 0
12#define MESON_USE_SCANOUT (1ull << 0)
13#define MESON_USE_CURSOR (1ull << 1)
14#define MESON_USE_RENDERING (1ull << 2)
15#define MESON_USE_LINEAR (1ull << 3)
16#define MESON_USE_PROTECTED (1ull << 11)
17#define MESON_USE_HW_VIDEO_ENCODER (1ull << 12)
18#define MESON_USE_CAMERA_WRITE (1ull << 13)
19#define MESON_USE_CAMERA_READ (1ull << 14)
20#define MESON_USE_TEXTURE (1ull << 17)
Ao Xu6fbd0322020-04-14 18:08:22 +080021#define MESON_USE_VIDEO_PLANE (1ull << 18)
22#define MESON_USE_VIDEO_AFBC (1ull << 19)
Ao Xu6747bbd2020-09-28 20:02:09 +080023#define MESON_USE_VD1 (1ull << 20)
24#define MESON_USE_VD2 (1ull << 21)
Yalong Liubdcf9122018-01-19 18:35:02 +080025
26/**
27 * User-desired buffer creation information structure.
28 *
29 * @size: user-desired memory allocation size.
Yalong Liubdcf9122018-01-19 18:35:02 +080030 * @flags: user request for setting memory type or cache attributes.
31 * @handle: returned a handle to created gem object.
Ao Xu0733c432018-11-02 17:35:02 +080032 * - this handle will be set by gem module of kernel side.
Yalong Liubdcf9122018-01-19 18:35:02 +080033 */
Yalong Liu22dc0a52018-02-22 10:27:20 +080034struct drm_meson_gem_create {
Ao Xu0733c432018-11-02 17:35:02 +080035 __u64 size;
36 __u32 flags;
37 __u32 handle;
Yalong Liubdcf9122018-01-19 18:35:02 +080038};
chen.wang1d5483452024-02-28 06:18:16 +000039/**
40 * struct drm_meson_dma_buf_export_sync_file - Get a sync_file from a dma-buf
41 *
42 * Userspace can perform a DMA_BUF_IOCTL_EXPORT_SYNC_FILE to retrieve the
43 * current set of fences on a dma-buf file descriptor as a sync_file. CPU
44 * waits via poll() or other driver-specific mechanisms typically wait on
45 * whatever fences are on the dma-buf at the time the wait begins. This
46 * is similar except that it takes a snapshot of the current fences on the
47 * dma-buf for waiting later instead of waiting immediately. This is
48 * useful for modern graphics APIs such as Vulkan which assume an explicit
49 * synchronization model but still need to inter-operate with dma-buf.
50 */
51struct drm_meson_dma_buf_export_sync_file {
52 /**
53 * @flags: Read/write flags
54 *
55 * Must be DMA_BUF_SYNC_READ, DMA_BUF_SYNC_WRITE, or both.
56 *
57 * If DMA_BUF_SYNC_READ is set and DMA_BUF_SYNC_WRITE is not set,
58 * the returned sync file waits on any writers of the dma-buf to
59 * complete. Waiting on the returned sync file is equivalent to
60 * poll() with POLLIN.
61 *
62 * If DMA_BUF_SYNC_WRITE is set, the returned sync file waits on
63 * any users of the dma-buf (read or write) to complete. Waiting
64 * on the returned sync file is equivalent to poll() with POLLOUT.
65 * If both DMA_BUF_SYNC_WRITE and DMA_BUF_SYNC_READ are set, this
66 * is equivalent to just DMA_BUF_SYNC_WRITE.
67 */
68 __u32 flags;
69 __u32 dmabuf_fd;
70 /** @fd: Returned sync file descriptor */
71 __s32 fd;
72};
Yalong Liubdcf9122018-01-19 18:35:02 +080073
chen.wang1d5483452024-02-28 06:18:16 +000074struct drm_meson_video_zpos_target {
chen.wang133a5c832023-07-12 04:23:36 +000075 __u32 index;
76 __u32 zpos;
77 __u32 flag;
78};
chen.wang1d5483452024-02-28 06:18:16 +000079
80struct drm_meson_plane_mute {
81 int plane_type; /* 0:osd plane, 1:video plane */
82 int plane_mute; /* 0:umute plane, 1:mute plane */
83};
84
85struct drm_mode_test_attr {
86 char modename[32];
87 char attr[32];
88 __u32 valid;
89};
90/*hdmitx relatde*/
91#define DRM_IOCTL_MESON_TESTATTR DRM_IOWR(DRM_COMMAND_BASE + \
92 0x11, struct drm_mode_test_attr)
93
chen.wang133a5c832023-07-12 04:23:36 +000094
sky zhouf05ca462020-10-29 18:07:40 +080095/*Memory related.*/
Ao Xu0733c432018-11-02 17:35:02 +080096#define DRM_IOCTL_MESON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
sky zhouf05ca462020-10-29 18:07:40 +080097 0x00, struct drm_meson_gem_create)
chen.wang1d5483452024-02-28 06:18:16 +000098#define DRM_IOCTL_MESON_DMABUF_EXPORT_SYNC_FILE DRM_IOWR(DRM_COMMAND_BASE + \
99 0x02, struct drm_meson_dma_buf_export_sync_file)
100
wenlong.zhang7d32ed92023-04-12 06:08:17 +0000101#define DRM_IOCTL_MESON_RMFB DRM_IOWR(DRM_COMMAND_BASE + \
102 0x01, unsigned int)
sky zhouf05ca462020-10-29 18:07:40 +0800103
104/*KMS related.*/
105#define DRM_IOCTL_MESON_ASYNC_ATOMIC DRM_IOWR(DRM_COMMAND_BASE + \
106 0x10, struct drm_mode_atomic)
chen.wang1d5483452024-02-28 06:18:16 +0000107
chen.wang133a5c832023-07-12 04:23:36 +0000108#define DRM_IOCTL_MESON_SET_VIDEO_ZPOS DRM_IOWR(DRM_COMMAND_BASE + \
109 0x11, struct drm_meson_video_zpos_target)
chen.wang1d5483452024-02-28 06:18:16 +0000110#define DRM_IOCTL_MESON_MUTE_PLANE DRM_IOWR(DRM_COMMAND_BASE + \
111 0x12, struct drm_meson_plane_mute)
112
Ao Xu0733c432018-11-02 17:35:02 +0800113#endif /* _MESON_DRM_H */