| Xiaohu.Huang | be56506 | 2021-10-15 17:29:19 +0800 | [diff] [blame] | 1 | // See LICENSE for license details. |
| 2 | |
| 3 | #include "riscv_encoding.h" |
| 4 | #include "soc.h" |
| 5 | |
| 6 | .section .init |
| 7 | |
| 8 | .globl _start |
| 9 | .type _start,@function |
| 10 | _start: |
| 11 | csrc CSR_MSTATUS, MSTATUS_MIE |
| Xiaohu.Huang | 0424881 | 2022-01-17 10:44:18 +0800 | [diff] [blame] | 12 | #ifndef CONFIG_N200_REVA |
| Xiaohu.Huang | be56506 | 2021-10-15 17:29:19 +0800 | [diff] [blame] | 13 | /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */ |
| 14 | li t0, (0x1 << 9); |
| 15 | csrs CSR_MMISC_CTL, t0 |
| 16 | |
| 17 | /* Intial the mtvt*/ |
| 18 | la t0, vector_base |
| 19 | csrw CSR_MTVT, t0 |
| 20 | |
| 21 | /* Intial the mtvt2 and enable it*/ |
| 22 | la t0, irq_entry |
| 23 | csrw CSR_MTVT2, t0 |
| 24 | csrs CSR_MTVT2, 0x1 |
| 25 | |
| 26 | /* Intial the CSR MTVEC for the Trap ane NMI base addr*/ |
| 27 | la t0, trap_entry |
| 28 | li t1, 0x3 // use ucliec |
| 29 | or t0, t0, t1 |
| 30 | csrw CSR_MTVEC, t0 |
| 31 | |
| 32 | #ifdef MPU_INIT |
| 33 | /* Setup MPU */ |
| 34 | li t0, SOC_PMP_BASE |
| 35 | /* Enable SRAM full range rwx */ |
| 36 | li t1, SRAM_BEGIN |
| 37 | li t2, SRAM_END - 0x80 |
| 38 | add t1, t1, 0x0f |
| 39 | sw t2, 28(t0) |
| 40 | sw t1, 24(t0) |
| 41 | /* Enable IO full range rw */ |
| 42 | li t1, IO_BEGIN |
| 43 | li t2, IO_END - 0x80 |
| 44 | add t1, t1, 0x0d |
| 45 | sw t2, 20(t0) |
| 46 | sw t1, 16(t0) |
| 47 | #endif |
| 48 | |
| 49 | #ifdef __riscv_flen |
| 50 | /* Enable FPU */ |
| 51 | li t0, MSTATUS_FS |
| 52 | csrs mstatus, t0 |
| 53 | csrw fcsr, x0 |
| 54 | #endif |
| 55 | #endif |
| 56 | .option push |
| 57 | .option norelax |
| 58 | .option pop |
| 59 | la sp, _sp |
| 60 | |
| 61 | #if defined (SOC_t3) |
| 62 | /* Fixme T3 axi_ram access issuse */ |
| 63 | lw a0, _data_start |
| 64 | lw a1, _data_end |
| 65 | lw a2, _data_img |
| 66 | bgeu a0, a1, 2f |
| 67 | 1: |
| 68 | lw a3, 0(a2) |
| 69 | sw a3, (a0) |
| 70 | addi a0, a0, 4 |
| 71 | addi a2, a2, 4 |
| 72 | bltu a0, a1, 1b |
| 73 | 2: |
| 74 | #endif |
| 75 | |
| 76 | /* Clear bss section */ |
| 77 | lw a0, _bss_start |
| 78 | lw a1, _bss_end |
| 79 | bgeu a0, a1, 2f |
| 80 | 1: |
| 81 | sw zero, (a0) |
| 82 | addi a0, a0, 4 |
| 83 | bltu a0, a1, 1b |
| 84 | 2: |
| 85 | |
| 86 | /* argc = argv = 0 */ |
| 87 | li a0, 0 |
| 88 | li a1, 0 |
| 89 | call main |
| 90 | |
| 91 | 1: |
| 92 | j 1b |
| 93 | |
| 94 | _bss_end: |
| 95 | .long _ebss |
| 96 | _bss_start: |
| 97 | .long _bss |
| 98 | #if defined (SOC_t3) |
| 99 | _data_end: |
| 100 | .long _edata |
| 101 | _data_start: |
| 102 | .long _data |
| 103 | _data_img: |
| 104 | .long _data_img_start |
| 105 | #endif |
| 106 | |
| Xiaohu.Huang | 0424881 | 2022-01-17 10:44:18 +0800 | [diff] [blame] | 107 | #ifndef CONFIG_N200_REVA |
| Xiaohu.Huang | be56506 | 2021-10-15 17:29:19 +0800 | [diff] [blame] | 108 | .global disable_mcycle_minstret |
| 109 | disable_mcycle_minstret: |
| 110 | csrsi CSR_MCOUNTINHIBIT, 0x5 |
| 111 | ret |
| 112 | |
| 113 | .global enable_mcycle_minstret |
| 114 | enable_mcycle_minstret: |
| 115 | csrci CSR_MCOUNTINHIBIT, 0x5 |
| 116 | ret |
| 117 | |
| 118 | .global core_wfe |
| 119 | core_wfe: |
| 120 | csrc CSR_MSTATUS, MSTATUS_MIE |
| 121 | csrs CSR_WFE, 0x1 |
| 122 | wfi |
| 123 | csrc CSR_WFE, 0x1 |
| 124 | csrs CSR_MSTATUS, MSTATUS_MIE |
| 125 | ret |
| 126 | #endif |