| xiaohu.huang | 797c4c1 | 2024-01-24 18:52:43 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef ENTRY_S |
| 8 | #define ENTRY_S |
| 9 | |
| 10 | #include "riscv_encoding.h" |
| 11 | |
| 12 | #if __riscv_xlen == 64 |
| 13 | #define SLL32 sllw |
| 14 | #define STORE sd |
| 15 | #define LOAD ld |
| 16 | #define LWU lwu |
| 17 | #define LOG_REGBYTES 3 |
| 18 | #else |
| 19 | #define SLL32 sll |
| 20 | #define STORE sw |
| 21 | #define LOAD lw |
| 22 | #define LWU lw |
| 23 | #define LOG_REGBYTES 2 |
| 24 | #endif |
| 25 | #define REGBYTES (1 << LOG_REGBYTES) |
| 26 | |
| 27 | #if __riscv_flen == 64 |
| 28 | #define FPSTORE fsd |
| 29 | #define FPLOAD fld |
| 30 | #define LOG_FPREGBYTES 3 |
| 31 | #else |
| 32 | #define FPSTORE fsw |
| 33 | #define FPLOAD flw |
| 34 | #define LOG_FPREGBYTES 2 |
| 35 | #endif |
| 36 | |
| 37 | .align 2 |
| 38 | .extern interrupt_register_nmi |
| 39 | .extern interrupt_register_exception |
| 40 | |
| 41 | .macro wr_reg, address, value |
| 42 | li t0, \address |
| 43 | li t1, \value |
| 44 | sw t1, (t0) |
| 45 | .endm |
| 46 | |
| 47 | ############################################### |
| 48 | ############################################### |
| 49 | #only save caller registers |
| 50 | .macro SAVE_CONTEXT |
| 51 | STORE x1, 0*REGBYTES(sp) |
| 52 | STORE x5, 1*REGBYTES(sp) |
| 53 | STORE x6, 2*REGBYTES(sp) |
| 54 | STORE x7, 3*REGBYTES(sp) |
| 55 | STORE x10, 4*REGBYTES(sp) |
| 56 | STORE x11, 5*REGBYTES(sp) |
| 57 | STORE x12, 6*REGBYTES(sp) |
| 58 | STORE x13, 7*REGBYTES(sp) |
| 59 | STORE x14, 8*REGBYTES(sp) |
| 60 | STORE x15, 9*REGBYTES(sp) |
| 61 | STORE x16, 10*REGBYTES(sp) |
| 62 | STORE x17, 11*REGBYTES(sp) |
| 63 | STORE x28, 12*REGBYTES(sp) |
| 64 | STORE x29, 13*REGBYTES(sp) |
| 65 | STORE x30, 14*REGBYTES(sp) |
| 66 | STORE x31, 15*REGBYTES(sp) |
| 67 | .endm |
| 68 | ############################################### |
| 69 | ############################################### |
| 70 | #restore caller registers |
| 71 | .macro RESTORE_CONTEXT |
| 72 | LOAD x1, 0*REGBYTES(sp) |
| 73 | LOAD x5, 1*REGBYTES(sp) |
| 74 | LOAD x6, 2*REGBYTES(sp) |
| 75 | LOAD x7, 3*REGBYTES(sp) |
| 76 | LOAD x10, 4*REGBYTES(sp) |
| 77 | LOAD x11, 5*REGBYTES(sp) |
| 78 | LOAD x12, 6*REGBYTES(sp) |
| 79 | LOAD x13, 7*REGBYTES(sp) |
| 80 | LOAD x14, 8*REGBYTES(sp) |
| 81 | LOAD x15, 9*REGBYTES(sp) |
| 82 | LOAD x16, 10*REGBYTES(sp) |
| 83 | LOAD x17, 11*REGBYTES(sp) |
| 84 | LOAD x28, 12*REGBYTES(sp) |
| 85 | LOAD x29, 13*REGBYTES(sp) |
| 86 | LOAD x30, 14*REGBYTES(sp) |
| 87 | LOAD x31, 15*REGBYTES(sp) |
| 88 | .endm |
| 89 | ############################################### |
| 90 | ############################################### |
| 91 | #restore caller registers |
| 92 | .macro RESTORE_CONTEXT_EXCEPT_X5 |
| 93 | LOAD x1, 0*REGBYTES(sp) |
| 94 | LOAD x6, 2*REGBYTES(sp) |
| 95 | LOAD x7, 3*REGBYTES(sp) |
| 96 | LOAD x10, 4*REGBYTES(sp) |
| 97 | LOAD x11, 5*REGBYTES(sp) |
| 98 | LOAD x12, 6*REGBYTES(sp) |
| 99 | LOAD x13, 7*REGBYTES(sp) |
| 100 | LOAD x14, 8*REGBYTES(sp) |
| 101 | LOAD x15, 9*REGBYTES(sp) |
| 102 | LOAD x16, 10*REGBYTES(sp) |
| 103 | LOAD x17, 11*REGBYTES(sp) |
| 104 | LOAD x28, 12*REGBYTES(sp) |
| 105 | LOAD x29, 13*REGBYTES(sp) |
| 106 | LOAD x30, 14*REGBYTES(sp) |
| 107 | LOAD x31, 15*REGBYTES(sp) |
| 108 | .endm |
| 109 | ############################################### |
| 110 | ############################################### |
| 111 | #restore caller registers |
| 112 | .macro RESTORE_CONTEXT_ONLY_X5 |
| 113 | LOAD x5, 1*REGBYTES(sp) |
| 114 | .endm |
| 115 | ############################################### |
| 116 | ############################################### |
| 117 | # Save the mepc and mstatus |
| 118 | # |
| 119 | .macro SAVE_MEPC_MSTATUS |
| 120 | csrr x5, CSR_MEPC |
| 121 | STORE x5, 16*REGBYTES(sp) |
| 122 | csrr x5, CSR_MSTATUS |
| 123 | STORE x5, 17*REGBYTES(sp) |
| 124 | csrr x5, CSR_MSUBM |
| 125 | STORE x5, 18*REGBYTES(sp) |
| 126 | .endm |
| 127 | |
| 128 | ############################################### |
| 129 | ############################################### |
| 130 | # Restore the mepc and mstatus |
| 131 | # |
| 132 | .macro RESTORE_MEPC_MSTATUS |
| 133 | LOAD x5, 16*REGBYTES(sp) |
| 134 | csrw CSR_MEPC, x5 |
| 135 | LOAD x5, 17*REGBYTES(sp) |
| 136 | csrw CSR_MSTATUS, x5 |
| 137 | LOAD x5, 18*REGBYTES(sp) |
| 138 | csrw CSR_MSUBM, x5 |
| 139 | .endm |
| 140 | ############################################### |
| 141 | ############################################### |
| 142 | # Disable Interrupt |
| 143 | # |
| 144 | .macro DISABLE_MIE |
| 145 | csrc CSR_MSTATUS, MSTATUS_MIE |
| 146 | .endm |
| 147 | ############################################### |
| 148 | ############################################### |
| 149 | # Enable Interrupt |
| 150 | # |
| 151 | .macro ENABLE_MIE |
| 152 | csrs CSR_MSTATUS, MSTATUS_MIE |
| 153 | .endm |
| 154 | ############################################### |
| 155 | ############################################### |
| 156 | |
| 157 | .align 6 |
| 158 | .global exception_entry |
| 159 | exception_entry: |
| 160 | addi sp, sp, -19*REGBYTES // allocate stack |
| 161 | |
| 162 | // saving registers |
| 163 | SAVE_CONTEXT |
| 164 | // saving mepc/mstatus |
| 165 | SAVE_MEPC_MSTATUS |
| 166 | |
| 167 | csrr a0, mcause |
| 168 | mv a1, sp |
| 169 | call interrupt_register_exception |
| 170 | |
| 171 | // restore mepc/mstatus registers |
| 172 | RESTORE_MEPC_MSTATUS |
| 173 | // restore registers |
| 174 | RESTORE_CONTEXT |
| 175 | |
| 176 | addi sp, sp, 19*REGBYTES // get back stack |
| 177 | mret |
| 178 | |
| 179 | ############################################### |
| 180 | ############################################### |
| 181 | |
| 182 | .align 2 |
| 183 | .global nmi_entry |
| 184 | nmi_entry: |
| 185 | addi sp, sp, -19*REGBYTES // allocate stack |
| 186 | |
| 187 | // saving registers |
| 188 | SAVE_CONTEXT |
| 189 | // saving mepc/mstatus |
| 190 | SAVE_MEPC_MSTATUS |
| 191 | |
| 192 | csrr a0, mcause |
| 193 | call interrupt_register_nmi |
| 194 | |
| 195 | // restore mepc/mstatus registers |
| 196 | RESTORE_MEPC_MSTATUS |
| 197 | // restore registers |
| 198 | RESTORE_CONTEXT |
| 199 | |
| 200 | addi sp, sp, 19*REGBYTES // get back stack |
| 201 | mret |
| 202 | |
| 203 | ############################################### |
| 204 | ############################################### |
| 205 | |
| 206 | .align 2 |
| 207 | .global int_entry |
| 208 | int_entry: |
| 209 | addi sp, sp, -19*REGBYTES // allocate stack |
| 210 | |
| 211 | // saving registers |
| 212 | SAVE_CONTEXT |
| 213 | // store mcause/mepc/msubm to stack |
| 214 | csrrwi x0, CSR_PUSHMCAUSE, 16 |
| 215 | csrrwi x0, CSR_PUSHMEPC, 17 |
| 216 | csrrwi x0, CSR_PUSHMSUBM, 18 |
| 217 | |
| 218 | service_loop: |
| 219 | // Claim the CLIC to find its pending highest ID |
| 220 | // if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label |
| 221 | // and update the link register |
| 222 | csrrw ra, CSR_JALMNXTI, ra |
| 223 | |
| 224 | RESTORE_CONTEXT_EXCEPT_X5 |
| 225 | |
| 226 | #---- Critical section with interrupts disabled ----------------------- |
| 227 | DISABLE_MIE # Disable interrupts |
| 228 | |
| 229 | LOAD x5, 18*REGBYTES(sp) |
| 230 | csrw CSR_MSUBM, x5 |
| 231 | LOAD x5, 17*REGBYTES(sp) |
| 232 | csrw CSR_MEPC, x5 |
| 233 | LOAD x5, 16*REGBYTES(sp) |
| 234 | csrw CSR_MCAUSE, x5 |
| 235 | |
| 236 | RESTORE_CONTEXT_ONLY_X5 |
| 237 | |
| 238 | // De-allocate the stack space |
| 239 | addi sp, sp, 19*REGBYTES |
| 240 | // Return to regular code |
| 241 | mret |
| 242 | |
| 243 | #endif |