| xiaohu.huang | 797c4c1 | 2024-01-24 18:52:43 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #include "riscv_encoding.h" |
| 8 | |
| 9 | .section .text.startup |
| 10 | .extern main |
| 11 | .extern vector_base |
| 12 | |
| 13 | .equ mtvec, 0x305 |
| 14 | .equ mtvt, 0x307 |
| 15 | .equ mtvt2, 0x7ec |
| 16 | .equ mnvec, 0x7c3 |
| 17 | |
| 18 | .global _start |
| 19 | .type _start,@function |
| 20 | |
| 21 | _start: |
| 22 | csrrci x0, mstatus, 0x8 //Disable the interrupt globally |
| 23 | |
| 24 | li x1, 0 |
| 25 | li x2, 0 |
| 26 | li x3, 0 |
| 27 | li x4, 0 |
| 28 | li x5, 0 |
| 29 | li x6, 0 |
| 30 | li x7, 0 |
| 31 | li x8, 0 |
| 32 | li x9, 0 |
| 33 | li x10, 0 |
| 34 | li x11, 0 |
| 35 | li x12, 0 |
| 36 | li x13, 0 |
| 37 | li x14, 0 |
| 38 | li x15, 0 |
| 39 | li x16, 0 |
| 40 | li x17, 0 |
| 41 | li x18, 0 |
| 42 | li x19, 0 |
| 43 | li x20, 0 |
| 44 | li x21, 0 |
| 45 | li x22, 0 |
| 46 | li x23, 0 |
| 47 | li x24, 0 |
| 48 | li x25, 0 |
| 49 | li x26, 0 |
| 50 | li x27, 0 |
| 51 | li x28, 0 |
| 52 | li x29, 0 |
| 53 | li x30, 0 |
| 54 | li x31, 0 |
| 55 | |
| 56 | .option push |
| 57 | .option norelax |
| 58 | la gp, __global_pointer$ |
| 59 | .option pop |
| 60 | //la sp, _sp |
| 61 | li sp, 0x0080c000 |
| 62 | |
| 63 | // set exception_entry for exception process |
| 64 | la t0, exception_entry |
| 65 | csrw mtvec, t0 |
| 66 | |
| 67 | // set nmi_entry for non-mask interrupt process |
| 68 | la t0, nmi_entry |
| 69 | csrw mnvec, t0 |
| 70 | |
| 71 | /* initial the mtvt*/ |
| 72 | la t0, vector_base |
| 73 | csrw CSR_MTVT, t0 |
| 74 | |
| 75 | // set int_entry for peripheral interrupt process |
| 76 | la t0, int_entry |
| 77 | csrw mtvt2, t0 |
| 78 | csrs mtvt2, 0x1 |
| 79 | |
| 80 | /* argc = argv = 0 */ |
| 81 | li a0, 0 |
| 82 | li a1, 0 |
| 83 | call main |
| 84 | 1: |
| 85 | wfi |
| 86 | j 1b /* just in case of pending imprecise data abort */ |