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git.odroid.com / yocto / rtos_sdk / drivers_aocpu / c4c3dd19ec48314ee7b8c164eaed3e4c75c2e5a7 / . / pmic / bd71837.h
blob: 38c487220664897a63e36e2621191c38e54e451a [file] [log] [blame]
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Copyright (C) 2018 ROHM Semiconductors */
3
4#ifndef __BD71837_H__
5
6#define __BD71837_H__
7
8#include "pmic.h"
9
10/* I2C slave address */
11#define bd718x7_slave_address 0x4b
12
13enum {
14 BD718XX_BUCK1 = 0,
15 BD718XX_BUCK2,
16 BD718XX_BUCK3,
17 BD718XX_BUCK4,
18 BD718XX_BUCK5,
19 BD718XX_BUCK6,
20 BD718XX_BUCK7,
21 BD718XX_BUCK8,
22 BD718XX_LDO1,
23 BD718XX_LDO2,
24 BD718XX_LDO3,
25 BD718XX_LDO4,
26 BD718XX_LDO5,
27 BD718XX_LDO6,
28 BD718XX_LDO7,
29 BD718XX_REGULATOR_AMOUNT,
30};
31
32
33/* Common voltage configurations */
34#define BD718XX_DVS_BUCK_VOLTAGE_NUM 0x3D
35#define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM 0x3D
36
37#define BD718XX_LDO1_VOLTAGE_NUM 0x08
38#define BD718XX_LDO2_VOLTAGE_NUM 0x02
39#define BD718XX_LDO3_VOLTAGE_NUM 0x10
40#define BD718XX_LDO4_VOLTAGE_NUM 0x0A
41#define BD718XX_LDO6_VOLTAGE_NUM 0x0A
42
43/* BD71837 specific voltage configurations */
44#define BD71837_BUCK5_VOLTAGE_NUM 0x10
45#define BD71837_BUCK6_VOLTAGE_NUM 0x04
46#define BD71837_BUCK7_VOLTAGE_NUM 0x08
47#define BD71837_LDO5_VOLTAGE_NUM 0x10
48#define BD71837_LDO7_VOLTAGE_NUM 0x10
49
50/* BD71847 specific voltage configurations */
51#define BD71847_BUCK3_VOLTAGE_NUM 0x18
52#define BD71847_BUCK4_VOLTAGE_NUM 0x08
53#define BD71847_LDO5_VOLTAGE_NUM 0x20
54
55
56
57/* Registers specific to BD71837 */
58enum {
59 BD71837_REG_BUCK3_CTRL = 0x07,
60 BD71837_REG_BUCK4_CTRL = 0x08,
61 BD71837_REG_BUCK3_VOLT_RUN = 0x12,
62 BD71837_REG_BUCK4_VOLT_RUN = 0x13,
63 BD71837_REG_LDO7_VOLT = 0x1E,
64};
65
66/* Registers common for BD71837 and BD71847 */
67enum {
68 BD718XX_REG_REV = 0x00,
69 BD718XX_REG_SWRESET = 0x01,
70 BD718XX_REG_I2C_DEV = 0x02,
71 BD718XX_REG_PWRCTRL0 = 0x03,
72 BD718XX_REG_PWRCTRL1 = 0x04,
73 BD718XX_REG_BUCK1_CTRL = 0x05,
74 BD718XX_REG_BUCK2_CTRL = 0x06,
75 BD718XX_REG_1ST_NODVS_BUCK_CTRL = 0x09,
76 BD718XX_REG_2ND_NODVS_BUCK_CTRL = 0x0A,
77 BD718XX_REG_3RD_NODVS_BUCK_CTRL = 0x0B,
78 BD718XX_REG_4TH_NODVS_BUCK_CTRL = 0x0C,
79 BD718XX_REG_BUCK1_VOLT_RUN = 0x0D,
80 BD718XX_REG_BUCK1_VOLT_IDLE = 0x0E,
81 BD718XX_REG_BUCK1_VOLT_SUSP = 0x0F,
82 BD718XX_REG_BUCK2_VOLT_RUN = 0x10,
83 BD718XX_REG_BUCK2_VOLT_IDLE = 0x11,
84 BD718XX_REG_1ST_NODVS_BUCK_VOLT = 0x14,
85 BD718XX_REG_2ND_NODVS_BUCK_VOLT = 0x15,
86 BD718XX_REG_3RD_NODVS_BUCK_VOLT = 0x16,
87 BD718XX_REG_4TH_NODVS_BUCK_VOLT = 0x17,
88 BD718XX_REG_LDO1_VOLT = 0x18,
89 BD718XX_REG_LDO2_VOLT = 0x19,
90 BD718XX_REG_LDO3_VOLT = 0x1A,
91 BD718XX_REG_LDO4_VOLT = 0x1B,
92 BD718XX_REG_LDO5_VOLT = 0x1C,
93 BD718XX_REG_LDO6_VOLT = 0x1D,
94 BD718XX_REG_TRANS_COND0 = 0x1F,
95 BD718XX_REG_TRANS_COND1 = 0x20,
96 BD718XX_REG_VRFAULTEN = 0x21,
97 BD718XX_REG_MVRFLTMASK0 = 0x22,
98 BD718XX_REG_MVRFLTMASK1 = 0x23,
99 BD718XX_REG_MVRFLTMASK2 = 0x24,
100 BD718XX_REG_RCVCFG = 0x25,
101 BD718XX_REG_RCVNUM = 0x26,
102 BD718XX_REG_PWRONCONFIG0 = 0x27,
103 BD718XX_REG_PWRONCONFIG1 = 0x28,
104 BD718XX_REG_RESETSRC = 0x29,
105 BD718XX_REG_MIRQ = 0x2A,
106 BD718XX_REG_IRQ = 0x2B,
107 BD718XX_REG_IN_MON = 0x2C,
108 BD718XX_REG_POW_STATE = 0x2D,
109 BD718XX_REG_OUT32K = 0x2E,
110 BD718XX_REG_REGLOCK = 0x2F,
111 BD718XX_REG_OTPVER = 0xFF,
112 BD718XX_MAX_REGISTER = 0x100,
113};
114
115#define REGLOCK_PWRSEQ 0x1
116#define REGLOCK_VREG 0x10
117
118/* Generic BUCK control masks */
119#define BD718XX_BUCK_SEL 0x02
120#define BD718XX_BUCK_EN 0x01
121#define BD718XX_BUCK_RUN_ON 0x04
122
123/* Generic LDO masks */
124#define BD718XX_LDO_SEL 0x80
125#define BD718XX_LDO_EN 0x40
126
127/* BD71837 BUCK ramp rate CTRL reg bits */
128#define BUCK_RAMPRATE_MASK 0xC0
129#define BUCK_RAMPRATE_10P00MV 0x0
130#define BUCK_RAMPRATE_5P00MV 0x1
131#define BUCK_RAMPRATE_2P50MV 0x2
132#define BUCK_RAMPRATE_1P25MV 0x3
133
134#define DVS_BUCK_RUN_MASK 0x3F
135#define DVS_BUCK_SUSP_MASK 0x3F
136#define DVS_BUCK_IDLE_MASK 0x3F
137
138#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
139#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
140#define BD718XX_4TH_NODVS_BUCK_MASK 0x3F
141
142#define BD71847_BUCK3_MASK 0x07
143#define BD71847_BUCK3_RANGE_MASK 0xC0
144#define BD71847_BUCK4_MASK 0x03
145#define BD71847_BUCK4_RANGE_MASK 0x40
146
147#define BD71837_BUCK5_MASK 0x07
148#define BD71837_BUCK5_RANGE_MASK 0x80
149#define BD71837_BUCK6_MASK 0x03
150
151#define BD718XX_LDO1_MASK 0x03
152#define BD718XX_LDO1_RANGE_MASK 0x20
153#define BD718XX_LDO2_MASK 0x20
154#define BD718XX_LDO3_MASK 0x0F
155#define BD718XX_LDO4_MASK 0x0F
156#define BD718XX_LDO6_MASK 0x0F
157
158#define BD71837_LDO5_MASK 0x0F
159#define BD71847_LDO5_MASK 0x0F
160#define BD71847_LDO5_RANGE_MASK 0x20
161
162#define BD71837_LDO7_MASK 0x0F
163
164/* BD718XX Voltage monitoring masks */
165#define BD718XX_BUCK1_VRMON80 0x1
166#define BD718XX_BUCK1_VRMON130 0x2
167#define BD718XX_BUCK2_VRMON80 0x4
168#define BD718XX_BUCK2_VRMON130 0x8
169#define BD718XX_1ST_NODVS_BUCK_VRMON80 0x1
170#define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2
171#define BD718XX_2ND_NODVS_BUCK_VRMON80 0x4
172#define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8
173#define BD718XX_3RD_NODVS_BUCK_VRMON80 0x10
174#define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20
175#define BD718XX_4TH_NODVS_BUCK_VRMON80 0x40
176#define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80
177#define BD718XX_LDO1_VRMON80 0x1
178#define BD718XX_LDO2_VRMON80 0x2
179#define BD718XX_LDO3_VRMON80 0x4
180#define BD718XX_LDO4_VRMON80 0x8
181#define BD718XX_LDO5_VRMON80 0x10
182#define BD718XX_LDO6_VRMON80 0x20
183
184/* BD71837 specific voltage monitoring masks */
185#define BD71837_BUCK3_VRMON80 0x10
186#define BD71837_BUCK3_VRMON130 0x20
187#define BD71837_BUCK4_VRMON80 0x40
188#define BD71837_BUCK4_VRMON130 0x80
189#define BD71837_LDO7_VRMON80 0x40
190
191/* BD718XX_REG_IRQ bits */
192#define IRQ_SWRST 0x40
193#define IRQ_PWRON_S 0x20
194#define IRQ_PWRON_L 0x10
195#define IRQ_PWRON 0x08
196#define IRQ_WDOG 0x04
197#define IRQ_ON_REQ 0x02
198#define IRQ_STBY_REQ 0x01
199
200/* BD718XX_REG_OUT32K bits */
201#define BD718XX_OUT32K_EN 0x01
202
203/* BD7183XX gated clock rate */
204#define BD718XX_CLK_RATE 32768
205
206/* ROHM BD718XX irqs */
207enum {
208 BD718XX_INT_STBY_REQ,
209 BD718XX_INT_ON_REQ,
210 BD718XX_INT_WDOG,
211 BD718XX_INT_PWRBTN,
212 BD718XX_INT_PWRBTN_L,
213 BD718XX_INT_PWRBTN_S,
214 BD718XX_INT_SWRST
215};
216
217/* ROHM BD718XX interrupt masks */
218#define BD718XX_INT_SWRST_MASK 0x40
219#define BD718XX_INT_PWRBTN_S_MASK 0x20
220#define BD718XX_INT_PWRBTN_L_MASK 0x10
221#define BD718XX_INT_PWRBTN_MASK 0x8
222#define BD718XX_INT_WDOG_MASK 0x4
223#define BD718XX_INT_ON_REQ_MASK 0x2
224#define BD718XX_INT_STBY_REQ_MASK 0x1
225
226/* Register write induced reset settings */
227
228/*
229 * Even though the bit zero is not SWRESET type we still want to write zero
230 * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we
231 * write 1 to it we will trigger the action. So always write 0 to it when
232 * changning SWRESET action - no matter what we read from it.
233 */
234#define BD718XX_SWRESET_TYPE_MASK 7
235#define BD718XX_SWRESET_TYPE_DISABLED 0
236#define BD718XX_SWRESET_TYPE_COLD 4
237#define BD718XX_SWRESET_TYPE_WARM 6
238
239#define BD718XX_SWRESET_RESET_MASK 1
240#define BD718XX_SWRESET_RESET 1
241
242/* Poweroff state transition conditions */
243
244#define BD718XX_ON_REQ_POWEROFF_MASK 1
245#define BD718XX_SWRESET_POWEROFF_MASK 2
246#define BD718XX_WDOG_POWEROFF_MASK 4
247#define BD718XX_KEY_L_POWEROFF_MASK 8
248
249#define BD718XX_POWOFF_TO_SNVS 0
250#define BD718XX_POWOFF_TO_RDY 0xF
251
252#define BD718XX_POWOFF_TIME_MASK 0xF0
253enum {
254 BD718XX_POWOFF_TIME_5MS = 0,
255 BD718XX_POWOFF_TIME_10MS,
256 BD718XX_POWOFF_TIME_15MS,
257 BD718XX_POWOFF_TIME_20MS,
258 BD718XX_POWOFF_TIME_25MS,
259 BD718XX_POWOFF_TIME_30MS,
260 BD718XX_POWOFF_TIME_35MS,
261 BD718XX_POWOFF_TIME_40MS,
262 BD718XX_POWOFF_TIME_45MS,
263 BD718XX_POWOFF_TIME_50MS,
264 BD718XX_POWOFF_TIME_75MS,
265 BD718XX_POWOFF_TIME_100MS,
266 BD718XX_POWOFF_TIME_250MS,
267 BD718XX_POWOFF_TIME_500MS,
268 BD718XX_POWOFF_TIME_750MS,
269 BD718XX_POWOFF_TIME_1500MS
270};
271
272/* Poweron sequence state transition conditions */
273#define BD718XX_RDY_TO_SNVS_MASK 0xF
274#define BD718XX_SNVS_TO_RUN_MASK 0xF0
275
276#define BD718XX_PWR_TRIG_KEY_L 1
277#define BD718XX_PWR_TRIG_KEY_S 2
278#define BD718XX_PWR_TRIG_PMIC_ON 4
279#define BD718XX_PWR_TRIG_VSYS_UVLO 8
280#define BD718XX_RDY_TO_SNVS_SIFT 0
281#define BD718XX_SNVS_TO_RUN_SIFT 4
282
283#define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF
284
285/* Timeout value for detecting short press */
286enum {
287 BD718XX_PWRBTN_SHORT_PRESS_10MS = 0,
288 BD718XX_PWRBTN_SHORT_PRESS_500MS,
289 BD718XX_PWRBTN_SHORT_PRESS_1000MS,
290 BD718XX_PWRBTN_SHORT_PRESS_1500MS,
291 BD718XX_PWRBTN_SHORT_PRESS_2000MS,
292 BD718XX_PWRBTN_SHORT_PRESS_2500MS,
293 BD718XX_PWRBTN_SHORT_PRESS_3000MS,
294 BD718XX_PWRBTN_SHORT_PRESS_3500MS,
295 BD718XX_PWRBTN_SHORT_PRESS_4000MS,
296 BD718XX_PWRBTN_SHORT_PRESS_4500MS,
297 BD718XX_PWRBTN_SHORT_PRESS_5000MS,
298 BD718XX_PWRBTN_SHORT_PRESS_5500MS,
299 BD718XX_PWRBTN_SHORT_PRESS_6000MS,
300 BD718XX_PWRBTN_SHORT_PRESS_6500MS,
301 BD718XX_PWRBTN_SHORT_PRESS_7000MS,
302 BD718XX_PWRBTN_SHORT_PRESS_7500MS
303};
304
305/* Timeout value for detecting LONG press */
306enum {
307 BD718XX_PWRBTN_LONG_PRESS_10MS = 0,
308 BD718XX_PWRBTN_LONG_PRESS_1S,
309 BD718XX_PWRBTN_LONG_PRESS_2S,
310 BD718XX_PWRBTN_LONG_PRESS_3S,
311 BD718XX_PWRBTN_LONG_PRESS_4S,
312 BD718XX_PWRBTN_LONG_PRESS_5S,
313 BD718XX_PWRBTN_LONG_PRESS_6S,
314 BD718XX_PWRBTN_LONG_PRESS_7S,
315 BD718XX_PWRBTN_LONG_PRESS_8S,
316 BD718XX_PWRBTN_LONG_PRESS_9S,
317 BD718XX_PWRBTN_LONG_PRESS_10S,
318 BD718XX_PWRBTN_LONG_PRESS_11S,
319 BD718XX_PWRBTN_LONG_PRESS_12S,
320 BD718XX_PWRBTN_LONG_PRESS_13S,
321 BD718XX_PWRBTN_LONG_PRESS_14S,
322 BD718XX_PWRBTN_LONG_PRESS_15S
323};
324
325enum {
326 ROHM_CHIP_TYPE_BD71837 = 0,
327 ROHM_CHIP_TYPE_BD71847,
328 ROHM_CHIP_TYPE_BD70528,
329 ROHM_CHIP_TYPE_AMOUNT
330};
331
332extern struct pmic_regulator BD71837_PMIC;
333
334#endif /* __BD71837_H__ */