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Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08001/*
yang.li24770372022-01-11 15:21:49 +08002 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08003 *
yang.li24770372022-01-11 15:21:49 +08004 * SPDX-License-Identifier: MIT
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +08005 */
6
7#ifndef _GPIO_H_
8#define _GPIO_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif
13#include <gpio-data.h>
14
15/* trigger type for GPIO IRQ */
xiaohu.huang2beac512022-05-07 15:10:04 +080016#define IRQF_TRIGGER_NONE 0x00000000
17#define IRQF_TRIGGER_RISING 0x00000001
18#define IRQF_TRIGGER_FALLING 0x00000002
19#define IRQF_TRIGGER_HIGH 0x00000004
20#define IRQF_TRIGGER_LOW 0x00000008
21#define IRQF_TRIGGER_BOTH 0x00000010
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080022
23/* pin features */
xiaohu.huang2beac512022-05-07 15:10:04 +080024#define PINF_CONFIG_BIAS_DISABLE 0x00000001
25#define PINF_CONFIG_BIAS_PULL_UP 0x00000002
26#define PINF_CONFIG_BIAS_PULL_DOWN 0x00000004
27#define PINF_CONFIG_DRV_STRENGTH_0 0x00000008
28#define PINF_CONFIG_DRV_STRENGTH_1 0x00000010
29#define PINF_CONFIG_DRV_STRENGTH_2 0x00000020
30#define PINF_CONFIG_DRV_STRENGTH_3 0x00000040
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080031
xiaohu.huang2beac512022-05-07 15:10:04 +080032#define PINF_CONFIG_DRV_MASK 0x00000078
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080033
34/**
35 * enum GpioDirtype - type of gpio direction
36 */
xiaohu.huang2beac512022-05-07 15:10:04 +080037enum GpioDirType {
38 GPIO_DIR_OUT = 0x0,
39 GPIO_DIR_IN,
40 GPIO_DIR_INVALID,
41};
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080042
43/**
44 * enum GpioOutLevelType - type of gpio output level
45 */
xiaohu.huang2beac512022-05-07 15:10:04 +080046enum GpioOutLevelType {
47 GPIO_LEVEL_LOW = 0x0,
48 GPIO_LEVEL_HIGH,
49 GPIO_LEVEL_INVALID,
50};
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080051
52/**
53 * enum PinMuxType - type of pin mux
54 */
xiaohu.huang2beac512022-05-07 15:10:04 +080055enum PinMuxType {
56 PIN_FUNC0 = 0x0,
57 PIN_FUNC1,
58 PIN_FUNC2,
59 PIN_FUNC3,
60 PIN_FUNC4,
61 PIN_FUNC5,
62 PIN_FUNC6,
63 PIN_FUNC7,
64 PIN_FUNC_INVALID,
65};
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080066
xiaohu.huang2beac512022-05-07 15:10:04 +080067typedef void (*GpioIRQHandler_t)(void);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080068
69/**
70 * xGpioSetDir() - Set gpio direction
71 * @gpio: GPIO number
72 * @dir : direction value, and defined in "enum GpioDirType"
73 *
74 * Returns 0 on success, negative value on error.
75 */
xiaohu.huang2beac512022-05-07 15:10:04 +080076extern int xGpioSetDir(uint16_t gpio, enum GpioDirType dir);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080077
78/**
79 * xGpioSetValue() - Configure output level on GPIO pin
80 * @gpio : GPIO number
81 * @level : level value, and defined in "enum GpioOutLevelType"
82 *
83 * Returns 0 on success, negative value on error.
84 */
xiaohu.huang2beac512022-05-07 15:10:04 +080085extern int xGpioSetValue(uint16_t gpio, enum GpioOutLevelType level);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080086
87/**
88 * xGpioGetValue() - Sample GPIO pin and return it's value
89 * @gpio: GPIO number
90 *
91 */
xiaohu.huang2beac512022-05-07 15:10:04 +080092extern int xGpioGetValue(uint16_t gpio);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +080093
94/**
95 * xPinconfSet() - Configure pin features
96 * @gpio : GPIO number
97 * @flags : pin features
98 *
99 * Returns 0 on success, negative value on error.
100 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800101extern int xPinconfSet(uint16_t gpio, uint32_t flags);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800102
103/**
104 * xPinmuxSet() - Select function for per pin
105 * @gpio : GPIO number
106 * @func : function value, and defined in "enum PinMuxType"
107 *
108 * Returns 0 on success, negative value on error.
109 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800110extern int xPinmuxSet(uint16_t gpio, enum PinMuxType func);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800111
112/**
113 * vGpioIRQInit() - initialize gpio IRQ
114 *
115 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800116extern void vGpioIRQInit(void);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800117
118/**
119 * xRequestGpioIRQ() - Request IRQ for gpio
120 * @gpio : GPIO number
121 * @handler: interrupt handler function
122 * @flags : Trigger type
123 *
124 * Returns 0 on success, negative value on error.
125 *
126 * Note: can't be called from interrupt context
127 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800128extern int32_t xRequestGpioIRQ(uint16_t gpio, GpioIRQHandler_t handler, uint32_t flags);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800129
130/**
131 * vFreeGpioIRQ() - Free IRQ for gpio
132 * @gpio : GPIO number
133 *
134 * Note: can't be called from interrupt context
135 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800136extern void vFreeGpioIRQ(uint16_t gpio);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800137
138/**
139 * vEnableGpioIRQ() - Enable IRQ for gpio
140 * @gpio : GPIO number
141 *
142 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800143extern void vEnableGpioIRQ(uint16_t gpio);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800144
145/**
146 * vDisableGpioIRQ() - Disable IRQ for gpio
147 * @gpio : GPIO number
148 *
149 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800150extern void vDisableGpioIRQ(uint16_t gpio);
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800151
152/**
153 * restore and backup irqreg
154 *
155 */
xiaohu.huang2beac512022-05-07 15:10:04 +0800156extern void vRestoreGpioIrqReg(void);
157extern void vBackupAndClearGpioIrqReg(void);
Huqiang Qined61e052023-12-14 15:35:51 +0800158
159/**
160 * restore and backup gpio register
161 * @name : Bank name
162 *
163 * Returns 0 on success, negative value on error.
164 */
165 extern int xBankStateBackup(const char *name);
166 extern int xBankStateRestore(const char *name);
167
Kelvin Zhangc4c3dd12021-12-24 20:59:18 +0800168#ifdef __cplusplus
169}
170#endif
xiaohu.huang2beac512022-05-07 15:10:04 +0800171#endif /* _GPIO_H_ */