Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 1 | /* |
yang.li | 2477037 | 2022-01-11 15:21:49 +0800 | [diff] [blame] | 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 3 | * |
yang.li | 2477037 | 2022-01-11 15:21:49 +0800 | [diff] [blame] | 4 | * SPDX-License-Identifier: MIT |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _GPIO_H_ |
| 8 | #define _GPIO_H_ |
| 9 | |
| 10 | #ifdef __cplusplus |
| 11 | extern "C" { |
| 12 | #endif |
| 13 | #include <gpio-data.h> |
| 14 | |
| 15 | /* trigger type for GPIO IRQ */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 16 | #define IRQF_TRIGGER_NONE 0x00000000 |
| 17 | #define IRQF_TRIGGER_RISING 0x00000001 |
| 18 | #define IRQF_TRIGGER_FALLING 0x00000002 |
| 19 | #define IRQF_TRIGGER_HIGH 0x00000004 |
| 20 | #define IRQF_TRIGGER_LOW 0x00000008 |
| 21 | #define IRQF_TRIGGER_BOTH 0x00000010 |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 22 | |
| 23 | /* pin features */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 24 | #define PINF_CONFIG_BIAS_DISABLE 0x00000001 |
| 25 | #define PINF_CONFIG_BIAS_PULL_UP 0x00000002 |
| 26 | #define PINF_CONFIG_BIAS_PULL_DOWN 0x00000004 |
| 27 | #define PINF_CONFIG_DRV_STRENGTH_0 0x00000008 |
| 28 | #define PINF_CONFIG_DRV_STRENGTH_1 0x00000010 |
| 29 | #define PINF_CONFIG_DRV_STRENGTH_2 0x00000020 |
| 30 | #define PINF_CONFIG_DRV_STRENGTH_3 0x00000040 |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 31 | |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 32 | #define PINF_CONFIG_DRV_MASK 0x00000078 |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 33 | |
| 34 | /** |
| 35 | * enum GpioDirtype - type of gpio direction |
| 36 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 37 | enum GpioDirType { |
| 38 | GPIO_DIR_OUT = 0x0, |
| 39 | GPIO_DIR_IN, |
| 40 | GPIO_DIR_INVALID, |
| 41 | }; |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 42 | |
| 43 | /** |
| 44 | * enum GpioOutLevelType - type of gpio output level |
| 45 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 46 | enum GpioOutLevelType { |
| 47 | GPIO_LEVEL_LOW = 0x0, |
| 48 | GPIO_LEVEL_HIGH, |
| 49 | GPIO_LEVEL_INVALID, |
| 50 | }; |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 51 | |
| 52 | /** |
| 53 | * enum PinMuxType - type of pin mux |
| 54 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 55 | enum PinMuxType { |
| 56 | PIN_FUNC0 = 0x0, |
| 57 | PIN_FUNC1, |
| 58 | PIN_FUNC2, |
| 59 | PIN_FUNC3, |
| 60 | PIN_FUNC4, |
| 61 | PIN_FUNC5, |
| 62 | PIN_FUNC6, |
| 63 | PIN_FUNC7, |
| 64 | PIN_FUNC_INVALID, |
| 65 | }; |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 66 | |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 67 | typedef void (*GpioIRQHandler_t)(void); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 68 | |
| 69 | /** |
| 70 | * xGpioSetDir() - Set gpio direction |
| 71 | * @gpio: GPIO number |
| 72 | * @dir : direction value, and defined in "enum GpioDirType" |
| 73 | * |
| 74 | * Returns 0 on success, negative value on error. |
| 75 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 76 | extern int xGpioSetDir(uint16_t gpio, enum GpioDirType dir); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 77 | |
| 78 | /** |
| 79 | * xGpioSetValue() - Configure output level on GPIO pin |
| 80 | * @gpio : GPIO number |
| 81 | * @level : level value, and defined in "enum GpioOutLevelType" |
| 82 | * |
| 83 | * Returns 0 on success, negative value on error. |
| 84 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 85 | extern int xGpioSetValue(uint16_t gpio, enum GpioOutLevelType level); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 86 | |
| 87 | /** |
| 88 | * xGpioGetValue() - Sample GPIO pin and return it's value |
| 89 | * @gpio: GPIO number |
| 90 | * |
| 91 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 92 | extern int xGpioGetValue(uint16_t gpio); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 93 | |
| 94 | /** |
| 95 | * xPinconfSet() - Configure pin features |
| 96 | * @gpio : GPIO number |
| 97 | * @flags : pin features |
| 98 | * |
| 99 | * Returns 0 on success, negative value on error. |
| 100 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 101 | extern int xPinconfSet(uint16_t gpio, uint32_t flags); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 102 | |
| 103 | /** |
| 104 | * xPinmuxSet() - Select function for per pin |
| 105 | * @gpio : GPIO number |
| 106 | * @func : function value, and defined in "enum PinMuxType" |
| 107 | * |
| 108 | * Returns 0 on success, negative value on error. |
| 109 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 110 | extern int xPinmuxSet(uint16_t gpio, enum PinMuxType func); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 111 | |
| 112 | /** |
| 113 | * vGpioIRQInit() - initialize gpio IRQ |
| 114 | * |
| 115 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 116 | extern void vGpioIRQInit(void); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 117 | |
| 118 | /** |
| 119 | * xRequestGpioIRQ() - Request IRQ for gpio |
| 120 | * @gpio : GPIO number |
| 121 | * @handler: interrupt handler function |
| 122 | * @flags : Trigger type |
| 123 | * |
| 124 | * Returns 0 on success, negative value on error. |
| 125 | * |
| 126 | * Note: can't be called from interrupt context |
| 127 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 128 | extern int32_t xRequestGpioIRQ(uint16_t gpio, GpioIRQHandler_t handler, uint32_t flags); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 129 | |
| 130 | /** |
| 131 | * vFreeGpioIRQ() - Free IRQ for gpio |
| 132 | * @gpio : GPIO number |
| 133 | * |
| 134 | * Note: can't be called from interrupt context |
| 135 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 136 | extern void vFreeGpioIRQ(uint16_t gpio); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 137 | |
| 138 | /** |
| 139 | * vEnableGpioIRQ() - Enable IRQ for gpio |
| 140 | * @gpio : GPIO number |
| 141 | * |
| 142 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 143 | extern void vEnableGpioIRQ(uint16_t gpio); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 144 | |
| 145 | /** |
| 146 | * vDisableGpioIRQ() - Disable IRQ for gpio |
| 147 | * @gpio : GPIO number |
| 148 | * |
| 149 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 150 | extern void vDisableGpioIRQ(uint16_t gpio); |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 151 | |
| 152 | /** |
| 153 | * restore and backup irqreg |
| 154 | * |
| 155 | */ |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 156 | extern void vRestoreGpioIrqReg(void); |
| 157 | extern void vBackupAndClearGpioIrqReg(void); |
Huqiang Qin | ed61e05 | 2023-12-14 15:35:51 +0800 | [diff] [blame] | 158 | |
| 159 | /** |
| 160 | * restore and backup gpio register |
| 161 | * @name : Bank name |
| 162 | * |
| 163 | * Returns 0 on success, negative value on error. |
| 164 | */ |
| 165 | extern int xBankStateBackup(const char *name); |
| 166 | extern int xBankStateRestore(const char *name); |
| 167 | |
Kelvin Zhang | c4c3dd1 | 2021-12-24 20:59:18 +0800 | [diff] [blame] | 168 | #ifdef __cplusplus |
| 169 | } |
| 170 | #endif |
xiaohu.huang | 2beac51 | 2022-05-07 15:10:04 +0800 | [diff] [blame] | 171 | #endif /* _GPIO_H_ */ |