Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef INTERRUPT_CONTROL_H_ |
| 8 | #define INTERRUPT_CONTROL_H_ |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | #include "n200_eclic.h" |
| 12 | #include "interrupt.h" |
| 13 | /////////////////////////////////////////////////////////////////// |
| 14 | /////// ECLIC relevant functions |
| 15 | /////// |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 16 | void eclic_init(uint32_t num_irq); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 17 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 18 | void eclic_enable_interrupt(uint32_t source); |
| 19 | void eclic_disable_interrupt(uint32_t source); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 20 | |
| 21 | void eclic_set_pending(uint32_t source); |
| 22 | void eclic_clear_pending(uint32_t source); |
| 23 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 24 | void eclic_set_intctrl(uint32_t source, uint8_t intctrl); |
| 25 | uint8_t eclic_get_intctrl(uint32_t source); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 26 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 27 | void eclic_set_intattr(uint32_t source, uint8_t intattr); |
| 28 | uint8_t eclic_get_intattr(uint32_t source); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 29 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 30 | void eclic_set_cliccfg(uint8_t cliccfg); |
| 31 | uint8_t eclic_get_cliccfg(void); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 32 | |
bangzheng.liu | 68c0115 | 2022-09-29 16:57:22 +0800 | [diff] [blame] | 33 | uint32_t eclic_get_clicinfo(void); |
| 34 | |
| 35 | uint8_t eclic_get_clicintctlbits(void); |
| 36 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 37 | void eclic_set_mth(uint8_t mth); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 38 | uint8_t eclic_get_mth(void); |
| 39 | |
| 40 | //sets nlbits |
| 41 | void eclic_set_nlbits(uint8_t nlbits); |
| 42 | |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 43 | //get nlbits |
| 44 | uint8_t eclic_get_nlbits(void); |
| 45 | |
| 46 | void eclic_set_irq_lvl(uint32_t source, uint8_t lvl); |
| 47 | uint8_t eclic_get_irq_lvl(uint32_t source); |
| 48 | |
| 49 | void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs); |
| 50 | uint8_t eclic_get_irq_lvl_abs(uint32_t source); |
| 51 | |
| 52 | void eclic_set_irq_pri(uint32_t source, uint8_t pri); |
| 53 | |
| 54 | void eclic_mode_enable(void); |
| 55 | |
| 56 | void eclic_set_vmode(uint32_t source); |
| 57 | void eclic_set_nonvmode(uint32_t source); |
| 58 | |
| 59 | void eclic_set_level_trig(uint32_t source); |
| 60 | void eclic_set_posedge_trig(uint32_t source); |
| 61 | void eclic_set_negedge_trig(uint32_t source); |
| 62 | |
| 63 | int eclic_map_interrupt(uint32_t ulIrq, uint32_t src); |
| 64 | |
| 65 | void print_eclic(void); |
| 66 | |
| 67 | void clean_int_src(void); |
| 68 | int int_src_sel(uint32_t ulIrq, uint32_t src); |
| 69 | int int_src_clean(uint32_t ulIrq); |
| 70 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 71 | extern uint32_t vector_base; |
| 72 | |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 73 | #endif |