Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #include <stdio.h> |
| 8 | #include <FreeRTOS.h> |
bangzheng.liu | 4d71f92 | 2022-09-29 16:12:20 +0800 | [diff] [blame] | 9 | #include "interrupt_control_pic.h" |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 10 | #include "common.h" |
| 11 | #include "register.h" |
| 12 | |
| 13 | void pic_set_threshold(uint32_t threshold) |
| 14 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 15 | volatile uint32_t *threshold_ptr = (uint32_t *)(PIC_CTRL_ADDR + PIC_THRESHOLD_OFFSET); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 16 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 17 | *threshold_ptr = threshold; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 18 | } |
| 19 | |
| 20 | void pic_enable_interrupt(uint32_t source) |
| 21 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 22 | volatile uint32_t *current_ptr = |
| 23 | (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_ENABLE_OFFSET + |
| 24 | ((source >> 3) & (~0x3)) // Source number divide 32 and then |
| 25 | // multip 4 (bytes) |
| 26 | ); |
| 27 | uint32_t current = *current_ptr; |
| 28 | |
| 29 | current = current | (1 << (source & 0x1f)); // Only check the least 5 bits |
| 30 | *current_ptr = current; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 31 | } |
| 32 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 33 | void pic_disable_interrupt(uint32_t source) |
| 34 | { |
| 35 | volatile uint32_t *current_ptr = |
| 36 | (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_ENABLE_OFFSET + |
| 37 | ((source >> 3) & (~0x3)) // Source number divide 32 and then |
| 38 | // multip 4 (bytes) |
| 39 | ); |
| 40 | uint32_t current = *current_ptr; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 41 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 42 | current = current & ~((1 << (source & 0x1f))); // Only check the least 5 bits |
| 43 | *current_ptr = current; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 44 | } |
| 45 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 46 | void pic_set_priority(uint32_t source, uint32_t priority) |
| 47 | { |
| 48 | if (PIC_NUM_PRIORITIES > 0) { |
| 49 | // Each priority reg occupy a word, so multiple 2 |
| 50 | volatile uint32_t *priority_ptr = |
| 51 | (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_PRIORITY_OFFSET + |
| 52 | (source |
| 53 | << PIC_PRIORITY_SHIFT_PER_SOURCE)); |
| 54 | *priority_ptr = priority; |
| 55 | } |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 56 | } |
| 57 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 58 | uint32_t pic_claim_interrupt(void) |
| 59 | { |
| 60 | volatile uint32_t *claim_addr = (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_CLAIM_OFFSET); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 61 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 62 | return *claim_addr; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 63 | } |
| 64 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 65 | uint32_t pic_check_eip(void) |
| 66 | { |
| 67 | volatile uint32_t *eip_addr = (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_EIP_OFFSET); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 68 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 69 | return *eip_addr; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 70 | } |
| 71 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 72 | void pic_complete_interrupt(uint32_t source) |
| 73 | { |
| 74 | volatile uint32_t *claim_addr = (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_CLAIM_OFFSET); |
| 75 | *claim_addr = source; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | void DefaultInterruptHandler(void) |
| 79 | { |
| 80 | } |
| 81 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 82 | int RegisterIrq(uint32_t int_num, uint32_t int_priority, function_ptr_t handler) |
| 83 | { |
| 84 | pic_interrupt_handlers[int_num] = handler; |
| 85 | pic_set_priority(int_num, int_priority); |
| 86 | // pic_enable_interrupt (int_num); |
| 87 | return 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | int UnRegisterIrq(uint32_t int_num) |
| 91 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 92 | pic_interrupt_handlers[int_num] = DefaultInterruptHandler; |
| 93 | pic_set_priority(int_num, 0); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 94 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 95 | return 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | int EnableIrq(uint32_t ulIrq) |
| 99 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 100 | UBaseType_t uxSavedInterruptStatus; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 101 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 102 | uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); |
| 103 | pic_enable_interrupt(ulIrq); |
| 104 | portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); |
| 105 | return 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | int DisableIrq(uint32_t ulIrq) |
| 109 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 110 | UBaseType_t uxSavedInterruptStatus; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 111 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 112 | uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); |
| 113 | pic_disable_interrupt(ulIrq); |
| 114 | portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); |
| 115 | return 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | int SetIrqPriority(uint32_t ulIrq, uint32_t ulPri) |
| 119 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 120 | pic_set_priority(ulIrq, ulPri); |
| 121 | return 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static unsigned int irq_setting[IRQ_EN_REG_NUM]; |
| 125 | /*N205 does not support clear pending irq.* |
| 126 | *Need use work around to clear pending: * |
| 127 | *1. disable irq (MIE) * |
| 128 | *2. store and disable current enable irq * |
| 129 | *3. enable target irq * |
| 130 | *4. claim and complete target irq * |
| 131 | *5. disable target irq * |
| 132 | *6. restore current irq enable setting * |
| 133 | *7. enable irq (MIE) |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 134 | */ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 135 | int ClearPendingIrq(uint32_t ulIrq) |
| 136 | { |
| 137 | unsigned int i; |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 138 | volatile uint32_t *current_ptr; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 139 | unsigned long irq_status; |
| 140 | |
| 141 | irq_status = interrupt_status_get(); |
bangzheng.liu | 27822a8 | 2022-09-29 16:34:05 +0800 | [diff] [blame] | 142 | if (irq_status & 0x1) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 143 | interrupt_disable(); |
| 144 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 145 | for (i = 0; i < IRQ_EN_REG_NUM; i++) { |
| 146 | current_ptr = (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_ENABLE_OFFSET + i * 4); |
| 147 | irq_setting[i] = REG32(current_ptr); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 148 | REG32(current_ptr) = 0; |
| 149 | } |
| 150 | pic_enable_interrupt(ulIrq); |
| 151 | i = pic_claim_interrupt(); |
bangzheng.liu | 27822a8 | 2022-09-29 16:34:05 +0800 | [diff] [blame] | 152 | pic_complete_interrupt(i); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 153 | pic_disable_interrupt(ulIrq); |
| 154 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 155 | for (i = 0; i < IRQ_EN_REG_NUM; i++) { |
| 156 | current_ptr = (volatile uint32_t *)(PIC_CTRL_ADDR + PIC_ENABLE_OFFSET + i * 4); |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 157 | REG32(current_ptr) = irq_setting[i]; |
| 158 | } |
| 159 | |
bangzheng.liu | 27822a8 | 2022-09-29 16:34:05 +0800 | [diff] [blame] | 160 | if (irq_status & 0x1) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 161 | interrupt_enable(); |
| 162 | |
| 163 | return 0; |
| 164 | } |