Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef __IRQ_H_ |
| 8 | #define __IRQ_H_ |
| 9 | |
| 10 | extern void eclic_irq20_handler(void); |
| 11 | extern void eclic_irq21_handler(void); |
| 12 | extern void eclic_irq22_handler(void); |
| 13 | extern void eclic_irq23_handler(void); |
| 14 | extern void eclic_irq24_handler(void); |
| 15 | |
| 16 | extern void eclic_irq50_handler(void); |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame^] | 17 | |
| 18 | #define CONCAT_STAGE_1(w, x, y, z) w##x##y##z |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 19 | #define CONCAT2(w, x) w##x |
| 20 | #define CONCAT3(w, x, y) w##x##y |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame^] | 21 | #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z) |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 22 | |
| 23 | /* Helper macros to build the IRQ handler and priority struct names */ |
| 24 | #define IRQ_HANDLER(irqname) CONCAT3(eclic_irq, irqname, _handler) |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame^] | 25 | |
| 26 | #define DECLARE_IRQ(irq, routine) |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 27 | |
| 28 | /*IRQ_NUM define list*/ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 29 | #define IRQ_NUM_MB_0 50 |
| 30 | #define IRQ_NUM_MB_1 49 |
| 31 | #define IRQ_NUM_MB_2 48 |
| 32 | #define IRQ_NUM_MB_3 47 |
| 33 | #define IRQ_NUM_MB_4 46 |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 34 | |
| 35 | /*You can add other interrupts num here 46~19*/ |
| 36 | |
| 37 | /* use for ir */ |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame^] | 38 | #define IRQ_NUM_IRIN 22 |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 39 | |
| 40 | /* cec */ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 41 | #define IRQ_NUM_CECA 40 |
| 42 | #define IRQ_NUM_CECB 41 |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 43 | |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 44 | /*wol*/ |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame^] | 45 | #define IRQ_ETH_PMT_NUM 76 |
| 46 | |
| 47 | /* timerA~timerJ */ |
| 48 | #define IRQ_NUM_TIMERA 0 |
| 49 | #define IRQ_NUM_TIMERB 1 |
| 50 | #define IRQ_NUM_TIMERC 2 |
| 51 | #define IRQ_NUM_TIMERD 3 |
| 52 | #define IRQ_NUM_TIMERG 4 |
| 53 | #define IRQ_NUM_TIMERH 5 |
| 54 | #define IRQ_NUM_TIMERI 6 |
| 55 | #define IRQ_NUM_TIMERJ 7 |
| 56 | |
| 57 | #define IRQ_NUM_TIMER IRQ_NUM_TIMERJ |
| 58 | #define IRQ_TIMER_PROI 8 |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 59 | |
| 60 | #endif |