| Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef _CLK_H_ |
| 8 | #define _CLK_H_ |
| 9 | |
| 10 | #ifdef __cplusplus |
| 11 | extern "C" { |
| 12 | #endif |
| 13 | |
| xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 14 | enum PLL_TYPE { |
| Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 15 | PLL_SYS, |
| 16 | PLL_GP0, |
| 17 | PLL_GP1, |
| 18 | PLL_FIX, |
| 19 | PLL_HIFI, |
| 20 | PLL_RTC, |
| 21 | PLL_DDR |
| xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 22 | }; |
| Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 23 | |
| 24 | void disable_pll(int id); |
| 25 | void set_time(uint32_t val); |
| 26 | uint32_t get_time(void); |
| 27 | void alt_timebase(int use_clk_src); |
| 28 | void set_sys_div_clk(int sel, int div); |
| 29 | void set_axi_div_clk(int sel, int div); |
| 30 | void clk_util_set_dsp_clk(uint32_t id, uint32_t freq_sel); |
| 31 | |
| 32 | #ifdef __cplusplus |
| 33 | } |
| 34 | #endif |
| 35 | #endif |