Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef __IRQ_H_ |
| 8 | #define __IRQ_H_ |
| 9 | |
| 10 | extern void eclic_irq20_handler(void); |
| 11 | extern void eclic_irq21_handler(void); |
| 12 | extern void eclic_irq22_handler(void); |
| 13 | extern void eclic_irq23_handler(void); |
| 14 | extern void eclic_irq24_handler(void); |
| 15 | |
| 16 | extern void eclic_irq50_handler(void); |
| 17 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 18 | #define CONCAT_STAGE_1(w, x, y, z) w##x##y##z |
| 19 | #define CONCAT2(w, x) w##x |
| 20 | #define CONCAT3(w, x, y) w##x##y |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 21 | #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z) |
| 22 | |
| 23 | /* Helper macros to build the IRQ handler and priority struct names */ |
| 24 | #define IRQ_HANDLER(irqname) CONCAT3(eclic_irq, irqname, _handler) |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 25 | |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 26 | #define DECLARE_IRQ(irq, routine) |
| 27 | |
| 28 | /*IRQ_NUM define list*/ |
bangzheng.liu | 4d71f92 | 2022-09-29 16:12:20 +0800 | [diff] [blame] | 29 | #define IRQ_NUM_MAX 255 |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 30 | #define IRQ_NUM_MB_0 50 |
| 31 | #define IRQ_NUM_MB_1 49 |
| 32 | #define IRQ_NUM_MB_2 48 |
| 33 | #define IRQ_NUM_MB_3 47 |
| 34 | #define IRQ_NUM_MB_4 46 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 35 | |
| 36 | /*You can add other interrupts num here 46~19*/ |
| 37 | |
| 38 | /* use for ir */ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 39 | #define IRQ_NUM_IRIN 22 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 40 | |
| 41 | /* cec */ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 42 | #define IRQ_NUM_CECA 40 |
| 43 | #define IRQ_NUM_CECB 41 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 44 | |
| 45 | /*wol*/ |
| 46 | #define IRQ_ETH_PMT_NUM 76 |
| 47 | |
| 48 | /* timerA~timerJ */ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 49 | #define IRQ_NUM_TIMERA 0 |
| 50 | #define IRQ_NUM_TIMERB 1 |
| 51 | #define IRQ_NUM_TIMERC 2 |
| 52 | #define IRQ_NUM_TIMERD 3 |
| 53 | #define IRQ_NUM_TIMERG 4 |
| 54 | #define IRQ_NUM_TIMERH 5 |
| 55 | #define IRQ_NUM_TIMERI 6 |
| 56 | #define IRQ_NUM_TIMERJ 7 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 57 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 58 | #define IRQ_NUM_TIMER IRQ_NUM_TIMERJ |
| 59 | #define IRQ_TIMER_PROI 8 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 60 | |
| 61 | #endif |