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Xiaohu.Huanga2c5a042022-03-12 22:41:09 +08001/*
2 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7#ifndef __MAILBOX_H__
8#define __MAILBOX_H__
9
10#include "register.h"
11
xiaohu.huang38262102022-05-06 22:21:48 +080012#define MHU_MAX_SIZE (0x20 * 4) /*128 char*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080013
xiaohu.huang38262102022-05-06 22:21:48 +080014#define MHU_TASKID_SIZE 0x8
15#define MHU_COPETE_SIZE 0x8
16#define MHU_ULLCTL_SIZE 0x8
17#define MHU_STS_SIZE 0x4
18#define MHU_HEAD_SIZE 0x1c /*inclule status 0x4 task id 0x8, completion 0x8*/
19#define MHU_RESEV_SIZE 0x4 /*inclule status 0x2 task id 0x8, completion 0x8*/
20#define MHU_DATA_SIZE (MHU_MAX_SIZE - MHU_HEAD_SIZE - MHU_RESEV_SIZE)
21#define MHU_DATA_OFFSET (MHU_HEAD_SIZE / 4) /*inclule status 0x4 task id 0x8, completion 0x8*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080022
xiaohu.huang38262102022-05-06 22:21:48 +080023#define IRQ_MAX 32
24#define MBOX_AO_IRQ 249 //MBOX_IRQ1
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080025
xiaohu.huang38262102022-05-06 22:21:48 +080026#define MAILBOX_ARMREE2AO 0x3 /*mailbox1*/
27#define MAILBOX_AO2ARMREE 0x2 /*mailbox1*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080028
xiaohu.huang38262102022-05-06 22:21:48 +080029#define MAILBOX_ARMTEE2AO 0x5 /*mailbox1*/
30#define MAILBOX_AO2ARMTEE 0x4 /*mailbox1*/
31#define MAILBOX_DSPA2AO 0xC /*mailbox1*/
Jianyi Shia3c107b2022-04-29 11:04:46 +080032#define MAILBOX_AO2DSPA 0xD /*mailboxD*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080033
xiaohu.huang38262102022-05-06 22:21:48 +080034#define MAILBOX_AOCPU_IRQ 249
35#define MAILBOX_IRQ_MASK MAILBOX_IRQB_MASK
36#define MAILBOX_IRQ_CLR MAILBOX_IRQB_CLR
37#define MAILBOX_IRQ_STS MAILBOX_IRQB_STS
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080038
xiaohu.huang38262102022-05-06 22:21:48 +080039#define IRQ_REV_BIT(mbox) (1 << ((mbox)*2))
40#define IRQ_SENDACK_BIT(mbox) (1 << ((mbox)*2 + 1))
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080041
xiaohu.huang38262102022-05-06 22:21:48 +080042#define IRQ_REV_NUM(mbox) ((mbox)*2)
43#define IRQ_SENDACK_NUM(mbox) ((mbox)*2 + 1)
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080044
xiaohu.huang38262102022-05-06 22:21:48 +080045#define IRQ_MASK \
46 (IRQ_REV_BIT(MAILBOX_ARMREE2AO) | IRQ_REV_BIT(MAILBOX_ARMTEE2AO) | \
Jianyi Shia3c107b2022-04-29 11:04:46 +080047 IRQ_REV_BIT(MAILBOX_DSPA2AO) | IRQ_SENDACK_BIT(MAILBOX_AO2DSPA))
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080048
xiaohu.huang38262102022-05-06 22:21:48 +080049#define MAILBOX_STAT(MBOX) (MAILBOX_STS_MBOX00 + 0x4 * (MBOX)) /*mailbox4 rev*/
50#define MAILBOX_CLR(MBOX) (MAILBOX_CLR_MBOX00 + 0x4 * (MBOX)) /*mailbox4 rev*/
51#define MAILBOX_SET(MBOX) (MAILBOX_SET_MBOX00 + 0x4 * (MBOX)) /*mailbox4 send*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080052
xiaohu.huang38262102022-05-06 22:21:48 +080053#define PAYLOAD_WRBASE MAILBOX_WR_MBOX00
54#define PAYLOAD_RDBASE MAILBOX_RD_MBOX00
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080055
xiaohu.huang38262102022-05-06 22:21:48 +080056#define PAYLOAD_WR_BASE(MBOX) (PAYLOAD_WRBASE + (0x80 * (MBOX))) /*WR*/
57#define PAYLOAD_RD_BASE(MBOX) (PAYLOAD_RDBASE + (0x80 * (MBOX))) /*RD*/
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080058
59typedef void (*vHandlerFunc)(void *);
60
xiaohu.huang38262102022-05-06 22:21:48 +080061struct xHandlerTableEntry {
62 void (*vHandler)(void *vArg);
63 void *vArg;
64 unsigned int xPriority;
65};
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080066#endif