Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef __MAILBOX_H__ |
| 8 | #define __MAILBOX_H__ |
| 9 | |
| 10 | #include "register.h" |
| 11 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 12 | #define MHU_MAX_SIZE (0x20 * 4) /*128 char*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 13 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 14 | #define MHU_TASKID_SIZE 0x8 |
| 15 | #define MHU_COPETE_SIZE 0x8 |
| 16 | #define MHU_ULLCTL_SIZE 0x8 |
| 17 | #define MHU_STS_SIZE 0x4 |
| 18 | #define MHU_HEAD_SIZE 0x1c /*inclule status 0x4 task id 0x8, completion 0x8*/ |
| 19 | #define MHU_RESEV_SIZE 0x4 /*inclule status 0x2 task id 0x8, completion 0x8*/ |
| 20 | #define MHU_DATA_SIZE (MHU_MAX_SIZE - MHU_HEAD_SIZE - MHU_RESEV_SIZE) |
| 21 | #define MHU_DATA_OFFSET (MHU_HEAD_SIZE / 4) /*inclule status 0x4 task id 0x8, completion 0x8*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 22 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 23 | #define IRQ_MAX 32 |
| 24 | #define MBOX_AO_IRQ 249 //MBOX_IRQ1 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 25 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 26 | #define MAILBOX_ARMREE2AO 0x3 /*mailbox1*/ |
| 27 | #define MAILBOX_AO2ARMREE 0x2 /*mailbox1*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 28 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 29 | #define MAILBOX_ARMTEE2AO 0x5 /*mailbox1*/ |
| 30 | #define MAILBOX_AO2ARMTEE 0x4 /*mailbox1*/ |
| 31 | #define MAILBOX_DSPA2AO 0xC /*mailbox1*/ |
Jianyi Shi | a3c107b | 2022-04-29 11:04:46 +0800 | [diff] [blame] | 32 | #define MAILBOX_AO2DSPA 0xD /*mailboxD*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 33 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 34 | #define MAILBOX_AOCPU_IRQ 249 |
| 35 | #define MAILBOX_IRQ_MASK MAILBOX_IRQB_MASK |
| 36 | #define MAILBOX_IRQ_CLR MAILBOX_IRQB_CLR |
| 37 | #define MAILBOX_IRQ_STS MAILBOX_IRQB_STS |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 38 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 39 | #define IRQ_REV_BIT(mbox) (1 << ((mbox)*2)) |
| 40 | #define IRQ_SENDACK_BIT(mbox) (1 << ((mbox)*2 + 1)) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 41 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 42 | #define IRQ_REV_NUM(mbox) ((mbox)*2) |
| 43 | #define IRQ_SENDACK_NUM(mbox) ((mbox)*2 + 1) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 44 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 45 | #define IRQ_MASK \ |
| 46 | (IRQ_REV_BIT(MAILBOX_ARMREE2AO) | IRQ_REV_BIT(MAILBOX_ARMTEE2AO) | \ |
Jianyi Shi | a3c107b | 2022-04-29 11:04:46 +0800 | [diff] [blame] | 47 | IRQ_REV_BIT(MAILBOX_DSPA2AO) | IRQ_SENDACK_BIT(MAILBOX_AO2DSPA)) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 48 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 49 | #define MAILBOX_STAT(MBOX) (MAILBOX_STS_MBOX00 + 0x4 * (MBOX)) /*mailbox4 rev*/ |
| 50 | #define MAILBOX_CLR(MBOX) (MAILBOX_CLR_MBOX00 + 0x4 * (MBOX)) /*mailbox4 rev*/ |
| 51 | #define MAILBOX_SET(MBOX) (MAILBOX_SET_MBOX00 + 0x4 * (MBOX)) /*mailbox4 send*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 52 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 53 | #define PAYLOAD_WRBASE MAILBOX_WR_MBOX00 |
| 54 | #define PAYLOAD_RDBASE MAILBOX_RD_MBOX00 |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 55 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 56 | #define PAYLOAD_WR_BASE(MBOX) (PAYLOAD_WRBASE + (0x80 * (MBOX))) /*WR*/ |
| 57 | #define PAYLOAD_RD_BASE(MBOX) (PAYLOAD_RDBASE + (0x80 * (MBOX))) /*RD*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 58 | |
| 59 | typedef void (*vHandlerFunc)(void *); |
| 60 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 61 | struct xHandlerTableEntry { |
| 62 | void (*vHandler)(void *vArg); |
| 63 | void *vArg; |
| 64 | unsigned int xPriority; |
| 65 | }; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 66 | #endif |