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Xiaohu.Huanga2c5a042022-03-12 22:41:09 +08001/*
2 * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +08007#ifndef _SARADC_DATA_H_
8#define _SARADC_DATA_H_
9
10#include <register.h>
11
xiaohu.huang38262102022-05-06 22:21:48 +080012#define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
13#define SARADC_BASE SAR_ADC_REG0
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080014
xiaohu.huang38262102022-05-06 22:21:48 +080015#define REG11_VREF_EN_VALUE 0
16#define REG11_CMV_SEL_VALUE 0
17#define REG11_EOC_VALUE 1
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080018
19/* sc2 saradc interrupt num */
xiaohu.huang38262102022-05-06 22:21:48 +080020#define SARADC_INTERRUPT_NUM 181
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080021
xiaohu.huang38262102022-05-06 22:21:48 +080022#define SARADC_REG_NUM (39 + 1)
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080023
Huqiang Qin886d4812023-10-30 14:53:22 +080024/* enable software calibration */
25#define SARADC_SOFTWARE_CALIBRATION
26
Xiaohu.Huanga2c5a042022-03-12 22:41:09 +080027#endif