Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 7 | #ifndef __WAKEUP_H__ |
| 8 | #define __WAKEUP_H__ |
| 9 | |
| 10 | /*use timerB to wakeup AP FSM*/ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 11 | static inline void wakeup_ap(void) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 12 | { |
| 13 | uint32_t value; |
| 14 | //uint32_t time_out = 20; |
| 15 | |
| 16 | /*set alarm timer*/ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 17 | REG32(FSM_TRIGER_SRC) = 1000; /*1ms*/ |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 18 | |
| 19 | value = REG32(FSM_TRIGER_CTRL); |
| 20 | value &= ~((1 << 7) | (0x3) | (1 << 6)); |
| 21 | value |= ((1 << 7) | (0 << 6) | (0x3)); |
| 22 | REG32(FSM_TRIGER_CTRL) = value; |
| 23 | vTaskDelay(1); |
| 24 | } |
| 25 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 26 | static inline void clear_wakeup_trigger(void) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 27 | { |
| 28 | REG32(FSM_TRIGER_SRC) = 0; |
| 29 | REG32(FSM_TRIGER_CTRL) = 0; |
| 30 | } |
| 31 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 32 | static inline void watchdog_reset_system(void) |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 33 | { |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 34 | int i = 0; |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 35 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 36 | printf("enter %s\n", __func__); |
| 37 | while (1) { |
| 38 | REG32(RESETCTRL_WATCHDOG_CTRL0) = 1 << 27 | 0 << 18; |
| 39 | /* Decive GCC for waiting some cycles */ |
| 40 | for (i = 0; i < 100; i++) |
| 41 | REG32(RESETCTRL_WATCHDOG_CTRL0); |
| 42 | } |
Xiaohu.Huang | a2c5a04 | 2022-03-12 22:41:09 +0800 | [diff] [blame] | 43 | } |
| 44 | #endif |