| Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SARADC_DATA_H_ |
| 8 | #define _SARADC_DATA_H_ |
| 9 | |
| 10 | #include <register.h> |
| 11 | |
| benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 12 | #define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0 |
| 13 | #define SARADC_BASE SAR_ADC_REG0 |
| Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 14 | |
| xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 15 | #define REG11_VREF_EN_VALUE 0 |
| 16 | #define REG11_CMV_SEL_VALUE 0 |
| 17 | #define REG11_EOC_VALUE 1 |
| Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 18 | |
| benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 19 | /* sc2 saradc interrupt num */ |
| 20 | #define SARADC_INTERRUPT_NUM 181 |
| Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 21 | |
| benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 22 | #define SARADC_REG_NUM (39 + 1) |
| Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 23 | |
| 24 | #endif |