Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef __WAKEUP_H__ |
| 8 | #define __WAKEUP_H__ |
| 9 | |
binbin.wang | 833cf58 | 2022-09-09 14:43:27 +0800 | [diff] [blame] | 10 | #define TIMER_CLK_IDX 3// 0:cts_sys_clk 1:1us 2:10us 3:100us |
| 11 | #define WAKEUP_TIMER_CNT 1000 //Delay : WAKEUP_TIMER_CNT * TIMER_CLK_IDX |
| 12 | |
| 13 | /* Calculate the actual value, unit ms */ |
| 14 | #ifndef TIMER_CLK_IDX |
| 15 | #error "Not define TIMER_CLK_IDX macro..\n" |
| 16 | #else |
| 17 | #if !((TIMER_CLK_IDX >= 0) && (TIMER_CLK_IDX <= 3)) |
| 18 | #error "Set invalid value for TIMER" |
| 19 | #else |
| 20 | #if (TIMER_CLK_IDX == 0) |
| 21 | #error "Not support!" |
| 22 | #elif (TIMER_CLK_IDX == 1) |
| 23 | #define SYSTEM_DELAY_VAL (WAKEUP_TIMER_CNT / 1000) |
| 24 | #elif (TIMER_CLK_IDX == 2) |
| 25 | #define SYSTEM_DELAY_VAL (WAKEUP_TIMER_CNT / 1000 * 10) |
| 26 | #elif (TIMER_CLK_IDX == 3) |
| 27 | #define SYSTEM_DELAY_VAL (WAKEUP_TIMER_CNT / 1000 * 100) |
| 28 | #endif |
| 29 | #endif //!((TIMER_CLK_IDX >= 0) && (TIMER_CLK_IDX <=3)) |
| 30 | #endif // TIMER_CLK_IDX |
| 31 | |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 32 | /*use timerB to wakeup AP FSM*/ |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 33 | static inline void wakeup_ap(void) |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 34 | { |
| 35 | uint32_t value; |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 36 | //uint32_t time_out = 20; |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 37 | |
| 38 | /*set alarm timer*/ |
binbin.wang | 833cf58 | 2022-09-09 14:43:27 +0800 | [diff] [blame] | 39 | REG32(FSM_TRIGER_SRC) = WAKEUP_TIMER_CNT; /*1ms*/ |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 40 | |
| 41 | value = REG32(FSM_TRIGER_CTRL); |
| 42 | value &= ~((1 << 7) | (0x3) | (1 << 6)); |
binbin.wang | 833cf58 | 2022-09-09 14:43:27 +0800 | [diff] [blame] | 43 | value |= ((1 << 7) | (0 << 6) | (TIMER_CLK_IDX)); |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 44 | REG32(FSM_TRIGER_CTRL) = value; |
binbin.wang | 833cf58 | 2022-09-09 14:43:27 +0800 | [diff] [blame] | 45 | vTaskDelay(pdMS_TO_TICKS(SYSTEM_DELAY_VAL) + 1); |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 46 | } |
| 47 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 48 | static inline void clear_wakeup_trigger(void) |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 49 | { |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 50 | REG32(FSM_TRIGER_SRC) = 0; |
| 51 | REG32(FSM_TRIGER_CTRL) = 0; |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 52 | } |
| 53 | |
xiaohu.huang | 3826210 | 2022-05-06 22:21:48 +0800 | [diff] [blame] | 54 | static inline void watchdog_reset_system(void) |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 55 | { |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 56 | int i = 0; |
| 57 | |
| 58 | printf("enter %s\n", __func__); |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 59 | while (1) { |
benlong.zhou | b408b35 | 2022-06-20 19:54:36 +0800 | [diff] [blame] | 60 | REG32(RESETCTRL_WATCHDOG_CTRL0) = 1 << 27 | 0 << 18; |
| 61 | /* Decive GCC for waiting some cycles */ |
| 62 | for (i = 0; i < 100; i++) |
| 63 | REG32(RESETCTRL_WATCHDOG_CTRL0); |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 64 | } |
| 65 | } |
Bo Lv | 092e8de | 2022-04-24 21:40:10 +0800 | [diff] [blame] | 66 | #endif |