| bangzheng.liu | fe648a9 | 2023-10-27 13:18:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CEC_S7D_DATA_H__ |
| 8 | #define __CEC_S7D_DATA_H__ |
| 9 | |
| 10 | /*s7D data define*/ |
| 11 | |
| 12 | /*GPIOH_3 FUNC4:ceca, FUNC1:ceca FUNC2:cecb*/ |
| 13 | #define CEC_PIN_MX GPIOH_3 //TODO |
| 14 | #define CEC_PIN_FUNC PIN_FUNC2 |
| 15 | #define CEC_IP 1 /* 0: cec a, 1: cecb*/ |
| 16 | |
| 17 | //reg table define |
| 18 | //#define CEC_CHIP_SEL_T7 |
| 19 | //#define CEC_CHIP_SEL_T5 |
| 20 | //#define CEC_CHIP_SEL_SC2 |
| 21 | #define CEC_CHIP_SEL_S7D |
| 22 | |
| 23 | #define CEC_ON 1 |
| 24 | |
| 25 | /*for compile pass, not defined in register.h, wait cec owner fix*/ |
| 26 | #define CLKCTRL_CECA_CTRL0 CLKCTRL_CECB_CTRL0 |
| 27 | #define CLKCTRL_CECA_CTRL1 CLKCTRL_CECB_CTRL1 |
| 28 | #define CECA_GEN_CNTL CECB_GEN_CNTL |
| 29 | #define CECA_RW_REG CECB_RW_REG |
| 30 | #define CECA_INTR_MASKN CECB_INTR_MASKN |
| 31 | #define CECA_INTR_CLR CECB_INTR_CLR |
| 32 | #define CECA_INTR_STAT CECB_INTR_STAT |
| 33 | #endif |