Merge "hdmitx: Optimize the hdmitx clk source switching process [1/2]" into amlogic-dev-2023
diff --git a/MAINTAINERS b/MAINTAINERS
index 2503e34..c60d908 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
F: cmd/amlogic/cmd_clkmsr.c
+F: cmd/amlogic/cmd_scmi_shmem.c
F: drivers/amlogic/mmc/meson_gx_mmc.c
F: drivers/clk/meson/
F: drivers/serial/serial_meson.c
diff --git a/arch/arm/cpu/armv8/string.c b/arch/arm/cpu/armv8/string.c
index b734c72..2f24c9e 100644
--- a/arch/arm/cpu/armv8/string.c
+++ b/arch/arm/cpu/armv8/string.c
@@ -9,7 +9,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_AML_UASAN
#ifdef __HAVE_ARCH_MEMSET
/*memset_non_cache
*function: for non-cache memory space
@@ -42,6 +41,7 @@
return s;
}
+#ifndef CONFIG_AML_UASAN
void *memset(void *s, int c, size_t count)
{
unsigned long *sl = (unsigned long *) s;
diff --git a/arch/arm/dts/amlogic/meson-s6-bl201.dtsi b/arch/arm/dts/amlogic/meson-s6-bl201.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bl201.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bl201.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bl204.dtsi b/arch/arm/dts/amlogic/meson-s6-bl204.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bl204.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bl204.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bl208.dtsi b/arch/arm/dts/amlogic/meson-s6-bl208.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bl208.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bl208.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bl209.dtsi b/arch/arm/dts/amlogic/meson-s6-bl209.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bl209.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bl209.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bn201.dtsi b/arch/arm/dts/amlogic/meson-s6-bn201.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bn201.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bn201.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bq201.dtsi b/arch/arm/dts/amlogic/meson-s6-bq201.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bq201.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bq201.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bq208.dtsi b/arch/arm/dts/amlogic/meson-s6-bq208.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bq208.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bq208.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-bq209.dtsi b/arch/arm/dts/amlogic/meson-s6-bq209.dtsi
index 12642e7..8725a89 100644
--- a/arch/arm/dts/amlogic/meson-s6-bq209.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-bq209.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6-series.dtsi b/arch/arm/dts/amlogic/meson-s6-series.dtsi
index 4d6a533..7e0536f 100644
--- a/arch/arm/dts/amlogic/meson-s6-series.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-series.dtsi
@@ -342,34 +342,6 @@
status = "disabled";
};
- spifc: spi@fe056000 {
- compatible = "amlogic,spifc";
- status = "disabled";
- reg = <0x0 0xfe056000 0x0 0x80>;
- /* clocks = <&clkc CLKID_CLK81>; */
- /* clock-names = "core"; */
- pinctrl-names = "default";
- pinctrl-0 = <&spifc_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- spi-flash@0 {
- compatible = "spi-flash";
- reg = <0>;
- spi-max-frequency = <20000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- status = "disabled";
- };
- spi-nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <20000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- status = "disabled";
- };
- };
-
ethmac: ethernet@fe368000 {
status = "disabled";
};
@@ -403,6 +375,30 @@
spi_cfg = <0 0xfe08d040>;
};
+ spi_nfc: spinfc@0xfe08d000 {
+ compatible = "amlogic,spi_nfc";
+ status = "disabled";
+ reg = <0x0 0xfe08d000 0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ spi-nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ };
+
apb: apb@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x1000000>;
diff --git a/arch/arm/dts/amlogic/meson-s6-skt.dtsi b/arch/arm/dts/amlogic/meson-s6-skt.dtsi
index 6074692..9a430ff 100644
--- a/arch/arm/dts/amlogic/meson-s6-skt.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6-skt.dtsi
@@ -11,7 +11,7 @@
aliases {
serial0 = &uart_a;
serial1 = &uart_b;
- spi0 = &spifc;
+ spi0 = &spi_nfc;
spi1 = &spicc0;
i2c0 = &i2c0;
i2c1 = &i2c1;
@@ -259,9 +259,10 @@
uart-has-rtscts;
};
-&spifc {
- status = "okay";
- cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+&spi_nfc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nfc_pins>;
spi-flash@0 {
status = "okay";
};
diff --git a/arch/arm/dts/amlogic/meson-s6.dtsi b/arch/arm/dts/amlogic/meson-s6.dtsi
index fb77ec8..03ffdf8 100644
--- a/arch/arm/dts/amlogic/meson-s6.dtsi
+++ b/arch/arm/dts/amlogic/meson-s6.dtsi
@@ -561,6 +561,25 @@
};
};
+ spi_nfc_pins: spi_nfc_pins {
+ mux {
+ groups = "spinf_clk",
+ "spinf_d4",
+ "spinf_d5",
+ "spinf_d6",
+ "spinf_d7",
+ "spinf_cs1",
+ "spinf_cs0",
+ "spinf_mo_d0",
+ "spinf_mi_d1",
+ "spinf_wp_d2",
+ "spinf_rstgpio",
+ "spinf_hold_d3";
+ function = "spinf";
+ drive-strength = <3>;
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@@ -649,19 +668,6 @@
};
};
- spifc_pins: spifc_pins {
- mux {
- groups = "spif_hold",
- "spif_mo",
- "spif_mi",
- //"spif_cs",
- "spif_clk",
- "spif_wp";
- function = "spif";
- drive-strength = <3>;
- };
- };
-
pwm_a_pins1: pwm_a_pins1 {
mux {
groups = "pwm_a_hiz";
diff --git a/arch/arm/dts/amlogic/meson-t6d.dtsi b/arch/arm/dts/amlogic/meson-t6d.dtsi
index b4bc81d..459e30b 100644
--- a/arch/arm/dts/amlogic/meson-t6d.dtsi
+++ b/arch/arm/dts/amlogic/meson-t6d.dtsi
@@ -127,7 +127,7 @@
pll_val = <0x608200a0 0xea002000 0x00000150>;
analog_val = <0x20200000 0x0000c000 0x00000023>;
chip_num = <3>;
- soc_num = <5>;
+// soc_num = <5>;
/* 5: S1A, S7 */
//tx_amp_src = <0xfe005b30>;
// clocks = <&clkc CLKID_ETH_CORE>,
diff --git a/arch/arm/include/asm/amlogic/arch-a4/cpu.h b/arch/arm/include/asm/amlogic/arch-a4/cpu.h
index 5eebed7..57f7fde 100644
--- a/arch/arm/include/asm/amlogic/arch-a4/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-a4/cpu.h
@@ -82,4 +82,7 @@
#define CONFIG_SYS_NAND_BASE_LIST {0}
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-s4/cpu.h b/arch/arm/include/asm/amlogic/arch-s4/cpu.h
index c257c21..d9d3df3 100644
--- a/arch/arm/include/asm/amlogic/arch-s4/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-s4/cpu.h
@@ -81,4 +81,7 @@
#define CONFIG_SYS_NAND_BASE_LIST {0}
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-s6/cpu.h b/arch/arm/include/asm/amlogic/arch-s6/cpu.h
index 28cdc61..213ea58 100644
--- a/arch/arm/include/asm/amlogic/arch-s6/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-s6/cpu.h
@@ -81,4 +81,9 @@
#define SBOOT_KEYSLOT_BASE 128
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-s6/storage.h b/arch/arm/include/asm/amlogic/arch-s6/storage.h
index c920d7c..5f7c535 100644
--- a/arch/arm/include/asm/amlogic/arch-s6/storage.h
+++ b/arch/arm/include/asm/amlogic/arch-s6/storage.h
@@ -33,7 +33,7 @@
#define BOOTLOADER_MODE_EMMC COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#ifdef ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
@@ -42,6 +42,9 @@
#endif
#define BOOTINFO_PROGRAMMER_SUPPORT 1
+
+#define SPINOR_HAS_BOOTINFO 1
+
/*
* TODO: This is the attribute of nand, it will be moved to the
* plat file of nand in the future.
diff --git a/arch/arm/include/asm/amlogic/arch-s7/cpu.h b/arch/arm/include/asm/amlogic/arch-s7/cpu.h
index 6c1657c..f943ef3 100644
--- a/arch/arm/include/asm/amlogic/arch-s7/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-s7/cpu.h
@@ -81,4 +81,7 @@
#define SBOOT_KEYSLOT_BASE 128
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-s7d/cpu.h b/arch/arm/include/asm/amlogic/arch-s7d/cpu.h
index 33543a0..70576ce 100644
--- a/arch/arm/include/asm/amlogic/arch-s7d/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-s7d/cpu.h
@@ -83,4 +83,7 @@
#define CONFIG_SYS_NAND_BASE_LIST {0}
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-t5m/cpu.h b/arch/arm/include/asm/amlogic/arch-t5m/cpu.h
index 42b945f..3f2d24f 100644
--- a/arch/arm/include/asm/amlogic/arch-t5m/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-t5m/cpu.h
@@ -102,4 +102,7 @@
#define CONFIG_MODIFY_INITRD_HIGH
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-t6d/cpu.h b/arch/arm/include/asm/amlogic/arch-t6d/cpu.h
index cb2e596..1771900 100644
--- a/arch/arm/include/asm/amlogic/arch-t6d/cpu.h
+++ b/arch/arm/include/asm/amlogic/arch-t6d/cpu.h
@@ -81,4 +81,7 @@
#define SBOOT_KEYSLOT_BASE 32
+/*improve eth performance*/
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/amlogic/arch-t6d/usb.h b/arch/arm/include/asm/amlogic/arch-t6d/usb.h
index 3747ff9..dced26a 100644
--- a/arch/arm/include/asm/amlogic/arch-t6d/usb.h
+++ b/arch/arm/include/asm/amlogic/arch-t6d/usb.h
@@ -242,12 +242,4 @@
int usb2_phy_init(struct phy *phy);
void usb_device_mode_init(int phy_num);
int m31_phy_init(unsigned int phy_num);
-
-/* cc */
-int aml_cc_get_ufp_status(u32 *val);
-void print_aml_cc_ufp_current_type(void);
-
-/* bc */
-int aml_bc_get_port_status(u32 *val);
-void print_aml_bc_port_status(void);
#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 5a3b74e..b61819a 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -495,7 +495,12 @@
{
#ifdef CONFIG_AML_UPDATE_PDVFS
run_command("update_pdvfs", 0);
+ run_command("update_cooling_state", 0);
#endif
+
+ if (IS_ENABLED(CONFIG_CMD_SCMI_SHMEM_ADDR))
+ run_command("update_scmi_shmem", 0);
+
#ifdef CONFIG_KEY_PRESERVE
(*((volatile unsigned int *)(STARTUP_KEY_PRESERVE))) |= 0x1;
#endif
@@ -689,7 +694,6 @@
boot_jump_linux(images, flag);
return 0;
}
-
boot_prep_linux(images);
boot_jump_linux(images, flag);
return 0;
diff --git a/arch/arm/mach-meson/s6/usb.c b/arch/arm/mach-meson/s6/usb.c
index 8114fd2..c8729ea 100644
--- a/arch/arm/mach-meson/s6/usb.c
+++ b/arch/arm/mach-meson/s6/usb.c
@@ -290,6 +290,20 @@
return 0;
}
+void set_usb_power_off(void)
+{
+ unsigned int val;
+ // only off the phy21 now.
+ printf("set s6 usb phy off.\n");
+ val = readl(RESETCTRL_RESET0_LEVEL);
+ val &= ~(1 << PHY20_RESET_LEVEL_BIT);
+ writel(val, RESETCTRL_RESET0_LEVEL);
+
+ val = readl(RESETCTRL_RESET0_LEVEL);
+ val &= ~(1 << PHY21_RESET_LEVEL_BIT);
+ writel(val, RESETCTRL_RESET0_LEVEL);
+}
+
/**************************************************************/
/* device mode config */
/**************************************************************/
diff --git a/arch/arm/mach-meson/s7/usb.c b/arch/arm/mach-meson/s7/usb.c
index 227a134..48a198e 100644
--- a/arch/arm/mach-meson/s7/usb.c
+++ b/arch/arm/mach-meson/s7/usb.c
@@ -303,9 +303,9 @@
{
unsigned int val;
// only off the phy21 now.
- printf("set s7 usb phy21 off.\n");
+ printf("set s7 usb phy off.\n");
val = readl(RESETCTRL_RESET0_LEVEL);
- val &= ~(1 << PHY21_RESET_LEVEL_BIT);
+ val &= ~(3 << PHY20_RESET_LEVEL_BIT);
writel(val, RESETCTRL_RESET0_LEVEL);
}
diff --git a/arch/arm/mach-meson/s7d/usb.c b/arch/arm/mach-meson/s7d/usb.c
index d4c607e..f552d3f 100644
--- a/arch/arm/mach-meson/s7d/usb.c
+++ b/arch/arm/mach-meson/s7d/usb.c
@@ -293,9 +293,9 @@
{
unsigned int val;
// only off the phy21 now.
- printf("set s7d usb phy21 off.\n");
+ printf("set s7d usb phy off.\n");
val = readl(RESETCTRL_RESET0_LEVEL);
- val &= ~(1 << PHY21_RESET_LEVEL_BIT);
+ val &= ~(3 << PHY20_RESET_LEVEL_BIT);
writel(val, RESETCTRL_RESET0_LEVEL);
}
diff --git a/arch/arm/mach-meson/t6d/usb.c b/arch/arm/mach-meson/t6d/usb.c
index f3a29e0..938d82f 100644
--- a/arch/arm/mach-meson/t6d/usb.c
+++ b/arch/arm/mach-meson/t6d/usb.c
@@ -20,6 +20,8 @@
#include <asm-generic/gpio.h>
#include <asm/amlogic/arch/timer.h>
+#include <amlogic/pm.h>
+
#define PHY20_RESET_LEVEL_BIT 6
#define PHY21_RESET_LEVEL_BIT 7
#define PHY22_RESET_LEVEL_BIT 8
@@ -313,16 +315,62 @@
return 0;
}
+static unsigned int usb_powerctrl_reg = 0xffffffff;
+
void set_usb_power_off(void)
{
unsigned int val;
// only off the phy21 now.
- printf("set s7 usb phy21 off.\n");
- val = readl(RESETCTRL_RESET0_LEVEL);
- val &= ~(1 << PHY21_RESET_LEVEL_BIT);
+ printf("set t6d usb phy off.\n");
+ usb_powerctrl_reg = readl(RESETCTRL_RESET0_LEVEL);
+ val = usb_powerctrl_reg;
+ val &= ~(7 << PHY20_RESET_LEVEL_BIT);
writel(val, RESETCTRL_RESET0_LEVEL);
}
+void set_usb_power_on(void)
+{
+ // only on the phy21 now.
+ printf("set t6d usb phy on.\n");
+ writel(usb_powerctrl_reg, RESETCTRL_RESET0_LEVEL);
+}
+
+int aml_usb_suspend(void *pm_ops)
+{
+ struct dev_pm_ops *pm = (struct dev_pm_ops *)pm_ops;
+
+ printf("usb suspend: %s\n", pm->name);
+ set_usb_power_off();
+
+ return 0;
+}
+
+int aml_usb_resume(void *pm_ops)
+{
+ struct dev_pm_ops *pm = (struct dev_pm_ops *)pm_ops;
+
+ printf("usb resume: %s\n", pm->name);
+ set_usb_power_on();
+
+ return 0;
+}
+
+int aml_usb_poweroff(void *pm_ops)
+{
+ struct dev_pm_ops *pm = (struct dev_pm_ops *)pm_ops;
+
+ printf("usb poweroff: %s\n", pm->name);
+ aml_usb_suspend(pm_ops);
+ return 0;
+}
+
+void usb_power_init(void)
+{
+ struct dev_pm_ops *pm_ops = NULL;
+
+ pm_ops = dev_register_pm("usb_ops", &aml_usb_suspend, &aml_usb_resume, &aml_usb_poweroff);
+}
+
/**************************************************************/
/* device mode config */
/**************************************************************/
@@ -402,247 +450,3 @@
//--------------------------------------------------
}
-
-/****************************************************************/
-/* CC config */
-/****************************************************************/
-#define CC_OTP_REG 0x0
-#define USB_CC_INT_CLR 0x4
-#define CC_INT_CLEAN BIT(0)
-#define USB_CC_ANA 0x8
-#define CC_ANA_CTRL_EN BIT(0)
-#define CC_UFP_EN BIT(1)
-#define CC_DFP_EN BIT(2)
-#define CC_RP_SEL0 (BIT(5) | BIT(6) | BIT(7))
-#define USB_CC_CNT 0xC
-#define USB_CC_INT_MASK 0x10
-#define CABLE_PLUG_IN BIT(6)
-#define CABLE_PLUG_OUT BIT(7)
-#define USB_CC_CTRL 0x14
-#define CC_TOP_ENABLE BIT(0)
-#define CC_FAST_ENABLE BIT(1)
-#define CC_VBUS_FORCE_EN BIT(4)
-#define USB_CC_INT_STATUS 0x18
-#define CC_UFP_CURRENT_INT BIT(0)
-#define CC_UFP_PLUG_IN_INT BIT(1)
-#define CC_UFP_PLUG_OUT_INT BIT(2)
-#define USB_CC_FSM_STATUS 0x1C
-#define USB_CC_UFP_STATUS 0x20
-#define USB_CC_DFP_STATUS 0x24
-
-#define RESETCTRL0_OFFSET 0
-#define CC_RESET_BIT 10
-
-#define CC_REG_BASE 0xfe35e000
-
-static void aml_cc_ufp_init(void)
-{
- u32 val;
-
- /* reset cc */
- val = readl(RESET_BASE + RESETCTRL0_OFFSET);
- val = CC_RESET_BIT;
- writel(val, RESET_BASE + RESETCTRL0_OFFSET);
-
- usb_udelay(800);
-
- /* set mode */
- val = readl(CC_REG_BASE + USB_CC_ANA);
- val &= (~(CC_ANA_CTRL_EN | CC_DFP_EN | CC_RP_SEL0));
- val |= CC_UFP_EN;
- writel(val, CC_REG_BASE + USB_CC_ANA);
-
- /* enable CC */
- val = readl(CC_REG_BASE + USB_CC_CTRL);
- val &= ~CC_VBUS_FORCE_EN;
- val |= CC_TOP_ENABLE;
- writel(val, CC_REG_BASE + USB_CC_CTRL);
-}
-
-int aml_cc_get_ufp_status(u32 *val)
-{
- u32 cnt = 0;
-
- aml_cc_ufp_init();
-
- do {
- usb_udelay(20);
- cnt++;
-
- if (cnt > 10000)
- break;
-
- } while (!(readl(CC_REG_BASE + USB_CC_INT_STATUS) &
- (CC_UFP_CURRENT_INT | CC_UFP_PLUG_IN_INT | CC_UFP_PLUG_OUT_INT)));
-
- *val = readl(CC_REG_BASE + USB_CC_UFP_STATUS);
-
- /* clear INT */
- if ((readl(CC_REG_BASE + USB_CC_INT_STATUS)) & CC_UFP_PLUG_OUT_INT)
- writel(CC_INT_CLEAN, CC_REG_BASE + USB_CC_INT_CLR);
-
- return 0;
-}
-
-void print_aml_cc_ufp_current_type(void)
-{
- u32 status, cnt = 0;
-
- aml_cc_ufp_init();
-
- do {
- usb_udelay(20);
- cnt++;
-
- if (cnt > 10000)
- break;
-
- } while (!(readl(CC_REG_BASE + USB_CC_INT_STATUS) &
- (CC_UFP_CURRENT_INT | CC_UFP_PLUG_IN_INT | CC_UFP_PLUG_OUT_INT)));
-
- status = readl(CC_REG_BASE + USB_CC_UFP_STATUS);
- switch (status & GENMASK(5, 3)) {
- case 0x0:
- printf("cc_ufp_current_type: detach\n");
- break;
- case 0x8:
- printf("cc_ufp_current_type: supply <= 0.5 current\n");
- break;
- case 0x18:
- printf("cc_ufp_current_type: Rp=12K, supply 1.5 current\n");
- break;
- case 0x38:
- printf("cc_ufp_current_type: Rp=4.7K, supply 3.0 current\n");
- break;
- }
-
- /* clear INT */
- if ((readl(CC_REG_BASE + USB_CC_INT_STATUS)) & CC_UFP_PLUG_OUT_INT)
- writel(CC_INT_CLEAN, CC_REG_BASE + USB_CC_INT_CLR);
-}
-
-/**************************************************************/
-/* BC config */
-/**************************************************************/
-#define BC_CTRL 0x4
-#define BC_ENABLE BIT(0)
-#define BC_DET_CLEAN BIT(1)
-#define BC_INT_CLEAN BIT(2)
-#define BC_DETECT_END BIT(3)
-#define BC_DIG_STATUS 0x1C
-
-#define CFG_REG0 0
-#define HOST_DEVICE BIT(0)
-#define IDPULLUP0 BIT(4)
-#define CFG_REG3 0xC
-#define VBUSDIG_IRQ BIT(7)
-#define VBUSDIG_EN1 BIT(5)
-#define VBUSDIG_EN0 BIT(4)
-
-#define BC_REG_BASE 0xfe35d000
-
-#define BC_RESET_BIT 11
-
-
-static void aml_bc_init(void)
-{
- u32 val;
-
- /* set phy device mode */
- val = readl(PHY_COMP_BASE + CFG_REG0);
- val &= ~HOST_DEVICE;
- writel(val, PHY_COMP_BASE + CFG_REG0);
-
- /* reset bc */
- val = readl(RESET_BASE + RESETCTRL0_OFFSET);
- val = BC_RESET_BIT;
- writel(val, RESET_BASE + RESETCTRL0_OFFSET);
-
- usb_udelay(200000);
-
- /* enable BC */
- val = readl(BC_REG_BASE + BC_CTRL);
- val |= BC_ENABLE;
- writel(val, BC_REG_BASE + BC_CTRL);
-}
-
-int aml_bc_get_port_status(u32 *val)
-{
- u32 cnt = 0;
-
- aml_bc_init();
-
- do {
- usb_udelay(20);
- cnt++;
-
- if (cnt > 10000) {
- printf("BC port status detect timeout\n");
- return -EINVAL;
- }
- } while (!(readl(BC_REG_BASE + BC_CTRL) & BC_DETECT_END));
-
- *val = readl(BC_REG_BASE + BC_DIG_STATUS);
-
- return 0;
-}
-
-void print_aml_bc_port_status(void)
-{
- u32 status, cnt = 0;
-
- aml_bc_init();
-
- do {
- usb_udelay(20);
- cnt++;
-
- if (cnt > 10000) {
- printf("BC port status detect timeout\n");
- return;
- }
- } while (!(readl(BC_REG_BASE + BC_CTRL) & BC_DETECT_END));
-
- status = readl(BC_REG_BASE + BC_DIG_STATUS);
- switch (status & GENMASK(3, 0)) {
- case 0x0:
- printf("BC STATUS is : default\n");
- break;
- case 0x1:
- printf("BC STATUS is : SDP\n");
- break;
- case 0x2:
- printf("BC STATUS is : DCP\n");
- break;
- case 0x3:
- printf("BC STATUS is : CDP\n");
- break;
- case 0x4:
- printf("BC STATUS is : ACA_A\n");
- break;
- case 0x5:
- printf("BC STATUS is : ACA_B\n");
- break;
- case 0x6:
- printf("BC STATUS is : ACA_C\n");
- break;
- case 0x7:
- printf("BC STATUS is : ACA_DOCK\n");
- break;
- case 0x8:
- printf("BC STATUS is : ACA GND ERROR\n");
- break;
- case 0x9:
- printf("BC STATUS is : analog output error\n");
- break;
- case 0xA:
- printf("BC STATUS is : VBUS remove\n");
- break;
- case 0xB:
- printf("BC STATUS is : VBUS invalid\n");
- break;
- default:
- printf("BC STATUS is : RESERVED\n");
- break;
- }
-}
diff --git a/board/amlogic/common/board.c b/board/amlogic/common/board.c
index 2d7a732..8baf7ea 100644
--- a/board/amlogic/common/board.c
+++ b/board/amlogic/common/board.c
@@ -343,7 +343,6 @@
#endif
}
-#ifdef CONFIG_BOARD_RNG_SEED
unsigned int random(void)
{
volatile unsigned int val;
@@ -391,13 +390,32 @@
return 0;
}
-#endif
#ifdef CONFIG_AML_DEFENV
const char * const _aml_env_reserv_array[] = {
"lock",
"upgrade_step",
"bootloader_version",
+ "hdmimode",
+ "is.bestmode",
+ "dts_to_gpt",
+ "fastboot_step",
+ "reboot_status",
+ "expect_index",
+ "recovery_check_part",
+ "defenv_para", //set in board_late_init
+#ifndef CONFIG_CMD_CAR_PARAMS
+ "outputmode",
+ "connector0_type",
+#endif
+ "sw_version", //linux swupdate version
+ NULL//Keep NULL be last to tell END
+};
+
+const char * const _aml_env_reserv_array1[] = {
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
"dts_to_gpt",
"fastboot_step",
"reboot_status",
diff --git a/board/amlogic/configs/a4_ba400.h b/board/amlogic/configs/a4_ba400.h
index d8607bb..e14eef1 100644
--- a/board/amlogic/configs/a4_ba400.h
+++ b/board/amlogic/configs/a4_ba400.h
@@ -338,5 +338,7 @@
#define CONFIG_FULL_RAMDUMP
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/a4_ba400_zircon.h b/board/amlogic/configs/a4_ba400_zircon.h
index fa31981..1744d9a 100644
--- a/board/amlogic/configs/a4_ba400_zircon.h
+++ b/board/amlogic/configs/a4_ba400_zircon.h
@@ -344,5 +344,7 @@
#define CONFIG_FULL_RAMDUMP
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/a4_ba409.h b/board/amlogic/configs/a4_ba409.h
index a32d35c..88a603c0 100644
--- a/board/amlogic/configs/a4_ba409.h
+++ b/board/amlogic/configs/a4_ba409.h
@@ -338,5 +338,7 @@
#define CONFIG_FULL_RAMDUMP
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/a4_skt.h b/board/amlogic/configs/a4_skt.h
index 3ee7d6f..1aaf05e 100644
--- a/board/amlogic/configs/a4_skt.h
+++ b/board/amlogic/configs/a4_skt.h
@@ -336,5 +336,7 @@
#define BL32_SHARE_MEM_SIZE 0x800000
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s1a_bg201.h b/board/amlogic/configs/s1a_bg201.h
index 7e3a38e..58224ee 100644
--- a/board/amlogic/configs/s1a_bg201.h
+++ b/board/amlogic/configs/s1a_bg201.h
@@ -381,5 +381,7 @@
#define CONFIG_INITRD_FDT_HIGH_ADDR
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s1a_bg209.h b/board/amlogic/configs/s1a_bg209.h
index 51487ca..105ef46 100644
--- a/board/amlogic/configs/s1a_bg209.h
+++ b/board/amlogic/configs/s1a_bg209.h
@@ -331,5 +331,7 @@
#define CONFIG_INITRD_FDT_HIGH_ADDR
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s1a_bg209_s805c1eng.h b/board/amlogic/configs/s1a_bg209_s805c1eng.h
index c6a6160..0c43cfa 100644
--- a/board/amlogic/configs/s1a_bg209_s805c1eng.h
+++ b/board/amlogic/configs/s1a_bg209_s805c1eng.h
@@ -330,5 +330,7 @@
#define CONFIG_INITRD_FDT_HIGH_ADDR
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s1a_skt.h b/board/amlogic/configs/s1a_skt.h
index 3494651..a83ff0a 100644
--- a/board/amlogic/configs/s1a_skt.h
+++ b/board/amlogic/configs/s1a_skt.h
@@ -331,5 +331,7 @@
#define CONFIG_FIP_IMG_SUPPORT 1
#define BL32_SHARE_MEM_SIZE 0x800000
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s4_ap222.h b/board/amlogic/configs/s4_ap222.h
index fe34d63..32dc4ec 100644
--- a/board/amlogic/configs/s4_ap222.h
+++ b/board/amlogic/configs/s4_ap222.h
@@ -341,5 +341,7 @@
#define CONFIG_FULL_RAMDUMP
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bl201.h b/board/amlogic/configs/s6_bl201.h
index 477891b..ee0563f 100644
--- a/board/amlogic/configs/s6_bl201.h
+++ b/board/amlogic/configs/s6_bl201.h
@@ -197,10 +197,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -370,5 +372,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bl204.h b/board/amlogic/configs/s6_bl204.h
index fa53bee..957e0f8 100644
--- a/board/amlogic/configs/s6_bl204.h
+++ b/board/amlogic/configs/s6_bl204.h
@@ -197,10 +197,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -369,5 +371,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bl208.h b/board/amlogic/configs/s6_bl208.h
index e5dd43f..5cd2633 100644
--- a/board/amlogic/configs/s6_bl208.h
+++ b/board/amlogic/configs/s6_bl208.h
@@ -191,10 +191,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -362,5 +364,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bl209.h b/board/amlogic/configs/s6_bl209.h
index ce4fe2e..d34e629 100644
--- a/board/amlogic/configs/s6_bl209.h
+++ b/board/amlogic/configs/s6_bl209.h
@@ -191,10 +191,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -362,5 +364,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bn201.h b/board/amlogic/configs/s6_bn201.h
index 2fb2fbe..341b3be 100644
--- a/board/amlogic/configs/s6_bn201.h
+++ b/board/amlogic/configs/s6_bn201.h
@@ -197,10 +197,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -370,5 +372,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bq201.h b/board/amlogic/configs/s6_bq201.h
index c77f61c..4fc899e 100644
--- a/board/amlogic/configs/s6_bq201.h
+++ b/board/amlogic/configs/s6_bq201.h
@@ -252,10 +252,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -423,5 +425,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bq208.h b/board/amlogic/configs/s6_bq208.h
index 1775d0c..31f31f0 100644
--- a/board/amlogic/configs/s6_bq208.h
+++ b/board/amlogic/configs/s6_bq208.h
@@ -251,10 +251,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -422,5 +424,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_bq209.h b/board/amlogic/configs/s6_bq209.h
index 2fba9a8..4c28ad0 100644
--- a/board/amlogic/configs/s6_bq209.h
+++ b/board/amlogic/configs/s6_bq209.h
@@ -252,10 +252,12 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
#define BOOTLOADER_MODE_ADVANCE_INIT 1
#define BOOTLOADER_DDR_FIP_SIZE 0x40000
@@ -423,5 +425,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s6_skt.h b/board/amlogic/configs/s6_skt.h
index 9e5ea4c..5dec129 100644
--- a/board/amlogic/configs/s6_skt.h
+++ b/board/amlogic/configs/s6_skt.h
@@ -190,12 +190,14 @@
#define CONFIG_NAND_TPL_COPY_NUM 2
#define CONFIG_NOR_TPL_COPY_NUM 1
#define CONFIG_TPL_SIZE_PER_COPY 0x380000
+/* define bootloader size for spi nor */
+#define CONFIG_BOOTLOADER_SIZE 0x380000
-#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_SNOR ADVANCE_BOOTLOADER
-#define BOOTLOADER_MODE_ADVANCE_INIT 1
-#define BOOTLOADER_DDR_FIP_SIZE 0x40000
+#define BOOTLOADER_MODE_NAND ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNAND ADVANCE_BOOTLOADER
+#define BOOTLOADER_MODE_SNOR COMPACT_BOOTLOADER
+#define BOOTLOADER_MODE_ADVANCE_INIT 1
+#define BOOTLOADER_DDR_FIP_SIZE 0x40000
/* mtd device rsv board config */
#ifndef CONFIG_ENV_IS_IN_NAND
@@ -360,5 +362,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_bh201.h b/board/amlogic/configs/s7_bh201.h
index 38cc611..d7527d4 100644
--- a/board/amlogic/configs/s7_bh201.h
+++ b/board/amlogic/configs/s7_bh201.h
@@ -369,5 +369,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_bh202.h b/board/amlogic/configs/s7_bh202.h
index 904e733..0e052f1 100644
--- a/board/amlogic/configs/s7_bh202.h
+++ b/board/amlogic/configs/s7_bh202.h
@@ -362,5 +362,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_bh209.h b/board/amlogic/configs/s7_bh209.h
index 96c1504..0c11d1a 100644
--- a/board/amlogic/configs/s7_bh209.h
+++ b/board/amlogic/configs/s7_bh209.h
@@ -362,5 +362,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_bp201.h b/board/amlogic/configs/s7_bp201.h
index 03c4a01..7c90174 100644
--- a/board/amlogic/configs/s7_bp201.h
+++ b/board/amlogic/configs/s7_bp201.h
@@ -369,5 +369,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_bp202.h b/board/amlogic/configs/s7_bp202.h
index ac64076..16ccac6 100644
--- a/board/amlogic/configs/s7_bp202.h
+++ b/board/amlogic/configs/s7_bp202.h
@@ -354,5 +354,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_skt.h b/board/amlogic/configs/s7_skt.h
index adb61a2..90f86c5 100644
--- a/board/amlogic/configs/s7_skt.h
+++ b/board/amlogic/configs/s7_skt.h
@@ -352,5 +352,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_t223.h b/board/amlogic/configs/s7_t223.h
index 983171b..d51682e 100644
--- a/board/amlogic/configs/s7_t223.h
+++ b/board/amlogic/configs/s7_t223.h
@@ -361,5 +361,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7_t233.h b/board/amlogic/configs/s7_t233.h
index 38cc611..d7527d4 100644
--- a/board/amlogic/configs/s7_t233.h
+++ b/board/amlogic/configs/s7_t233.h
@@ -369,5 +369,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7d_bm201.h b/board/amlogic/configs/s7d_bm201.h
index e59fc24..6be1d71 100644
--- a/board/amlogic/configs/s7d_bm201.h
+++ b/board/amlogic/configs/s7d_bm201.h
@@ -369,5 +369,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7d_bm202.h b/board/amlogic/configs/s7d_bm202.h
index d3b3d15..6b040ba 100644
--- a/board/amlogic/configs/s7d_bm202.h
+++ b/board/amlogic/configs/s7d_bm202.h
@@ -368,5 +368,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7d_bm209.h b/board/amlogic/configs/s7d_bm209.h
index 515e963..d7f4ece 100644
--- a/board/amlogic/configs/s7d_bm209.h
+++ b/board/amlogic/configs/s7d_bm209.h
@@ -364,5 +364,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7d_skt.h b/board/amlogic/configs/s7d_skt.h
index 4d8a512..0057239 100644
--- a/board/amlogic/configs/s7d_skt.h
+++ b/board/amlogic/configs/s7d_skt.h
@@ -347,5 +347,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/s7d_t232.h b/board/amlogic/configs/s7d_t232.h
index 7f1169d..e0f24d6 100644
--- a/board/amlogic/configs/s7d_t232.h
+++ b/board/amlogic/configs/s7d_t232.h
@@ -370,5 +370,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/t6d_br301.h b/board/amlogic/configs/t6d_br301.h
index 9501009..4e973e3 100644
--- a/board/amlogic/configs/t6d_br301.h
+++ b/board/amlogic/configs/t6d_br301.h
@@ -109,7 +109,6 @@
"dv_fw_dir=/reserved/firmware/dovi_fw.bin\0"\
"hdr_policy=0\0"\
"frac_rate_policy=1\0"\
- "ffv_wake=off\0"\
#ifndef CONFIG_PXP_DDR
#define CONFIG_PREBOOT \
@@ -120,7 +119,8 @@
"run upgrade_key;" \
"bcb uboot-command;"\
"run switch_bootmode;"\
- "run switch_usbmode;"
+ "run switch_usbmode;"\
+ "run reset_suspend;"
#else
#define CONFIG_PREBOOT "echo preboot"
@@ -382,5 +382,6 @@
#define CONFIG_AVB2_UBOOT_SHA256
#endif
+#define CONFIG_AML_KASLR_SEED
#define CONFIG_CMD_AFM 1
diff --git a/board/amlogic/configs/t6d_br309.h b/board/amlogic/configs/t6d_br309.h
index 4d2e4f5..d34f020 100644
--- a/board/amlogic/configs/t6d_br309.h
+++ b/board/amlogic/configs/t6d_br309.h
@@ -111,7 +111,6 @@
"dv_fw_dir=/reserved/firmware/dovi_fw.bin\0"\
"hdr_policy=0\0"\
"frac_rate_policy=1\0"\
- "ffv_wake=off\0"\
#ifndef CONFIG_PXP_DDR
#define CONFIG_PREBOOT \
@@ -121,7 +120,8 @@
"run storeargs;"\
"run upgrade_key;" \
"bcb uboot-command;"\
- "run switch_bootmode;"
+ "run switch_bootmode;"\
+ "run reset_suspend;"
#else
#define CONFIG_PREBOOT "echo preboot"
#endif
@@ -379,5 +379,7 @@
#define BL32_SHARE_MEM_SIZE 0x800000
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/t6d_skt.h b/board/amlogic/configs/t6d_skt.h
index eee3da7..ab46b08 100644
--- a/board/amlogic/configs/t6d_skt.h
+++ b/board/amlogic/configs/t6d_skt.h
@@ -101,7 +101,6 @@
"dv_fw_dir=/reserved/firmware/dovi_fw.bin\0"\
"hdr_policy=0\0"\
"frac_rate_policy=1\0"\
- "ffv_wake=off\0"\
#ifndef CONFIG_PXP_DDR
#define CONFIG_PREBOOT \
@@ -111,7 +110,8 @@
"run storeargs;"\
"run upgrade_key;" \
"bcb uboot-command;"\
- "run switch_bootmode;"
+ "run switch_bootmode;"\
+ "run reset_suspend;"
#else
#define CONFIG_PREBOOT "echo preboot"
#endif
@@ -368,5 +368,7 @@
#define BL32_SHARE_MEM_SIZE 0x800000
#define CONFIG_AVB2_UBOOT_SHA256
+#define CONFIG_AML_KASLR_SEED
+
#endif
diff --git a/board/amlogic/configs/t6d_t335.h b/board/amlogic/configs/t6d_t335.h
index 138a360..4c81b44 100644
--- a/board/amlogic/configs/t6d_t335.h
+++ b/board/amlogic/configs/t6d_t335.h
@@ -15,7 +15,7 @@
* platform power init config
*/
-#define AML_VCCK_INIT_VOLTAGE 1010 //VCCK power up voltage
+#define AML_VCCK_INIT_VOLTAGE 1009 //VCCK power up voltage
#define AML_VDDEE_INIT_VOLTAGE 870 // VDDEE power up voltage
/*Distinguish whether to use efuse to adjust vddee*/
@@ -123,7 +123,8 @@
"run upgrade_key;" \
"bcb uboot-command;"\
"run switch_bootmode;"\
- "run switch_usbmode;"
+ "run switch_usbmode;"\
+ "run reset_suspend;"
#else
#define CONFIG_PREBOOT "echo preboot"
@@ -385,5 +386,7 @@
#define CONFIG_AVB2_UBOOT_SHA256
#endif
+#define CONFIG_AML_KASLR_SEED
+
#define CONFIG_CMD_AFM 1
diff --git a/board/amlogic/env/android_multidisplay.env b/board/amlogic/env/android_multidisplay.env
index c69a072..f93d704 100644
--- a/board/amlogic/env/android_multidisplay.env
+++ b/board/amlogic/env/android_multidisplay.env
@@ -53,6 +53,9 @@
fs_type=rootfstype=ramfs
fastboot_step=0
usb_status=detach
+ffv_wake=off
+powermode=on
+suspend=off
#ifdef CONFIG_NOVERBOSE_BUILD
loglevel=2
@@ -92,7 +95,7 @@
upgrade_check=
echo recovery_status=${recovery_status};
if itest.s "${recovery_status}" == "in_progress"; then
- run storeargs; run recovery_from_flash;
+ run init_display; run storeargs; run recovery_from_flash;
else fi;
echo upgrade_step=${upgrade_step};
if itest ${upgrade_step} == 3; then run storeargs; run update; fi;
@@ -190,6 +193,7 @@
if test ${active_slot} = normal; then
setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt}
recovery_part=${recovery_part} recovery_offset=${recovery_offset};
+ avb recovery 1;
if test ${upgrade_step} = 3; then
if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;
if test ${vendor_boot_mode} = true; then
diff --git a/board/amlogic/env/android_ott.env b/board/amlogic/env/android_ott.env
index 910d7d1..3ab27b6 100644
--- a/board/amlogic/env/android_ott.env
+++ b/board/amlogic/env/android_ott.env
@@ -96,7 +96,7 @@
upgrade_check=
echo recovery_status=${recovery_status};
if itest.s "${recovery_status}" == "in_progress"; then
- run storeargs; run recovery_from_flash;
+ run init_display; run storeargs; run recovery_from_flash;
else fi;
echo upgrade_step=${upgrade_step};
if itest ${upgrade_step} == 3; then run storeargs; run update; fi;
@@ -141,6 +141,9 @@
else if test ${reboot_mode} = fastboot; then fastboot 0; fi;
fi;fi;fi;fi;fi;
+enter_fastboot=
+ fastboot 0;
+
storeboot=
run get_os_type;
run storage_param;
@@ -191,6 +194,7 @@
if test ${active_slot} = normal; then
setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt}
recovery_part=${recovery_part} recovery_offset=${recovery_offset};
+ avb recovery 1;
if test ${upgrade_step} = 3; then
if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;
if test ${vendor_boot_mode} = true; then
diff --git a/board/amlogic/env/android_tv.env b/board/amlogic/env/android_tv.env
index 2bbcdf5..e9e0910 100644
--- a/board/amlogic/env/android_tv.env
+++ b/board/amlogic/env/android_tv.env
@@ -64,6 +64,9 @@
ddr_size=0
fs_type=rootfstype=ramfs
fastboot_step=0
+ffv_wake=off
+powermode=on
+suspend=off
#ifdef CONFIG_NOVERBOSE_BUILD
loglevel=2
@@ -103,16 +106,17 @@
upgrade_check=
echo recovery_status=${recovery_status};
if itest.s "${recovery_status}" == "in_progress"; then
- run storeargs; run recovery_from_flash;
+ run init_display; run storeargs; run recovery_from_flash;
else fi;
echo upgrade_step=${upgrade_step};
if itest ${upgrade_step} == 3; then run storeargs; run update; fi;
initargs=init=/init ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4
+console=ttyS0,115200
storeargs=get_bootloaderversion;
setenv bootargs ${initargs}
- loglevel=${loglevel} console=ttyS0,${baudrate} no_console_suspend earlycon=aml_uart,${uart_base}
+ loglevel=${loglevel} console=${console} no_console_suspend earlycon=aml_uart,${uart_base}
scramble_reg=${scramble_reg} cma_first_wm_low=on
otg_device=${otg_device} disable_ir=${disable_ir} cpufreq.default_governor=${default_governor}
logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} connector0_type=${connector0_type}
@@ -209,6 +213,9 @@
fastboot 1;
fi; fi; fi; fi; fi; fi; fi;
+enter_fastboot=
+ fastboot 1;
+
switch_usbmode=
if test ${usb2t_mode} = 1; then
#setenv bootargs ${bootargs} usb2t_mode=1;
@@ -264,6 +271,7 @@
if test ${active_slot} = normal; then
setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt}
recovery_part=${recovery_part} recovery_offset=${recovery_offset};
+ avb recovery 1;
if test ${upgrade_step} = 3; then
if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;
if test ${vendor_boot_mode} = true; then
diff --git a/board/amlogic/env/linux.env b/board/amlogic/env/linux.env
index 586c002..43a4b7e 100644
--- a/board/amlogic/env/linux.env
+++ b/board/amlogic/env/linux.env
@@ -36,6 +36,9 @@
fb_addr=0x00300000
fastboot_step=0
default_governor=performance
+ffv_wake=off
+powermode=on
+suspend=off
#ifdef CONFIG_NOVERBOSE_BUILD
loglevel=2
@@ -59,7 +62,7 @@
upgrade_check=
echo recovery_status=${recovery_status};
if itest.s "${recovery_status}" == "in_progress"; then
- run storeargs; run recovery_from_flash;
+ run init_display; run storeargs; run recovery_from_flash;
else fi;
echo upgrade_step=${upgrade_step};
if itest ${upgrade_step} == 3; then run storeargs; run update; fi;
@@ -97,6 +100,9 @@
else if test ${reboot_mode} = fastboot; then fastboot 0; fi;
fi;fi;fi;fi;fi;
+enter_fastboot=
+ fastboot 0;
+
storeboot=
run get_os_type;
run storage_param;
@@ -146,6 +152,7 @@
if test ${active_slot} = normal; then
setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt}
recovery_part=${recovery_part} recovery_offset=${recovery_offset};
+ avb recovery 1;
if test ${upgrade_step} = 3; then
if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;
if test ${vendor_boot_mode} = true; then
diff --git a/board/amlogic/env/pxp.env b/board/amlogic/env/pxp.env
index 3c6d039..b4c54ca 100644
--- a/board/amlogic/env/pxp.env
+++ b/board/amlogic/env/pxp.env
@@ -31,6 +31,9 @@
write_boot=0
fastboot_step=0
default_governor=performance
+ffv_wake=off
+powermode=on
+system=off
#ifdef CONFIG_KNL_LOG_LEVEL
loglevel=CONFIG_KNL_LOG_LEVEL
@@ -50,7 +53,7 @@
upgrade_check=
echo recovery_status=${recovery_status};
if itest.s "${recovery_status}" == "in_progress"; then
- run storeargs; run recovery_from_flash;
+ run init_display; run storeargs; run recovery_from_flash;
else fi;
echo upgrade_step=${upgrade_step};
if itest ${upgrade_step} == 3; then run storeargs; run update; fi;
@@ -85,6 +88,9 @@
else if test ${reboot_mode} = fastboot; then fastboot 0; fi;
fi;fi;fi;fi;fi;
+enter_fastboot=
+ fastboot 0;
+
storeboot=
run get_os_type;
run storage_param;
@@ -128,6 +134,7 @@
if test ${active_slot} = normal; then
setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt}
recovery_part=${recovery_part} recovery_offset=${recovery_offset};
+ avb recovery 1;
if test ${upgrade_step} = 3; then
if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;
if test ${vendor_boot_mode} = true; then
diff --git a/board/amlogic/s6_bl201/firmware/ddr_timing.c b/board/amlogic/s6_bl201/firmware/ddr_timing.c
index 67ccde8..3e6d74a 100644
--- a/board/amlogic/s6_bl201/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bl201/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bl201/s6_bl201.c b/board/amlogic/s6_bl201/s6_bl201.c
index a96fe11..5b73e2d 100644
--- a/board/amlogic/s6_bl201/s6_bl201.c
+++ b/board/amlogic/s6_bl201/s6_bl201.c
@@ -160,6 +160,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
@@ -366,9 +368,9 @@
ulong ddr_size = (readl(SYSCTRL_SEC_STATUS_REG4) & ~0xfffffUL) << 4;
switch (ddr_size) {
- case 0x100000000UL:
- strcpy(dtb_name, "s6_s905x5_bl201-4g\0");
- break;
+ //case 0x100000000UL:
+ // strcpy(dtb_name, "s6_s905x5_bl201-4g\0");
+ // break;
case 0x200000000UL:
strcpy(dtb_name, "s6_s905x5_bl201-8g\0");
break;
@@ -376,7 +378,7 @@
strcpy(dtb_name, "s6_s905x5_bl201-16g\0");
break;
default:
- strcpy(dtb_name, "s6_s905x5_bl201\0");
+ strcpy(dtb_name, "s6_s905x5_bl201-2g\0");
break;
}
diff --git a/board/amlogic/s6_bl204/firmware/ddr_timing.c b/board/amlogic/s6_bl204/firmware/ddr_timing.c
index 7f09dde..3e6d74a 100644
--- a/board/amlogic/s6_bl204/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bl204/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
@@ -319,7 +321,7 @@
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_version = 9196,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
diff --git a/board/amlogic/s6_bl204/s6_bl204.c b/board/amlogic/s6_bl204/s6_bl204.c
index e09d1b0..ca0240f 100644
--- a/board/amlogic/s6_bl204/s6_bl204.c
+++ b/board/amlogic/s6_bl204/s6_bl204.c
@@ -168,6 +168,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
@@ -384,11 +386,11 @@
// strcpy(dtb_name, "s6_s905x5_bl201-16g\0");
// break;
// default:
-// strcpy(dtb_name, "s6_s905x5_bl201\0");
+// strcpy(dtb_name, "s6_s905x5_bl201-2g\0");
// break;
// }
- strcpy(dtb_name, "s6_s905x5_bl204-4g\0");
+ strcpy(dtb_name, "s6_s905x5_bl204-2g\0");
strcpy(name, dtb_name);
env_set("aml_dt", dtb_name);
return 0;
diff --git a/board/amlogic/s6_bl208/firmware/ddr_timing.c b/board/amlogic/s6_bl208/firmware/ddr_timing.c
index 67ccde8..3e6d74a 100644
--- a/board/amlogic/s6_bl208/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bl208/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bl208/s6_bl208.c b/board/amlogic/s6_bl208/s6_bl208.c
index ed76aa8..16bf01f 100644
--- a/board/amlogic/s6_bl208/s6_bl208.c
+++ b/board/amlogic/s6_bl208/s6_bl208.c
@@ -160,6 +160,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_bl209/firmware/ddr_timing.c b/board/amlogic/s6_bl209/firmware/ddr_timing.c
index 67ccde8..3e6d74a 100644
--- a/board/amlogic/s6_bl209/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bl209/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bl209/s6_bl209.c b/board/amlogic/s6_bl209/s6_bl209.c
index 04c27d9..2942b44 100644
--- a/board/amlogic/s6_bl209/s6_bl209.c
+++ b/board/amlogic/s6_bl209/s6_bl209.c
@@ -160,6 +160,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_bn201/firmware/ddr_timing.c b/board/amlogic/s6_bn201/firmware/ddr_timing.c
index 67ccde8..3e6d74a 100644
--- a/board/amlogic/s6_bn201/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bn201/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bn201/s6_bn201.c b/board/amlogic/s6_bn201/s6_bn201.c
index 526706d..be9d437 100644
--- a/board/amlogic/s6_bn201/s6_bn201.c
+++ b/board/amlogic/s6_bn201/s6_bn201.c
@@ -160,6 +160,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_bq201/firmware/ddr_timing.c b/board/amlogic/s6_bq201/firmware/ddr_timing.c
index c4a0df0..b5a972b 100644
--- a/board/amlogic/s6_bq201/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bq201/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bq201/s6_bq201.c b/board/amlogic/s6_bq201/s6_bq201.c
index 7dbf1a2..1dd3e77 100644
--- a/board/amlogic/s6_bq201/s6_bq201.c
+++ b/board/amlogic/s6_bq201/s6_bq201.c
@@ -163,6 +163,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_bq208/firmware/ddr_timing.c b/board/amlogic/s6_bq208/firmware/ddr_timing.c
index c4a0df0..b5a972b 100644
--- a/board/amlogic/s6_bq208/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bq208/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bq208/s6_bq208.c b/board/amlogic/s6_bq208/s6_bq208.c
index e3ef518..83b0b1c 100644
--- a/board/amlogic/s6_bq208/s6_bq208.c
+++ b/board/amlogic/s6_bq208/s6_bq208.c
@@ -163,6 +163,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_bq209/firmware/ddr_timing.c b/board/amlogic/s6_bq209/firmware/ddr_timing.c
index c4a0df0..b5a972b 100644
--- a/board/amlogic/s6_bq209/firmware/ddr_timing.c
+++ b/board/amlogic/s6_bq209/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s6_bq209/s6_bq209.c b/board/amlogic/s6_bq209/s6_bq209.c
index 3f0f29e..7bcdb2b 100644
--- a/board/amlogic/s6_bq209/s6_bq209.c
+++ b/board/amlogic/s6_bq209/s6_bq209.c
@@ -163,6 +163,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
get_stick_reboot_flag_mbx();
#ifdef CONFIG_PXP_EMULATOR
diff --git a/board/amlogic/s6_skt/firmware/ddr_timing.c b/board/amlogic/s6_skt/firmware/ddr_timing.c
index 67ccde8..3e6d74a 100644
--- a/board/amlogic/s6_skt/firmware/ddr_timing.c
+++ b/board/amlogic/s6_skt/firmware/ddr_timing.c
@@ -10,6 +10,7 @@
#define DDR_FUNC_CONFIG_RX_REPLICA_VT_ENABLE (0 + (1 << 17))
#define DDR_FUNC_CONFIG_ENABLE_PZQ_DET_DRAM_TYPE_RETURN (0 + (1 << 20))
#define DDR_FUNC_CONFIG_AUTO_DET_DQ_PINMUX_FUNCTION (0 + (1 << 21))
+#define DDR_FUNC_CONFIG_RD_ECC_FUNCTION (0 + (1 << 22))
#define DDR_FUNC_CONFIG_WR_ECC_FUNCTION (0 + (1 << 17))
//bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
#define DDR_ID_ACS_ADC ((3 << 6) | (8))
@@ -147,12 +148,12 @@
ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default[] = {
#if LPDDR5_SKT
-#define CACLU_CLK_LP5 792 //1792//600 //1200 //(1900)// (1440)//(1008)
+#define CACLU_CLK_LP5 687 //687--5500//600 //1200 //(1900)// (1440)//(1008)
//ddr_set_ps0_only_t __attribute__ ((aligned(8))) ddr_set_t_default_lp5 = {
{
.cfg_board_common_setting.timming_magic = 0,
.cfg_board_common_setting.timming_max_valid_configs = 1,
- .cfg_board_common_setting.timming_struct_version = 9196,
+ .cfg_board_common_setting.timming_struct_version = 9304,
.cfg_board_common_setting.timming_struct_org_size =
sizeof(ddr_set_ps0_only_t),
.cfg_board_common_setting.timming_struct_real_size = 0,
@@ -165,7 +166,8 @@
0x0, 0, 0, 0
},
#endif
- .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION |
+ DDR_FUNC_CONFIG_RD_ECC_FUNCTION,
.cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
.cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR5,
.cfg_board_common_setting.enable_lpddr4x_mode = 0,
@@ -261,22 +263,22 @@
.cfg_ddr_training_delay_ps.dac_offset[3] = (0 << 7) | 0x1,//1step 2mv
//.cfg_ddr_training_delay_ps.dac_offset[0] = (1 << 7) | 0x3,
//.cfg_ddr_training_delay_ps.dac_offset[1] = (0 << 7) | 0x3,
- //.cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x8, //write dqs
- //.cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x8, //write dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x4,//read dqs
- .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x4,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[0] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[1] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[2] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[3] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[4] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[5] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[6] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[7] = (0 << 7) | 0x5, //write dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 0] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 1] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 2] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 3] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 4] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 5] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 6] = (1 << 7) | 0x2,//read dqs
+ .cfg_ddr_training_delay_ps.reserve_para[8 + 7] = (1 << 7) | 0x2,//read dqs
.cfg_ddr_training_delay_ps.ac_trace_delay[0] = 128 - 20, //0-11 cha,12-23 chb
.cfg_ddr_training_delay_ps.ac_trace_delay[1] = 128 - 20,//max511 1trip = 2wckUI =1Twck
.cfg_ddr_training_delay_ps.ac_trace_delay[2] = 128 - 20,
diff --git a/board/amlogic/s7_bh201/firmware/timing.c b/board/amlogic/s7_bh201/firmware/timing.c
index cec73e2..7dc4684 100644
--- a/board/amlogic/s7_bh201/firmware/timing.c
+++ b/board/amlogic/s7_bh201/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -185,7 +181,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_bh201/s7_bh201.c b/board/amlogic/s7_bh201/s7_bh201.c
index db63d71..cf9d8e7 100644
--- a/board/amlogic/s7_bh201/s7_bh201.c
+++ b/board/amlogic/s7_bh201/s7_bh201.c
@@ -151,6 +151,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7_bh202/firmware/timing.c b/board/amlogic/s7_bh202/firmware/timing.c
index 94bf33d..18fabc8 100644
--- a/board/amlogic/s7_bh202/firmware/timing.c
+++ b/board/amlogic/s7_bh202/firmware/timing.c
@@ -36,84 +36,79 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
-
/* VDDEE_VAL_REG */
#if (VDDEE_VAL == 700)
#define VDDEE_VAL_REG 0x120000
@@ -185,7 +180,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_bh202/s7_bh202.c b/board/amlogic/s7_bh202/s7_bh202.c
index bde6043..9709f64 100644
--- a/board/amlogic/s7_bh202/s7_bh202.c
+++ b/board/amlogic/s7_bh202/s7_bh202.c
@@ -153,6 +153,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7_bh209/firmware/timing.c b/board/amlogic/s7_bh209/firmware/timing.c
index 4ebf1a1..c902405 100644
--- a/board/amlogic/s7_bh209/firmware/timing.c
+++ b/board/amlogic/s7_bh209/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -185,7 +181,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_bh209/s7_bh209.c b/board/amlogic/s7_bh209/s7_bh209.c
index 79b7919..64f5e4a 100644
--- a/board/amlogic/s7_bh209/s7_bh209.c
+++ b/board/amlogic/s7_bh209/s7_bh209.c
@@ -151,6 +151,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7_bp201/firmware/timing.c b/board/amlogic/s7_bp201/firmware/timing.c
index 62e3ce0..21eb29e 100644
--- a/board/amlogic/s7_bp201/firmware/timing.c
+++ b/board/amlogic/s7_bp201/firmware/timing.c
@@ -37,84 +37,79 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
-
/* VDDEE_VAL_REG */
#if (VDDEE_VAL == 700)
#define VDDEE_VAL_REG 0x120000
@@ -186,7 +181,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_bp201/s7_bp201.c b/board/amlogic/s7_bp201/s7_bp201.c
index 495c24f..4c066ef 100644
--- a/board/amlogic/s7_bp201/s7_bp201.c
+++ b/board/amlogic/s7_bp201/s7_bp201.c
@@ -151,6 +151,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7_bp202/firmware/timing.c b/board/amlogic/s7_bp202/firmware/timing.c
index 62e3ce0..68e4181 100644
--- a/board/amlogic/s7_bp202/firmware/timing.c
+++ b/board/amlogic/s7_bp202/firmware/timing.c
@@ -37,80 +37,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -186,7 +182,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_bp202/s7_bp202.c b/board/amlogic/s7_bp202/s7_bp202.c
index d03c46f..329e469 100644
--- a/board/amlogic/s7_bp202/s7_bp202.c
+++ b/board/amlogic/s7_bp202/s7_bp202.c
@@ -153,6 +153,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7_skt/firmware/timing.c b/board/amlogic/s7_skt/firmware/timing.c
index 6fca3c4..c2999e1 100644
--- a/board/amlogic/s7_skt/firmware/timing.c
+++ b/board/amlogic/s7_skt/firmware/timing.c
@@ -37,80 +37,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -186,7 +182,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_t223/firmware/timing.c b/board/amlogic/s7_t223/firmware/timing.c
index ceef7b7..64d87c3 100644
--- a/board/amlogic/s7_t223/firmware/timing.c
+++ b/board/amlogic/s7_t223/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -185,7 +181,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M 666M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7_t233/firmware/timing.c b/board/amlogic/s7_t233/firmware/timing.c
index cec73e2..7dc4684 100644
--- a/board/amlogic/s7_t233/firmware/timing.c
+++ b/board/amlogic/s7_t233/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -185,7 +181,7 @@
{ PWM_MISC_REG_J, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm j and pwm h clock rate to 24M, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_bm201/firmware/ddr_timing.c b/board/amlogic/s7d_bm201/firmware/ddr_timing.c
index 01a5428..8349c2d 100644
--- a/board/amlogic/s7d_bm201/firmware/ddr_timing.c
+++ b/board/amlogic/s7d_bm201/firmware/ddr_timing.c
@@ -177,7 +177,7 @@
.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_common_setting.dbi_enable = 0,
.cfg_board_common_setting.org_tdqs2dq = 0,
@@ -351,7 +351,7 @@
//.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_FORCE_ENABLE_X8,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_SI_setting_ps.DRAMFreq = CACLU_CLK_D4,
.cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
@@ -596,7 +596,7 @@
.cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
.cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
.cfg_board_common_setting.log_level = 0xff,
- //.cfg_board_common_setting.log_level = 4,
+ .cfg_board_common_setting.log_level = 4,
//4,//LOG_LEVEL_BASIC,
.cfg_board_SI_setting_ps.DRAMFreq = CACLU_CLK_D3,
.cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
diff --git a/board/amlogic/s7d_bm201/firmware/timing.c b/board/amlogic/s7d_bm201/firmware/timing.c
index 249cb03..8b68a56 100644
--- a/board/amlogic/s7d_bm201/firmware/timing.c
+++ b/board/amlogic/s7d_bm201/firmware/timing.c
@@ -37,68 +37,64 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0x3E8
-#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0x2703BF
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0x4503A1
+#define VCCK_VAL_REG 0x0001001b
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x630383
+#define VCCK_VAL_REG 0x0002001a
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x00030019
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x00040018
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x00050017
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0xEF02F7
+#define VCCK_VAL_REG 0x00060016
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x10D02D9
+#define VCCK_VAL_REG 0x00070015
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x12B02BB
+#define VCCK_VAL_REG 0x00080014
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x149029D
+#define VCCK_VAL_REG 0x00090013
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000a0012
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x18F0257
+#define VCCK_VAL_REG 0x000b0011
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x1AD0239
+#define VCCK_VAL_REG 0x000c0010
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x1D50211
+#define VCCK_VAL_REG 0x000d000f
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x000e000e
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x21B01CB
+#define VCCK_VAL_REG 0x000f000d
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x24301A3
+#define VCCK_VAL_REG 0x0010000c
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2610185
+#define VCCK_VAL_REG 0x0011000b
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0012000a
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x00130009
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x00140008
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x2E30103
+#define VCCK_VAL_REG 0x00150007
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x30100E5
+#define VCCK_VAL_REG 0x00160006
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x00170005
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x00180004
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x00190003
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x38D0059
+#define VCCK_VAL_REG 0x001a0002
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3AB003B
+#define VCCK_VAL_REG 0x001b0001
#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3C9001D
-#elif (VCCK_VAL == 679)
-#define VCCK_VAL_REG 0x3e80000
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
@@ -166,7 +162,7 @@
/* set pwm h clock rate to 500M, enable them */
/* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_bm201/fw_arb.cfg b/board/amlogic/s7d_bm201/fw_arb.cfg
index 699a25d..d30842a 100644
--- a/board/amlogic/s7d_bm201/fw_arb.cfg
+++ b/board/amlogic/s7d_bm201/fw_arb.cfg
@@ -1,7 +1,7 @@
# Configure Firmware Anti-rollback Versions
-device_scs_vers=0x0
-device_tee_vers=0x0
-device_ree_vers=0x0
+device_scs_vers=0x6
+device_tee_vers=0x6
+device_ree_vers=0x6
# Configure Segmentation ID
DEVICE_SCS_SEGID=0x0
@@ -23,3 +23,4 @@
echo $DEVICE_TEE_VERS
echo $DEVICE_REE_VERS
echo $DEVICE_SCS_LVL1CERT_VERS_SUBMASK
+
diff --git a/board/amlogic/s7d_bm201/s7d_bm201.c b/board/amlogic/s7d_bm201/s7d_bm201.c
index 317c2d2..79190ae 100644
--- a/board/amlogic/s7d_bm201/s7d_bm201.c
+++ b/board/amlogic/s7d_bm201/s7d_bm201.c
@@ -205,6 +205,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7d_bm202/firmware/timing.c b/board/amlogic/s7d_bm202/firmware/timing.c
index b34fa91..49d62b4 100644
--- a/board/amlogic/s7d_bm202/firmware/timing.c
+++ b/board/amlogic/s7d_bm202/firmware/timing.c
@@ -35,68 +35,64 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0x3E8
-#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0x2703BF
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0x4503A1
+#define VCCK_VAL_REG 0x0001001b
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x630383
+#define VCCK_VAL_REG 0x0002001a
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x00030019
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x00040018
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x00050017
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0xEF02F7
+#define VCCK_VAL_REG 0x00060016
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x10D02D9
+#define VCCK_VAL_REG 0x00070015
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x12B02BB
+#define VCCK_VAL_REG 0x00080014
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x149029D
+#define VCCK_VAL_REG 0x00090013
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000a0012
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x18F0257
+#define VCCK_VAL_REG 0x000b0011
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x1AD0239
+#define VCCK_VAL_REG 0x000c0010
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x1D50211
+#define VCCK_VAL_REG 0x000d000f
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x000e000e
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x21B01CB
+#define VCCK_VAL_REG 0x000f000d
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x24301A3
+#define VCCK_VAL_REG 0x0010000c
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2610185
+#define VCCK_VAL_REG 0x0011000b
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0012000a
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x00130009
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x00140008
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x2E30103
+#define VCCK_VAL_REG 0x00150007
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x30100E5
+#define VCCK_VAL_REG 0x00160006
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x00170005
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x00180004
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x00190003
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x38D0059
+#define VCCK_VAL_REG 0x001a0002
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3AB003B
+#define VCCK_VAL_REG 0x001b0001
#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3C9001D
-#elif (VCCK_VAL == 679)
-#define VCCK_VAL_REG 0x3e80000
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
@@ -164,7 +160,7 @@
/* set pwm h clock rate to 500M, enable them */
/* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_bm202/s7d_bm202.c b/board/amlogic/s7d_bm202/s7d_bm202.c
index 532f27f..219a490 100644
--- a/board/amlogic/s7d_bm202/s7d_bm202.c
+++ b/board/amlogic/s7d_bm202/s7d_bm202.c
@@ -199,6 +199,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7d_bm209/firmware/timing.c b/board/amlogic/s7d_bm209/firmware/timing.c
index 2f3cc53..5eb3940 100644
--- a/board/amlogic/s7d_bm209/firmware/timing.c
+++ b/board/amlogic/s7d_bm209/firmware/timing.c
@@ -37,68 +37,64 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0x3E8
-#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0x2703BF
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0x4503A1
+#define VCCK_VAL_REG 0x0001001b
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x630383
+#define VCCK_VAL_REG 0x0002001a
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x00030019
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x00040018
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x00050017
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0xEF02F7
+#define VCCK_VAL_REG 0x00060016
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x10D02D9
+#define VCCK_VAL_REG 0x00070015
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x12B02BB
+#define VCCK_VAL_REG 0x00080014
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x149029D
+#define VCCK_VAL_REG 0x00090013
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000a0012
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x18F0257
+#define VCCK_VAL_REG 0x000b0011
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x1AD0239
+#define VCCK_VAL_REG 0x000c0010
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x1D50211
+#define VCCK_VAL_REG 0x000d000f
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x000e000e
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x21B01CB
+#define VCCK_VAL_REG 0x000f000d
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x24301A3
+#define VCCK_VAL_REG 0x0010000c
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2610185
+#define VCCK_VAL_REG 0x0011000b
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0012000a
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x00130009
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x00140008
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x2E30103
+#define VCCK_VAL_REG 0x00150007
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x30100E5
+#define VCCK_VAL_REG 0x00160006
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x00170005
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x00180004
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x00190003
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x38D0059
+#define VCCK_VAL_REG 0x001a0002
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3AB003B
+#define VCCK_VAL_REG 0x001b0001
#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3C9001D
-#elif (VCCK_VAL == 679)
-#define VCCK_VAL_REG 0x3e80000
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
@@ -166,7 +162,7 @@
/* set pwm h clock rate to 500M, enable them */
/* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_bm209/s7d_bm209.c b/board/amlogic/s7d_bm209/s7d_bm209.c
index c702f62..d44e921 100644
--- a/board/amlogic/s7d_bm209/s7d_bm209.c
+++ b/board/amlogic/s7d_bm209/s7d_bm209.c
@@ -198,6 +198,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/s7d_skt/firmware/timing.c b/board/amlogic/s7d_skt/firmware/timing.c
index 19e2fc1..83047c4 100644
--- a/board/amlogic/s7d_skt/firmware/timing.c
+++ b/board/amlogic/s7d_skt/firmware/timing.c
@@ -36,68 +36,64 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0x3E8
-#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0x2703BF
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0x4503A1
+#define VCCK_VAL_REG 0x0001001b
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x630383
+#define VCCK_VAL_REG 0x0002001a
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x00030019
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x00040018
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x00050017
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0xEF02F7
+#define VCCK_VAL_REG 0x00060016
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x10D02D9
+#define VCCK_VAL_REG 0x00070015
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x12B02BB
+#define VCCK_VAL_REG 0x00080014
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x149029D
+#define VCCK_VAL_REG 0x00090013
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000a0012
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x18F0257
+#define VCCK_VAL_REG 0x000b0011
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x1AD0239
+#define VCCK_VAL_REG 0x000c0010
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x1D50211
+#define VCCK_VAL_REG 0x000d000f
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x000e000e
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x21B01CB
+#define VCCK_VAL_REG 0x000f000d
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x24301A3
+#define VCCK_VAL_REG 0x0010000c
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2610185
+#define VCCK_VAL_REG 0x0011000b
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0012000a
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x00130009
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x00140008
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x2E30103
+#define VCCK_VAL_REG 0x00150007
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x30100E5
+#define VCCK_VAL_REG 0x00160006
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x00170005
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x00180004
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x00190003
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x38D0059
+#define VCCK_VAL_REG 0x001a0002
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3AB003B
+#define VCCK_VAL_REG 0x001b0001
#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3C9001D
-#elif (VCCK_VAL == 679)
-#define VCCK_VAL_REG 0x3e80000
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
@@ -171,7 +167,7 @@
/* set pwm h clock rate to 500M, enable them */
/* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_t232/firmware/timing.c b/board/amlogic/s7d_t232/firmware/timing.c
index c295229..8b68a56 100644
--- a/board/amlogic/s7d_t232/firmware/timing.c
+++ b/board/amlogic/s7d_t232/firmware/timing.c
@@ -37,71 +37,68 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0x3E8
-#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0x2703BF
+#if (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0000001c
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0x4503A1
+#define VCCK_VAL_REG 0x0001001b
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x630383
+#define VCCK_VAL_REG 0x0002001a
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x00030019
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x00040018
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x00050017
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0xEF02F7
+#define VCCK_VAL_REG 0x00060016
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x10D02D9
+#define VCCK_VAL_REG 0x00070015
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x12B02BB
+#define VCCK_VAL_REG 0x00080014
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x149029D
+#define VCCK_VAL_REG 0x00090013
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000a0012
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x18F0257
+#define VCCK_VAL_REG 0x000b0011
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x1AD0239
+#define VCCK_VAL_REG 0x000c0010
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x1D50211
+#define VCCK_VAL_REG 0x000d000f
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x000e000e
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x21B01CB
+#define VCCK_VAL_REG 0x000f000d
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x24301A3
+#define VCCK_VAL_REG 0x0010000c
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2610185
+#define VCCK_VAL_REG 0x0011000b
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0012000a
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x00130009
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x00140008
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x2E30103
+#define VCCK_VAL_REG 0x00150007
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x30100E5
+#define VCCK_VAL_REG 0x00160006
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x00170005
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x00180004
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x00190003
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x38D0059
+#define VCCK_VAL_REG 0x001a0002
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3AB003B
+#define VCCK_VAL_REG 0x001b0001
#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3C9001D
-#elif (VCCK_VAL == 679)
-#define VCCK_VAL_REG 0x3e80000
+#define VCCK_VAL_REG 0x001c0000
#else
#error "VCCK val out of range\n"
#endif
+
/* VDDEE_VAL_REG */
#if (VDDEE_VAL == 680)
#define VDDEE_VAL_REG 0xf0000
@@ -165,7 +162,7 @@
/* set pwm h clock rate to 500M, enable them */
/* set pwm j clock rate to fdiv3, enable them */
{ CLKCTRL_PWM_CLK_GH_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
- { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24) | (0x3 << 25), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (0x1 << 24), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 3 */
{ PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
diff --git a/board/amlogic/s7d_t232/s7d_t232.c b/board/amlogic/s7d_t232/s7d_t232.c
index 317c2d2..79190ae 100644
--- a/board/amlogic/s7d_t232/s7d_t232.c
+++ b/board/amlogic/s7d_t232/s7d_t232.c
@@ -205,6 +205,8 @@
{
printf("board late init\n");
env_set("defenv_para", "-c");
+ if (env_get_ulong("default_env", 10, 0))
+ env_set("defenv_para", "-c0"); //andr factory reset or factory burn
aml_board_late_init_front(NULL);
#ifdef CONFIG_PXP_EMULATOR
return 0;
diff --git a/board/amlogic/t6d_br301/firmware/timing.c b/board/amlogic/t6d_br301/firmware/timing.c
index 4e40a91..47a53ae 100644
--- a/board/amlogic/t6d_br301/firmware/timing.c
+++ b/board/amlogic/t6d_br301/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -191,7 +187,7 @@
{ PWM_MISC_REG_A, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
{ PWM_MISC_REG_B, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm a and pwm b clock rate to 24M, enable them */
- { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (3 << 25 ) | (0x1 << 8) , 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (0x1 << 8), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwma pwmb */
diff --git a/board/amlogic/t6d_br301/fw_arb.cfg b/board/amlogic/t6d_br301/fw_arb.cfg
index 5237e72..cf02888 100644
--- a/board/amlogic/t6d_br301/fw_arb.cfg
+++ b/board/amlogic/t6d_br301/fw_arb.cfg
@@ -7,6 +7,14 @@
DEVICE_SCS_SEGID=0x0
DEVICE_VENDOR_SEGID=0x0
+# Configure Device Level-1 Certificate ARB Vers SubMask
+DEVICE_SCS_LVL1CERT_VERS_SUBMASK=0
+max_device_scs_vers=0x1C
+if [ $(($device_scs_vers)) -gt $(($max_device_scs_vers)) ]; then
+ echo "$(pwd)/fw_arb.cfg Error: device_scs_vers exceed limit $max_device_scs_vers"
+ exit -1
+fi
+
###############################################################
DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
@@ -14,3 +22,4 @@
echo $DEVICE_SCS_VERS
echo $DEVICE_TEE_VERS
echo $DEVICE_REE_VERS
+echo $DEVICE_SCS_LVL1CERT_VERS_SUBMASK
\ No newline at end of file
diff --git a/board/amlogic/t6d_br301/t6d_br301.c b/board/amlogic/t6d_br301/t6d_br301.c
index 026c394..ccfe486 100644
--- a/board/amlogic/t6d_br301/t6d_br301.c
+++ b/board/amlogic/t6d_br301/t6d_br301.c
@@ -98,6 +98,8 @@
}
}
+extern void usb_power_init(void);
+
int board_init(void)
{
printf("board init\n");
@@ -129,6 +131,7 @@
#ifdef CONFIG_AMLOGIC_AMFC
amfc_init();
#endif
+ usb_power_init();
return 0;
}
@@ -153,36 +156,6 @@
wifi_init();
#endif
aml_board_late_init_tail(NULL);
-
- run_command("amlsecurecheck", 0);
- run_command("update_tries", 0);
-
- unsigned char chipid[16];
-
- memset(chipid, 0, 16);
-
- if (get_chip_id(chipid, 16) != -1) {
- char chipid_str[32];
- int i, j;
- char buf_tmp[4];
-
- memset(chipid_str, 0, 32);
-
- char *buff = &chipid_str[0];
-
- for (i = 0, j = 0; i < 12; ++i) {
- sprintf(&buf_tmp[0], "%02x", chipid[15 - i]);
- if (strcmp(buf_tmp, "00") != 0) {
- sprintf(buff + j, "%02x", chipid[15 - i]);
- j = j + 2;
- }
- }
- env_set("cpu_id", chipid_str);
- printf("buff: %s\n", buff);
- } else {
- env_set("cpu_id", "1234567890");
- }
-// emmc_quirks();
return 0;
}
diff --git a/board/amlogic/t6d_br309/firmware/timing.c b/board/amlogic/t6d_br309/firmware/timing.c
index 82f020f..fedb27d 100644
--- a/board/amlogic/t6d_br309/firmware/timing.c
+++ b/board/amlogic/t6d_br309/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -191,7 +187,7 @@
{ PWM_MISC_REG_A, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
{ PWM_MISC_REG_B, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm a and pwm b clock rate to 24M, enable them */
- { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (3 << 25 ) | (0x1 << 8) , 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (0x1 << 8), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwma pwmb */
@@ -201,6 +197,12 @@
{ PADCTRL_GPIOD_PULL_UP, (0x1 << 2), (0x1 << 2), 0, 0, 0 },
/* GPIOH_3 has an external pull-up, so disable the default internal pull-up */
{ PADCTRL_GPIOH_PULL_EN, (0x0 << 3), (0x1 << 3), 0, 0, 0 },
+#ifdef CONFIG_NOVERBOSE_BUILD
+ /* use acs flag to disable uart print in each blx
+ * reg must be UART_B_WFIFO, flags: 1 --> disable uart print, 0: enable
+ */
+ { UART_B_WFIFO, 0, 0xffffffff, 0, 1, 0 },
+#endif
};
#define __section(x) __attribute__((__section__(x)))
diff --git a/board/amlogic/t6d_br309/fw_arb.cfg b/board/amlogic/t6d_br309/fw_arb.cfg
index 5237e72..cf02888 100644
--- a/board/amlogic/t6d_br309/fw_arb.cfg
+++ b/board/amlogic/t6d_br309/fw_arb.cfg
@@ -7,6 +7,14 @@
DEVICE_SCS_SEGID=0x0
DEVICE_VENDOR_SEGID=0x0
+# Configure Device Level-1 Certificate ARB Vers SubMask
+DEVICE_SCS_LVL1CERT_VERS_SUBMASK=0
+max_device_scs_vers=0x1C
+if [ $(($device_scs_vers)) -gt $(($max_device_scs_vers)) ]; then
+ echo "$(pwd)/fw_arb.cfg Error: device_scs_vers exceed limit $max_device_scs_vers"
+ exit -1
+fi
+
###############################################################
DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
@@ -14,3 +22,4 @@
echo $DEVICE_SCS_VERS
echo $DEVICE_TEE_VERS
echo $DEVICE_REE_VERS
+echo $DEVICE_SCS_LVL1CERT_VERS_SUBMASK
\ No newline at end of file
diff --git a/board/amlogic/t6d_br309/t6d_br309.c b/board/amlogic/t6d_br309/t6d_br309.c
index 3f81a21..72a8a66 100644
--- a/board/amlogic/t6d_br309/t6d_br309.c
+++ b/board/amlogic/t6d_br309/t6d_br309.c
@@ -96,6 +96,8 @@
}
}
+extern void usb_power_init(void);
+
int board_init(void)
{
printf("board init\n");
@@ -128,6 +130,7 @@
#ifdef CONFIG_AMLOGIC_AMFC
amfc_init();
#endif
+ usb_power_init();
return 0;
}
@@ -148,35 +151,6 @@
PUSH_TIME_TE("vpu vpp init", BL33_VPUVPP_INIT_e);
aml_board_late_init_tail(NULL);
- run_command("amlsecurecheck", 0);
- run_command("update_tries", 0);
-
- unsigned char chipid[16];
-
- memset(chipid, 0, 16);
-
- if (get_chip_id(chipid, 16) != -1) {
- char chipid_str[32];
- int i, j;
- char buf_tmp[4];
-
- memset(chipid_str, 0, 32);
-
- char *buff = &chipid_str[0];
-
- for (i = 0, j = 0; i < 12; ++i) {
- sprintf(&buf_tmp[0], "%02x", chipid[15 - i]);
- if (strcmp(buf_tmp, "00") != 0) {
- sprintf(buff + j, "%02x", chipid[15 - i]);
- j = j + 2;
- }
- }
- env_set("cpu_id", chipid_str);
- printf("buff: %s\n", buff);
- } else {
- env_set("cpu_id", "1234567890");
- }
-// emmc_quirks();
return 0;
}
diff --git a/board/amlogic/t6d_skt/firmware/timing.c b/board/amlogic/t6d_skt/firmware/timing.c
index bb533b4..06698c9 100644
--- a/board/amlogic/t6d_skt/firmware/timing.c
+++ b/board/amlogic/t6d_skt/firmware/timing.c
@@ -36,80 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1049)
-#define VCCK_VAL_REG 0x3e8
-#elif (VCCK_VAL == 1039)
-#define VCCK_VAL_REG 0x1D03C9
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
#elif (VCCK_VAL == 1029)
-#define VCCK_VAL_REG 0x3B03AB
+#define VCCK_VAL_REG 0x00010021
#elif (VCCK_VAL == 1019)
-#define VCCK_VAL_REG 0x59038D
+#define VCCK_VAL_REG 0x00020020
#elif (VCCK_VAL == 1009)
-#define VCCK_VAL_REG 0x77036F
+#define VCCK_VAL_REG 0x0003001f
#elif (VCCK_VAL == 999)
-#define VCCK_VAL_REG 0x8B035B
+#define VCCK_VAL_REG 0x0004001e
#elif (VCCK_VAL == 989)
-#define VCCK_VAL_REG 0xA9033D
+#define VCCK_VAL_REG 0x0005001d
#elif (VCCK_VAL == 979)
-#define VCCK_VAL_REG 0xC7031F
+#define VCCK_VAL_REG 0x0006001c
#elif (VCCK_VAL == 969)
-#define VCCK_VAL_REG 0xE50301
+#define VCCK_VAL_REG 0x0007001b
#elif (VCCK_VAL == 959)
-#define VCCK_VAL_REG 0xF902ED
+#define VCCK_VAL_REG 0x0008001a
#elif (VCCK_VAL == 949)
-#define VCCK_VAL_REG 0x11702CF
+#define VCCK_VAL_REG 0x00090019
#elif (VCCK_VAL == 939)
-#define VCCK_VAL_REG 0x13502B1
+#define VCCK_VAL_REG 0x000a0018
#elif (VCCK_VAL == 929)
-#define VCCK_VAL_REG 0x1530293
+#define VCCK_VAL_REG 0x000b0017
#elif (VCCK_VAL == 919)
-#define VCCK_VAL_REG 0x1710275
+#define VCCK_VAL_REG 0x000c0016
#elif (VCCK_VAL == 909)
-#define VCCK_VAL_REG 0x1850261
+#define VCCK_VAL_REG 0x000d0015
#elif (VCCK_VAL == 899)
-#define VCCK_VAL_REG 0x1A30243
+#define VCCK_VAL_REG 0x000e0014
#elif (VCCK_VAL == 889)
-#define VCCK_VAL_REG 0x1C10225
+#define VCCK_VAL_REG 0x000f0013
#elif (VCCK_VAL == 879)
-#define VCCK_VAL_REG 0x1DF0207
+#define VCCK_VAL_REG 0x00100012
#elif (VCCK_VAL == 869)
-#define VCCK_VAL_REG 0x1F301F3
+#define VCCK_VAL_REG 0x00110011
#elif (VCCK_VAL == 859)
-#define VCCK_VAL_REG 0x21101D5
+#define VCCK_VAL_REG 0x00120010
#elif (VCCK_VAL == 849)
-#define VCCK_VAL_REG 0x22F01B7
+#define VCCK_VAL_REG 0x0013000f
#elif (VCCK_VAL == 839)
-#define VCCK_VAL_REG 0x24D0199
+#define VCCK_VAL_REG 0x0014000e
#elif (VCCK_VAL == 829)
-#define VCCK_VAL_REG 0x26B017B
+#define VCCK_VAL_REG 0x0015000d
#elif (VCCK_VAL == 819)
-#define VCCK_VAL_REG 0x27F0167
+#define VCCK_VAL_REG 0x0016000c
#elif (VCCK_VAL == 809)
-#define VCCK_VAL_REG 0x29D0149
+#define VCCK_VAL_REG 0x0017000b
#elif (VCCK_VAL == 799)
-#define VCCK_VAL_REG 0x2BB012B
+#define VCCK_VAL_REG 0x0018000a
#elif (VCCK_VAL == 789)
-#define VCCK_VAL_REG 0x2D9010D
+#define VCCK_VAL_REG 0x00190009
#elif (VCCK_VAL == 779)
-#define VCCK_VAL_REG 0x2ED00F9
+#define VCCK_VAL_REG 0x001a0008
#elif (VCCK_VAL == 769)
-#define VCCK_VAL_REG 0x30B00DB
+#define VCCK_VAL_REG 0x001b0007
#elif (VCCK_VAL == 759)
-#define VCCK_VAL_REG 0x32900BD
+#define VCCK_VAL_REG 0x001c0006
#elif (VCCK_VAL == 749)
-#define VCCK_VAL_REG 0x347009F
+#define VCCK_VAL_REG 0x001d0005
#elif (VCCK_VAL == 739)
-#define VCCK_VAL_REG 0x3650081
+#define VCCK_VAL_REG 0x001e0004
#elif (VCCK_VAL == 729)
-#define VCCK_VAL_REG 0x379006D
+#define VCCK_VAL_REG 0x001f0003
#elif (VCCK_VAL == 719)
-#define VCCK_VAL_REG 0x397004F
+#define VCCK_VAL_REG 0x00200002
#elif (VCCK_VAL == 709)
-#define VCCK_VAL_REG 0x3B50031
+#define VCCK_VAL_REG 0x00210001
#elif (VCCK_VAL == 699)
-#define VCCK_VAL_REG 0x3D30013
-#elif (VCCK_VAL == 689)
-#define VCCK_VAL_REG 0x3E80000
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -187,7 +183,7 @@
{ PWM_MISC_REG_A, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
{ PWM_MISC_REG_B, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm a and pwm b clock rate to 24M, enable them */
- { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (3 << 25 ) | (0x1 << 8) , 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (0x1 << 8), 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwma pwmb */
diff --git a/board/amlogic/t6d_t335/firmware/timing.c b/board/amlogic/t6d_t335/firmware/timing.c
index 943a92c..3e26866 100644
--- a/board/amlogic/t6d_t335/firmware/timing.c
+++ b/board/amlogic/t6d_t335/firmware/timing.c
@@ -36,76 +36,76 @@
#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
/* VCCK PWM table */
-#if (VCCK_VAL == 1040)
-#define VCCK_VAL_REG 0x1D03C9
-#elif (VCCK_VAL == 1030)
-#define VCCK_VAL_REG 0x3B03AB
-#elif (VCCK_VAL == 1020)
-#define VCCK_VAL_REG 0x59038D
-#elif (VCCK_VAL == 1010)
-#define VCCK_VAL_REG 0x77036F
-#elif (VCCK_VAL == 1000)
-#define VCCK_VAL_REG 0x8B035B
-#elif (VCCK_VAL == 990)
-#define VCCK_VAL_REG 0xA9033D
-#elif (VCCK_VAL == 980)
-#define VCCK_VAL_REG 0xC7031F
-#elif (VCCK_VAL == 970)
-#define VCCK_VAL_REG 0xE50301
-#elif (VCCK_VAL == 960)
-#define VCCK_VAL_REG 0x10302E3
-#elif (VCCK_VAL == 950)
-#define VCCK_VAL_REG 0x12102C5
-#elif (VCCK_VAL == 940)
-#define VCCK_VAL_REG 0x13502B1
-#elif (VCCK_VAL == 930)
-#define VCCK_VAL_REG 0x1530293
-#elif (VCCK_VAL == 920)
-#define VCCK_VAL_REG 0x1710275
-#elif (VCCK_VAL == 910)
-#define VCCK_VAL_REG 0x18F0257
-#elif (VCCK_VAL == 900)
-#define VCCK_VAL_REG 0x1AD0239
-#elif (VCCK_VAL == 890)
-#define VCCK_VAL_REG 0x1C10225
-#elif (VCCK_VAL == 880)
-#define VCCK_VAL_REG 0x1DF0207
-#elif (VCCK_VAL == 870)
-#define VCCK_VAL_REG 0x1FD01E9
-#elif (VCCK_VAL == 860)
-#define VCCK_VAL_REG 0x21B01CB
-#elif (VCCK_VAL == 850)
-#define VCCK_VAL_REG 0x22F01B7
-#elif (VCCK_VAL == 840)
-#define VCCK_VAL_REG 0x24D0199
-#elif (VCCK_VAL == 830)
-#define VCCK_VAL_REG 0x26B017B
-#elif (VCCK_VAL == 820)
-#define VCCK_VAL_REG 0x289015D
-#elif (VCCK_VAL == 810)
-#define VCCK_VAL_REG 0x2A7013F
-#elif (VCCK_VAL == 800)
-#define VCCK_VAL_REG 0x2BB012B
-#elif (VCCK_VAL == 790)
-#define VCCK_VAL_REG 0x2D9010D
-#elif (VCCK_VAL == 780)
-#define VCCK_VAL_REG 0x2F700EF
-#elif (VCCK_VAL == 770)
-#define VCCK_VAL_REG 0x31500D1
-#elif (VCCK_VAL == 760)
-#define VCCK_VAL_REG 0x32900BD
-#elif (VCCK_VAL == 750)
-#define VCCK_VAL_REG 0x347009F
-#elif (VCCK_VAL == 740)
-#define VCCK_VAL_REG 0x3650081
-#elif (VCCK_VAL == 730)
-#define VCCK_VAL_REG 0x379006D
-#elif (VCCK_VAL == 720)
-#define VCCK_VAL_REG 0x397004F
-#elif (VCCK_VAL == 710)
-#define VCCK_VAL_REG 0x3B50031
-#elif (VCCK_VAL == 700)
-#define VCCK_VAL_REG 0x3D30013
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+#define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+#define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+#define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+#define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+#define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+#define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+#define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+#define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+#define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+#define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+#define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+#define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+#define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+#define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+#define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+#define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+#define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+#define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+#define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+#define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+#define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+#define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+#define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+#define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+#define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+#define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+#define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+#define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+#define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+#define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+#define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+#define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+#define VCCK_VAL_REG 0x00220000
#else
#error "VCCK val out of range\n"
#endif
@@ -187,7 +187,7 @@
{ PWM_MISC_REG_A, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
{ PWM_MISC_REG_B, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
/* set pwm a and pwm b clock rate to 24M, enable them */
- { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (3 << 25 ) | (0x1 << 8) , 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24) | (0x1 << 8) , 0xffffffff, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 drive strength to 2 ,already set by gpio owner on bl2*/
// { PADCTRL_GPIOE_DS, 0xa, 0xf, 0, 0, 0 },
/* set GPIOE_0 GPIOE_1 mux to pwma pwmb */
@@ -197,6 +197,12 @@
{ PADCTRL_GPIOD_PULL_UP, (0x1 << 2), (0x1 << 2), 0, 0, 0 },
/* GPIOH_3 has an external pull-up, so disable the default internal pull-up */
{ PADCTRL_GPIOH_PULL_EN, (0x0 << 3), (0x1 << 3), 0, 0, 0 },
+#ifdef CONFIG_NOVERBOSE_BUILD
+ /* use acs flag to disable uart print in each blx
+ * reg must be UART_B_WFIFO, flags: 1 --> disable uart print, 0: enable
+ */
+ { UART_B_WFIFO, 0, 0xffffffff, 0, 1, 0 },
+#endif
};
#define __section(x) __attribute__((__section__(x)))
diff --git a/board/amlogic/t6d_t335/t6d_t335.c b/board/amlogic/t6d_t335/t6d_t335.c
index e633712..2622dae 100644
--- a/board/amlogic/t6d_t335/t6d_t335.c
+++ b/board/amlogic/t6d_t335/t6d_t335.c
@@ -153,36 +153,6 @@
wifi_init();
#endif
aml_board_late_init_tail(NULL);
-
- run_command("amlsecurecheck", 0);
- run_command("update_tries", 0);
-
- unsigned char chipid[16];
-
- memset(chipid, 0, 16);
-
- if (get_chip_id(chipid, 16) != -1) {
- char chipid_str[32];
- int i, j;
- char buf_tmp[4];
-
- memset(chipid_str, 0, 32);
-
- char *buff = &chipid_str[0];
-
- for (i = 0, j = 0; i < 12; ++i) {
- sprintf(&buf_tmp[0], "%02x", chipid[15 - i]);
- if (strcmp(buf_tmp, "00") != 0) {
- sprintf(buff + j, "%02x", chipid[15 - i]);
- j = j + 2;
- }
- }
- env_set("cpu_id", chipid_str);
- printf("buff: %s\n", buff);
- } else {
- env_set("cpu_id", "1234567890");
- }
-// emmc_quirks();
return 0;
}
diff --git a/cmd/amlogic/Kconfig b/cmd/amlogic/Kconfig
index b70457d..7bbe6d0 100644
--- a/cmd/amlogic/Kconfig
+++ b/cmd/amlogic/Kconfig
@@ -237,6 +237,12 @@
help
support partition local encryption
+config CMD_SCMI_SHMEM_ADDR
+ bool "support update address of shmem for SCMI"
+ help
+ When the address of shmem in DTB is inconsistent with BL31,
+ support updating the address of shmem in DTB.
+
#prduct mode end<----
endmenu
diff --git a/cmd/amlogic/Makefile b/cmd/amlogic/Makefile
index a509961..0c2de33 100644
--- a/cmd/amlogic/Makefile
+++ b/cmd/amlogic/Makefile
@@ -19,8 +19,11 @@
obj-y += cmd_version.o
ifdef CONFIG_AML_UPDATE_PDVFS
obj-y += cmd_pdvfs.o
+obj-y += cmd_cooling.o
endif
+obj-$(CONFIG_CMD_SCMI_SHMEM_ADDR) += cmd_scmi_shmem.o
+
obj-$(CONFIG_CMD_DMCRW) += cmd_dmc.o
obj-$(CONFIG_CMD_CAR_PARAMS) += cmd_car_param.o
diff --git a/cmd/amlogic/bootloader_status.c b/cmd/amlogic/bootloader_status.c
index fdfac02..d78c529 100644
--- a/cmd/amlogic/bootloader_status.c
+++ b/cmd/amlogic/bootloader_status.c
@@ -364,12 +364,14 @@
return -1;
}
+#ifdef CONFIG_MESON_S7D
iret = update_boot_hdr_4_s7d_reva(buffer, BOOTLOADER_MAX_SIZE - BOOTLOADER_OFFSET, 0);
if (iret) {
printf("Failed to write s7d reva boot0\n");
free(buffer);
return -1;
}
+#endif//#ifdef CONFIG_MESON_S7D
iret = store_boot_write("bootloader", i, BOOTLOADER_MAX_SIZE - BOOTLOADER_OFFSET, buffer);
if (iret) {
diff --git a/cmd/amlogic/cmd_cooling.c b/cmd/amlogic/cmd_cooling.c
new file mode 100644
index 0000000..f32cd00
--- /dev/null
+++ b/cmd/amlogic/cmd_cooling.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/amlogic/arch/secure_apb.h>
+#include <linux/libfdt_env.h>
+#include <dt-bindings/amlogic/thermal/s6-thermal.h>
+#include "cmd_pdvfs.h"
+
+#define GET_DVFS_TABLE_INDEX 0x82000088
+
+static int get_table_size(const char *path)
+{
+ int ret = 0;
+ char cmdbuf[256] = {0};
+ char *phandle_str = NULL;
+ unsigned int phandle_val = 0;
+
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ sprintf(cmdbuf, "fdt get size table_size %s", path);
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0) {
+ printf("Error: Failed to get phandle for %s\n", path);
+ return -EBADMSG;
+ }
+
+ phandle_str = env_get("table_size");
+ if (phandle_str == NULL) {
+ printf("Error: Failed to retrieve table_size from environment\n");
+ return -EBADMSG;
+ }
+
+ phandle_val = strtoul(phandle_str, NULL, 10);
+ return phandle_val;
+}
+
+static int set_cooling_state(const char *path, unsigned int cpus_phandle,
+ unsigned int lower, unsigned int upper)
+{
+ int ret = 0;
+ char cmdbuf[256] = {0};
+
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ sprintf(cmdbuf, "fdt set %s cooling-device <%d %d %d>", path, cpus_phandle, lower, upper);
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0) {
+ printf("Error: Failed to update cooling-device state.\n");
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+static int do_update_cooling_state(cmd_tbl_t *cmdtp, int flag1, int argc, char * const argv[])
+{
+ unsigned int cpus_phandle = 0;
+ unsigned int board_id = 0;
+ unsigned int state = 0;
+ unsigned int table_size = 0;
+ unsigned int pdvfs_index = 0;
+
+ cpus_phandle = get_phandle("/cpus/cpu@0");
+ board_id = get_board_id();
+ pdvfs_index = get_cpufreq_table_index(GET_DVFS_TABLE_INDEX, 0, 0, 0);
+
+ if (board_id == 2 && (pdvfs_index == 2 || pdvfs_index == 3)) {
+ table_size = get_table_size(CONFIG_CPU_OPP_TABLE);
+ state = table_size - CONFIG_OPP_TABLE_667M_SIZE;
+ set_cooling_state("/thermal-zones/soc_thermal/cooling-maps/cpufreq_cooling_map",
+ cpus_phandle, 0, state);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ update_cooling_state, 1, 0, do_update_cooling_state,
+ "update cpu cooling_state",
+ "update_cooling_state pos"
+);
+
diff --git a/cmd/amlogic/cmd_hdmitx21.c b/cmd/amlogic/cmd_hdmitx21.c
index d16da4e..8311fa6 100644
--- a/cmd/amlogic/cmd_hdmitx21.c
+++ b/cmd/amlogic/cmd_hdmitx21.c
@@ -850,6 +850,102 @@
static void aud_cap_show(struct hdmitx_dev *hdev)
{
+ struct rx_cap *prxcap = &hdev->RXCap;
+ int i, j;
+ struct dolby_vsadb_cap *cap = &prxcap->dolby_vsadb_cap;
+ static const char * const aud_ct[] = {
+ "ReferToStreamHeader", "PCM", "AC-3", "MPEG1", "MP3",
+ "MPEG2", "AAC", "DTS", "ATRAC", "OneBitAudio",
+ "Dolby_Digital+", "DTS-HD", "MAT", "DST", "WMA_Pro",
+ "Reserved", NULL};
+ static const char * const aud_sampling_frequency[] = {
+ "ReferToStreamHeader", "32", "44.1", "48", "88.2", "96",
+ "176.4", "192", NULL};
+ const char * const aud_sample_size[] = {"ReferToStreamHeader",
+ "16", "20", "24", NULL};
+
+ printf("\naud_cap\n");
+ printf("CodingType MaxChannels SamplingFreq SampleSize\n");
+ for (i = 0; i < prxcap->AUD_count; i++) {
+ if (prxcap->RxAudioCap[i].audio_format_code == CT_CXT) {
+ if ((prxcap->RxAudioCap[i].cc3 >> 3) == 0xb) {
+ printf("MPEG-H, 8ch, ");
+ for (j = 0; j < 7; j++) {
+ if (prxcap->RxAudioCap[i].freq_cc & (1 << j))
+ printf("%s/", aud_sampling_frequency[j + 1]);
+ }
+ printf(" kHz\n");
+ }
+ continue;
+ }
+ printf("%s", aud_ct[prxcap->RxAudioCap[i].audio_format_code]);
+ if (prxcap->RxAudioCap[i].audio_format_code == CT_DD_P &&
+ (prxcap->RxAudioCap[i].cc3 & 1))
+ printf("/ATMOS");
+ if (prxcap->RxAudioCap[i].audio_format_code != CT_CXT)
+ printf(", %d ch, ", prxcap->RxAudioCap[i].channel_num_max + 1);
+ for (j = 0; j < 7; j++) {
+ if (prxcap->RxAudioCap[i].freq_cc & (1 << j))
+ printf("%s/", aud_sampling_frequency[j + 1]);
+ }
+ printf(" kHz, ");
+ switch (prxcap->RxAudioCap[i].audio_format_code) {
+ case CT_PCM:
+ for (j = 0; j < 3; j++) {
+ if (prxcap->RxAudioCap[i].cc3 & (1 << j))
+ printf("%s/", aud_sample_size[j + 1]);
+ }
+ printf(" bit\n");
+ break;
+ case CT_AC_3:
+ case CT_MPEG1:
+ case CT_MP3:
+ case CT_MPEG2:
+ case CT_AAC:
+ case CT_DTS:
+ case CT_ATRAC:
+ case CT_ONE_BIT_AUDIO:
+ printf("MaxBitRate %dkHz\n", prxcap->RxAudioCap[i].cc3 * 8);
+ break;
+ case CT_DD_P:
+ case CT_DTS_HD:
+ case CT_MAT:
+ case CT_DST:
+ printf("DepValue 0x%x\n", prxcap->RxAudioCap[i].cc3);
+ break;
+ case CT_WMA:
+ default:
+ break;
+ }
+ }
+
+ if (cap->ieeeoui == DOVI_IEEEOUI) {
+ /*
+ * Dolby Vendor Specific:
+ * headphone_playback_only:0,
+ * center_speaker:1,
+ * surround_speaker:1,
+ * height_speaker:1,
+ * Ver:1.0,
+ * MAT_PCM_48kHz_only:1,
+ * e61146d0007001,
+ */
+ printf("Dolby Vendor Specific:\n");
+ if (cap->dolby_vsadb_ver == 0)
+ printf(" Ver:1.0,\n");
+ else
+ printf(" Ver:Reversed,\n");
+ printf(" center_speaker:%d,\n", cap->spk_center);
+ printf(" surround_speaker:%d,\n", cap->spk_surround);
+ printf(" height_speaker:%d,\n", cap->spk_height);
+ printf(" headphone_playback_only:%d,\n", cap->headphone_only);
+ printf(" MAT_PCM_48kHz_only:%d,\n", cap->mat_48k_pcm_only);
+
+ printf(" ");
+ for (i = 0; i < 7; i++)
+ printf("%02x", cap->rawdata[i]);
+ printf(",\n");
+ }
}
static void hdr_cap_show(struct hdmitx_dev *hdev)
@@ -979,16 +1075,12 @@
/*
* printf(
* "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
- *
- *
- * printf(
- * "Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
- * hdmitx_device->hdmi_info.vsdb_phy_addr.a,
- * hdmitx_device->hdmi_info.vsdb_phy_addr.b,
- * hdmitx_device->hdmi_info.vsdb_phy_addr.c,
- * hdmitx_device->hdmi_info.vsdb_phy_addr.d);
*/
+ printf("Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
+ prxcap->vsdb_phy_addr.a, prxcap->vsdb_phy_addr.b,
+ prxcap->vsdb_phy_addr.c, prxcap->vsdb_phy_addr.d);
+
/* TODO native_vic2 */
printf("native Mode %x, VIC (native %d):\n",
prxcap->native_Mode, prxcap->native_vic);
@@ -1367,6 +1459,8 @@
/* parse edid data */
hdmitx_edid_parse(&hdev->RXCap, hdev->rawedid);
+ hdmitx_cec_phy_addr_parse(&hdev->RXCap, hdev->rawedid);
+ hdmitx_audio_parse(&hdev->RXCap, hdev->rawedid);
/* Update the member variables used by the dv running strategy */
hdmitx_update_dv_strategy_info(&hdev->RXCap.dv_info);
diff --git a/cmd/amlogic/cmd_pdvfs.c b/cmd/amlogic/cmd_pdvfs.c
index cc2f34d..6ed199c 100644
--- a/cmd/amlogic/cmd_pdvfs.c
+++ b/cmd/amlogic/cmd_pdvfs.c
@@ -14,8 +14,10 @@
#define cmd_pdvfs_info(fmt...) printf("[cmd_pdvfs] "fmt)
#define cmd_pdvfs_err(fmt...) printf("[cmd_pdvfs] "fmt)
#define GET_DVFS_TABLE_INDEX 0x82000088
+#define REVA 0xA
+#define REVB 0xB
-static int get_board_id(void)
+int get_board_id(void)
{
int board_id = 0;
@@ -39,40 +41,40 @@
sprintf(cmdbuf, "fdt set %s status %s;", node, status);
ret = run_command(cmdbuf, 0);
if (ret != 0) {
- cmd_pdvfs_err("Error: Failed to set regulator status\n");
- return -EBADMSG;
- }
+ cmd_pdvfs_err("Error: Failed to set regulator status\n");
+ return -EBADMSG;
+ }
- return 0;
+ return 0;
}
-static int get_phandle(const char *path) {
- int ret = 0;
- char cmdbuf[256] = {0};
+int get_phandle(const char *path) {
+ int ret = 0;
+ char cmdbuf[256] = {0};
char *phandle_str = NULL;
unsigned int phandle_val = 0;
- memset(cmdbuf, 0, sizeof(cmdbuf));
- sprintf(cmdbuf, "fdt get value phandle_value %s phandle", path);
- ret = run_command(cmdbuf, 0);
- if (ret != 0) {
- cmd_pdvfs_err("Error: Failed to get phandle for %s\n", path);
- return -EBADMSG;
- }
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ sprintf(cmdbuf, "fdt get value phandle_value %s phandle", path);
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0) {
+ cmd_pdvfs_err("Error: Failed to get phandle for %s\n", path);
+ return -EBADMSG;
+ }
- phandle_str = env_get("phandle_value");
- if (phandle_str == NULL) {
- cmd_pdvfs_err("Error: Failed to retrieve phandle_value from environment\n");
- return -EBADMSG;
- }
+ phandle_str = env_get("phandle_value");
+ if (phandle_str == NULL) {
+ cmd_pdvfs_err("Error: Failed to retrieve phandle_value from environment\n");
+ return -EBADMSG;
+ }
phandle_val = strtoul(phandle_str, NULL, 16);
- return phandle_val;
+ return phandle_val;
}
static int update_pwm_f_board_regulator(void) {
- int ret = 0;
- char cmdbuf[256] = {0};
+ int ret = 0;
+ char cmdbuf[256] = {0};
unsigned int pwm_f_board0_phandle = 0;
pwm_f_board0_phandle = get_phandle("/pwm_f_board0-regulator");
@@ -94,12 +96,12 @@
return -EBADMSG;
}
- return 0;
+ return 0;
}
-static unsigned int get_cpufreq_table_index(u64 function_id,
- u64 arg0, u64 arg1, u64 arg2)
+unsigned int get_cpufreq_table_index(u64 function_id,
+ u64 arg0, u64 arg1, u64 arg2)
{
struct arm_smccc_res res;
@@ -124,6 +126,7 @@
opp_table_1_phandle = get_phandle("/cpu_opp_table1");
opp_table_2_phandle = get_phandle("/cpu_opp_table2_2000");
opp_table_3_phandle = get_phandle("/cpu_opp_table3_2000");
+
memset(cmdbuf, 0, sizeof(cmdbuf));
sprintf(cmdbuf, "fdt set /cpus/cpu@0 operating-points-v2 <0x%x 0x%x 0x%x 0x%x>;", \
opp_table_0_phandle, opp_table_1_phandle, \
@@ -142,11 +145,11 @@
{
unsigned int ret = 0;
unsigned int board_id = 0;
- unsigned int board_rev = 0;
+ unsigned int chip_rev = 0;
unsigned int pdvfs_index = 0;
board_id = get_board_id();
- board_rev = get_chip_rev();
+ chip_rev = get_chip_rev();
pdvfs_index = get_cpufreq_table_index(GET_DVFS_TABLE_INDEX, 0, 0, 0);
cmd_pdvfs_info("update_pdvfs dtb\n");
if (board_id < 2) {
@@ -156,16 +159,25 @@
ret = set_cpu_opp_tbl();
if (ret != 0)
cmd_pdvfs_err("fix_cpu_opp_tbl fail\n");
- }
- else if (board_id == 2) {
+ } else {
if (pdvfs_index == 0 || pdvfs_index == 1) {
ret = set_cpu_opp_tbl();
if (ret != 0)
cmd_pdvfs_err("fix_cpu_opp_tbl fail\n");
}
}
- else
- cmd_pdvfs_err("get board_id fail,board_id = %d\n", board_id);
+ if (chip_rev >= REVB) {
+ if (board_id < 2 && pdvfs_index) {
+ cmd_pdvfs_err("board_id is not correct, board_id = %d \n", board_id);
+ while (1)
+ ; // software protect
+ }
+ if (board_id >= 2 && !pdvfs_index) {
+ cmd_pdvfs_err("pdvfs_index is conflict with board_id, pdvfs_index = %d \n", pdvfs_index);
+ while (1)
+ ; // software protect
+ }
+ }
return 0;
}
diff --git a/cmd/amlogic/cmd_pdvfs.h b/cmd/amlogic/cmd_pdvfs.h
new file mode 100644
index 0000000..a6dfab6
--- /dev/null
+++ b/cmd/amlogic/cmd_pdvfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CMD_PDVFS_H
+#define __CMD_PDVFS_H
+
+int get_phandle(const char *path);
+int get_board_id(void);
+unsigned int get_cpufreq_table_index(u64 function_id,
+ u64 arg0, u64 arg1, u64 arg2);
+
+#endif
diff --git a/cmd/amlogic/cmd_reboot.c b/cmd/amlogic/cmd_reboot.c
index 322310d..439066e 100644
--- a/cmd/amlogic/cmd_reboot.c
+++ b/cmd/amlogic/cmd_reboot.c
@@ -325,7 +325,6 @@
int do_systemoff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- //aml_system_off();
pm_poweroff();
return 0;
}
diff --git a/cmd/amlogic/cmd_rma.c b/cmd/amlogic/cmd_rma.c
index 6963893..7ef738e 100644
--- a/cmd/amlogic/cmd_rma.c
+++ b/cmd/amlogic/cmd_rma.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <command.h>
#include <mapmem.h>
#include <tee.h>
diff --git a/cmd/amlogic/cmd_scmi_shmem.c b/cmd/amlogic/cmd_scmi_shmem.c
new file mode 100644
index 0000000..9c03241
--- /dev/null
+++ b/cmd/amlogic/cmd_scmi_shmem.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/arm-smccc.h>
+#include <linux/libfdt_env.h>
+
+#define SIP_SMC_SCMI_CMD 0x820000C1
+#define SCMI_SUBID_GET_SHMEM_ADDR 0x1
+
+
+static uint32_t get_scmi_shmem_addr(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SMC_SCMI_CMD, SCMI_SUBID_GET_SHMEM_ADDR,
+ 0, 0, 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+static int ftd_get_root_address_cells(void)
+{
+ char *address_cells_str = NULL;
+ int ret = 0;
+
+ ret = run_command("fdt get value address_cells / \\#address-cells", 0);
+ if (ret != 0) {
+ printf("Error: Failed to get address_cells for root\n");
+ return -EBADMSG;
+ }
+
+ address_cells_str = env_get("address_cells");
+ if (!address_cells_str) {
+ printf("Error: Failed to retrieve address_cells from environment\n");
+ return -EBADMSG;
+ }
+
+ return strtoul(address_cells_str, NULL, 16);
+}
+
+static int ftd_get_scmi_shmem_addr(void)
+{
+ char *shmem_addr_str = NULL;
+ u32 *shmem_addr = NULL;
+ int root_addrs_cells = ftd_get_root_address_cells();
+ int ret = 0;
+
+ ret = run_command("fdt get addr shmem_addr /shmem reg", 0);
+ if (ret != 0) {
+ printf("Error: Failed to get shmem_addr for /shmem\n");
+ return -EBADMSG;
+ }
+
+ shmem_addr_str = env_get("shmem_addr");
+ if (!shmem_addr_str) {
+ printf("Error: Failed to retrieve shmem_addr from environment\n");
+ return -EBADMSG;
+ }
+ shmem_addr = (u32 *)strtoul(shmem_addr_str, NULL, 16);
+ if (!shmem_addr)
+ return -EFAULT;
+
+ if (root_addrs_cells == 2) /* CONFIG_ARM64 */
+ return be32_to_cpu(*(++shmem_addr));
+ else /* CONFIG_ARM */
+ return be32_to_cpu(*shmem_addr);
+}
+
+static int fdt_set_scmi_shmem_reg(void)
+{
+ int ret = 0;
+ char cmdbuf[256] = {0};
+ u32 bl31_shmem_addr = get_scmi_shmem_addr();
+ u32 dtb_shmem_addr = ftd_get_scmi_shmem_addr();
+
+ if (dtb_shmem_addr == bl31_shmem_addr)
+ return 0;
+
+ printf("Warning: Address of shmem in DTB is inconsistent with BL31!!!\n");
+ printf("bl31_shmem_addr = 0x%x, dtb_shmem_addr = 0x%x\n",
+ bl31_shmem_addr, dtb_shmem_addr);
+ printf("Update the address of shmem in DTB\n");
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ if (ftd_get_root_address_cells() == 1) { /* CONFIG_ARM */
+ sprintf(cmdbuf, "fdt set /shmem reg <0x%x 0x100>",
+ bl31_shmem_addr);
+ } else if (ftd_get_root_address_cells() == 2) { /* CONFIG_ARM64 */
+ sprintf(cmdbuf, "fdt set /shmem reg <0 0x%x 0 0x100>",
+ bl31_shmem_addr);
+ } else {
+ printf("Error: Failed to adapt address-cells for DTB.\n");
+ return -ENXIO;
+ }
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0) {
+ printf("Error: Failed to set reg of scmi_shmem for DTB\n");
+ return -EBADMSG;
+ }
+
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ sprintf(cmdbuf, "fdt set /shmem ranges <0 0 0x%x 0x100>",
+ bl31_shmem_addr);
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0) {
+ printf("Error: Failed to set ranges of scmi_shmem for DTB\n");
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+static int do_update_scmi_shmem(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return fdt_set_scmi_shmem_reg();
+}
+
+U_BOOT_CMD(update_scmi_shmem, 1, 0, do_update_scmi_shmem,
+ "Update the shared memory address of the SCMI in the DTB",
+ ""
+);
diff --git a/cmd/amlogic/defenv_without.c b/cmd/amlogic/defenv_without.c
index 9b09a65..b3af308 100644
--- a/cmd/amlogic/defenv_without.c
+++ b/cmd/amlogic/defenv_without.c
@@ -19,6 +19,7 @@
static const char* const temp_for_compile[] = {"__test1","__test2","__test3",NULL};
extern const char * const _env_args_reserve_[0] __attribute__((weak, alias("temp_for_compile")));
extern const char * const _aml_env_reserv_array[0] __attribute__((weak, alias("temp_for_compile")));
+extern const char * const _aml_env_reserv_array1[0] __attribute__((weak, alias("temp_for_compile")));
extern const char * const _board_env_reserv_array0[0] __attribute__((weak, alias("temp_for_compile")));
extern const char * const _board_env_reserv_array1[0] __attribute__((weak, alias("temp_for_compile")));
extern const char * const _board_env_reserv_array2[0] __attribute__((weak, alias("temp_for_compile")));
@@ -30,6 +31,7 @@
enum DEF_ENV_RESERV_ARRAY {
BIT_ENV_RESERV_ARRAY_AML_COMMON, //-c, common aml env array_aml_env_reserv_array
+ BIT_ENV_RESERV_ARRAY_AML_COMMON1, //-c, common aml env array_aml_env_reserv_array
BIT_ENV_RESERV_ARRAY_USER_INPUT, //input env1/env2/env3...
BIT_ENV_RESERV_ARRAY_BOARD_DEFINE0, //-b0, board env array _board_env_reserv_array0
BIT_ENV_RESERV_ARRAY_BOARD_DEFINE1, //-b1, board env array _board_env_reserv_array1
@@ -132,6 +134,7 @@
const char * const*_aml_env_reserv_[DEF_ENV_RESERV_ARRAY_COUNT];
_aml_env_reserv_[BIT_ENV_RESERV_ARRAY_AML_COMMON] = _aml_env_reserv_array;
+ _aml_env_reserv_[BIT_ENV_RESERV_ARRAY_AML_COMMON1] = _aml_env_reserv_array1;
_aml_env_reserv_[BIT_ENV_RESERV_ARRAY_USER_INPUT] = temp_for_compile;
_aml_env_reserv_[BIT_ENV_RESERV_ARRAY_BOARD_DEFINE0] = _board_env_reserv_array0;
_aml_env_reserv_[BIT_ENV_RESERV_ARRAY_BOARD_DEFINE1] = _board_env_reserv_array1;
@@ -140,7 +143,7 @@
while (argc > 1 && **(argv + 1) == '-') {
arg = *++argv;
--argc;
- while (*++arg) {
+ if (*++arg) {
switch (*arg) {
case 'b':{//board env
const int bd = *++arg - '0';
@@ -152,10 +155,18 @@
debugP("board reserv _board_env_reserv_array%d\n", bd);
rsv_flags |= 1 << (BIT_ENV_RESERV_ARRAY_BOARD_DEFINE0 + bd);
} break;
- case 'c'://common env
- MsgP("common reserv _aml_env_reserv_array\n");
- rsv_flags |= 1 << BIT_ENV_RESERV_ARRAY_AML_COMMON;
- break;
+ case 'c': {//common env
+ int icmn = arg[1];
+
+ if (icmn > '0') {
+ errorP("invalid cmn para %s\n", arg);
+ return CMD_RET_FAILURE;
+ }
+ if (icmn)
+ icmn = 1;
+ MsgP("common reserv para: %s\n", arg);
+ rsv_flags |= 1 << (BIT_ENV_RESERV_ARRAY_AML_COMMON + icmn);
+ } break;
default:
errorP("Invalid para -%s\n", arg);
return CMD_RET_USAGE;
diff --git a/cmd/amlogic/ini/ini_io.c b/cmd/amlogic/ini/ini_io.c
index 21f3cf1..46dd2b3 100644
--- a/cmd/amlogic/ini/ini_io.c
+++ b/cmd/amlogic/ini/ini_io.c
@@ -384,6 +384,44 @@
return tmp_ret;
}
+int read_model_name_param(int index, unsigned char data_buf[])
+{
+ int rd_size = 0;
+ const char *item_name = CS_MODEL_NAME_ITEM_NAME;
+
+ if (!data_buf)
+ return -1;
+
+ if (index == 1)
+ item_name = CS_MODEL1_NAME_ITEM_NAME;
+ else if (index == 2)
+ item_name = CS_MODEL2_NAME_ITEM_NAME;
+
+ rd_size = read_bin_data(item_name, data_buf);
+
+ return rd_size;
+}
+
+int save_model_name_param(int index, int wr_size, unsigned char data_buf[])
+{
+ int tmp_ret = 0;
+ const char *item_name = CS_MODEL_NAME_ITEM_NAME;
+
+ if (!data_buf)
+ return -1;
+
+ if (index == 1)
+ item_name = CS_MODEL1_NAME_ITEM_NAME;
+ else if (index == 2)
+ item_name = CS_MODEL2_NAME_ITEM_NAME;
+
+ tmp_ret = write_bin_data(item_name, wr_size, data_buf);
+ if (tmp_ret != wr_size)
+ return -1;
+
+ return tmp_ret;
+}
+
int read_tcon_spi_param(unsigned char data_buf[])
{
int rd_size = 0;
diff --git a/cmd/amlogic/ini/ini_io.h b/cmd/amlogic/ini/ini_io.h
index 530a0f6..1e8c726 100644
--- a/cmd/amlogic/ini/ini_io.h
+++ b/cmd/amlogic/ini/ini_io.h
@@ -14,16 +14,19 @@
#define CS_LCD_TCON_ITEM_NAME "lcd_tcon"
#define CS_LCD_TCON_SPI_ITEM_NAME "lcd_tcon_spi"
#define CS_LCD_OPTICAL_ITEM_NAME "lcd_optical"
+#define CS_MODEL_NAME_ITEM_NAME "model_name"
#define CS_LCD1_ITEM_NAME "lcd1"
#define CS_LCD1_EXT_ITEM_NAME "lcd1_extern"
#define CS_BACKLIGHT1_ITEM_NAME "backlight1"
#define CS_LCD1_OPTICAL_ITEM_NAME "lcd1_optical"
+#define CS_MODEL1_NAME_ITEM_NAME "model1_name"
#define CS_LCD2_ITEM_NAME "lcd2"
#define CS_LCD2_EXT_ITEM_NAME "lcd2_extern"
#define CS_BACKLIGHT2_ITEM_NAME "backlight2"
#define CS_LCD2_OPTICAL_ITEM_NAME "lcd2_optical"
+#define CS_MODEL2_NAME_ITEM_NAME "model2_name"
#define CS_PANEL_INI_PATH_ITEM_NAME "panel_ini_path"
#define CS_PANEL_PQ_PATH_ITEM_NAME "panel_pq_path"
@@ -45,6 +48,8 @@
int save_backlight_param(int index, int wr_size, unsigned char data_buf[]);
int read_ldim_dev_param(unsigned char data_buf[]);
int save_ldim_dev_param(int wr_size, unsigned char data_buf[]);
+int read_model_name_param(int index, unsigned char data_buf[]);
+int save_model_name_param(int index, int wr_size, unsigned char data_buf[]);
int read_tcon_spi_param(unsigned char data_buf[]);
int save_tcon_spi_param(int wr_size, unsigned char data_buf[]);
int read_lcd_optical_param(int index, unsigned char data_buf[]);
diff --git a/cmd/amlogic/ini/model.c b/cmd/amlogic/ini/model.c
index 8526bc0..02705eb 100644
--- a/cmd/amlogic/ini/model.c
+++ b/cmd/amlogic/ini/model.c
@@ -3595,20 +3595,25 @@
int handle_model_list(void)
{
- char *model, str[15];
+ char *model, str[15], model_val[50];
int i;
for (i = 0; i < 3; i++) {
+ memset(model_val, 0, sizeof(model_val));
if (i == 0)
sprintf(str, "model_name");
else
sprintf(str, "model%d_name", i);
- model = env_get(str);
- if (!model) {
- if (model_debug_flag & DEBUG_NORMAL)
- ALOGD("%s, no %s\n", __func__, str);
- continue;
+ if (read_model_name_param(i, model_val) <= 0) {
+ model = env_get(str);
+ if (!model) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no %s\n", __func__, str);
+ continue;
+ }
+ } else {
+ model = model_val;
}
printf("current %s: %s\n", str, model);
#ifdef CONFIG_AML_LCD
@@ -3657,25 +3662,112 @@
return NULL;
}
+int handle_model_get(const char *model, char buf[])
+{
+ const char *model_name = model;
+ char *str = NULL;
+ int index = 0, ret = -1;
+
+ if (!model || !buf)
+ goto __model_get_exit;
+
+ if (!model_name || !strcmp(model, "model_name") ||
+ !strcmp(model, "0")) {
+ index = 0;
+ model_name = "model_name";
+ } else if (!strcmp(model, "model1_name") ||
+ !strcmp(model, "1")) {
+ index = 1;
+ model_name = "model1_name";
+ } else if (!strcmp(model, "model2_name") ||
+ !strcmp(model, "2")) {
+ index = 2;
+ model_name = "model2_name";
+ }
+
+ ret = read_model_name_param(index, buf);
+ if (ret <= 0) {
+ str = env_get(model_name);
+ if (!str) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no %s\n", __func__, model);
+ goto __model_get_exit;
+ }
+ strcpy(buf, str);
+ }
+
+ ret = 0;
+
+__model_get_exit:
+ return ret;
+}
+
+int handle_model_set(const char *model, const char *val)
+{
+ const char *name = model;
+ int index = 0, ukey_ok = 0, env_ok = 0;
+
+ if (!val)
+ return -1;
+
+ if (!name || !strcmp(name, "model_name") ||
+ !strcmp(name, "0")) {
+ index = 0;
+ name = "model_name";
+ } else if (!strcmp(name, "model1_name") ||
+ !strcmp(name, "1")) {
+ index = 1;
+ name = "model1_name";
+ } else if (!strcmp(name, "model2_name") ||
+ !strcmp(name, "2")) {
+ index = 2;
+ name = "model2_name";
+ }
+
+ if (save_model_name_param(index, strlen(val) + 1,
+ (char *)val) > 0) {
+ ukey_ok = 1;
+ }
+ env_set(name, val);
+ env_ok = !env_save();
+
+ if (!ukey_ok || !env_ok) {
+ ALOGE("%s, [%d](%s): set %s=%s fail\n", __func__, index,
+ (ukey_ok ? (env_ok ? "unknown" : "env") : "ukey"),
+ name, val);
+ } else {
+ if (model_debug_flag & DEBUG_NORMAL) {
+ ALOGD("%s, [%d]: set %s=%s ok\n", __func__, index,
+ name, val);
+ }
+ }
+ return 0;
+}
+
int handle_model_sum(void)
{
- char *model, str[15];
+ char *model, str[15], model_val[50];
#ifdef CONFIG_AML_LCD
char *file_name, *p;
#endif
int i, ret;
for (i = 0; i < 3; i++) {
+ memset(model_val, 0, sizeof(model_val));
if (i == 0)
sprintf(str, "model_name");
else
sprintf(str, "model%d_name", i);
- model = env_get(str);
- if (!model) {
- if (model_debug_flag & DEBUG_NORMAL)
- ALOGD("%s, no %s\n", __func__, str);
- continue;
+ if (read_model_name_param(i, model_val) <= 0) {
+ model = env_get(str);
+ if (!model) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no %s\n", __func__, str);
+ continue;
+ }
+ } else {
+ model = model_val;
}
ret = parse_model_sum(i, get_model_sum_path(i), model);
if (ret < 0)
diff --git a/cmd/amlogic/storage.c b/cmd/amlogic/storage.c
index fa4e15f..d6f4aa5 100644
--- a/cmd/amlogic/storage.c
+++ b/cmd/amlogic/storage.c
@@ -1054,6 +1054,26 @@
return 0;
}
+static int do_store_ffu_op(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct storage_t *store = store_get_current();
+ u64 ver, cnt;
+ int ret = CMD_RET_FAILURE;
+ void *addr;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ ver = simple_strtoul(argv[1], NULL, 16);
+ addr = (void *)simple_strtoul(argv[2], NULL, 16);
+ cnt = simple_strtoul(argv[3], NULL, 16);
+
+ if (store->ffu_op)
+ ret = store->ffu_op(ver, addr, cnt);
+
+ return (ret == 0) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+}
+
static cmd_tbl_t cmd_store_sub[] = {
U_BOOT_CMD_MKENT(init, 4, 0, do_store_init, "", ""),
U_BOOT_CMD_MKENT(device, 4, 0, do_store_device, "", ""),
@@ -1071,6 +1091,7 @@
U_BOOT_CMD_MKENT(rsv, 6, 0, do_store_rsv_ops, "", ""),
U_BOOT_CMD_MKENT(param, 2, 0, do_store_param_ops, "", ""),
U_BOOT_CMD_MKENT(boot_copy_enable, 3, 0, do_store_boot_copy_enable, "", ""),
+ U_BOOT_CMD_MKENT(ffu_op, 4, 0, do_store_ffu_op, "", ""),
};
static int do_store(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -1177,5 +1198,7 @@
"store param\n"
" transfer bl2e/x ddrfip devfip size to kernel in such case like sc2\n"
"store boot_copy_enable [boot_index]\n"
- " check bootloader_x whether enable\n"
+ " check bootloader_x whether enable\n"
+ "store ffu [version] [addr] [cnt]\n"
+ " update ffu fw\n"
);
diff --git a/cmd/amlogic/store_wrapper.c b/cmd/amlogic/store_wrapper.c
index c07f6d3..213c529 100644
--- a/cmd/amlogic/store_wrapper.c
+++ b/cmd/amlogic/store_wrapper.c
@@ -9,6 +9,7 @@
#include <asm/amlogic/arch/cpu_config.h>
#include <amlogic/store_wrapper.h>
#include <u-boot/sha256.h>
+#include <amlogic/aml_mmc.h>
#define debugP(fmt...) //printf("Dbg[WRP]L%d:", __LINE__),printf(fmt)
#define errorP(fmt...) printf("Err[WRP]L%d:", __LINE__),printf(fmt)
@@ -150,6 +151,113 @@
return ret;
}
+#ifdef CONFIG_CMD_MMC
+static int _amlmmc_rdwr_bootloader(int dev, int map, unsigned int size, void *src, int iswrite)
+{
+ int ret = 0, i, count = 3;
+ unsigned long n;
+ char *partname[3] = {"user", "boot0", "boot1"};
+ struct mmc *mmc = NULL;
+ lbaint_t start = 1, blkcnt;
+
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("%s() %d: not valid emmc %d\n", __func__, __LINE__, dev);
+ return -1;
+ }
+ /* make sure mmc is initialized! */
+ ret = mmc_init(mmc);
+ if (ret) {
+ printf("%s() %d: emmc %d init %d\n", __func__, __LINE__, dev, ret);
+ return -2;
+ }
+
+ blkcnt = (size + mmc->read_bl_len - 1) / mmc->read_bl_len;
+
+ /* erase bootloader in user/boot0/boot1 */
+ for (i = 0; i < count; i++) {
+ if (map & (1 << i)) {
+ if (blk_select_hwpart_devnum(UCLASS_MMC, 1, i)) {
+ printf("%s() %d: switch dev %d to %s fail\n",
+ __func__, __LINE__, dev, partname[i]);
+ ret = -3;
+ break;
+ }
+
+ printf("To %s " LBAFU " blocks at " LBAFU " @%s\n",
+ iswrite ? "Write" : "Read", blkcnt, start, partname[i]);
+ if (iswrite)
+ n = blk_dwrite(mmc_get_blk_desc(mmc), start, blkcnt, src);
+ else
+ n = blk_dread(mmc_get_blk_desc(mmc), start, blkcnt, src);
+ if (n != blkcnt) {
+ printf("mmc rd/wr %s failed\n", partname[i]);
+ ret = -4;
+ break;
+ }
+ }
+ }
+
+ /* try to switch back to user. */
+ if (blk_select_hwpart_devnum(UCLASS_MMC, 1, 0)) {
+ errorP("Fail switch to user\n");
+ return -5;
+ }
+ return ret;
+}
+#else
+static int _amlmmc_rdwr_bootloader(int dev, int map, unsigned int size, void *src, int iswrite)
+{
+ errorP("MMC not enable\n");
+ return -1;
+}
+#endif// #ifdef CONFIG_CMD_MMC
+
+static int _amlmmc_write_bootloader(int dev, int map, unsigned int size, void *src)
+{
+ return _amlmmc_rdwr_bootloader(dev, map, size, src, 1);
+}
+
+static int _amlmmc_read_bootloader(int dev, int map, unsigned int size, void *src)
+{
+ return _amlmmc_rdwr_bootloader(dev, map, size, src, 0);
+}
+
+int store_bootloader_ops(int ops, const char *name, void *pdata, unsigned int szdata)
+{
+ int map = 0;
+ int cpy = 0;
+ int ret = -1;
+ const int DEV = 1;
+ const char *_names[] = {"bootloader-user", "bootloader-boot0", "bootloader-boot1"};
+
+ for (; cpy < ARRAY_SIZE(_names); ++cpy) {
+ if (!strcmp(_names[cpy], name))
+ break;
+ }
+ if (cpy > 2) {
+ errorP("inval cpy %d\n", cpy);
+ return -__LINE__;
+ }
+ map = (1<<cpy);
+ switch (ops) {
+ case _STORE_BOOT_OP_WRITE: {
+ ret = _amlmmc_write_bootloader(DEV, map, szdata, pdata);
+ break;
+ }
+ case _STORE_BOOT_OP_READ: {
+ ret = _amlmmc_read_bootloader(DEV, map, szdata, pdata);
+ break;
+ }
+ case _STORE_BOOT_OP_ERASE:
+ default:
+ errorP("inval op:%d\n", ops);
+ return -__LINE__;
+ }
+
+ return ret;
+}
+
#ifndef CONFIG_AML_V3_FACTORY_BURN//storage wrapper
#define FB_ERR(fmt ...) printf("[ERR]%s:L%d:", __func__, __LINE__), printf(fmt)
#define FB_EXIT(fmt ...) do { FB_ERR(fmt); return -__LINE__; } while (0)
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 01f7d88..599d0b2 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -138,7 +138,7 @@
for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) {
u64 rb_idx = out_data->rollback_indexes[i];
- if (get_avb_antirollback(i, &version) &&
+ if (rb_idx != 0 && get_avb_antirollback(i, &version) &&
version < (u32)rb_idx &&
!set_avb_antirollback(i, (u32)rb_idx)) {
printf("rollback(%d) = %u failed\n",
diff --git a/common/cmd_afm.c b/common/cmd_afm.c
index 1c21243..e9639b2 100644
--- a/common/cmd_afm.c
+++ b/common/cmd_afm.c
@@ -4,10 +4,56 @@
*/
#include <common.h>
#include <command.h>
+#include "../include/amlogic/ini.h"
+
static int do_afm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *str_cmd, *str_value = NULL;
-
+ if (argc == 2 && !strcmp(argv[1], "print"))
+ {
+ char *serialno = env_get("usid");
+ char *mac = env_get("mac");
+ char *console = env_get("console");
+ char *silent = env_get("silent");
+ char *powermode = env_get("powermode");
+ char *otg_device = env_get("otg_device");
+ char *selinux = env_get("EnableSelinux");
+ char model_name[50] = {0}, model1_name[50] = {0}, model2_name[50] = {0}, modelt_name[150] = {0};
+ handle_model_get("0", model_name);
+ handle_model_get("1", model1_name);
+ handle_model_get("2", model2_name);
+ if (strlen(model_name) != 0)
+ {
+ strcat(modelt_name, model_name);
+ }
+ if (strlen(model1_name) != 0) {
+ strcat(modelt_name, "|");
+ strcat(modelt_name, model1_name);
+ }
+ if (strlen(model2_name) !=0 ) {
+ strcat(modelt_name, "|");
+ strcat(modelt_name, model2_name);
+ }
+ //printf("current %s: %s\n", str, model_name);
+ printf("\n"
+ "model_name : %s\n"
+ "serialno : %s\n"
+ "mac : %s\n"
+ "console : %s\n"
+ "silent : %s\n"
+ "powermode : %s\n"
+ "otg_device : %s\n"
+ "selinux : %s\n"
+ , strlen(modelt_name) != 0 ? modelt_name : ""
+ , serialno != NULL? serialno : ""
+ , mac != NULL? mac : ""
+ , console != NULL && !strcmp(console, "ttyS0,115200") ? "on" : "off"
+ , silent != NULL? (!strcmp(silent, "0")? "on" : "off") : "on"
+ , powermode != NULL? powermode : ""
+ , otg_device != NULL? otg_device : ""
+ , selinux != NULL? selinux : "");
+ return 0;
+ }
if (argc != 3)
return CMD_RET_USAGE;
str_cmd = argv[1];
@@ -27,6 +73,16 @@
}
run_command("saveenv", 0);
return 0;
+ } else if (!strcmp(str_cmd, "serialno")) {
+ char result[50] = "keyman write usid str ";//size 21
+ if (strlen(str_value) > 17) {//str_value size 17
+ printf("invalid no\n");
+ return CMD_RET_USAGE;
+ }
+ strcat(result, str_value);
+ run_command(result, 0);
+ run_command("keyman read usid $loadaddr str; printenv usid", 0);
+ return 0;
} else if (!strcmp(str_cmd, "mac")) {
char result[50] = "keyman write mac str ";//size 21
@@ -38,6 +94,59 @@
run_command(result, 0);
run_command("keyman read mac $loadaddr str; printenv mac", 0);
return 0;
+ } else if (!strcmp(str_cmd, "silent")) {
+ if (!strcmp(str_value, "on")) {
+ run_command("setenv silent 0", 0);
+ } else if (!strcmp(str_value, "off")) {
+ run_command("setenv silent 1", 0);
+ } else {
+ printf("invalid value\n");
+ return CMD_RET_USAGE;
+ }
+ run_command("saveenv", 0);
+ } else if (!strcmp(str_cmd, "powermode")) {
+ if (!strcmp(str_value, "on")) {
+ run_command("setenv powermode on", 0);
+ } else if (!strcmp(str_value, "standby")) {
+ run_command("setenv powermode standby", 0);
+ } else {
+ printf("invalid value\n");
+ return CMD_RET_USAGE;
+ }
+ run_command("saveenv", 0);
+ } else if (!strcmp(str_cmd, "selinux")) {
+ if (!strcmp(str_value, "enforcing")) {
+ run_command("setenv EnableSelinux enforcing", 0);
+ } else if (!strcmp(str_value, "permissive")) {
+ run_command("setenv EnableSelinux permissive", 0);
+ } else if (!strcmp(str_value, "disabled")) {
+ run_command("setenv EnableSelinux disabled", 0);
+ } else {
+ printf("invalid value\n");
+ return CMD_RET_USAGE;
+ }
+ run_command("saveenv", 0);
+ } else if (!strcmp(str_cmd, "model_name")) {
+ handle_model_set("model_name", str_value);
+ } else if (!strcmp(str_cmd, "model1_name")) {
+ handle_model_set("model1_name", str_value);
+ } else if (!strcmp(str_cmd, "model2_name")) {
+ handle_model_set("model2_name", str_value);
+ } else if (!strcmp(str_cmd, "console")) {
+ if (!strcmp(str_value, "on")) {
+ run_command("setenv console ttyS0,115200", 0);
+ run_command("setenv loglevel 7", 0);
+ } else if (!strcmp(str_value, "off")) {
+ run_command("setenv console off", 0);
+ run_command("setenv loglevel 0", 0);
+ } else {
+ printf("invalid value\n");
+ return CMD_RET_USAGE;
+ }
+ run_command("saveenv", 0);
+ } else {
+ printf("invalid value\n");
+ return CMD_RET_USAGE;
}
return 0;
}
@@ -49,9 +158,9 @@
"afm serialno <serial no> - modify serial no\n"
"afm mac <mac address> - modify mac address\n"
"afm console <on|off> - modify console state\n"
- "afm model_name <ModelName> - modify screen parameters\n"
"afm silent <on|off> - modify the print state of uboot bl33 serial port\n"
"afm powermode <on|standby> - modify power on mode\n"
"afm otg_device <1|0> - modify the USB host/device state\n"
"afm selinux <0|1|2(permissive|enforcing|disabled)> - modify the selinux mode\n"
+ "afm print - Print the values of all parameters\n"
);
diff --git a/common/fdt_support.c b/common/fdt_support.c
index ebebffc..0b40ddd 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -296,7 +296,11 @@
if (nodeoffset < 0)
return nodeoffset;
+#ifndef CONFIG_AMLOGIC_MODIFY
if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
+#else
+ if (!board_rng_seed(&buf)) {
+#endif
err = fdt_setprop(fdt, nodeoffset, "rng-seed",
abuf_data(&buf), abuf_size(&buf));
abuf_uninit(&buf);
diff --git a/configs/amlogic/s6_bl201_defconfig b/configs/amlogic/s6_bl201_defconfig
index cc68d1a..ae836b9 100644
--- a/configs/amlogic/s6_bl201_defconfig
+++ b/configs/amlogic/s6_bl201_defconfig
@@ -73,6 +73,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -82,6 +87,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -108,6 +115,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -124,3 +132,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bl204_defconfig b/configs/amlogic/s6_bl204_defconfig
index 48994c7..3476e8b 100644
--- a/configs/amlogic/s6_bl204_defconfig
+++ b/configs/amlogic/s6_bl204_defconfig
@@ -73,6 +73,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -82,6 +87,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -108,6 +115,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -124,3 +132,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bl208_defconfig b/configs/amlogic/s6_bl208_defconfig
index 27f7337..ba0afb3 100644
--- a/configs/amlogic/s6_bl208_defconfig
+++ b/configs/amlogic/s6_bl208_defconfig
@@ -71,6 +71,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -80,6 +85,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -105,6 +112,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -121,3 +129,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bl209_defconfig b/configs/amlogic/s6_bl209_defconfig
index 7836660..a59c240 100644
--- a/configs/amlogic/s6_bl209_defconfig
+++ b/configs/amlogic/s6_bl209_defconfig
@@ -71,6 +71,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -80,6 +85,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -105,6 +112,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -121,3 +129,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bn201_defconfig b/configs/amlogic/s6_bn201_defconfig
index ac093af..4c9ac98 100644
--- a/configs/amlogic/s6_bn201_defconfig
+++ b/configs/amlogic/s6_bn201_defconfig
@@ -74,6 +74,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -83,6 +88,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -108,6 +115,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -122,3 +130,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=16
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bq201_defconfig b/configs/amlogic/s6_bq201_defconfig
index 43fbf5c..bb5248b 100644
--- a/configs/amlogic/s6_bq201_defconfig
+++ b/configs/amlogic/s6_bq201_defconfig
@@ -71,6 +71,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -80,6 +85,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -109,6 +116,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -125,3 +133,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bq208_defconfig b/configs/amlogic/s6_bq208_defconfig
index debb45d..7082190 100644
--- a/configs/amlogic/s6_bq208_defconfig
+++ b/configs/amlogic/s6_bq208_defconfig
@@ -71,6 +71,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -80,6 +85,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -109,6 +116,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -125,3 +133,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_bq209_defconfig b/configs/amlogic/s6_bq209_defconfig
index 2d7605a..c63f90a 100644
--- a/configs/amlogic/s6_bq209_defconfig
+++ b/configs/amlogic/s6_bq209_defconfig
@@ -71,6 +71,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
@@ -80,6 +85,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -109,6 +116,7 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -125,3 +133,4 @@
CONFIG_LMB_MAX_REGIONS=16
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s6_skt_defconfig b/configs/amlogic/s6_skt_defconfig
index df4e6c6..fc23017 100644
--- a/configs/amlogic/s6_skt_defconfig
+++ b/configs/amlogic/s6_skt_defconfig
@@ -68,6 +68,11 @@
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=2
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_AMLOGIC=y
CONFIG_DM_ETH=y
@@ -79,6 +84,8 @@
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -103,6 +110,7 @@
CONFIG_AMLOGIC_TEE=y
CONFIG_PHY_AMLOGIC=y
CONFIG_PINCTRL_MESON_S6=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_MESON_NFC=y
CONFIG_AMLOGIC_USB=y
CONFIG_USB_XHCI_CRG=y
@@ -122,3 +130,4 @@
CONFIG_AML_CRYPTO_64=y
CONFIG_ARMV8_CRYPTO=y
CONFIG_AML_UPDATE_PDVFS=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_bh201_defconfig b/configs/amlogic/s7_bh201_defconfig
index ffced4a..d1ea804 100644
--- a/configs/amlogic/s7_bh201_defconfig
+++ b/configs/amlogic/s7_bh201_defconfig
@@ -126,3 +126,4 @@
CONFIG_SHA1=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_bh202_defconfig b/configs/amlogic/s7_bh202_defconfig
index 2917dda..304a600 100644
--- a/configs/amlogic/s7_bh202_defconfig
+++ b/configs/amlogic/s7_bh202_defconfig
@@ -122,3 +122,4 @@
CONFIG_SHA1=y
CONFIG_LMB_MAX_REGIONS=9
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_bh209_defconfig b/configs/amlogic/s7_bh209_defconfig
index e0b3c66..a093739 100644
--- a/configs/amlogic/s7_bh209_defconfig
+++ b/configs/amlogic/s7_bh209_defconfig
@@ -122,3 +122,4 @@
CONFIG_SHA1=y
CONFIG_LMB_MAX_REGIONS=9
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_bp201_defconfig b/configs/amlogic/s7_bp201_defconfig
index 1fc5633..0ffd839 100644
--- a/configs/amlogic/s7_bp201_defconfig
+++ b/configs/amlogic/s7_bp201_defconfig
@@ -125,3 +125,4 @@
CONFIG_SHA1=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_bp202_defconfig b/configs/amlogic/s7_bp202_defconfig
index 445541a..200d8fd 100644
--- a/configs/amlogic/s7_bp202_defconfig
+++ b/configs/amlogic/s7_bp202_defconfig
@@ -121,3 +121,4 @@
CONFIG_SHA1=y
CONFIG_LMB_MAX_REGIONS=9
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_pxp_defconfig b/configs/amlogic/s7_pxp_defconfig
index 6fd8efe..8ba3726 100644
--- a/configs/amlogic/s7_pxp_defconfig
+++ b/configs/amlogic/s7_pxp_defconfig
@@ -97,3 +97,4 @@
CONFIG_SARADC_MESON_G12A=y
CONFIG_SHA1=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_t223_defconfig b/configs/amlogic/s7_t223_defconfig
index 55907c1..2a6ec35 100644
--- a/configs/amlogic/s7_t223_defconfig
+++ b/configs/amlogic/s7_t223_defconfig
@@ -103,3 +103,4 @@
CONFIG_SHA1=y
CONFIG_LMB_MAX_REGIONS=9
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7_t233_defconfig b/configs/amlogic/s7_t233_defconfig
index c73a21b..cbebe21 100644
--- a/configs/amlogic/s7_t233_defconfig
+++ b/configs/amlogic/s7_t233_defconfig
@@ -125,3 +125,4 @@
CONFIG_SHA1=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7d_bm201_defconfig b/configs/amlogic/s7d_bm201_defconfig
index 5ba544f..f2a48ab 100644
--- a/configs/amlogic/s7d_bm201_defconfig
+++ b/configs/amlogic/s7d_bm201_defconfig
@@ -113,3 +113,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7d_bm202_defconfig b/configs/amlogic/s7d_bm202_defconfig
index 66c90b2..210e540 100644
--- a/configs/amlogic/s7d_bm202_defconfig
+++ b/configs/amlogic/s7d_bm202_defconfig
@@ -89,6 +89,7 @@
CONFIG_AML_MEDIA=y
CONFIG_AML_VOUT=y
CONFIG_AML_OSD=y
+CONFIG_AML_DOLBY=y
CONFIG_AML_VPP=y
CONFIG_AML_VPU=y
CONFIG_AML_CVBS=y
@@ -112,3 +113,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7d_bm209_defconfig b/configs/amlogic/s7d_bm209_defconfig
index 85a1dcb..29ceeca 100644
--- a/configs/amlogic/s7d_bm209_defconfig
+++ b/configs/amlogic/s7d_bm209_defconfig
@@ -100,6 +100,7 @@
CONFIG_AML_MEDIA=y
CONFIG_AML_VOUT=y
CONFIG_AML_OSD=y
+CONFIG_AML_DOLBY=y
CONFIG_AML_VPP=y
CONFIG_AML_VPU=y
CONFIG_AML_CVBS=y
@@ -125,3 +126,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7d_pxp_defconfig b/configs/amlogic/s7d_pxp_defconfig
index 2ea49e8..68917d2 100644
--- a/configs/amlogic/s7d_pxp_defconfig
+++ b/configs/amlogic/s7d_pxp_defconfig
@@ -101,3 +101,4 @@
CONFIG_AML_VPU=y
CONFIG_AMLOGIC_AMFC=y
CONFIG_ZSTD=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/s7d_t232_defconfig b/configs/amlogic/s7d_t232_defconfig
index 62c1da7..fb31588 100644
--- a/configs/amlogic/s7d_t232_defconfig
+++ b/configs/amlogic/s7d_t232_defconfig
@@ -112,3 +112,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=9
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/t6d_br301_defconfig b/configs/amlogic/t6d_br301_defconfig
index 2f11924..abaf17c 100644
--- a/configs/amlogic/t6d_br301_defconfig
+++ b/configs/amlogic/t6d_br301_defconfig
@@ -120,3 +120,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=16
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/t6d_br309_defconfig b/configs/amlogic/t6d_br309_defconfig
index 7f696f9..06ea8f2 100644
--- a/configs/amlogic/t6d_br309_defconfig
+++ b/configs/amlogic/t6d_br309_defconfig
@@ -127,3 +127,4 @@
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=16
CONFIG_BAUDRATE=115200
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/t6d_pxp_defconfig b/configs/amlogic/t6d_pxp_defconfig
index cff8c4c..f3e4d32 100644
--- a/configs/amlogic/t6d_pxp_defconfig
+++ b/configs/amlogic/t6d_pxp_defconfig
@@ -101,3 +101,4 @@
CONFIG_AML_LCD=y
CONFIG_AML_LCD_TV=y
CONFIG_AML_LCD_TABLET=y
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/configs/amlogic/t6d_t335_defconfig b/configs/amlogic/t6d_t335_defconfig
index 75e01f0..4603a7b 100644
--- a/configs/amlogic/t6d_t335_defconfig
+++ b/configs/amlogic/t6d_t335_defconfig
@@ -120,3 +120,4 @@
CONFIG_ZSTD=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_LMB_MAX_REGIONS=16
+CONFIG_CMD_SCMI_SHMEM_ADDR=y
diff --git a/drivers/amlogic/amfc/amfc.c b/drivers/amlogic/amfc/amfc.c
index 1a3a6df..9b525ae 100644
--- a/drivers/amlogic/amfc/amfc.c
+++ b/drivers/amlogic/amfc/amfc.c
@@ -40,7 +40,7 @@
if (cpu_id.family_id == MESON_CPU_MAJOR_ID_S7D && cpu_id.chip_rev == 0x0A) {
writel(0 | (1 << 6) | (5 << 7), CLKCTRL_AMFC_CLK_CTRL); // 500MHz
} else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_T6D) {
- writel(0 | (1 << 8) | (1 << 9), CLKCTRL_AMFC_CLK_CTRL); // 666MHz
+ writel(1 | (1 << 8) | (6 << 9), CLKCTRL_AMFC_CLK_CTRL); // 576MHz
} else { // s7d/s6
writel(0 | (1 << 6) | (4 << 7), CLKCTRL_AMFC_CLK_CTRL); // 666MHz
}
diff --git a/drivers/amlogic/media/common/vpp/vpp.c b/drivers/amlogic/media/common/vpp/vpp.c
index d5ecbe4..d365653 100644
--- a/drivers/amlogic/media/common/vpp/vpp.c
+++ b/drivers/amlogic/media/common/vpp/vpp.c
@@ -2310,6 +2310,45 @@
vpp_reg_write(0x2654, 0x00000000);
}
+void set_vpp_mute(void)
+{
+ char *s = NULL;
+ u32 clip_max = 0x0;
+ u32 clip_min = 0x0;
+ u32 family_id = get_cpu_id().family_id;
+
+ if (family_id == MESON_CPU_MAJOR_ID_T3X ||
+ family_id == MESON_CPU_MAJOR_ID_S5)
+ return;
+ s = env_get("connector0_type");
+ if (!s) {
+ VPP_PR("can not get connector0_type!\n");
+ return;
+ }
+ if (!strncmp(s, "HDMI", 4)) {
+ clip_max = (0x0 << 20) | (0x200 << 10) | 0x200;
+ clip_min = (0x0 << 20) | (0x200 << 10) | 0x200;
+ } else {
+ clip_max = (0x0 << 20) | (0x0 << 10) | 0;
+ clip_min = (0x0 << 20) | (0x0 << 10) | 0;
+ }
+ vpp_reg_write(VPP_CLIP_MISC0, clip_max);
+ vpp_reg_write(VPP_CLIP_MISC1, clip_min);
+}
+
+void set_vpp_unmute(void)
+{
+ u32 clip_max = 0x3fffffff;
+ u32 clip_min = 0x0;
+ u32 family_id = get_cpu_id().family_id;
+
+ if (family_id == MESON_CPU_MAJOR_ID_T3X ||
+ family_id == MESON_CPU_MAJOR_ID_S5)
+ return;
+ vpp_reg_write(VPP_CLIP_MISC0, clip_max);
+ vpp_reg_write(VPP_CLIP_MISC1, clip_min);
+}
+
void vpp_init(void)
{
int chip_id;
diff --git a/drivers/amlogic/media/osd/osd_fb.h b/drivers/amlogic/media/osd/osd_fb.h
index e09041d..f62ce9f 100644
--- a/drivers/amlogic/media/osd/osd_fb.h
+++ b/drivers/amlogic/media/osd/osd_fb.h
@@ -17,6 +17,5 @@
int img_display(ulong bmp_image, int x, int y);
int img_scale(void);
void img_raw_size_set(u32 raw_width, u32 raw_height, u32 raw_bpp);
-bool is_keystone_enable_for_t6d(void);
#endif
diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c
index c920f88..15b10b5 100644
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -2558,7 +2558,8 @@
u32 h = osd_hw.free_dst_data[index].y_end -
osd_hw.free_dst_data[index].y_start + 1;
- if ((w > 3840 && h > 2160) || (w > 4096 && h > 2160))
+ /* 4096x2160p and 8k need use pi */
+ if (w > 3840 && h >= 2160)
pi_enable = 1;
else
pi_enable = 0;
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
index be9e5f5..93f1c12 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmitx_drv.c
@@ -135,6 +135,9 @@
hdmitx21_set_reg_bits(PCLK2TMDS_MISC0_IVCTX, 0, 0, 2);
/* Control signals for repeat count */
hdmitx21_set_reg_bits(HBLANK_REKEY_CONTROL_IVCTX, 1, 6, 1);
+
+ /* for 480/576 ddp case, Internal circuit detected Hsync polarity: Use legacy Tx logic */
+ hdmitx21_set_reg_bits(HDPLL_FIX0_IVCTX, 0, 0, 1);
hdmitx21_set_reg_bits(GCP_CNTL_IVCTX, 1, 0, 1);
/* clear avmute */
hdmitx21_set_reg_bits(GCP_AUTO_GEN_IVCTX, 2, 2, 2);
@@ -1029,15 +1032,18 @@
hd21_set_reg_bits(VPU_HDMI_FMT_CTRL, 3, 0, 2);
}
+/* need enable phy to digital and keep tmds clk */
static void hdmitx_set_phy_todig(struct hdmitx_dev *hdev)
{
switch (hdev->chip_type) {
case MESON_CPU_ID_S7:
+ case MESON_CPU_ID_S7D:
+ case MESON_CPU_ID_S6:
hd21_set_reg_bits(ANACTRL_HDMIPHY_CTRL3, 3, 0, 2);
hd21_set_reg_bits(ANACTRL_HDMIPHY_CTRL3, 1, 3, 1);
break;
default:
- //pr_info("not match chip type to enable phy to dig\n");
+ /* pr_info("not match chip type to enable phy to dig\n"); */
return;
}
pr_info("enable phy to dig\n");
@@ -1575,8 +1581,7 @@
hdmitx_set_phy_todig(hdev);
/*
- * when in deep color, htotal is fractional value
- * here need check the phase is stable or not
+ * when GCP phase is a fix value, here need check the phase is stable or not
* otherwise it may cause display flash and abnormal issue
*/
{
@@ -1586,6 +1591,7 @@
bool h_unstable = 0;
int loop = 20;
+ /*check the GCP phase is a fix value*/
h_unstable = is_deep_htotal_frac(0, h_total, cs, cd);
pr_info("%s[%d] frl_rate %d htotal %d cs %d cd %d h_unstable %d\n",
__func__, __LINE__, get_current_frl_rate(), h_total, cs, cd, h_unstable);
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_edid_parse.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_edid_parse.c
index 0cb8674..1bd37ea 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_edid_parse.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx_common/hdmitx_edid_parse.c
@@ -65,17 +65,108 @@
const struct hdmi_timing *hdmitx_mode_match_timing_name(const char *name);
static void edid_dtd_parsing(struct rx_cap *prxcap, unsigned char *data);
static void hdmitx_edid_set_default_aud(struct rx_cap *prxcap);
+static void edid_check_pcm_declare(struct rx_cap *prxcap);
-static void phy_addr_clear(struct vsdb_phyaddr *vsdb_phy_addr)
+/*
+ * cec_get_edid_spa_location() - find location of the Source Physical Address
+ *
+ * @edid: the EDID
+ * @size: the size of the EDID
+ *
+ * This EDID is expected to be a CEA-861 compliant, which means that there are
+ * at least two blocks and one or more of the extensions blocks are CEA-861
+ * blocks.
+ *
+ * The returned location is guaranteed to be <= size-2.
+ *
+ * This is an inline function since it is used by both CEC and V4L2.
+ * Ideally this would go in a module shared by both, but it is overkill to do
+ * that for just a single function.
+ */
+static unsigned int cec_get_edid_spa_location(const u8 *edid, unsigned int size)
{
- if (!vsdb_phy_addr)
+ unsigned int blocks = size / 128;
+ unsigned int block;
+ u8 d;
+
+ /* Sanity check: at least 2 blocks and a multiple of the block size */
+ if (blocks < 2 || size % 128)
+ return 0;
+
+ /*
+ * If there are fewer extension blocks than the size, then update
+ * 'blocks'. It is allowed to have more extension blocks than the size,
+ * since some hardware can only read e.g. 256 bytes of the EDID, even
+ * though more blocks are present. The first CEA-861 extension block
+ * should normally be in block 1 anyway.
+ */
+ if (edid[0x7e] + 1 < blocks)
+ blocks = edid[0x7e] + 1;
+
+ for (block = 1; block < blocks; block++) {
+ unsigned int offset = block * 128;
+
+ /* Skip any non-CEA-861 extension blocks */
+ if (edid[offset] != 0x02 || edid[offset + 1] != 0x03)
+ continue;
+
+ /* search Vendor Specific Data Block (tag 3) */
+ d = edid[offset + 2] & 0x7f;
+ /* Check if there are Data Blocks */
+ if (d <= 4)
+ continue;
+ if (d > 4) {
+ unsigned int i = offset + 4;
+ unsigned int end = offset + d;
+
+ /* Note: 'end' is always < 'size' */
+ do {
+ u8 tag = edid[i] >> 5;
+ u8 len = edid[i] & 0x1f;
+
+ if (tag == 3 && len >= 5 && i + len <= end &&
+ edid[i + 1] == 0x03 &&
+ edid[i + 2] == 0x0c &&
+ edid[i + 3] == 0x00)
+ return i + 4;
+ i += len + 1;
+ } while (i < end);
+ }
+ }
+ return 0;
+}
+
+static u16 hdmitx_cec_get_edid_phys_addr(const u8 *edid, unsigned int size)
+{
+ unsigned int loc = cec_get_edid_spa_location(edid, size);
+
+ if (loc == 0)
+ return 0xffff;
+ return (edid[loc] << 8) | edid[loc + 1];
+}
+
+void hdmitx_cec_phy_addr_parse(struct rx_cap *prxcap, u8 *edid_buf)
+{
+ u16 pa = 0xffff;
+ unsigned char edid_check = 0;
+
+ if (!prxcap || !edid_buf)
return;
- vsdb_phy_addr->a = 0;
- vsdb_phy_addr->b = 0;
- vsdb_phy_addr->c = 0;
- vsdb_phy_addr->d = 0;
- vsdb_phy_addr->valid = 0;
+ edid_check = prxcap->edid_check;
+ if (hdmitx_edid_check_data_valid(edid_check, edid_buf) == false)
+ return;
+
+ if (edid_buf && edid_buf[0x7e]) {
+ pa = hdmitx_cec_get_edid_phys_addr((const u8 *)edid_buf,
+ 128 * (edid_buf[0x7e] + 1));
+ prxcap->vsdb_phy_addr.a = (pa >> 12) & 0xf;
+ prxcap->vsdb_phy_addr.b = (pa >> 8) & 0xf;
+ prxcap->vsdb_phy_addr.c = (pa >> 4) & 0xf;
+ prxcap->vsdb_phy_addr.d = (pa >> 0) & 0xf;
+ if (pa != 0xffff)
+ prxcap->vsdb_phy_addr.valid = 1;
+ }
}
static bool hdmitx_edid_header_invalid(u8 edid_check, const u8 *buf)
@@ -380,7 +471,7 @@
*/
u32 hdmitx_edid_get_hdmi14_4k_vic(u32 vic)
{
- bool ret = 0;
+ u32 ret = 0;
int i;
for (i = 0; i < ARRAY_SIZE(hdmi14_4k_vics); i++) {
@@ -644,39 +735,6 @@
}
}
-static struct vsdb_phyaddr vsdb_local = {0};
-int get_vsdb_phy_addr(struct vsdb_phyaddr *vsdb)
-{
- if (!vsdb)
- return -1;
-
- vsdb = &vsdb_local;
- return vsdb->valid;
-}
-
-static void set_vsdb_phy_addr(struct rx_cap *prxcap,
- unsigned char *edid_offset)
-{
- int phy_addr;
- struct vsdb_phyaddr *vsdb;
-
- if (!prxcap || !edid_offset)
- return;
- vsdb = &prxcap->vsdb_phy_addr;
- vsdb->a = (edid_offset[0] >> 4) & 0xf;
- vsdb->b = (edid_offset[0] >> 0) & 0xf;
- vsdb->c = (edid_offset[1] >> 4) & 0xf;
- vsdb->d = (edid_offset[1] >> 0) & 0xf;
- vsdb_local = *vsdb;
- vsdb->valid = 1;
-
- phy_addr = ((vsdb->a & 0xf) << 12) |
- ((vsdb->b & 0xf) << 8) |
- ((vsdb->c & 0xf) << 4) |
- ((vsdb->d & 0xf) << 0);
- prxcap->physical_addr = phy_addr;
-}
-
static void set_vsdb_dc_cap(struct rx_cap *prxcap)
{
if (!prxcap)
@@ -1132,13 +1190,13 @@
(svr >= 193 && svr <= 253)) {
prxcap->flag_vfpdb = 1;
prxcap->preferred_mode = svr;
- pr_debug("preferred mode 0 srv %d\n", prxcap->preferred_mode);
+ HDMITX_DEBUG("preferred mode 0 srv %d\n", prxcap->preferred_mode);
return 1;
}
if (svr >= 129 && svr <= 144) {
prxcap->flag_vfpdb = 1;
prxcap->preferred_mode = prxcap->dtd[svr - 129].vic;
- pr_debug("preferred mode 0 dtd %d\n", prxcap->preferred_mode);
+ HDMITX_DEBUG("preferred mode 0 dtd %d\n", prxcap->preferred_mode);
return 1;
}
return 0;
@@ -1208,21 +1266,21 @@
pos = 0;
length = buf[pos] & 0x1f;
if (length != 0x06)
- pr_debug("%s[%d]: the length is %d, should be 6 bytes\n",
+ HDMITX_DEBUG("%s[%d]: the length is %d, should be 6 bytes\n",
__func__, __LINE__, length);
cap->length = length;
pos += 2;
ieeeoui = buf[pos] + (buf[pos + 1] << 8) + (buf[pos + 2] << 16);
if (ieeeoui != DOVI_IEEEOUI)
- pr_debug("%s[%d]: the ieeeoui is 0x%x, should be 0x%x\n",
+ HDMITX_DEBUG("%s[%d]: the ieeeoui is 0x%x, should be 0x%x\n",
__func__, __LINE__, ieeeoui, DOVI_IEEEOUI);
cap->ieeeoui = ieeeoui;
pos += 3;
cap->dolby_vsadb_ver = buf[pos] & 0x7;
if (cap->dolby_vsadb_ver)
- pr_debug("%s[%d]: the version is 0x%x, should be 0x0\n",
+ HDMITX_DEBUG("%s[%d]: the version is 0x%x, should be 0x0\n",
__func__, __LINE__, cap->dolby_vsadb_ver);
cap->spk_center = (buf[pos] >> 4) & 1;
@@ -1418,7 +1476,7 @@
return;
if (size > 4 || size == 0) {
- pr_debug(EDID "4k2k in edid out of range, SIZE = %d\n", size);
+ HDMITX_DEBUG("4k2k in edid out of range, SIZE = %d\n", size);
return;
}
while (size--) {
@@ -1430,8 +1488,6 @@
store_cea_idx(prxcap, HDMI_93_3840x2160p24_16x9);
else if (*dat == 4)
store_cea_idx(prxcap, HDMI_98_4096x2160p24_256x135);
- else
- ;
dat++;
}
}
@@ -1485,7 +1541,6 @@
return;
prxcap->ieeeoui = HDMI_IEEE_OUI;
- set_vsdb_phy_addr(prxcap, &block_buf[offset + 3]);
prxcap->ColorDeepSupport = (count > 5) ? block_buf[offset + 5] : 0;
set_vsdb_dc_cap(prxcap);
@@ -1534,89 +1589,6 @@
}
}
-/*
- * force_vsvdb
- * 0: no force, use TV's
- * 1~n: use preset vsvdb 0~n-1
- * 255: use current vsvdb_data
- * update by module param vsvdb_data
- */
-static unsigned int force_vsvdb;
-static unsigned int vsvdb_size = 12;
-static unsigned char vsvdb_data[32] = {
- 0xeb, 0x01, 0x46, 0xd0, 0x00, 0x45, 0x0b, 0x90,
- 0x86, 0x60, 0x76, 0x8f, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-#define PRESET_VSVDB_COUNT 4
-static unsigned char tv_vsvdb[PRESET_VSVDB_COUNT][32] = {
- /* source-led */
- {
- 0xeb, 0x01, 0x46, 0xd0,
- 0x00, 0x45, 0x0b, 0x90,
- 0x86, 0x60, 0x76, 0x8f
- },
- /* sink-led */
- {
- 0xee, 0x01, 0x46, 0xd0,
- 0x00, 0x24, 0x0f, 0x8b,
- 0xa8, 0x53, 0x4b, 0x9d,
- 0x27, 0x0b, 0x00
- },
- /* sink-led & source-led */
- {
- 0xeb, 0x01, 0x46, 0xd0,
- 0x00, 0x44, 0x4f, 0x42,
- 0x8c, 0x46, 0x56, 0x8e
- },
- /* hdr10+ */
- {
- 0xe5, 0x01, 0x8b, 0x84,
- 0x90, 0x01
- }
-};
-
-module_param(force_vsvdb, uint, 0664);
-MODULE_PARM_DESC(force_vsvdb, "\n force_vsvdb\n");
-module_param_array(vsvdb_data, byte, &vsvdb_size, 0664);
-MODULE_PARM_DESC(vsvdb_data, "\n vsvdb data\n");
-
-/*
- * force_hdr
- * 0: no force, use TV's
- * 1~n: use preset drm 0~n-1
- * 255: use current drm_data
- * update by module param drm_data
- */
-static unsigned int force_hdr;
-static unsigned int drm_size = 4;
-static unsigned char drm_data[8] = {
- 0xe3, 0x06, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00
-};
-
-#define PRESET_DRM_COUNT 3
-static unsigned char tv_drm[PRESET_DRM_COUNT][32] = {
- /* hdr10 + hlg */
- {
- 0xe3, 0x06, 0x0d, 0x01
- },
- /* hdr10 */
- {
- 0xe3, 0x06, 0x05, 0x01
- },
- /* hlg */
- {
- 0xe3, 0x06, 0x09, 0x01
- }
-};
-
-module_param(force_hdr, uint, 0664);
-MODULE_PARM_DESC(force_hdr, "\n force_drm\n");
-module_param_array(drm_data, byte, &drm_size, 0664);
-MODULE_PARM_DESC(drm_data, "\n drm data\n");
-
static void hdmitx_edid_parse_ifdb(struct rx_cap *prxcap, u8 *blockbuf)
{
u8 payload_len;
@@ -1732,7 +1704,7 @@
prxcap->dsc_1p2 = 0;
if (prxcap->dsc_1p2) {
if (count < 13) {
- pr_info(EDID "error: dsc_1p2 support, but dsc not complete\n");
+ HDMITX_INFO("error: dsc_1p2 support, but dsc not complete\n");
prxcap->dsc_1p2 = 0;
return;
}
@@ -1871,14 +1843,87 @@
}
}
-static int hdmitx_edid_cta_block_parse(struct rx_cap *prxcap, u8 *block_buf)
+static int hdmitx_edid_audio_block_parse(struct rx_cap *prxcap, u8 *block_buf)
{
u8 offset, end;
u8 count;
u8 tag;
int i, tmp, idx;
+
+ if (!prxcap || !block_buf)
+ return -1;
+
+ /* CEA description */
+ end = block_buf[2];
+ /* Initialize SVD_VIC used for SVD storage in the video data block */
+ if (end > 127)
+ return 0;
+
+ /* this loop should be parsing when revision number is larger than 2 */
+ for (offset = 4 ; offset < end ; ) {
+ tag = block_buf[offset] >> 5;
+ count = block_buf[offset] & 0x1f;
+ switch (tag) {
+ case HDMI_EDID_BLOCK_TYPE_AUDIO:
+ tmp = count / 3;
+ idx = prxcap->AUD_count;
+ prxcap->AUD_count += tmp;
+ offset++;
+ for (i = 0; i < tmp; i++) {
+ prxcap->RxAudioCap[idx + i].audio_format_code =
+ (block_buf[offset + i * 3] >> 3) & 0xf;
+ prxcap->RxAudioCap[idx + i].channel_num_max =
+ block_buf[offset + i * 3] & 0x7;
+ prxcap->RxAudioCap[idx + i].freq_cc =
+ block_buf[offset + i * 3 + 1] & 0x7f;
+ prxcap->RxAudioCap[idx + i].cc3 =
+ block_buf[offset + i * 3 + 2];
+ }
+ offset += count;
+ break;
+ default:
+ offset++;
+ offset += count;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int hdmitx_audio_parse(struct rx_cap *prxcap, u8 *block_buf)
+{
+ int i;
+ unsigned char cta_block_count;
+ unsigned char edid_check = 0;
+
+ edid_check = prxcap->edid_check;
+ if (hdmitx_edid_check_data_valid(edid_check, block_buf) == false)
+ return 0;
+
+ cta_block_count = hdmitx_edid_get_cta_block_count(block_buf);
+ for (i = 1; i <= cta_block_count; i++) {
+ if (block_buf[i * 0x80] == 0x02 || edid_check & 0x01)
+ hdmitx_edid_audio_block_parse(prxcap, &block_buf[i * 0x80]);
+ }
+ /*
+ * CEA-861F 7.5.2 If only Basic Audio is supported,
+ * no Short Audio Descriptors are necessary.
+ */
+ if (!prxcap->AUD_count)
+ hdmitx_edid_set_default_aud(prxcap);
+ edid_check_pcm_declare(prxcap);
+
+ return 0;
+}
+
+static int hdmitx_edid_cta_block_parse(struct rx_cap *prxcap, u8 *block_buf)
+{
+ u8 offset, end;
+ u8 count;
+ u8 tag;
+ int i;
u8 *vfpdb_offset = NULL;
- u32 aud_flag = 0;
if (!prxcap || !block_buf)
return -1;
@@ -1913,25 +1958,6 @@
tag = block_buf[offset] >> 5;
count = block_buf[offset] & 0x1f;
switch (tag) {
- case HDMI_EDID_BLOCK_TYPE_AUDIO:
- aud_flag = 1;
- tmp = count / 3;
- idx = prxcap->AUD_count;
- prxcap->AUD_count += tmp;
- offset++;
- for (i = 0; i < tmp; i++) {
- prxcap->RxAudioCap[idx + i].audio_format_code =
- (block_buf[offset + i * 3] >> 3) & 0xf;
- prxcap->RxAudioCap[idx + i].channel_num_max =
- block_buf[offset + i * 3] & 0x7;
- prxcap->RxAudioCap[idx + i].freq_cc =
- block_buf[offset + i * 3 + 1] & 0x7f;
- prxcap->RxAudioCap[idx + i].cc3 =
- block_buf[offset + i * 3 + 2];
- }
- offset += count;
- break;
-
case HDMI_EDID_BLOCK_TYPE_VIDEO:
offset++;
for (i = 0; i < count ; i++) {
@@ -2049,30 +2075,12 @@
break;
default:
+ offset++;
+ offset += count;
break;
}
}
next:
- if (force_vsvdb) {
- if (force_vsvdb <= PRESET_VSVDB_COUNT) {
- vsvdb_size = (tv_vsvdb[force_vsvdb - 1][0] & 0x1f) + 1;
- memcpy(vsvdb_data, tv_vsvdb[force_vsvdb - 1],
- vsvdb_size);
- }
- edid_parsingvendspec(prxcap, vsvdb_data);
- }
- if (force_hdr) {
- if (force_hdr <= PRESET_DRM_COUNT) {
- drm_size = (tv_drm[force_hdr - 1][0] & 0x1f) + 1;
- memcpy(drm_data, tv_drm[force_hdr - 1],
- drm_size);
- }
- edid_parsedrmsb(prxcap, drm_data);
- }
-
- if (aud_flag == 0)
- hdmitx_edid_set_default_aud(prxcap);
-
edid_y420cmdb_postprocess(prxcap);
/* dtds in extended blocks */
@@ -2224,15 +2232,15 @@
return;
if (0) {
- pr_debug(EDID "%s[%d]\n", __func__, __LINE__);
- pr_debug(EDID "pixel_clock: %d\n", t->pixel_clock);
- pr_debug(EDID "h_active: %d\n", t->h_active);
- pr_debug(EDID "v_active: %d\n", t->v_active);
- pr_debug(EDID "v_blank: %d\n", t->v_blank);
- pr_debug(EDID "h_sync_offset: %d\n", t->h_sync_offset);
- pr_debug(EDID "h_sync: %d\n", t->h_sync);
- pr_debug(EDID "v_sync_offset: %d\n", t->v_sync_offset);
- pr_debug(EDID "v_sync: %d\n", t->v_sync);
+ HDMITX_DEBUG("%s[%d]\n", __func__, __LINE__);
+ HDMITX_DEBUG("pixel_clock: %d\n", t->pixel_clock);
+ HDMITX_DEBUG("h_active: %d\n", t->h_active);
+ HDMITX_DEBUG("v_active: %d\n", t->v_active);
+ HDMITX_DEBUG("v_blank: %d\n", t->v_blank);
+ HDMITX_DEBUG("h_sync_offset: %d\n", t->h_sync_offset);
+ HDMITX_DEBUG("h_sync: %d\n", t->h_sync);
+ HDMITX_DEBUG("v_sync_offset: %d\n", t->v_sync_offset);
+ HDMITX_DEBUG("v_sync: %d\n", t->v_sync);
}
}
@@ -2303,7 +2311,7 @@
}
/* Select dtd0 */
prxcap->preferred_mode = prxcap->dtd[0].vic;
- pr_debug(EDID "get dtd%d vic: %d\n",
+ HDMITX_DEBUG("get dtd%d vic: %d\n",
prxcap->dtd_idx, t->vic);
prxcap->dtd_idx++;
if (t->vic < HDMITX_VESA_OFFSET)
@@ -2389,7 +2397,7 @@
timing = hdmitx_mode_match_vesa_timing(t);
if (timing && (timing->vic < (HDMI_107_3840x2160p60_64x27 + 1))) {
prxcap->native_vic = timing->vic;
- pr_debug("hdmitx: get PMT vic: %d\n", timing->vic);
+ HDMITX_DEBUG("hdmitx: get PMT vic: %d\n", timing->vic);
}
if (timing && timing->vic >= HDMITX_VESA_OFFSET)
store_vesa_idx(prxcap, timing->vic);
@@ -2511,7 +2519,7 @@
/*
* both standard and LL are supported. 4k60 LL
* DV support should/can be determined using
- * video formats supported inthe E-EDID as flag
+ * video formats supported in the E-EDID as flag
* sup_2160p60hz might not be set.
*/
if ((dv->sup_2160p60hz ||
@@ -2567,7 +2575,6 @@
phyaddr->c = 0xf;
phyaddr->d = 0xf;
phyaddr->valid = 0;
- prxcap->physical_addr = 0xffff;
/* 165MHZ / 5 */
prxcap->Max_TMDS_Clock1 = DEFAULT_MAX_TMDS_CLK;
@@ -2610,6 +2617,10 @@
cta_block_count = hdmitx_edid_get_cta_block_count(EDID_buf);
+ /*
+ * only one block, need parse continue, at the end of parse, it will determine
+ * whether to use the default vic
+ */
if (cta_block_count == 0) {
HDMITX_INFO("EDID BlockCount=0\n");
/*
@@ -2631,7 +2642,6 @@
prxcap->ieeeoui = HDMI_IEEE_OUI;
if (zero_numbers > 120)
prxcap->ieeeoui = HDMI_IEEE_OUI;
- hdmitx_edid_set_default_vic(prxcap);
}
}
@@ -2701,7 +2711,7 @@
}
}
- pr_debug(EDID "EDID Parser:\n");
+ HDMITX_DEBUG("EDID Parser:\n");
if (hdmitx_edid_check_data_valid(edid_check, edid_buf) == false) {
edid_set_fallback_mode(prxcap);
@@ -2716,7 +2726,6 @@
hdmitx_edid_cta_block_parse(prxcap, &edid_buf[i * 0x80]);
}
- edid_check_pcm_declare(prxcap);
/*
* move parts that may contain cea timing parse behind
* VDB parse, so that to not affect VDB index which
@@ -2735,7 +2744,7 @@
if (!prxcap->flag_vfpdb &&
prxcap->preferred_mode != prxcap->VIC[0] &&
prxcap->number_of_dtd == 0) {
- pr_debug(EDID "change preferred_mode from %d to %d\n",
+ HDMITX_DEBUG("change preferred_mode from %d to %d\n",
prxcap->preferred_mode, prxcap->VIC[0]);
prxcap->preferred_mode = prxcap->VIC[0];
}
@@ -2777,10 +2786,10 @@
if (hdmitx_edid_search_IEEEOUI(&edid_buf[128])) {
prxcap->ieeeoui = HDMI_IEEE_OUI;
- pr_debug(EDID "find IEEEOUT\n");
+ HDMITX_DEBUG("find IEEEOUT\n");
} else {
prxcap->ieeeoui = 0x0;
- pr_debug(EDID "not find IEEEOUT\n");
+ HDMITX_DEBUG("not find IEEEOUT\n");
}
/* strictly DVI device judgement */
@@ -2788,22 +2797,13 @@
if (hdmitx_edid_check_data_valid(edid_check, &edid_buf[0]) &&
!hdmitx_edid_search_IEEEOUI(&edid_buf[128])) {
prxcap->ieeeoui = 0x0;
- pr_debug(EDID "sink is DVI device\n");
+ HDMITX_DEBUG("sink is DVI device\n");
} else {
prxcap->ieeeoui = HDMI_IEEE_OUI;
}
if (edid_zero_data(edid_buf))
prxcap->ieeeoui = HDMI_IEEE_OUI;
- if (!prxcap->AUD_count && !prxcap->ieeeoui)
- hdmitx_edid_set_default_aud(prxcap);
- /*
- * CEA-861F 7.5.2 If only Basic Audio is supported,
- * no Short Audio Descriptors are necessary.
- */
- if (!prxcap->AUD_count)
- hdmitx_edid_set_default_aud(prxcap);
-
update_edid_chksum(prxcap, edid_buf);
if (!hdmitx_edid_valid_block_num(&edid_buf[0])) {
@@ -2831,11 +2831,9 @@
if (edid_zero_data(edid_buf) || prxcap->VIC_count == 0)
hdmitx_edid_set_default_vic(prxcap);
- if (prxcap->ieeeoui != HDMI_IEEE_OUI)
- prxcap->physical_addr = 0xffff;
-
return 0;
}
+EXPORT_SYMBOL(hdmitx_edid_parse);
void hdmitx_edid_buffer_clear(u8 *edid_buf, int size)
{
@@ -2865,10 +2863,8 @@
prxcap->ieeeoui = HDMI_IEEE_OUI;
prxcap->edid_parsing = 0;
- hdmitx_edid_set_default_aud(prxcap);
rx_set_hdr_lumi(&tmp[0], 2);
/* rx_set_receiver_edid(&tmp[0], 2); */
- phy_addr_clear(&prxcap->vsdb_phy_addr);
}
/*
@@ -2888,7 +2884,7 @@
return;
memset(tmp_buf, 0, TMP_EDID_BUF_SIZE);
- HDMITX_INFO("edid: blk%d raw data\n", blk_idx);
+ HDMITX_DEBUG_EDID("edid: blk%d raw data\n", blk_idx);
for (i = 0, pos = 0; i < 128; i++) {
pos += sprintf(tmp_buf + pos, "%02x", blk[i]);
/* print 64 bytes a line */
@@ -2917,9 +2913,9 @@
if (tmp_chksum != 0) {
valid_blk_no++;
if ((tmp_chksum & 0xff) == 0)
- pr_debug(EDID "check sum valid\n");
+ HDMITX_DEBUG("check sum valid\n");
else
- pr_warn(EDID "check sum invalid\n");
+ HDMITX_ERROR("check sum invalid\n");
}
tmp_chksum = 0;
}
@@ -2945,7 +2941,7 @@
valid_blk_no = hdmitx_edid_valid_block_num(edid_buf);
if (valid_blk_no == 0) {
- pr_debug(EDID "raw data are all zeroes\n");
+ HDMITX_DEBUG("raw data are all zeroes\n");
} else {
for (blk_idx = 0; blk_idx < valid_blk_no; blk_idx++)
hdmitx_edid_blk_print(&edid_buf[blk_idx * 128], blk_idx);
@@ -2988,6 +2984,7 @@
* pos += snprintf(buffer + pos, buffer_len - pos,
* "EDID block number: 0x%x\n", tx_comm->EDID_buf[0x7e]);
*/
+
pos += snprintf(buffer + pos, buffer_len - pos,
"Source Physical Address[a.b.c.d]: %x.%x.%x.%x\n",
prxcap->vsdb_phy_addr.a,
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_config.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_config.c
index 7487e26..290f172 100644
--- a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_config.c
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_config.c
@@ -756,11 +756,11 @@
((*(p + LCD_UKEY_LDIM_DEV_IF_FREQ + 3)) << 24));
dev_drv->spi_info.mode = *(p + LCD_UKEY_LDIM_DEV_IF_ATTR_2);
dev_drv->cs_hold_delay =
- (*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_3) |
- ((*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_3 + 1)) << 8));
- dev_drv->cs_clk_delay =
(*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_4) |
((*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_4 + 1)) << 8));
+ dev_drv->cs_clk_delay =
+ (*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_5) |
+ ((*(p + LCD_UKEY_LDIM_DEV_IF_ATTR_5 + 1)) << 8));
if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
LDIMPR("spi bus_num: %d, chip_select: %d, max_speed_hz: %d\n",
dev_drv->spi_info.bus_num, dev_drv->spi_info.chip_select,
@@ -1127,38 +1127,40 @@
dev_drv->cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC;
str = json_get_obj_str(jsp, child, "init_on", NULL);
- nums_size = (strlen(str)) * sizeof(unsigned int);
- nums = malloc(nums_size);
- if (!nums) {
- LDIMPR("ldim find init_on: no memory to save nums\n");
- goto parse_ldim_init_off;
- }
+ if (str) {
+ nums_size = (strlen(str)) * sizeof(unsigned int);
+ nums = malloc(nums_size);
+ if (!nums) {
+ LDIMPR("ldim find init_on: no memory to save nums\n");
+ goto parse_ldim_init_off;
+ }
- memset(nums, 0, nums_size);
- cnt = string_to_numbers(str, nums);
- ldim_dev_init_dynamic_load_array(dev_drv, nums, cnt, 1);
-
-parse_ldim_init_off:
- if (nums)
+ memset(nums, 0, nums_size);
+ cnt = string_to_numbers(str, nums);
+ ldim_dev_init_dynamic_load_array(dev_drv, nums, cnt, 1);
free(nums);
- str = json_get_obj_str(jsp, child, "init_off", NULL);
- nums_size = (strlen(str)) * sizeof(unsigned int);
- nums = malloc(nums_size);
- if (!nums) {
- LDIMPR("ldim find init_on: no memory to save nums\n");
- goto ldim_dev_get_config_from_json_end;
+ nums = NULL;
}
+parse_ldim_init_off:
+ str = json_get_obj_str(jsp, child, "init_off", NULL);
+ if (str) {
+ nums_size = (strlen(str)) * sizeof(unsigned int);
+ nums = malloc(nums_size);
+ if (!nums) {
+ LDIMPR("ldim find init_on: no memory to save nums\n");
+ goto ldim_dev_get_config_from_json_end;
+ }
- memset(nums, 0, nums_size);
- cnt = string_to_numbers(str, nums);
- ldim_dev_init_dynamic_load_array(dev_drv, nums, cnt, 0);
-
+ memset(nums, 0, nums_size);
+ cnt = string_to_numbers(str, nums);
+ ldim_dev_init_dynamic_load_array(dev_drv, nums, cnt, 0);
+ free(nums);
+ nums = NULL;
+ }
dev_drv->init_loaded = 1;
}
ldim_dev_get_config_from_json_end:
- if (nums)
- free(nums);
return ret;
}
diff --git a/drivers/amlogic/media/vout/lcd/backlight/lcd_bl_config.c b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl_config.c
index 6271edc..4809c7b 100644
--- a/drivers/amlogic/media/vout/lcd/backlight/lcd_bl_config.c
+++ b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl_config.c
@@ -1422,7 +1422,7 @@
{
#ifdef CONFIG_OF_LIBFDT
int parent_offset;
- char str[10];
+ char str[16];
char *propdata;
if (index == 0)
diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.c b/drivers/amlogic/media/vout/lcd/lcd_common.c
index 5c7bad7..76d60a9 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_common.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_common.c
@@ -63,21 +63,19 @@
int item_ind = 0, i = 0;
char *token = NULL;
char *tmp_buf = NULL;
- int str_len = strlen(str);
+ int str_len;
- if (!str) {
- printf("%s : null str\n", __func__);
+ if (!str)
return 0;
- }
- tmp_buf = (char *)malloc(str_len + 1);
- if (!tmp_buf) {
- printf("%s, malloc buffer memory error!!!\n", __func__);
- return -1;
- }
+ str_len = strlen(str);
+ tmp_buf = (char *)malloc(str_len + 2);
+ if (!tmp_buf)
+ return 0;
strcpy(tmp_buf, str);
tmp_buf[str_len] = '\0';
+ tmp_buf[str_len + 1] = '\0';
token = tmp_buf;
while (i <= str_len) {
if (tmp_buf[i] == ',' || i == str_len) {
diff --git a/drivers/amlogic/media/vout/lcd/lcd_config.c b/drivers/amlogic/media/vout/lcd/lcd_config.c
index 8e81815..e6e18ea 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_config.c
@@ -1199,6 +1199,7 @@
pctrl->mipi_cfg.operation_mode_display = be32_to_cpup((((u32 *)propdata) + 4));
pctrl->mipi_cfg.video_mode_type = be32_to_cpup((((u32 *)propdata) + 5));
pctrl->mipi_cfg.clk_always_hs = be32_to_cpup((((u32 *)propdata) + 6));
+ pctrl->mipi_cfg.user_pkt_size = be32_to_cpup((((u32 *)propdata) + 7));
pctrl->mipi_cfg.check_en = 0;
pctrl->mipi_cfg.check_reg = 0xff;
@@ -2426,12 +2427,14 @@
dt->cfmt = CFMT_RGB_8bit;
bits = json_get_obj_u32(jsp, child, "lcd_bits", 8);
str = json_get_obj_str(jsp, child, "color_fmt", NULL);
- if (strcmp(str, "RGB565"))
- snprintf(strtmp, 63, "%s_%dbit", str, bits);
- else
- snprintf(strtmp, 63, "%s", str);
+ if (str) {
+ if (strcmp(str, "RGB565"))
+ snprintf(strtmp, 63, "%s_%dbit", str, bits);
+ else
+ snprintf(strtmp, 63, "%s", str);
- panel_str2fmt(strtmp, &dt->cfmt, &dt->lcd_bits);
+ panel_str2fmt(strtmp, &dt->cfmt, &dt->lcd_bits);
+ }
str = json_get_obj_str(jsp, child, "mode_switch_type", NULL);
dt->switch_type = strnum_get_num(str, vmode_switch_name,
ARRAY_SIZE(vmode_switch_name),
@@ -2762,6 +2765,9 @@
{
int i = 0;
+ if (!name)
+ return LCD_CPU_GPIO_NUM_MAX;
+
for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++)
if (!strcmp(pdrv->config.power.cpu_gpio[i], name))
return i;
@@ -2784,7 +2790,7 @@
return -1;
}
- cnt = lcd_s32_constraint(cnt, 0, LCD_PWR_STEP_MAX);
+ cnt = lcd_s32_constraint(cnt, 0, LCD_PWR_STEP_MAX - 1);
for (i = 0; i < cnt; i++) {
child = json_get_array_child(jsp, parent, i);
if (!child)
@@ -2838,7 +2844,7 @@
return -1;
}
- cnt = lcd_s32_constraint(cnt, 0, LCD_PWR_STEP_MAX);
+ cnt = lcd_s32_constraint(cnt, 0, LCD_PWR_STEP_MAX - 1);
for (i = 0; i < cnt; i++) {
child = json_get_array_child(jsp, parent, i);
if (!child)
@@ -3080,7 +3086,7 @@
static unsigned int lcd_dt_valid(char *dt_addr, int index)
{
int parent_offset, ret = 0;
- char str[10];
+ char str[16];
char *propdata;
if (index == 0)
diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c
index daf7081..b0bc81d 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_debug.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c
@@ -520,6 +520,9 @@
{MIPI_DSI_DWC_LPCLK_CTRL_OS, "DWC_LPCLK_CTRL_OS"},
{MIPI_DSI_DWC_CMD_MODE_CFG_OS, "DWC_CMD_MODE_CFG_OS"},
{MIPI_DSI_DWC_VID_MODE_CFG_OS, "DWC_VID_MODE_CFG_OS"},
+ {MIPI_DSI_DWC_VID_PKT_SIZE_OS, "DWC_VID_PKT_SIZE_OS"},
+ {MIPI_DSI_DWC_VID_NUM_CHUNKS_OS, "DWC_VID_NUM_CHUNKS_OS"},
+ {MIPI_DSI_DWC_VID_NULL_SIZE_OS, "DWC_VID_NULL_SIZE_OS"},
{MIPI_DSI_DWC_MODE_CFG_OS, "DWC_MODE_CFG_OS"},
{MIPI_DSI_DWC_PHY_STATUS_OS, "DWC_PHY_STATUS_OS"},
{MIPI_DSI_DWC_INT_ST0_OS, "DWC_INT_ST0_OS"},
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern_config.c b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern_config.c
index 340c398..af8f7f4 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern_config.c
@@ -1261,13 +1261,15 @@
return -1;
}
parent = json_get_array_child(jsp, parent, edev->dev_index);
- if (!parent)
+ if (!parent) {
EXTERR("find /lcd_ext_dev[%d]\n", edev->dev_index);
+ return -1;
+ }
cfg = &edev->config;
cfg->index = edev->dev_index;
str = json_get_obj_str(jsp, parent, "name", "ext_default");
- strcpy(cfg->name, str ? str : "ext_default");
+ strlcpy(cfg->name, str ? str : "ext_default", LCD_EXTERN_NAME_LEN_MAX);
str = json_get_obj_str(jsp, parent, "type", NULL);
cfg->type = strnum_get_num(str, ext_type_name, ARRAY_SIZE(ext_type_name), LCD_EXTERN_MAX);
cfg->status = json_get_obj_u32(jsp, parent, "status", 0);
@@ -1444,7 +1446,7 @@
{
#ifdef CONFIG_OF_LIBFDT
int parent_offset;
- char str[10];
+ char str[16];
char *propdata;
if (index == 0)
diff --git a/drivers/amlogic/media/vout/lcd/lcd_parser/json_parse.h b/drivers/amlogic/media/vout/lcd/lcd_parser/json_parse.h
index 117c23d..b71feea 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_parser/json_parse.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_parser/json_parse.h
@@ -189,27 +189,27 @@
/*=json util=====================================================================================*/
static inline int __json_is_string(struct json_s *json)
{
- return (json->type == JSON_STRING);
+ return (json && json->type == JSON_STRING);
}
static inline int __json_is_number(struct json_s *json)
{
- return (json->type == JSON_NUMBER);
+ return (json && json->type == JSON_NUMBER);
}
static inline int __json_is_string_or_number(struct json_s *json)
{
- return ((json->type == JSON_STRING) || (json->type == JSON_NUMBER));
+ return (json && ((json->type == JSON_STRING) || (json->type == JSON_NUMBER)));
}
static inline int __json_is_object(struct json_s *json)
{
- return (json->type == JSON_OBJECT);
+ return (json && json->type == JSON_OBJECT);
}
static inline int __json_is_array(struct json_s *json)
{
- return (json->type == JSON_ARRAY);
+ return (json && json->type == JSON_ARRAY);
}
void json_obj_dump(char *js, struct json_s *json_array, struct json_s *json, s32 indent);
diff --git a/drivers/amlogic/media/vout/lcd/lcd_phy/lcd_phy_t6d.c b/drivers/amlogic/media/vout/lcd/lcd_phy/lcd_phy_t6d.c
index 0b56fb4..01fe7a9 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_phy/lcd_phy_t6d.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_phy/lcd_phy_t6d.c
@@ -227,8 +227,10 @@
if (phy_cfg->lane_valid & (1 << i)) {
bit = i & 0x1 ? 16 : 0;
chreg = reg_data;
- chdig = 1 << 10 |
- (is_mlvds ? 0xf : 0) << 2; //pn swap;
+ if (is_mlvds)
+ chdig = 0xf << 2; //pn swap
+ else
+ chdig = 1 << 10; //clk inv
if (status) {
chdig |= 1 << 15;
chreg |= (phy->lane[i].preem & 0xf) << 12;
@@ -253,6 +255,24 @@
}
}
+static void lcd_phy_init_off(void)
+{
+ int i;
+
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL14, 0x1300d100);
+ if (phy_ctrl_bit_on)
+ lcd_ana_setb(ANACTRL_DIF_PHY_CNTL15, 0x10, 16, 8);
+ else
+ lcd_ana_setb(ANACTRL_DIF_PHY_CNTL15, 0x90, 16, 8);
+
+ for (i = 0; i < 5; i++) {
+ lcd_ana_write(chreg_reg[i], 0);
+ lcd_ana_write(chdig_reg[i], 0);
+ }
+
+ LCDPR("%s done\n", __func__);
+}
+
static void lcd_lvds_phy_set(struct aml_lcd_drv_s *pdrv, int status)
{
unsigned int cntl14 = 0;
@@ -366,6 +386,8 @@
cali_bias = lcd_phy_get_def_bias();
phy_ctrl_bit_on = (pdata->rev_type > 0xa) ? 1 : 0;
+ lcd_phy_init_off();
+
return &lcd_phy_ctrl_t6d;
}
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_common.h b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_common.h
index faf1089..a528036 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_common.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_common.h
@@ -155,9 +155,9 @@
/* **** DPHY timing parameter Value (unit: 0.01ns) **** */
/* >100ns (4M) */
-#define DPHY_TIME_LP_TESC(ui) (250 * 100)
+#define DPHY_TIME_LP_TESC(ui) (120 * 100)
/* >50ns */
-#define DPHY_TIME_LP_LPX(ui) (100 * 100)
+#define DPHY_TIME_LP_LPX(ui) (60 * 100)
/* (lpx, 2*lpx) */
#define DPHY_TIME_LP_TA_SURE(ui) DPHY_TIME_LP_LPX(ui)
/* 4*lpx */
@@ -230,7 +230,4 @@
#define DSI_RD_MAX 4
-#define MIPI_DSI_COLOR_18BIT COLOR_18BIT_CFG_2//COLOR_18BIT_CFG_1
-#define MIPI_DSI_COLOR_24BIT COLOR_24BIT
-
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.c
index 633c42a..5931182 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.c
@@ -27,13 +27,11 @@
return;
pr_info("MIPI DSI NON-BURST setting:\n"
- " multi_pkt_en: %d\n"
- " vid_num_chunks: %d\n"
- " pixel_per_chunk: %d\n"
- " byte_per_chunk: %d\n"
- " vid_null_size: %d\n\n",
- pconf->control.mipi_cfg.multi_pkt_en, pconf->control.mipi_cfg.vid_num_chunks,
- pconf->control.mipi_cfg.pixel_per_chunk, pconf->control.mipi_cfg.byte_per_chunk,
+ " vid_num_chunks: %d\n"
+ " vid_pkt_size: %d\n"
+ " vid_null_size: %d\n\n",
+ pconf->control.mipi_cfg.vid_num_chunks,
+ pconf->control.mipi_cfg.vid_pkt_size,
pconf->control.mipi_cfg.vid_null_size);
}
@@ -249,7 +247,7 @@
{
u32 dpi_data_format, venc_data_width;
u32 lane_num, vid_mode_type;
- u32 h_act, v_act, v_sync, v_bp, v_fp;
+ u32 v_act, v_sync, v_bp, v_fp;
u32 temp;
struct dsi_config_s *dconf;
@@ -258,7 +256,6 @@
dpi_data_format = dconf->dpi_data_format;
lane_num = (u32)(dconf->lane_num);
vid_mode_type = (u32)(dconf->video_mode_type);
- h_act = pdrv->config.timing.act_timing.h_active;
v_act = pdrv->config.timing.act_timing.v_active;
v_sync = pdrv->config.timing.act_timing.vsync_width;
v_bp = pdrv->config.timing.act_timing.vsync_bp;
@@ -280,7 +277,7 @@
dsi_host_write(pdrv, MIPI_DSI_DWC_DPI_VCID_OS, vcid);
/* 2.2, Configure Color format */
dsi_host_write(pdrv, MIPI_DSI_DWC_DPI_COLOR_CODING_OS,
- (((dpi_data_format == COLOR_18BIT_CFG_2) ? 1 : 0) << BIT_LOOSELY18_EN) |
+ (((dpi_data_format == DSI_DPI_COLOR_18BIT_CFG_2) ? 1 : 0) << BIT_LOOSELY18_EN) |
(dpi_data_format << BIT_DPI_COLOR_CODING));
/* 2.2.1 Configure Set color format for DPI register */
temp = (dsi_host_read(pdrv, MIPI_DSI_TOP_CNTL) &
@@ -303,27 +300,25 @@
if (operation_mode == OPERATION_VIDEO_MODE) {
/* 3.1 Configure Low power and video mode type settings */
dsi_host_write(pdrv, MIPI_DSI_DWC_VID_MODE_CFG_OS,
- // (1 << BIT_LP_CMD_EN) |
+ (1 << BIT_LP_CMD_EN) |
(0 << BIT_FRAME_BTA_ACK_EN) | /* enable BTA after one frame, need check */
- (1 << BIT_LP_HFP_EN) | /* enable lp */
- (1 << BIT_LP_HBP_EN) | /* enable lp */
+ // (1 << BIT_LP_HFP_EN) | /* enable lp */
+ // (1 << BIT_LP_HBP_EN) | /* enable lp */
+ (0 << BIT_LP_HFP_EN) | /* enable lp */
+ (0 << BIT_LP_HBP_EN) | /* enable lp */
(1 << BIT_LP_VACT_EN) | /* enable lp */
(1 << BIT_LP_VFP_EN) | /* enable lp */
(1 << BIT_LP_VBP_EN) | /* enable lp */
(1 << BIT_LP_VSA_EN) | /* enable lp */
- (vid_mode_type << BIT_VID_MODE_TYPE)); /* burst non burst mode */
+ (vid_mode_type << BIT_VID_MODE_TYPE)); /* burst/non-burst mode */
/* [23:16]outvact, [7:0]invact */
- dsi_host_write(pdrv, MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS, (4 << 16) | (4 << 0));
+ dsi_host_write(pdrv, MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS, (8 << 16) | (0 << 0));
/* 3.2 Configure video packet size settings */
/* 3.3 Configure number of chunks and null packet size for one line */
- if (vid_mode_type == BURST_MODE) {
- dsi_host_write(pdrv, MIPI_DSI_DWC_VID_PKT_SIZE_OS, h_act);
- } else { // NON_BURST_SYNC_PULSE || NON_BURST_SYNC_EVENT
- dsi_host_write(pdrv, MIPI_DSI_DWC_VID_PKT_SIZE_OS, dconf->pixel_per_chunk);
- dsi_host_write(pdrv, MIPI_DSI_DWC_VID_NUM_CHUNKS_OS, dconf->vid_num_chunks);
- dsi_host_write(pdrv, MIPI_DSI_DWC_VID_NULL_SIZE_OS, dconf->vid_null_size);
- }
+ dsi_host_write(pdrv, MIPI_DSI_DWC_VID_PKT_SIZE_OS, dconf->vid_pkt_size);
+ dsi_host_write(pdrv, MIPI_DSI_DWC_VID_NUM_CHUNKS_OS, dconf->vid_num_chunks);
+ dsi_host_write(pdrv, MIPI_DSI_DWC_VID_NULL_SIZE_OS, dconf->vid_null_size);
/* 4 Configure the video relative parameters according to the output type */
/* include horizontal timing and vertical line */
@@ -652,112 +647,9 @@
mdelay(20); /* wait for vsync trigger */
}
-static void mipi_dsi_non_burst_packet_config(struct lcd_config_s *pconf)
-{
- struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
- u32 lane_num, hactive, multi_pkt_en;
- u64 bit_rate_required;
- u32 pixel_per_chunk = 0, vid_num_chunks = 0;
- u32 byte_per_chunk = 0, vid_pkt_byte_per_chunk = 0;
- u32 total_bytes_per_chunk = 0;
- u32 chunk_overhead = 0, vid_null_size = 0;
- int i, done = 0;
-
- lane_num = (int)(dconf->lane_num);
- hactive = pconf->timing.act_timing.h_active;
- bit_rate_required = pconf->timing.act_timing.pixel_clk;
- bit_rate_required = bit_rate_required * pconf->timing.act_timing.lcd_bits;
- bit_rate_required = lcd_do_div(bit_rate_required, lane_num);
- if (pconf->timing.bit_rate > bit_rate_required)
- multi_pkt_en = 1;
- else
- multi_pkt_en = 0;
- if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
- LCDPR("non-burst: bit_rate_required=%lld, bit_rate=%lld, multi_pkt_en=%d\n",
- bit_rate_required, pconf->timing.bit_rate, multi_pkt_en);
- }
-
- if (multi_pkt_en == 0) {
- pixel_per_chunk = hactive;
- if (dconf->dpi_data_format == COLOR_18BIT_CFG_1) {
- /* 18bit (4*18/8=9byte) */
- byte_per_chunk = pixel_per_chunk * (9 / 4);
- } else {
- /* 24bit or 18bit-loosely */
- byte_per_chunk = pixel_per_chunk * 3;
- }
- vid_pkt_byte_per_chunk = 4 + byte_per_chunk + 2;
- total_bytes_per_chunk = lane_num * pixel_per_chunk * dconf->factor_denominator;
- total_bytes_per_chunk = total_bytes_per_chunk / (8 * dconf->factor_numerator);
-
- vid_num_chunks = 0;
- vid_null_size = 0;
- } else {
- i = 2;
- while ((i < hactive) && (done == 0)) {
- vid_num_chunks = i;
- pixel_per_chunk = hactive / vid_num_chunks;
-
- if (dconf->dpi_data_format == COLOR_18BIT_CFG_1) {
- if ((pixel_per_chunk % 4) > 0)
- continue;
- /* 18bit (4*18/8=9byte) */
- byte_per_chunk = pixel_per_chunk * (9 / 4);
- } else {
- /* 24bit or 18bit-loosely */
- byte_per_chunk = pixel_per_chunk * 3;
- }
- vid_pkt_byte_per_chunk = 4 + byte_per_chunk + 2;
- total_bytes_per_chunk = lane_num * pixel_per_chunk *
- dconf->factor_denominator;
- total_bytes_per_chunk = total_bytes_per_chunk /
- (8 * dconf->factor_numerator);
-
- chunk_overhead = total_bytes_per_chunk - vid_pkt_byte_per_chunk;
- if (chunk_overhead >= 12) {
- vid_null_size = chunk_overhead - 12;
- done = 1;
- } else if (chunk_overhead >= 6) {
- vid_null_size = 0;
- done = 1;
- }
- i += 2;
- }
- if (done == 0) {
- LCDERR("Packet no room for chunk_overhead\n");
- //pixel_per_chunk = hactive;
- //vid_num_chunks = 0;
- //vid_null_size = 0;
- }
- }
-
- dconf->pixel_per_chunk = pixel_per_chunk;
- dconf->vid_num_chunks = vid_num_chunks;
- dconf->vid_null_size = vid_null_size;
- dconf->byte_per_chunk = byte_per_chunk;
- dconf->multi_pkt_en = multi_pkt_en;
-
- if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
- LCDPR("MIPI DSI NON-BURST setting:\n"
- " multi_pkt_en = %d\n"
- " vid_num_chunks = %d\n"
- " pixel_per_chunk = %d\n"
- " byte_per_chunk = %d\n"
- " vid_pkt_byte_per_chunk = %d\n"
- " total_bytes_per_chunk = %d\n"
- " chunk_overhead = %d\n"
- " vid_null_size = %d\n\n",
- multi_pkt_en, vid_num_chunks,
- pixel_per_chunk, byte_per_chunk,
- vid_pkt_byte_per_chunk, total_bytes_per_chunk,
- chunk_overhead, vid_null_size);
- }
-}
-
-static void mipi_dsi_vid_mode_config(struct lcd_config_s *pconf)
+static void mipi_dsi_burst_packet_config(struct lcd_config_s *pconf)
{
u64 h_period, hs_width, hs_bp;
- u16 vfp;
u32 den, num;
struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
@@ -771,10 +663,117 @@
dconf->hsa = (u16)div_around(hs_width * num, den);
dconf->hbp = (u16)div_around(hs_bp * num, den);
- vfp = pconf->timing.act_timing.v_period
- - pconf->timing.act_timing.vsync_width
- - pconf->timing.act_timing.vsync_bp
- - pconf->timing.act_timing.v_active;
+ dconf->vid_pkt_size = pconf->timing.act_timing.h_active;
+ dconf->vid_num_chunks = 0;
+ dconf->vid_null_size = 0;
+}
+
+static void mipi_dsi_non_burst_packet_config(struct lcd_config_s *pconf)
+{
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
+ u32 lane_num, hactive, multi_pkt_en;
+ u64 bit_rate_required;
+ u32 vid_num_chunks = 0, vid_pkt_size = 0;
+ u64 total_bytes_per_chunk = 0, vid_byte_per_chunk = 0;
+ u32 chunk_overhead = 0, vid_null_size = 0;
+ u64 h_period, hs_width, hs_bp;
+ u32 byte_pixel = 0, temp;
+ u32 den, num, i;
+
+ h_period = pconf->timing.act_timing.h_period;
+ hs_width = pconf->timing.act_timing.hsync_width;
+ hs_bp = pconf->timing.act_timing.hsync_bp;
+ den = pconf->control.mipi_cfg.factor_denominator;
+ num = pconf->control.mipi_cfg.factor_numerator;
+
+ hactive = pconf->timing.act_timing.h_active;
+
+ lane_num = dconf->lane_num;
+ bit_rate_required = pconf->timing.act_timing.pixel_clk;
+ bit_rate_required = bit_rate_required * pconf->timing.act_timing.lcd_bits; //18/24/30
+ bit_rate_required = div_around(bit_rate_required, lane_num);
+
+ if (pconf->timing.bit_rate > bit_rate_required) {
+ multi_pkt_en = 1;
+
+ switch (dconf->dpi_data_format) {
+ case DSI_DPI_COLOR_18BIT_CFG_1:
+ case DSI_DPI_COLOR_24BIT:
+ //bpc = 3
+ byte_pixel = 3;
+ break;
+ case DSI_DPI_COLOR_30BIT:
+ //bpc = 4
+ byte_pixel = 4;
+ break;
+ case DSI_DPI_COLOR_18BIT_CFG_2:
+ default:
+ byte_pixel = 3;
+ break;
+
+ }
+
+ i = dconf->user_pkt_size ? dconf->user_pkt_size : 1;
+ for (; i < hactive; i++) { //i == vid_pkt_size
+ if (i % (den / 8))
+ continue;
+ if (hactive % i)
+ continue;
+ temp = (num * lane_num - den * byte_pixel) * (i / (den / 8));
+ if ((temp % 8 == 0) && temp > 48)
+ break;
+ }
+ vid_pkt_size = i;
+ vid_num_chunks = (hactive + vid_pkt_size - 1) / vid_pkt_size;
+
+ vid_byte_per_chunk = vid_pkt_size * byte_pixel;
+ total_bytes_per_chunk = (num * lane_num * (vid_pkt_size / (den / 8))) / 8;
+ chunk_overhead = total_bytes_per_chunk - vid_byte_per_chunk;
+ if (chunk_overhead >= 12) {
+ vid_null_size = chunk_overhead - 12; //null_packet_overhead = 12
+ } else if (chunk_overhead >= 6) { //chunk: header=4, CRC=2
+ vid_null_size = 0;
+ } else { //should larger vid_pkt_size
+ vid_null_size = 0;
+ LCDERR("%s: wrong vid_pkt_size(overhead=%d)\n", __func__, chunk_overhead);
+ }
+ } else {
+ multi_pkt_en = 0;
+ vid_pkt_size = hactive;
+ vid_null_size = 0;
+ vid_num_chunks = 0;
+ }
+
+ dconf->hline = (u16)div_around(h_period * num, den);
+ dconf->hsa = (u16)div_around(hs_width * num, den);
+ dconf->hbp = (u16)div_around(hs_bp * num, den);
+
+ dconf->vid_num_chunks = vid_num_chunks;
+ dconf->vid_null_size = vid_null_size;
+ dconf->vid_pkt_size = vid_pkt_size;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("MIPI DSI NON-BURST setting:\n"
+ " multi_pkt_en = %d\n"
+ " chunks_num = %d\n"
+ " chunks[%lld] = vid_byte[%lld](byte_pix[%d] * vid_pkt_size[%d]) +"
+ " overhead[%d](vid_null_size[%d])\n",
+ multi_pkt_en,
+ vid_num_chunks,
+ total_bytes_per_chunk, vid_byte_per_chunk, byte_pixel, vid_pkt_size,
+ chunk_overhead, vid_null_size);
+ }
+}
+
+static void mipi_dsi_vid_mode_config(struct lcd_config_s *pconf)
+{
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
+
+ if (pconf->control.mipi_cfg.video_mode_type == BURST_MODE) {
+ mipi_dsi_burst_packet_config(pconf);
+ } else {
+ mipi_dsi_non_burst_packet_config(pconf);
+ }
if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("MIPI DSI video timing:\n"
@@ -788,15 +787,8 @@
dconf->hline, dconf->hsa, dconf->hbp,
pconf->timing.act_timing.vsync_width,
pconf->timing.act_timing.vsync_bp,
- vfp, pconf->timing.act_timing.v_active);
- }
-
- if (pconf->control.mipi_cfg.video_mode_type == BURST_MODE) {
- dconf->pixel_per_chunk = pconf->timing.act_timing.h_active;
- dconf->vid_num_chunks = 0;
- dconf->vid_null_size = 0;
- } else {
- mipi_dsi_non_burst_packet_config(pconf);
+ pconf->timing.act_timing.vsync_fp,
+ pconf->timing.act_timing.v_active);
}
}
@@ -980,10 +972,13 @@
if (pdrv->config.timing.base_timing->lcd_bits == 18) {
dconf->venc_data_width = MIPI_DSI_VENC_COLOR_18B;
- dconf->dpi_data_format = MIPI_DSI_COLOR_18BIT;
- } else {
+ dconf->dpi_data_format = DSI_DPI_COLOR_18BIT_CFG_1;
+ } else if (pdrv->config.timing.base_timing->lcd_bits == 24) {
dconf->venc_data_width = MIPI_DSI_VENC_COLOR_24B;
- dconf->dpi_data_format = MIPI_DSI_COLOR_24BIT;
+ dconf->dpi_data_format = DSI_DPI_COLOR_24BIT;
+ } else if (pdrv->config.timing.base_timing->lcd_bits == 30) {
+ dconf->venc_data_width = MIPI_DSI_VENC_COLOR_30B;
+ dconf->dpi_data_format = DSI_DPI_COLOR_30BIT;
}
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.h b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.h
index ea6c71d..89e90d6 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/MIPI_DSI/dsi_ctrl/dsi_ctrl_v1.h
@@ -12,21 +12,21 @@
#define MIPI_DSI_VENC_COLOR_18B 0x2
#define MIPI_DSI_VENC_COLOR_16B 0x3
-#define COLOR_16BIT_CFG_1 0x0
-#define COLOR_16BIT_CFG_2 0x1
-#define COLOR_16BIT_CFG_3 0x2
-#define COLOR_18BIT_CFG_1 0x3
-#define COLOR_18BIT_CFG_2 0x4
-#define COLOR_24BIT 0x5
-#define COLOR_20BIT_LOOSE 0x6
-#define COLOR_24_BIT_YCBCR 0x7
-#define COLOR_16BIT_YCBCR 0x8
-#define COLOR_30BIT 0x9
-#define COLOR_36BIT 0xa
-#define COLOR_12BIT 0xb
-#define COLOR_RGB_111 0xc
-#define COLOR_RGB_332 0xd
-#define COLOR_RGB_444 0xe
+#define DSI_DPI_COLOR_16BIT_CFG_1 0x0
+#define DSI_DPI_COLOR_16BIT_CFG_2 0x1
+#define DSI_DPI_COLOR_16BIT_CFG_3 0x2
+#define DSI_DPI_COLOR_18BIT_CFG_1 0x3
+#define DSI_DPI_COLOR_18BIT_CFG_2 0x4
+#define DSI_DPI_COLOR_24BIT 0x5
+#define DSI_DPI_COLOR_20BIT_LOOSE 0x6
+#define DSI_DPI_COLOR_24_BIT_YCBCR 0x7
+#define DSI_DPI_COLOR_16BIT_YCBCR 0x8
+#define DSI_DPI_COLOR_30BIT 0x9
+#define DSI_DPI_COLOR_36BIT 0xa
+#define DSI_DPI_COLOR_12BIT 0xb
+#define DSI_DPI_COLOR_RGB_111 0xc
+#define DSI_DPI_COLOR_RGB_332 0xd
+#define DSI_DPI_COLOR_RGB_444 0xe
/* MIPI DSI Relative REGISTERs Definitions */
/* For MIPI_DSI_TOP_CNTL */
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.c b/drivers/amlogic/media/vout/lcd/lcd_tcon.c
index 137eeed..8599a0f 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tcon.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.c
@@ -1672,6 +1672,11 @@
{ TCON_AXI_MEM_TYPE_DEMURA, 0x00100000, 0x19b, 0 }, /* 1M */
};
+static struct lcd_tcon_axi_mem_cfg_s axi_mem_cfg_tbl_t6d[] = {
+ { TCON_AXI_MEM_TYPE_OD, 0x00200000, 0x261, 0 }, /* 2M */
+ { TCON_AXI_MEM_TYPE_DEMURA, 0x00100000, 0x19b, 0 }, /* 1M */
+};
+
static struct lcd_tcon_dma_ops_s lcd_tcon_dma_ops_t5m = {
.status = 0,
.addr_list = NULL,
@@ -1858,8 +1863,8 @@
.axi_bank = LCD_TCON_AXI_BANK_T6D,
- .rsv_mem_size = 0x00502840,
- .axi_size = 0x00500000, /* 5M*/
+ .rsv_mem_size = 0x00302840,
+ .axi_size = 0x00300000, /* 3M*/
.bin_path_size = 0x00002800, /* 10K */
.secure_cfg_size = 0x00000040, /* 64byte */
.vac_size = 0,
@@ -1867,8 +1872,8 @@
.demura_lut_size = 0,
.acc_lut_size = 0,
- .axi_tbl_len = ARRAY_SIZE(axi_mem_cfg_tbl_txhd2),
- .axi_mem_cfg_tbl = axi_mem_cfg_tbl_txhd2,
+ .axi_tbl_len = ARRAY_SIZE(axi_mem_cfg_tbl_t6d),
+ .axi_mem_cfg_tbl = axi_mem_cfg_tbl_t6d,
.lut_dma_ops = &lcd_tcon_dma_ops_t6d,
.tcon_init_table_pre_proc = lcd_tcon_init_table_pre_proc,
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vbyone.c b/drivers/amlogic/media/vout/lcd/lcd_vbyone.c
index 368e562..e67e2a7 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_vbyone.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_vbyone.c
@@ -370,26 +370,53 @@
}
}
-#define VX1_LOCKN_WAIT_TIMEOUT 500 /* 500ms */
-void lcd_vbyone_wait_stable(struct aml_lcd_drv_s *pdrv)
+#define VX1_LOCKN_INTERVAL 20 //unit:us
+#define VX1_LOCKN_WAIT_TIMEOUT 20000 /* 20000*50us=1000ms */
+#define VX1_LOCKN_STABLE_CNT 100
+#define VX1_LOCKN_CONFIRM_DELAY 100 //us
+#define VX1_LOCKN_CONFIRM_CNT 5
+
+static void lcd_vbyone_wait_lock(struct aml_lcd_drv_s *pdrv)
{
+ int i = VX1_LOCKN_WAIT_TIMEOUT, lock_cnt = 0, lock_ok = 0, lock_confirm_cnt = 0;
unsigned int reg, offset;
- int i = 0;
offset = pdrv->data->offset_venc_if[pdrv->index];
reg = VBO_STATUS_L + offset;
+ while ((i > 0)) {
+ if ((lcd_vcbus_read(reg) & 0x3f) == 0x20) {
+ if (++lock_cnt >= VX1_LOCKN_STABLE_CNT) {
+ lock_ok = 1;
+ lock_confirm_cnt++;
+ }
+ } else {
+ lock_cnt = 0;
+ lock_confirm_cnt = 0;
+ }
+ if (lock_confirm_cnt == VX1_LOCKN_CONFIRM_CNT)
+ break;
+ if (lock_ok) {
+ lock_ok = 0;
+ lock_cnt = 0;
+ udelay(VX1_LOCKN_CONFIRM_DELAY * lock_confirm_cnt);
+ } else {
+ udelay(VX1_LOCKN_INTERVAL);
+ }
+ i--;
+ }
+ LCDPR("%s status: 0x%x, time=%dus\n",
+ __func__, lcd_vcbus_read(reg),
+ (VX1_LOCKN_WAIT_TIMEOUT - i) * VX1_LOCKN_INTERVAL);
+}
+
+void lcd_vbyone_wait_stable(struct aml_lcd_drv_s *pdrv)
+{
/* training hold release */
if (pdrv->config.control.vbyone_cfg.ctrl_flag & 0x4)
lcd_vbyone_cdr_training_hold(pdrv, 0);
- while (i++ < VX1_LOCKN_WAIT_TIMEOUT) {
- if ((lcd_vcbus_read(reg) & 0x3f) == 0x20)
- break;
- mdelay(1);
- }
- LCDPR("[%d]: %s status: 0x%x, i=%d\n",
- pdrv->index, __func__, lcd_vcbus_read(reg), i);
+ lcd_vbyone_wait_lock(pdrv);
/* power on reset */
if (pdrv->config.control.vbyone_cfg.ctrl_flag & 0x1) {
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c
index 1d83c80..601910d 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_vout.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c
@@ -19,7 +19,7 @@
#endif
#include "lcd_reg.h"
#include "lcd_common.h"
-// #include <amlogic/pm.h>
+#include <amlogic/pm.h>
#include "env.h"
#include "command.h"
@@ -31,11 +31,14 @@
static struct aml_lcd_drv_s *lcd_driver[LCD_MAX_DRV];
static struct lcd_debug_ctrl_s debug_ctrl;
static char *g_dt_addr = (char *)0x01000000;
-//static int lcd_poweron_suspend = 1;
char *lcd_pm_name[LCD_MAX_DRV] = {"lcd_drv0_pm", "lcd_drv1_pm", "lcd_drv2_pm"};
unsigned int lcd_prbs_freq = 0, lcd_prbs_performed = 0, lcd_prbs_err = 0;
+static int aml_lcd_driver_suspend(void *pm_ops);
+static int aml_lcd_driver_resume(void *pm_ops);
+static int aml_lcd_driver_poweroff(void *pm_ops);
+
static void lcd_update_ctrl_bootargs(struct aml_lcd_drv_s *pdrv);
static struct aml_lcd_data_s lcd_data_c3 = {
@@ -583,10 +586,8 @@
static struct aml_lcd_drv_s *lcd_driver_add(int index)
{
struct aml_lcd_drv_s *pdrv;
-#if 0
struct dev_pm_ops *pm_ops = NULL;
char *ddr_resume = NULL;
-#endif
if (index >= lcd_data->drv_max) {
LCDERR("%s: invalid index: %d\n", __func__, index);
@@ -603,28 +604,22 @@
LCDERR("%s: Not enough memory\n", __func__);
return NULL;
}
-#if 0
pm_ops = dev_register_pm(lcd_pm_name[index],
&aml_lcd_driver_suspend,
&aml_lcd_driver_resume,
&aml_lcd_driver_poweroff);
-#endif
} else {
-#if 0
pm_ops = lcd_driver[index]->dev_pm_ops;
-#endif
}
pdrv = lcd_driver[index];
memset(pdrv, 0, sizeof(struct aml_lcd_drv_s));
pdrv->index = index;
-#if 0
pdrv->dev_pm_ops = pm_ops;
ddr_resume = env_get("ddr_resume");
if (ddr_resume && ddr_resume[0] == '1')
pdrv->power_on_suspend = 1;
-#endif
/* default config */
pdrv->data = lcd_data;
@@ -652,10 +647,8 @@
if (!lcd_driver[index])
return 0;
-#if 0
if (lcd_driver[index]->dev_pm_ops)
dev_unregister_pm(lcd_driver[index]->dev_pm_ops);
-#endif
free(lcd_driver[index]);
lcd_driver[index] = NULL;
@@ -997,10 +990,8 @@
for (i = 0; i < LCD_MAX_DRV; i++) {
if (lcd_driver[i]) {
-#if 0
if (lcd_driver[i]->dev_pm_ops)
dev_unregister_pm(lcd_driver[i]->dev_pm_ops);
-#endif
free(lcd_driver[i]);
lcd_driver[i] = NULL;
}
@@ -1510,9 +1501,8 @@
}
}
-int aml_lcd_driver_suspend(void *pm_ops)
+static int aml_lcd_driver_suspend(void *pm_ops)
{
-#if 0
int i = 0;
struct dev_pm_ops *pm = (struct dev_pm_ops *)pm_ops;
struct aml_lcd_drv_s *pdrv;
@@ -1531,13 +1521,12 @@
pdrv->power_on_suspend = 1;
LCDPR("%s driver disabled\n", __func__);
LCDPR("[%d]: %s: driver disabled\n", pdrv->index, __func__);
-#endif
+
return 0;
}
-int aml_lcd_driver_resume(void *pm_ops)
+static int aml_lcd_driver_resume(void *pm_ops)
{
-#if 0
int i = 0;
struct dev_pm_ops *pm = (struct dev_pm_ops *)pm_ops;
struct aml_lcd_drv_s *pdrv;
@@ -1555,11 +1544,11 @@
pdrv->power_on_suspend = 0;
aml_lcd_driver_enable(i, pdrv->init_mode);
LCDPR("[%d]: %s: driver enable\n", pdrv->index, __func__);
-#endif
+
return 0;
}
-int aml_lcd_driver_poweroff(void *pm_ops)
+static int aml_lcd_driver_poweroff(void *pm_ops)
{
aml_lcd_driver_suspend(pm_ops);
diff --git a/drivers/amlogic/mmc/meson_gx_mmc.h b/drivers/amlogic/mmc/meson_gx_mmc.h
index 8e65f37..3580311 100644
--- a/drivers/amlogic/mmc/meson_gx_mmc.h
+++ b/drivers/amlogic/mmc/meson_gx_mmc.h
@@ -50,13 +50,6 @@
u32 resp_addr;
};
-#define SAMSUNG_MID 0x15
-#define KINGSTON_MID 0x70
-#define BIWIN_MID 0xf4
-#define SAMSUNG_FFU_ADDR 0xc7810000
-#define KINGSTON_FFU_ADDR 0x0000ffff
-#define BIWIN_FFU_ADDR 0x0
-
/* unknown */
#define CARD_TYPE_UNKNOWN 0
/* MMC card */
diff --git a/drivers/amlogic/mmc/storage_emmc.c b/drivers/amlogic/mmc/storage_emmc.c
index b09cee3..00964f4 100644
--- a/drivers/amlogic/mmc/storage_emmc.c
+++ b/drivers/amlogic/mmc/storage_emmc.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/amlogic/arch/efuse.h>
#include "../../../cmd/amlogic/ini/ini_io.h"
+#include "../../drivers/mmc/mmc_private.h"
#if IS_ENABLED(CONFIG_EFUSE_OBJ_API)
extern efuse_obj_field_t efuse_field;
@@ -1119,7 +1120,116 @@
printf("Disprotect the key partition!\n");
}
return ret;
+}
+static int mmc_ffu_op(u64 ffu_ver, void *addr, u64 cnt)
+{
+ int err, i, supported_modes, fw_cfg, ffu_status;
+ u64 fw_ver = 0, n;
+ u8 ext_csd_ffu[512] = {0};
+ lbaint_t ffu_addr = 0;
+ struct mmc *mmc;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
+ if (!mmc)
+ return -ENODEV;
+
+ printf("FFU update start\n");
+ /* check Manufacturer MID */
+ if ((mmc->cid[0] >> 24) == SAMSUNG_MID) {
+ ffu_addr = SAMSUNG_FFU_ADDR;
+ } else if ((mmc->cid[0] >> 24) == KINGSTON_MID) {
+ ffu_addr = KINGSTON_FFU_ADDR;
+ } else if ((mmc->cid[0] >> 24) == BIWIN_MID) {
+ ffu_addr = BIWIN_FFU_ADDR;
+ } else {
+ printf("FFU update for this manufacturer not support yet\n");
+ return -EOPNOTSUPP;
+ }
+
+ /*
+ * check FFU Supportability
+ * check FFU Prohibited or not
+ * check current firmware version
+ */
+ memset(ext_csd_ffu, 0, 512);
+ err = mmc_get_ext_csd(mmc, ext_csd_ffu);
+ if (err)
+ return err;
+
+ supported_modes = ext_csd_ffu[EXT_CSD_SUPPORTED_MODES] & 0x1;
+ fw_cfg = ext_csd_ffu[EXT_CSD_FW_CFG] & 0x1;
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("old fw_ver = %llx\n", fw_ver);
+ if (!supported_modes || fw_cfg || fw_ver >= ffu_ver)
+ return -EOPNOTSUPP;
+
+ /* Set FFU Mode */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 1);
+ if (err) {
+ printf("Failed: set FFU mode\n");
+ return err;
+ }
+
+ /* Write patch file at one write command */
+ n = blk_dwrite(mmc_get_blk_desc(mmc), ffu_addr, cnt, addr);
+ if (n != cnt) {
+ printf("target is %llx block, but only %llx block has been write\n", cnt, n);
+ return -1;
+ }
+
+ memset(ext_csd_ffu, 0, 512);
+ err = mmc_get_ext_csd(mmc, ext_csd_ffu);
+ if (err)
+ return err;
+
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("new fw_ver = %llx\n", fw_ver);
+ if ((mmc->cid[0] >> 24) == SAMSUNG_MID) {
+ /* Set Normal Mode */
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 0);
+ if (err)
+ return err;
+ }
+
+ /* Initialization */
+ mmc->has_init = 0;
+ err = mmc_init(mmc);
+ if (err)
+ return err;
+
+ /* Read ffu_status, check ffu_version */
+ memset(ext_csd_ffu, 0, 512);
+ err = mmc_get_ext_csd(mmc, ext_csd_ffu);
+ if (err)
+ return err;
+ ffu_status = ext_csd_ffu[EXT_CSD_FFU_STATUS] & 0xff;
+ fw_ver = 0;
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("new fw_ver = %llx\n", fw_ver);
+ if (ffu_status || fw_ver != ffu_ver)
+ return ffu_status;
+
+ printf("FFU update ok!\n");
+ return 0;
}
void config_storage_dev_func(struct storage_t *dev, struct mmc* mmc)
@@ -1159,6 +1269,7 @@
dev->gpt_erase = mmc_gpt_erase;
dev->boot_copy_enable = mmc_boot_copy_enable;
+ dev->ffu_op = mmc_ffu_op;
return;
}
diff --git a/drivers/amlogic/mtd/nand/raw/aml_nand.c b/drivers/amlogic/mtd/nand/raw/aml_nand.c
index 4734dd3..50f5412 100644
--- a/drivers/amlogic/mtd/nand/raw/aml_nand.c
+++ b/drivers/amlogic/mtd/nand/raw/aml_nand.c
@@ -1380,12 +1380,9 @@
int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
struct aml_nand_platform *plat = aml_chip->platform;
- struct mtd_oob_ops aml_oob_ops;
- int32_t ret = 0, read_cnt, mtd_erase_shift, blk_addr, pages_per_blk;
- loff_t addr;
+ int32_t mtd_erase_shift, blk_addr;
if ((!strncmp((char *)plat->name,
NAND_BOOT_NAME, strlen((const char *)NAND_BOOT_NAME))))
@@ -1400,54 +1397,16 @@
blk_addr = (int)(ofs >> mtd_erase_shift);
if (aml_chip->block_status != NULL) {
- if (aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD) {
- printf(" NAND bbt detect Bad block at %llx \n",
- (u64)ofs);
- return EFAULT;
- }
- if (aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD) {
- printf(" NAND bbt detect factory Bad block at %llx \n",
- (u64)ofs);
- return FACTORY_BAD_BLOCK_ERROR;//159 EFAULT
- } else if (aml_chip->block_status[blk_addr] == NAND_BLOCK_GOOD)
- return 0;
+ if (aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD)
+ printf("NAND bbt detect Bad block at %llx\n", (u64)ofs);
+ if (aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD)
+ printf("NAND bbt detect factory Bad block at %llx\n",
+ (u64)ofs);
+ return aml_chip->block_status[blk_addr];
}
- chip->pagebuf = -1;
- pages_per_blk = (1 << (chip->phys_erase_shift - chip->page_shift));
- aml_oob_ops.mode = MTD_OPS_AUTO_OOB;
- aml_oob_ops.len = mtd->writesize;
- aml_oob_ops.ooblen = mtd->oobavail;
- aml_oob_ops.ooboffs = chip->ecc.layout->oobfree[0].offset;
- aml_oob_ops.datbuf = chip->buffers->databuf;
- aml_oob_ops.oobbuf = chip->oob_poi;
- for (read_cnt = 0; read_cnt < 2; read_cnt++) {
- addr =
- ofs + (pages_per_blk - 1) * read_cnt * mtd->writesize;
- ret = mtd->_read_oob(mtd, addr, &aml_oob_ops);
- if (ret == -EUCLEAN)
- ret = 0;
- if (ret < 0) {
- pr_info("1 NAND detect Bad block:%llx\n",
- (u64)addr);
- return EFAULT;
- }
- if (aml_oob_ops.oobbuf[chip->badblockpos] == 0xFF)
- continue;
- if (aml_oob_ops.oobbuf[chip->badblockpos] == 0) {
- memset(aml_chip->aml_nand_data_buf,
- 0, aml_oob_ops.ooblen);
- if (!memcmp(aml_chip->aml_nand_data_buf,
- aml_oob_ops.oobbuf, aml_oob_ops.ooblen)) {
- pr_info("2 NAND detect Bad block:%llx\n",
- (u64)addr);
- return EFAULT;
- }
- }
- }
-
-
- return 0;
+ pr_err("BUG at %s:%d/%s() no rsv bbt!\n", __FILE__, __LINE__, __func__);
+ return -EFAULT;
}
int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
diff --git a/drivers/amlogic/mtd/spi/storage_sf.c b/drivers/amlogic/mtd/spi/storage_sf.c
index 979d722..1a34996 100644
--- a/drivers/amlogic/mtd/spi/storage_sf.c
+++ b/drivers/amlogic/mtd/spi/storage_sf.c
@@ -105,6 +105,7 @@
static int probe_flag;
struct storage_t *spi_nor = NULL;
struct spi_flash *flash = NULL;
+ struct dm_spi_ops *ops;
int ret;
flash = (struct spi_flash *)get_spi_flash();
@@ -121,6 +122,10 @@
return 1;
}
+ /* set clock */
+ ops = spi_get_ops(flash->spi->dev->parent);
+ ops->set_mode(flash->spi->dev->parent, 0);
+
if (probe_flag)
return 0;
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index 777884d..5650311 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -65,6 +65,7 @@
#ifdef CONFIG_FASTBOOT_WRITING_CMD
#ifdef CONFIG_AMLOGIC_MODIFY
static void fetch(char *, char *);
+static void oem_cmd(char *, char *);
#if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
static void flashing(char *, char *);
#endif
@@ -114,6 +115,10 @@
.command = "fetch",
.dispatch = fetch
},
+ [FASTBOOT_COMMAND_OEM] = {
+ .command = "oem",
+ .dispatch = oem_cmd,
+ },
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
[FASTBOOT_COMMAND_FLASH] = {
@@ -605,12 +610,14 @@
char *slot_name = NULL;
char partname[32] = {0};
+#ifdef CONFIG_MESON_S7D
ret = update_boot_hdr_4_s7d_reva(fastboot_buf_addr, image_size, 0);
if (ret) {
printf("Failed to write s7d reva boot0\n");
fastboot_fail("Failed to write s7d reva boot0", response);
return;
}
+#endif//#ifdef CONFIG_MESON_S7D
slot_name = env_get("active_slot");
if (slot_name && (strcmp(slot_name, "_a") == 0))
@@ -802,12 +809,14 @@
strcpy(name, "dtb");
} else if (!strcmp(cmd_parameter, "bootloader-boot0") ||
!strcmp(cmd_parameter, "bootloader-boot1")) {
+#ifdef CONFIG_MESON_S7D
ret = update_boot_hdr_4_s7d_reva(fastboot_buf_addr, image_size, 0);
if (ret) {
printf("Failed to write s7d reva boot0\n");
fastboot_fail("Failed to write s7d reva boot0-1", response);
return;
}
+#endif//#ifdef CONFIG_MESON_S7D
strlcpy(name, cmd_parameter, 31);
} else {
strlcpy(name, cmd_parameter, 31);
@@ -1109,6 +1118,43 @@
fastboot_response("DATA", response, "%12llx", read_size);
}
+static void oem_cmd(char *cmd_parameter, char *response)
+{
+ char *cmd;
+ int i = 0, len = 0, j = 0;
+ char cmd_str[FASTBOOT_RESPONSE_LEN];
+
+ printf("oem cmd_parameter: %s\n", cmd_parameter);
+
+ if (IS_FEAT_BOOT_VERIFY()) {
+ printf("device is secure mode, can not run this cmd.\n");
+ fastboot_fail("secure boot device", response);
+ return;
+ }
+
+ if (check_lock() == 1) {
+ printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n");
+ fastboot_fail("locked device", response);
+ return;
+ }
+
+ cmd = cmd_parameter;
+ strsep(&cmd, " ");
+ printf("To run cmd[%s]\n", cmd);
+
+ len = strlen(cmd);
+ for (i = 0; i < len; i++) {
+ if (cmd[i] != '\'')
+ cmd_str[j++] = cmd[i];
+ }
+ cmd_str[j] = '\0';
+ printf("cmd_str2: %s\n", cmd_str);
+
+ run_command(cmd_str, 0);
+
+ fastboot_okay(NULL, response);
+}
+
static void set_active_cmd(char *cmd_parameter, char *response)
{
char *cmd;
@@ -1135,6 +1181,7 @@
}
#if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
+#ifdef CONFIG_AVB2
static void try_unlock_dev(u64 rc)
{
#if defined(CONFIG_AML_ANTIROLLBACK) || defined(CONFIG_AML_AVB2_ANTIROLLBACK)
@@ -1198,6 +1245,7 @@
printf("locking device. Erasing metadata partition!\n");
run_command("store erase metadata 0 0", 0);
}
+#endif
/**
* flashing() - lock/unlock.
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
index ab6208a..a5ad2bb 100644
--- a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
+++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
@@ -82,6 +82,9 @@
if (!strcmp("bootloader", part)) {
ret = bootloader_read(vryBuff, 0, imgTotalLen);
sha1_update(&ctx, vryBuff, imgTotalLen);
+ } else if (!strncmp("bootloader-", part, strnlen("bootloader-", 12))) {
+ ret = store_bootloader_ops(_STORE_BOOT_OP_READ, part, vryBuff, imgTotalLen);
+ sha1_update(&ctx, vryBuff, imgTotalLen);
} else if (!strcmp("_aml_dtb", part)) {
ret = store_dtb_rw(vryBuff, imgTotalLen, 2);
sha1_update(&ctx, vryBuff, imgTotalLen);
@@ -283,6 +286,7 @@
if (strcmp("bootloader", cmnInf->partName) &&
strcmp("_aml_dtb", cmnInf->partName) &&
+ strncmp("bootloader-", cmnInf->partName, strnlen("bootloader-", 12)) &&
strcmp("gpt", cmnInf->partName))
_usbDownInf.dataSize = _mymin(leftLen, _RAW_IMG_TRANSFER_LEN);
else
@@ -398,6 +402,9 @@
case V3TOOL_MEDIA_TYPE_STORE: {
if (!strcmp("bootloader", partName)) {
ret = bootloader_write(dataBuf, 0, thisTransferLen);
+ } else if (!strncmp("bootloader-", partName, strnlen("bootloader-", 12))) {
+ FB_MSG("write %s \n", partName);
+ ret = store_bootloader_ops(_STORE_BOOT_OP_WRITE, partName, dataBuf, thisTransferLen);
} else if (!strcmp("_aml_dtb", partName)) {
ret = store_dtb_rw(dataBuf, thisTransferLen, 1);
} else if (!strcmp("gpt", partName)) {
@@ -483,12 +490,16 @@
case V3TOOL_MEDIA_TYPE_STORE: {
if (!strcmp("bootloader", partName) ||
!strcmp("_aml_dtb", partName) ||
+ !strncmp("bootloader-", partName, strnlen("bootloader-", 12)) ||
!strcmp("gpt", partName)) {
_usbUpInf.dataSize = leftLen;
dataSize = leftLen;
}
if (!strcmp("bootloader", partName)) {
ret = bootloader_read(dataBuf, 0, dataSize);
+ } else if (!strncmp("bootloader-", partName, strnlen("bootloader-", 12))) {
+ FB_MSG("write %s \n", partName);
+ ret = store_bootloader_ops(_STORE_BOOT_OP_READ, partName, dataBuf, dataSize);
} else if (!strcmp("_aml_dtb", partName)) {
//'2' means using 'store dtb iread' rather than 'read'
ret = store_dtb_rw(dataBuf, dataSize, 2);
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
index 30e046f..37cb3c7 100644
--- a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
+++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
@@ -340,6 +340,7 @@
return 0;
}
+#ifdef CONFIG_MESON_S7D
int update_boot_hdr_4_s7d_reva(u8 *data_buf, unsigned int binsz, int isread)
{
const cpu_id_t cpuid = get_cpu_id();
@@ -394,6 +395,7 @@
FB_MSG("boot hdr changed\n");
return 0;
}
+#endif//#ifdef CONFIG_MESON_S7D
int bootloader_write(u8 *dataBuf, unsigned off, unsigned binsz)
{
@@ -403,10 +405,12 @@
//_bl2x_mode_check_header(pInfo);
if (is_bootloader_discrte(&discreteMode))
return -__LINE__;
+#ifdef CONFIG_MESON_S7D
if (update_boot_hdr_4_s7d_reva(dataBuf, binsz, 0)) {
FB_ERR("Fail in update x5m inf\n");
return -__LINE__;
}
+#endif//#ifdef CONFIG_MESON_S7D
if (!discreteMode) {
return _bootloader_write(dataBuf, off, binsz, "bootloader");
} else {
@@ -569,10 +573,13 @@
memcpy(pBuf, src_data, binsz);
}
#endif//#ifdef CONFIG_UPDATE_UBOOT_NOCS
+#ifdef CONFIG_MESON_S7D
if (update_boot_hdr_4_s7d_reva(pBuf, binsz, 1)) {
FB_ERR("Fail in update x5m inf\n");
return -__LINE__;
}
+#endif//#ifdef CONFIG_MESON_S7D
+
return 0;
}
@@ -613,11 +620,14 @@
#endif// #if 1//storage wrapper
-int v3tool_media_check_image_size(int64_t imgsz, const char *part)
+int v3tool_media_check_image_size(int64_t imgsz, const char *_part)
{
int ret = 0;
u64 partcap = 0;
+ const char *part = _part;
+ if (!strncmp("bootloader-", part, strnlen("bootloader-", 11)))
+ part = "bootloader";
if (!strcmp("bootloader", part)) {
const unsigned int bootSz = bootloader_copy_sz();
if (imgsz > bootSz)
@@ -800,7 +810,8 @@
FB_MSG("remain bootloader as nocs scs chip\n");
ret = usb_burn_erase_data(1);
} else {
- if (v3tool_work_mode_get() == V3TOOL_WORK_MODE_USB_PRODUCE) {
+ if (v3tool_work_mode_get() == V3TOOL_WORK_MODE_USB_PRODUCE ||
+ store_get_type() != BOOT_EMMC) {
ret = store_erase(NULL, 0, 0, 0);
} else {
FB_MSG("remain bootloader as not usb boot\n");
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
index 002d025..821c449 100644
--- a/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
+++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
@@ -961,7 +961,7 @@
} else if (!strcmp("save_setting", argv[0])) {
if (IS_ENABLED(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
env_set("firstboot", "1");
- env_set("upgrade_step", "1");
+ env_set("default_env", "1");
ret = run_command("store rsv erase env", 0);
ret = run_command("saveenv", 0);
} else {
diff --git a/include/amlogic/aml_mmc.h b/include/amlogic/aml_mmc.h
index daf6ec9..eec7f73 100644
--- a/include/amlogic/aml_mmc.h
+++ b/include/amlogic/aml_mmc.h
@@ -56,15 +56,23 @@
#define MMC_KEY_SIZE (256*1024)
#define EMMC_KEY_DEV (1)
-#define EXT_CSD_CLASS_6_CTRL 59 /*R/W/E_P*/
-#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
+/* FFU operation */
+#define SAMSUNG_MID 0x15
+#define KINGSTON_MID 0x70
+#define BIWIN_MID 0xf4
+#define SAMSUNG_FFU_ADDR 0xc7810000
+#define KINGSTON_FFU_ADDR 0x0000ffff
+#define BIWIN_FFU_ADDR 0x0
+
+#define EXT_CSD_CLASS_6_CTRL 59 /*R/W/E_P*/
+#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
#define EXT_CSD_DEV_LIFETIME_EST_TYP_A 268 /* RO */
#define EXT_CSD_DEV_LIFETIME_EST_TYP_B 269 /* RO */
-#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
-#define EXT_CSD_FW_VERSION 254 /* RO, 261:254 */
-#define EXT_CSD_FW_CFG 169 /* R/W */
-#define EXT_CSD_MODE_CFG 30 /* R/W */
-#define EXT_CSD_FFU_STATUS 26 /* RO */
+#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
+#define EXT_CSD_FW_VERSION 254 /* RO, 261:254 */
+#define EXT_CSD_FW_CFG 169 /* R/W */
+#define EXT_CSD_MODE_CFG 30 /* R/W */
+#define EXT_CSD_FFU_STATUS 26 /* RO */
#define US_PWR_WP_DIS_BIT 1<<3
#define US_PERM_WP_DIS_BIT 1<<4
diff --git a/include/amlogic/fb.h b/include/amlogic/fb.h
index a3fb43e..0d5e448 100644
--- a/include/amlogic/fb.h
+++ b/include/amlogic/fb.h
@@ -297,7 +297,6 @@
int get_osd_layer(void);
bool is_keystone_enable_for_txhd2(void);
bool is_keystone_enable_for_t6d(void);
-bool is_keystone_enable_for_t6d(void);
int get_osd_viux_scale_cap(void);
void osd_set_4k2k_fb_mode_hw(u32 fb_for_4k2k);
void osd2_layer_init(void);
diff --git a/include/amlogic/ini.h b/include/amlogic/ini.h
index 2c226f7..aa908f5 100644
--- a/include/amlogic/ini.h
+++ b/include/amlogic/ini.h
@@ -9,5 +9,7 @@
int handle_model_list_panel_key(void);
int handle_model_list(void);
int handle_model_sum(void);
+int handle_model_get(const char *model, char buf[]);
+int handle_model_set(const char *model, const char *val);
#endif /* __AML_INI_H__ */
diff --git a/include/amlogic/media/vout/hdmitx_common/hdmitx_edid.h b/include/amlogic/media/vout/hdmitx_common/hdmitx_edid.h
index 610c989..c4fbfd6 100644
--- a/include/amlogic/media/vout/hdmitx_common/hdmitx_edid.h
+++ b/include/amlogic/media/vout/hdmitx_common/hdmitx_edid.h
@@ -114,7 +114,6 @@
/*vendor*/
u32 ieeeoui;
u8 Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
- u16 physical_addr; /* CEC physical address */
u32 hf_ieeeoui; /* For HDMI Forum */
u32 Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
/* CEA861-F, Table 56, Colorimetry Data Block */
@@ -289,5 +288,7 @@
void hdmitx_edid_buffer_clear(u8 *edid_buf, int size);
void hdmitx_edid_rxcap_clear(struct rx_cap *prxcap);
bool is_support_y422(struct rx_cap *prxcap);
+void hdmitx_cec_phy_addr_parse(struct rx_cap *prxcap, u8 *edid_buf);
+int hdmitx_audio_parse(struct rx_cap *prxcap, u8 *block_buf);
#endif
diff --git a/include/amlogic/media/vout/lcd/lcd_vout.h b/include/amlogic/media/vout/lcd/lcd_vout.h
index e6c9f38..c5ea259 100644
--- a/include/amlogic/media/vout/lcd/lcd_vout.h
+++ b/include/amlogic/media/vout/lcd/lcd_vout.h
@@ -322,11 +322,10 @@
unsigned int lane_byte_clk;
/* non_burst vid packet */
+ unsigned int user_pkt_size;
unsigned int vid_num_chunks;
- unsigned int pixel_per_chunk; /* pkt_size */
unsigned int vid_null_size;
- unsigned int byte_per_chunk; /* internal usage */
- unsigned int multi_pkt_en; /* internal usage */
+ unsigned int vid_pkt_size;
/* vid timing */
unsigned int hline;
diff --git a/include/amlogic/media/vpp/vpp.h b/include/amlogic/media/vpp/vpp.h
index 97124cc..b1d74ef 100644
--- a/include/amlogic/media/vpp/vpp.h
+++ b/include/amlogic/media/vpp/vpp.h
@@ -19,6 +19,8 @@
VPP_GAMMA_B
};
+void set_vpp_mute(void);
+void set_vpp_unmute(void);
extern void vpp_load_gamma_table(unsigned short *data, unsigned int len, enum vpp_gamma_sel_e flag);
extern void vpp_init_lcd_gamma_table(int index);
void vpp_enable_lcd_gamma_table(int index);
diff --git a/include/amlogic/storage.h b/include/amlogic/storage.h
index 0509ff0..13acee6 100644
--- a/include/amlogic/storage.h
+++ b/include/amlogic/storage.h
@@ -138,6 +138,7 @@
int (*protect_rsv)(const char *rsv_name,
bool ops);/*true:on false:off*/
int (*param_ops)(void);
+ int (*ffu_op)(u64 ffu_ver, void *addr, u64 cnt);
};
struct device_node_t {
diff --git a/include/amlogic/store_wrapper.h b/include/amlogic/store_wrapper.h
index 6a38566..a520402 100644
--- a/include/amlogic/store_wrapper.h
+++ b/include/amlogic/store_wrapper.h
@@ -19,6 +19,15 @@
int store_boot_copy_enable(int id);
+enum {
+ _STORE_BOOT_OP_WRITE = 0,
+ _STORE_BOOT_OP_READ,
+ _STORE_BOOT_OP_ERASE,
+ _STORE_BOOT_OP_NUM
+};
+
+int store_bootloader_ops(int ops, const char *name, void *pdata, unsigned int szdata);
+
int update_boot_hdr_4_s7d_reva(u8 *data_buf, unsigned int binsz, int isread);
#ifdef CONFIG_CMD_MMC
int usb_burn_erase_data(unsigned char init_flag);
diff --git a/include/dt-bindings/amlogic/thermal/s6-thermal.h b/include/dt-bindings/amlogic/thermal/s6-thermal.h
new file mode 100644
index 0000000..95cfc9f
--- /dev/null
+++ b/include/dt-bindings/amlogic/thermal/s6-thermal.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_THERMAL_S6_H
+#define __DT_BINDINGS_THERMAL_S6_H
+
+/*update thermal cooling state*/
+#define CONFIG_CPU_OPP_TABLE "/cpu_opp_table3_2400"
+#define CONFIG_OPP_TABLE_667M_SIZE 2
+
+#endif /* __S6_THERMAL_H */
diff --git a/include/fastboot.h b/include/fastboot.h
index f2d0421..b9ab7f3 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -40,6 +40,7 @@
FASTBOOT_COMMAND_FLASHING,
#endif
FASTBOOT_COMMAND_FETCH,
+ FASTBOOT_COMMAND_OEM,
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
FASTBOOT_COMMAND_FLASH,