| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/amlogic/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/amlogic/pwm/pwm.h> |
| #include <dt-bindings/amlogic/pwm/meson.h> |
| #include <dt-bindings/amlogic/clock/t6d-clkc.h> |
| #include <dt-bindings/amlogic/input/meson_rc.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* 16 MiB reserved for Hardware ROM Firmware */ |
| hwrom_reserved: hwrom@0 { |
| reg = <0x0 0x0 0x0 0x1000000>; |
| no-map; |
| }; |
| |
| /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ |
| secmon_reserved: secmon@10000000 { |
| reg = <0x0 0x10000000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0xbc00000>; |
| alignment = <0x0 0x400000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <0x2>; |
| #size-cells = <0x0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| l2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| arm-pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| firmware { |
| sm: secure-monitor { |
| compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; |
| }; |
| }; |
| |
| efuse: efuse { |
| compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| }; |
| |
| scpi { |
| compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; |
| mboxes = <&mailbox 1 &mailbox 2>; |
| shmem = <&cpu_scp_lpri &cpu_scp_hpri>; |
| |
| scpi_clocks: clocks { |
| compatible = "arm,scpi-clocks"; |
| |
| scpi_dvfs: scpi_clocks@0 { |
| compatible = "arm,scpi-dvfs-clocks"; |
| #clock-cells = <1>; |
| clock-indices = <0>; |
| clock-output-names = "vcpu"; |
| }; |
| }; |
| |
| scpi_sensors: sensors { |
| compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; |
| #thermal-sensor-cells = <1>; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gic: interrupt-controller@2c001000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xffc01000 0 0x1000>, |
| <0x0 0xffc02000 0 0x2000>, |
| <0x0 0xffc04000 0 0x2000>, |
| <0x0 0xffc06000 0 0x2000>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| }; |
| |
| sram: sram@f7000000 { |
| compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram"; |
| reg = <0x0 0xf7000000 0x0 0x48000>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x0 0xf7000000 0x48000>; |
| |
| cpu_scp_lpri: scp-shmem@0 { |
| compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; |
| reg = <0x47000 0x400>; |
| }; |
| |
| cpu_scp_hpri: scp-shmem@200 { |
| compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; |
| reg = <0x47400 0x400>; |
| }; |
| }; |
| |
| cbus: cbus@fe070000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xfe070000 0x0 0xF000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>; |
| |
| uart_a: serial@8000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x8000 0x0 0x18>; |
| clocks = <&xtal>; |
| clock-names = "baud"; |
| status = "disabled"; |
| }; |
| |
| uart_b: serial@8400 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x8400 0x0 0x18>; |
| clocks = <&xtal>; |
| clock-names = "baud"; |
| status = "disabled"; |
| }; |
| |
| reset: reset-controller@1000 { |
| compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; |
| reg = <0x0 0x01000 0x0 0x1000>; |
| #reset-cells = <1>; |
| }; |
| |
| uart_c: serial@22000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x0 0x22000 0x0 0x18>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>; |
| status = "disabled"; |
| }; |
| |
| jtag { |
| compatible = "amlogic, jtag"; |
| status = "okay"; |
| select = "disable"; /* disable/jtag-a/jtag-b */ |
| pinctrl-names="jtag_a_pins", "jtag_b_pins"; |
| pinctrl-0=<&jtag_a_pins>; |
| pinctrl-1=<&jtag_b_pins>; |
| }; |
| }; |
| |
| ir: meson-ir { |
| compatible = "amlogic, meson-ir"; |
| reg = <0x0 0xfe08e040 0x0 0x44>, /*Multi-format IR controller*/ |
| <0x0 0xfe08e000 0x0 0x20>; /*Legacy IR controller*/ |
| protocol = <REMOTE_TYPE_NEC>; |
| status = "disabled"; |
| }; |
| |
| periphs: periphs@ff634000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff634000 0x0 0x2000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; |
| |
| hwrng: rng { |
| compatible = "amlogic,meson-rng"; |
| reg = <0x0 0x0 0x0 0x4>; |
| }; |
| }; |
| |
| hiubus: hiubus@ff63c000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff63c000 0x0 0x2000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; |
| |
| mailbox: mailbox@404 { |
| compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; |
| reg = <0 0x404 0 0x4c>; |
| interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, |
| <0 209 IRQ_TYPE_EDGE_RISING>, |
| <0 210 IRQ_TYPE_EDGE_RISING>; |
| #mbox-cells = <1>; |
| }; |
| }; |
| |
| clkc: clock-controller@0 { |
| compatible = "amlogic,t6d-clkc"; |
| #clock-cells = <1>; |
| reg = <0x0 0xfe000000 0x0 0x8380>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| }; |
| |
| i2c0: i2c@fe066000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0xfe066000 0x0 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@fe066400 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0xfe066400 0x0 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@fe066800 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0xfe066800 0x0 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@fe066c00 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0xfe066c00 0x0 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@fe067000 { |
| compatible = "amlogic,meson-i2c"; |
| reg = <0x0 0xfe067000 0x0 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spicc0: spi@fe050000 { |
| compatible = "amlogic,meson-a4-spicc"; |
| reg = <0x0 0xfe050000 0x0 0x38>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi_nfc: spi@0xfe08c000 { |
| compatible = "amlogic,spi_nfc"; |
| status = "disabled"; |
| reg = <0x0 0xfe08c000 0x0 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| spi-flash@0 { |
| compatible = "spi-flash"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| status = "disabled"; |
| }; |
| spi-nand@1 { |
| compatible = "spi-nand"; |
| reg = <1>; |
| spi-max-frequency = <20000000>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| status = "disabled"; |
| }; |
| }; |
| |
| ethmac: ethernet@ff3f0000 { |
| compatible = "amlogic,g12a-eth-dwmac"; |
| phy_cntl1 = <0x41054147>; |
| pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; |
| analog_val = <0x20200000 0x0000c000 0x00000023>; |
| status = "disabled"; |
| }; |
| |
| saradc: adc { |
| compatible = "amlogic,meson-saradc"; |
| reg = <0x0 0xfe026000 0x0 0xf0>; |
| status = "disabled"; |
| }; |
| |
| nand: nfc@fe08d000 { |
| compatible = "amlogic,meson-nfc"; |
| reg = <0x0 0xfe08d000 0x0 0x200>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clk_reg = <0 0xfe08c000>; |
| }; |
| |
| apb: apb@fe000000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xfe000000 0x0 0x1000000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; |
| |
| watchdog { |
| compatible = "amlogic,meson-sc2-wdt"; |
| reg = <0x0 0x2100 0x0 0x10>; |
| clocks = <&xtal>; |
| clock-names = "wdt-clk"; |
| }; |
| |
| sd_emmc_a: sdio { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x88000 0x0 0x800>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| pinname = "sdio"; |
| }; |
| |
| sd_emmc_b: sd { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x8a000 0x0 0x800>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| pinname = "sd"; |
| }; |
| |
| sd_emmc_c: emmc { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x8c000 0x0 0x800>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| pinname = "emmc"; |
| source-clock = <1536000000>; |
| }; |
| }; |
| |
| crg1: crg1@fe350000 { |
| compatible = "crg-xhci"; |
| status = "disable"; |
| reg = <0x0 0xfe350000 0x0 0x100000>; |
| phys = <&usb21_phy_v2>, <&usb31_phy_v2>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| |
| usb21_phy_v2: usb21phy@fe358000 { |
| compatible = "amlogic, amlogic-new-usb2-v2"; |
| status = "disable"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| phy-version = <2>; |
| reg = <0x0 0xfe358000 0x0 0x80 |
| 0x0 0xFE002000 0x0 0x100 |
| 0x0 0xfe35c000 0x0 0x2000>; |
| dwc2_a_reg = <0xfe350000>; |
| #phy-cells = <0>; |
| }; |
| |
| usb31_phy_v2: usb31phy@fe358080 { |
| compatible = "amlogic, amlogic-new-usb3-v2"; |
| status = "disable"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| phy-version = <3>; |
| reg = <0x0 0xfe358080 0x0 0x20>; |
| #phy-cells = <0>; |
| }; |
| |
| crg2: crg2@fe340000 { |
| compatible = "crg-xhci"; |
| status = "disable"; |
| reg = <0x0 0xfe340000 0x0 0x100000>; |
| phys = <&usb22_phy_v2>, <&usb32_phy_v2>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| |
| usb22_phy_v2: usb21phy@fe348000 { |
| compatible = "amlogic, amlogic-new-usb2-v2"; |
| status = "disable"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| phy-version = <2>; |
| reg = <0x0 0xfe348000 0x0 0x20 |
| 0x0 0xFE002000 0x0 0x100 |
| 0x0 0xfe34c000 0x0 0x2000>; |
| dwc2_a_reg = <0xfe350000>; |
| #phy-cells = <0>; |
| }; |
| |
| usb32_phy_v2: usb32phy@fe348080 { |
| compatible = "amlogic, amlogic-new-usb3-v2"; |
| status = "disable"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| phy-version = <3>; |
| reg = <0x0 0xfe348080 0x0 0x20>; |
| #phy-cells = <0>; |
| }; |
| }; |
| }; |