blob: 9f86da46e8883dd1059f608a5c59a8634d7ad031 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +05302/*
3 * (C) Copyright 2008
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +05306 */
7
8#ifndef _KWBIMAGE_H_
9#define _KWBIMAGE_H_
10
Reinhard Pfaua8840dc2015-11-29 15:48:25 +010011#include <compiler.h>
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +053012#include <stdint.h>
13
14#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
15#define MAX_TEMPBUF_LEN 32
16
17/* NAND ECC Mode */
18#define IBR_HDR_ECC_DEFAULT 0x00
19#define IBR_HDR_ECC_FORCED_HAMMING 0x01
20#define IBR_HDR_ECC_FORCED_RS 0x02
21#define IBR_HDR_ECC_DISABLED 0x03
22
23/* Boot Type - block ID */
24#define IBR_HDR_I2C_ID 0x4D
25#define IBR_HDR_SPI_ID 0x5A
26#define IBR_HDR_NAND_ID 0x8B
27#define IBR_HDR_SATA_ID 0x78
28#define IBR_HDR_PEX_ID 0x9C
29#define IBR_HDR_UART_ID 0x69
Marek Behúnbd487ce2021-07-23 11:13:58 +020030#define IBR_HDR_SDIO_ID 0xAE
Marek Behún35fd1002021-07-23 11:14:05 +020031#define IBR_DEF_ATTRIB 0x00
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +053032
Stefan Roesee29f1db2015-09-29 09:19:59 +020033/* Structure of the main header, version 0 (Kirkwood, Dove) */
34struct main_hdr_v0 {
Baruch Siach37d108b2017-07-04 20:23:39 +030035 uint8_t blockid; /* 0x0 */
36 uint8_t nandeccmode; /* 0x1 */
37 uint16_t nandpagesize; /* 0x2-0x3 */
38 uint32_t blocksize; /* 0x4-0x7 */
39 uint32_t rsvd1; /* 0x8-0xB */
40 uint32_t srcaddr; /* 0xC-0xF */
41 uint32_t destaddr; /* 0x10-0x13 */
42 uint32_t execaddr; /* 0x14-0x17 */
43 uint8_t satapiomode; /* 0x18 */
44 uint8_t rsvd3; /* 0x19 */
45 uint16_t ddrinitdelay; /* 0x1A-0x1B */
46 uint16_t rsvd2; /* 0x1C-0x1D */
47 uint8_t ext; /* 0x1E */
48 uint8_t checksum; /* 0x1F */
Stefan Roesee29f1db2015-09-29 09:19:59 +020049};
50
51struct ext_hdr_v0_reg {
52 uint32_t raddr;
53 uint32_t rdata;
54};
55
56#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
57
58struct ext_hdr_v0 {
59 uint32_t offset;
60 uint8_t reserved[0x20 - sizeof(uint32_t)];
61 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
62 uint8_t reserved2[7];
63 uint8_t checksum;
64};
65
66struct kwb_header {
67 struct main_hdr_v0 kwb_hdr;
68 struct ext_hdr_v0 kwb_exthdr;
69};
70
Baruch Siached727412017-07-04 20:23:38 +030071/* Structure of the main header, version 1 (Armada 370/38x/XP) */
Stefan Roesee29f1db2015-09-29 09:19:59 +020072struct main_hdr_v1 {
Baruch Siach37d108b2017-07-04 20:23:39 +030073 uint8_t blockid; /* 0x0 */
74 uint8_t flags; /* 0x1 */
75 uint16_t reserved2; /* 0x2-0x3 */
76 uint32_t blocksize; /* 0x4-0x7 */
77 uint8_t version; /* 0x8 */
78 uint8_t headersz_msb; /* 0x9 */
79 uint16_t headersz_lsb; /* 0xA-0xB */
80 uint32_t srcaddr; /* 0xC-0xF */
81 uint32_t destaddr; /* 0x10-0x13 */
82 uint32_t execaddr; /* 0x14-0x17 */
83 uint8_t options; /* 0x18 */
84 uint8_t nandblocksize; /* 0x19 */
85 uint8_t nandbadblklocation; /* 0x1A */
86 uint8_t reserved4; /* 0x1B */
87 uint16_t reserved5; /* 0x1C-0x1D */
88 uint8_t ext; /* 0x1E */
89 uint8_t checksum; /* 0x1F */
Stefan Roesee29f1db2015-09-29 09:19:59 +020090};
91
92/*
Chris Packham4bdb5472016-11-09 22:07:45 +130093 * Main header options
94 */
95#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
96#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
97#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
98#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
99#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
100#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
101#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
102#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
103
104/*
Stefan Roesee29f1db2015-09-29 09:19:59 +0200105 * Header for the optional headers, version 1 (Armada 370, Armada XP)
106 */
107struct opt_hdr_v1 {
108 uint8_t headertype;
109 uint8_t headersz_msb;
110 uint16_t headersz_lsb;
111 char data[0];
112};
113
114/*
Mario Sixa1b6b0a2017-01-11 16:01:00 +0100115 * Public Key data in DER format
116 */
117struct pubkey_der_v1 {
118 uint8_t key[524];
119};
120
121/*
122 * Signature (RSA 2048)
123 */
124struct sig_v1 {
125 uint8_t sig[256];
126};
127
128/*
129 * Structure of secure header (Armada 38x)
130 */
131struct secure_hdr_v1 {
132 uint8_t headertype; /* 0x0 */
133 uint8_t headersz_msb; /* 0x1 */
134 uint16_t headersz_lsb; /* 0x2 - 0x3 */
135 uint32_t reserved1; /* 0x4 - 0x7 */
136 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
137 uint8_t jtag_delay; /* 0x214 */
138 uint8_t reserved2; /* 0x215 */
139 uint16_t reserved3; /* 0x216 - 0x217 */
140 uint32_t boxid; /* 0x218 - 0x21B */
141 uint32_t flashid; /* 0x21C - 0x21F */
142 struct sig_v1 hdrsig; /* 0x220 - 0x31F */
143 struct sig_v1 imgsig; /* 0x320 - 0x41F */
144 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
145 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
146 uint8_t next; /* 0x25E0 */
147 uint8_t reserved4; /* 0x25E1 */
148 uint16_t reserved5; /* 0x25E2 - 0x25E3 */
149};
150
151/*
Pali Rohár02ba70a2021-07-23 11:14:11 +0200152 * Structure of register set
153 */
154struct register_set_hdr_v1 {
155 uint8_t headertype; /* 0x0 */
156 uint8_t headersz_msb; /* 0x1 */
157 uint16_t headersz_lsb; /* 0x2 - 0x3 */
158 union {
159 struct {
160 uint32_t address; /* 0x4+8*N - 0x7+8*N */
161 uint32_t value; /* 0x8+8*N - 0xB+8*N */
162 } entry;
163 struct {
164 uint8_t next; /* 0xC+8*N */
165 uint8_t delay; /* 0xD+8*N */
166 uint16_t reserved; /* 0xE+8*N - 0xF+8*N */
167 } last_entry;
168 } data[];
169};
170
171/*
172 * Value 0 in register_set_hdr_v1 delay field is special.
173 * Instead of delay it setup SDRAM Controller.
174 */
175#define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
176#define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
177
178/*
Stefan Roesee29f1db2015-09-29 09:19:59 +0200179 * Various values for the opt_hdr_v1->headertype field, describing the
180 * different types of optional headers. The "secure" header contains
181 * informations related to secure boot (encryption keys, etc.). The
182 * "binary" header contains ARM binary code to be executed prior to
183 * executing the main payload (usually the bootloader). This is
184 * typically used to execute DDR3 training code. The "register" header
185 * allows to describe a set of (address, value) tuples that are
186 * generally used to configure the DRAM controller.
187 */
188#define OPT_HDR_V1_SECURE_TYPE 0x1
189#define OPT_HDR_V1_BINARY_TYPE 0x2
190#define OPT_HDR_V1_REGISTER_TYPE 0x3
191
192#define KWBHEADER_V1_SIZE(hdr) \
Reinhard Pfaua8840dc2015-11-29 15:48:25 +0100193 (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
Stefan Roesee29f1db2015-09-29 09:19:59 +0200194
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +0530195enum kwbimage_cmd {
196 CMD_INVALID,
197 CMD_BOOT_FROM,
198 CMD_NAND_ECC_MODE,
199 CMD_NAND_PAGE_SIZE,
200 CMD_SATA_PIO_MODE,
201 CMD_DDR_INIT_DELAY,
202 CMD_DATA
203};
204
205enum kwbimage_cmd_types {
206 CFG_INVALID = -1,
207 CFG_COMMAND,
208 CFG_DATA0,
209 CFG_DATA1
210};
211
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +0530212/*
213 * functions
214 */
215void init_kwb_image_type (void);
216
Stefan Roesee29f1db2015-09-29 09:19:59 +0200217/*
218 * Byte 8 of the image header contains the version number. In the v0
219 * header, byte 8 was reserved, and always set to 0. In the v1 header,
220 * byte 8 has been changed to a proper field, set to 1.
221 */
222static inline unsigned int image_version(void *header)
223{
224 unsigned char *ptr = header;
225 return ptr[8];
226}
227
Prafulla Wadaskaraa0c7a82009-09-07 15:05:02 +0530228#endif /* _KWBIMAGE_H_ */