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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +02002/*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +02004 */
5
Olliver Schinagl048447c2018-11-21 20:05:27 +02006#include <linux/bitops.h>
7
Paul Kocialkowski940382f2015-03-22 18:08:21 +01008enum axp209_reg {
9 AXP209_POWER_STATUS = 0x00,
10 AXP209_CHIP_VERSION = 0x03,
Hans de Goedebeba4012015-10-04 12:01:17 +020011 AXP209_OUTPUT_CTRL = 0x12,
Paul Kocialkowski940382f2015-03-22 18:08:21 +010012 AXP209_DCDC2_VOLTAGE = 0x23,
13 AXP209_DCDC3_VOLTAGE = 0x27,
14 AXP209_LDO24_VOLTAGE = 0x28,
15 AXP209_LDO3_VOLTAGE = 0x29,
16 AXP209_IRQ_ENABLE1 = 0x40,
17 AXP209_IRQ_ENABLE2 = 0x41,
18 AXP209_IRQ_ENABLE3 = 0x42,
19 AXP209_IRQ_ENABLE4 = 0x43,
20 AXP209_IRQ_ENABLE5 = 0x44,
21 AXP209_IRQ_STATUS5 = 0x4c,
22 AXP209_SHUTDOWN = 0x32,
Paul Kocialkowski940382f2015-03-22 18:08:21 +010023};
24
Olliver Schinagl048447c2018-11-21 20:05:27 +020025#define AXP209_POWER_STATUS_ON_BY_DC BIT(0)
26#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010027
Olliver Schinagl048447c2018-11-21 20:05:27 +020028#define AXP209_OUTPUT_CTRL_EXTEN BIT(0)
29#define AXP209_OUTPUT_CTRL_DCDC3 BIT(1)
30#define AXP209_OUTPUT_CTRL_LDO2 BIT(2)
31#define AXP209_OUTPUT_CTRL_LDO4 BIT(3)
32#define AXP209_OUTPUT_CTRL_DCDC2 BIT(4)
33#define AXP209_OUTPUT_CTRL_LDO3 BIT(6)
Hans de Goedebeba4012015-10-04 12:01:17 +020034
Olliver Schinagl048447c2018-11-21 20:05:27 +020035#define AXP209_IRQ5_PEK_UP BIT(6)
36#define AXP209_IRQ5_PEK_DOWN BIT(5)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010037
Olliver Schinagl048447c2018-11-21 20:05:27 +020038#define AXP209_POWEROFF BIT(7)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010039
Hans de Goede2fcf0332015-04-25 17:25:14 +020040/* For axp_gpio.c */
41#define AXP_POWER_STATUS 0x00
Olliver Schinagl048447c2018-11-21 20:05:27 +020042#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
Hans de Goede2fcf0332015-04-25 17:25:14 +020043#define AXP_GPIO0_CTRL 0x90
44#define AXP_GPIO1_CTRL 0x92
45#define AXP_GPIO2_CTRL 0x93
Olliver Schinagl048447c2018-11-21 20:05:27 +020046#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
47#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
48#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
Hans de Goede2fcf0332015-04-25 17:25:14 +020049#define AXP_GPIO_STATE 0x94
Olliver Schinagl048447c2018-11-21 20:05:27 +020050#define AXP_GPIO_STATE_OFFSET 4