blob: 65cb3a6fe311ac578f112d2765be8cd8b878e1f4 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbellcba69ee2014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
Ian Campbellcba69ee2014-05-05 11:52:26 +010011 */
12
13#include <common.h>
Jagan Teki237050f2018-05-07 13:03:36 +053014#include <dm.h>
Simon Glassc7694dd2019-08-01 09:46:46 -060015#include <env.h>
Simon Glassdb41d652019-12-28 10:45:07 -070016#include <hang.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060017#include <image.h>
Simon Glass9b4a2052019-12-28 10:45:05 -070018#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060019#include <log.h>
Hans de Goedee79c7c82014-10-02 21:13:54 +020020#include <mmc.h>
Hans de Goede6944aff2015-10-03 15:18:33 +020021#include <axp_pmic.h>
Jagan Teki237050f2018-05-07 13:03:36 +053022#include <generic-phy.h>
23#include <phy-sun4i-usb.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010024#include <asm/arch/clock.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020025#include <asm/arch/cpu.h>
Luc Verhaegen2d7a0842014-08-13 07:55:07 +020026#include <asm/arch/display.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010027#include <asm/arch/dram.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010028#include <asm/arch/mmc.h>
Samuel Holland8a8b73b2020-10-24 10:21:52 -050029#include <asm/arch/prcm.h>
Hans de Goede4a8c7c12016-07-09 09:56:56 +020030#include <asm/arch/spl.h>
Simon Glass401d1c42020-10-30 21:38:53 -060031#include <asm/global_data.h>
Simon Glassc05ed002020-05-10 11:40:11 -060032#include <linux/delay.h>
Simon Glass3db71102019-11-14 12:57:16 -070033#include <u-boot/crc.h>
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020034#ifndef CONFIG_ARM64
35#include <asm/armv7.h>
36#endif
Hans de Goede4f7e01c2015-04-23 23:23:50 +020037#include <asm/gpio.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020038#include <asm/io.h>
Philipp Tomsicha740ee92018-11-25 19:22:18 +010039#include <u-boot/crc.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060040#include <env_internal.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090041#include <linux/libfdt.h>
Andre Heider9267ff82021-10-01 19:29:00 +010042#include <fdt_support.h>
Hans de Goedef62bfa52015-08-15 11:55:26 +020043#include <nand.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020044#include <net.h>
Maxime Ripardf4c35232017-08-23 10:08:29 +020045#include <spl.h>
Jelle van der Waa0d8382a2016-02-23 18:47:19 +010046#include <sy8106a.h>
Simon Glass5d982852017-05-17 08:23:00 -060047#include <asm/setup.h>
Arnaud Ferraris8f872bb2021-09-08 21:14:19 +020048#include <status_led.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010049
Tom Rinide695722021-08-17 17:59:46 -040050#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
Hans de Goede55410082015-02-16 17:23:25 +010051/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
52int soft_i2c_gpio_sda;
53int soft_i2c_gpio_scl;
Hans de Goede4f7e01c2015-04-23 23:23:50 +020054
55static int soft_i2c_board_init(void)
56{
57 int ret;
58
59 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
60 if (soft_i2c_gpio_sda < 0) {
61 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
63 return soft_i2c_gpio_sda;
64 }
65 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
66 if (ret) {
67 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
69 return ret;
70 }
71
72 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
73 if (soft_i2c_gpio_scl < 0) {
74 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
75 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
76 return soft_i2c_gpio_scl;
77 }
78 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
79 if (ret) {
80 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
81 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
82 return ret;
83 }
84
85 return 0;
86}
87#else
88static int soft_i2c_board_init(void) { return 0; }
Hans de Goede55410082015-02-16 17:23:25 +010089#endif
90
Ian Campbellcba69ee2014-05-05 11:52:26 +010091DECLARE_GLOBAL_DATA_PTR;
92
Jernej Skrabecacbc7e02017-04-27 00:03:35 +020093void i2c_init_board(void)
94{
95#ifdef CONFIG_I2C0_ENABLE
96#if defined(CONFIG_MACH_SUN4I) || \
97 defined(CONFIG_MACH_SUN5I) || \
98 defined(CONFIG_MACH_SUN7I) || \
99 defined(CONFIG_MACH_SUN8I_R40)
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
102 clock_twi_onoff(0, 1);
103#elif defined(CONFIG_MACH_SUN6I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
106 clock_twi_onoff(0, 1);
Icenowy Zheng8c51c652020-10-26 22:19:34 +0800107#elif defined(CONFIG_MACH_SUN8I_V3S)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
110 clock_twi_onoff(0, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200111#elif defined(CONFIG_MACH_SUN8I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
114 clock_twi_onoff(0, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200115#elif defined(CONFIG_MACH_SUN50I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
118 clock_twi_onoff(0, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200119#endif
120#endif
121
122#ifdef CONFIG_I2C1_ENABLE
123#if defined(CONFIG_MACH_SUN4I) || \
124 defined(CONFIG_MACH_SUN7I) || \
125 defined(CONFIG_MACH_SUN8I_R40)
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
128 clock_twi_onoff(1, 1);
129#elif defined(CONFIG_MACH_SUN5I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
132 clock_twi_onoff(1, 1);
133#elif defined(CONFIG_MACH_SUN6I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
136 clock_twi_onoff(1, 1);
137#elif defined(CONFIG_MACH_SUN8I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
140 clock_twi_onoff(1, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200141#elif defined(CONFIG_MACH_SUN50I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
143 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
144 clock_twi_onoff(1, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200145#endif
146#endif
147
148#ifdef CONFIG_I2C2_ENABLE
149#if defined(CONFIG_MACH_SUN4I) || \
150 defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
154 clock_twi_onoff(2, 1);
155#elif defined(CONFIG_MACH_SUN5I)
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
157 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
158 clock_twi_onoff(2, 1);
159#elif defined(CONFIG_MACH_SUN6I)
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
161 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
162 clock_twi_onoff(2, 1);
163#elif defined(CONFIG_MACH_SUN8I)
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
165 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
166 clock_twi_onoff(2, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200167#elif defined(CONFIG_MACH_SUN50I)
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
169 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
170 clock_twi_onoff(2, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200171#endif
172#endif
173
174#ifdef CONFIG_I2C3_ENABLE
175#if defined(CONFIG_MACH_SUN6I)
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
177 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
178 clock_twi_onoff(3, 1);
179#elif defined(CONFIG_MACH_SUN7I) || \
180 defined(CONFIG_MACH_SUN8I_R40)
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
183 clock_twi_onoff(3, 1);
184#endif
185#endif
186
187#ifdef CONFIG_I2C4_ENABLE
188#if defined(CONFIG_MACH_SUN7I) || \
189 defined(CONFIG_MACH_SUN8I_R40)
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
191 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
192 clock_twi_onoff(4, 1);
193#endif
194#endif
195
196#ifdef CONFIG_R_I2C_ENABLE
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800197#ifdef CONFIG_MACH_SUN50I
198 clock_twi_onoff(5, 1);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
200 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
Jernej Skrabecd0b07c12021-01-11 21:11:42 +0100201#elif CONFIG_MACH_SUN50I_H616
202 clock_twi_onoff(5, 1);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
204 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800205#else
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200206 clock_twi_onoff(5, 1);
207 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
208 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
209#endif
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800210#endif
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200211}
212
Maxime Ripardb39117c2018-01-23 21:17:03 +0100213#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
214enum env_location env_get_location(enum env_operation op, int prio)
215{
216 switch (prio) {
217 case 0:
218 return ENVL_FAT;
219
220 case 1:
221 return ENVL_MMC;
222
223 default:
224 return ENVL_UNKNOWN;
225 }
226}
227#endif
228
Andre Przywaraa7ae1592019-01-29 15:54:14 +0000229#ifdef CONFIG_DM_MMC
230static void mmc_pinmux_setup(int sdc);
231#endif
232
Ian Campbellcba69ee2014-05-05 11:52:26 +0100233/* add board specific code here */
234int board_init(void)
235{
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200236 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100237
238 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
239
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200240#ifndef CONFIG_ARM64
Ian Campbellcba69ee2014-05-05 11:52:26 +0100241 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
242 debug("id_pfr1: 0x%08x\n", id_pfr1);
243 /* Generic Timer Extension available? */
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200244 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
245 uint32_t freq;
246
Ian Campbellcba69ee2014-05-05 11:52:26 +0100247 debug("Setting CNTFRQ\n");
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200248
249 /*
250 * CNTFRQ is a secure register, so we will crash if we try to
251 * write this from the non-secure world (read is OK, though).
252 * In case some bootcode has already set the correct value,
253 * we avoid the risk of writing to it.
254 */
255 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
Andre Przywarae4916e82017-02-16 01:20:19 +0000256 if (freq != COUNTER_FREQUENCY) {
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200257 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
Andre Przywarae4916e82017-02-16 01:20:19 +0000258 freq, COUNTER_FREQUENCY);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200259#ifdef CONFIG_NON_SECURE
260 printf("arch timer frequency is wrong, but cannot adjust it\n");
261#else
262 asm volatile("mcr p15, 0, %0, c14, c0, 0"
Andre Przywarae4916e82017-02-16 01:20:19 +0000263 : : "r"(COUNTER_FREQUENCY));
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200264#endif
265 }
Ian Campbellcba69ee2014-05-05 11:52:26 +0100266 }
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200267#endif /* !CONFIG_ARM64 */
Ian Campbellcba69ee2014-05-05 11:52:26 +0100268
Hans de Goede2fcf0332015-04-25 17:25:14 +0200269 ret = axp_gpio_init();
270 if (ret)
271 return ret;
272
Andre Przywarae9ad1b82021-01-18 23:23:59 +0000273 /* strcmp() would look better, but doesn't get optimised away. */
274 if (CONFIG_SATAPWR[0]) {
275 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
276 if (satapwr_pin >= 0) {
277 gpio_request(satapwr_pin, "satapwr");
278 gpio_direction_output(satapwr_pin, 1);
279
280 /*
281 * Give the attached SATA device time to power-up
282 * to avoid link timeouts
283 */
284 mdelay(500);
285 }
286 }
287
288 if (CONFIG_MACPWR[0]) {
289 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
290 if (macpwr_pin >= 0) {
291 gpio_request(macpwr_pin, "macpwr");
292 gpio_direction_output(macpwr_pin, 1);
293 }
294 }
Hans de Goedefc8991c2016-03-17 13:53:03 +0100295
Igor Opaniuk2147a162021-02-09 13:52:45 +0200296#if CONFIG_IS_ENABLED(DM_I2C)
Jernej Skrabeca8f01cc2017-04-27 00:03:36 +0200297 /*
298 * Temporary workaround for enabling I2C clocks until proper sunxi DM
299 * clk, reset and pinctrl drivers land.
300 */
301 i2c_init_board();
302#endif
303
Andre Przywaraa7ae1592019-01-29 15:54:14 +0000304#ifdef CONFIG_DM_MMC
305 /*
306 * Temporary workaround for enabling MMC clocks until a sunxi DM
307 * pinctrl driver lands.
308 */
309 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
310#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
311 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
312#endif
313#endif /* CONFIG_DM_MMC */
314
Hans de Goede4f7e01c2015-04-23 23:23:50 +0200315 /* Uses dm gpio code so do this here and not in i2c_init_board() */
316 return soft_i2c_board_init();
Ian Campbellcba69ee2014-05-05 11:52:26 +0100317}
318
Andre Przywaracff5c132018-10-25 17:23:04 +0800319/*
320 * On older SoCs the SPL is actually at address zero, so using NULL as
321 * an error value does not work.
322 */
323#define INVALID_SPL_HEADER ((void *)~0UL)
324
325static struct boot_file_head * get_spl_header(uint8_t req_version)
326{
327 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
328 uint8_t spl_header_version = spl->spl_signature[3];
329
330 /* Is there really the SPL header (still) there? */
331 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
332 return INVALID_SPL_HEADER;
333
334 if (spl_header_version < req_version) {
335 printf("sunxi SPL version mismatch: expected %u, got %u\n",
336 req_version, spl_header_version);
337 return INVALID_SPL_HEADER;
338 }
339
340 return spl;
341}
342
Samuel Holland467b7e52020-10-24 10:21:50 -0500343static const char *get_spl_dt_name(void)
344{
345 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
346
347 /* Check if there is a DT name stored in the SPL header. */
348 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
349 return (char *)spl + spl->dt_name_offset;
350
351 return NULL;
352}
Samuel Holland467b7e52020-10-24 10:21:50 -0500353
Ian Campbellcba69ee2014-05-05 11:52:26 +0100354int dram_init(void)
355{
Andre Przywara57766102018-10-25 17:23:07 +0800356 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
357
358 if (spl == INVALID_SPL_HEADER)
359 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
360 PHYS_SDRAM_0_SIZE);
361 else
362 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
363
364 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
365 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100366
367 return 0;
368}
369
Boris Brezillon4ccae812016-06-15 21:09:23 +0200370#if defined(CONFIG_NAND_SUNXI)
Karol Gugalaad008292015-07-23 14:33:01 +0200371static void nand_pinmux_setup(void)
372{
373 unsigned int pin;
Hans de Goede022a99d2015-08-15 13:17:49 +0200374
375 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
Karol Gugalaad008292015-07-23 14:33:01 +0200376 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
377
Hans de Goede022a99d2015-08-15 13:17:49 +0200378#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
379 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
Karol Gugalaad008292015-07-23 14:33:01 +0200380 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
Hans de Goede022a99d2015-08-15 13:17:49 +0200381#endif
382 /* sun4i / sun7i do have a PC23, but it is not used for nand,
383 * only sun7i has a PC24 */
384#ifdef CONFIG_MACH_SUN7I
Karol Gugalaad008292015-07-23 14:33:01 +0200385 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
Hans de Goede022a99d2015-08-15 13:17:49 +0200386#endif
Karol Gugalaad008292015-07-23 14:33:01 +0200387}
388
389static void nand_clock_setup(void)
390{
391 struct sunxi_ccm_reg *const ccm =
392 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goede31c21472015-08-15 11:58:03 +0200393
Karol Gugalaad008292015-07-23 14:33:01 +0200394 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
Miquel Raynalba1c98b2018-02-28 20:51:53 +0100395#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
396 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
397 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
398#endif
Karol Gugalaad008292015-07-23 14:33:01 +0200399 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
400}
Hans de Goedef62bfa52015-08-15 11:55:26 +0200401
402void board_nand_init(void)
403{
404 nand_pinmux_setup();
405 nand_clock_setup();
Boris Brezillon4ccae812016-06-15 21:09:23 +0200406#ifndef CONFIG_SPL_BUILD
407 sunxi_nand_init();
408#endif
Hans de Goedef62bfa52015-08-15 11:55:26 +0200409}
Karol Gugalaad008292015-07-23 14:33:01 +0200410#endif
411
Masahiro Yamada4aa2ba32017-05-09 20:31:39 +0900412#ifdef CONFIG_MMC
Ian Campbelle24ea552014-05-05 14:42:31 +0100413static void mmc_pinmux_setup(int sdc)
414{
415 unsigned int pin;
416
417 switch (sdc) {
418 case 0:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100419 /* SDC0: PF0-PF5 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100420 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
424 }
425 break;
426
427 case 1:
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800428#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
429 defined(CONFIG_MACH_SUN8I_R40)
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500430 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100431 /* SDC1: PH22-PH-27 */
432 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
433 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
434 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
435 sunxi_gpio_set_drv(pin, 2);
436 }
437 } else {
438 /* SDC1: PG0-PG5 */
439 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
440 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
441 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
442 sunxi_gpio_set_drv(pin, 2);
443 }
444 }
445#elif defined(CONFIG_MACH_SUN5I)
446 /* SDC1: PG3-PG8 */
Hans de Goedebbff84b2014-10-03 16:44:57 +0200447 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100448 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
Ian Campbelle24ea552014-05-05 14:42:31 +0100449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
450 sunxi_gpio_set_drv(pin, 2);
451 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100452#elif defined(CONFIG_MACH_SUN6I)
453 /* SDC1: PG0-PG5 */
454 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
455 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
456 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
457 sunxi_gpio_set_drv(pin, 2);
458 }
459#elif defined(CONFIG_MACH_SUN8I)
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500460 /* SDC1: PG0-PG5 */
461 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
462 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
463 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
464 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100465 }
466#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100467 break;
468
469 case 2:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100470#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
471 /* SDC2: PC6-PC11 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100472 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100473 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 2);
476 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100477#elif defined(CONFIG_MACH_SUN5I)
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500478 /* SDC2: PC6-PC15 */
479 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
480 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
481 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
482 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100483 }
484#elif defined(CONFIG_MACH_SUN6I)
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500485 /* SDC2: PC6-PC15, PC24 */
486 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100490 }
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500491
492 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
493 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
494 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800495#elif defined(CONFIG_MACH_SUN8I_R40)
496 /* SDC2: PC6-PC15, PC24 */
497 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
498 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
499 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
500 sunxi_gpio_set_drv(pin, 2);
501 }
502
503 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
504 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
505 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200506#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100507 /* SDC2: PC5-PC6, PC8-PC16 */
508 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
509 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100510 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
511 sunxi_gpio_set_drv(pin, 2);
512 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100513
514 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
515 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
516 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
517 sunxi_gpio_set_drv(pin, 2);
518 }
Icenowy Zheng42956f12018-07-21 16:20:29 +0800519#elif defined(CONFIG_MACH_SUN50I_H6)
520 /* SDC2: PC4-PC14 */
521 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
522 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
523 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
524 sunxi_gpio_set_drv(pin, 2);
525 }
Andre Przywara212224e2021-04-26 00:38:04 +0100526#elif defined(CONFIG_MACH_SUN50I_H616)
527 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
528 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
529 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
530 continue;
531 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
532 continue;
533 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
534 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
535 sunxi_gpio_set_drv(pin, 3);
536 }
Philipp Tomsich3ebb4562016-10-28 18:21:33 +0800537#elif defined(CONFIG_MACH_SUN9I)
538 /* SDC2: PC6-PC16 */
539 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
540 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
541 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
542 sunxi_gpio_set_drv(pin, 2);
543 }
Andre Przywara212224e2021-04-26 00:38:04 +0100544#else
545 puts("ERROR: No pinmux setup defined for MMC2!\n");
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100546#endif
547 break;
548
549 case 3:
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800550#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
551 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100552 /* SDC3: PI4-PI9 */
553 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
554 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
555 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
556 sunxi_gpio_set_drv(pin, 2);
557 }
558#elif defined(CONFIG_MACH_SUN6I)
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500559 /* SDC3: PC6-PC15, PC24 */
560 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
561 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
562 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
563 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100564 }
Samuel Hollanddda9fa72021-09-12 10:28:35 -0500565
566 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
567 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
568 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100569#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100570 break;
571
572 default:
573 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
574 break;
575 }
576}
577
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900578int board_mmc_init(struct bd_info *bis)
Ian Campbelle24ea552014-05-05 14:42:31 +0100579{
Hans de Goedee79c7c82014-10-02 21:13:54 +0200580 __maybe_unused struct mmc *mmc0, *mmc1;
Hans de Goedee79c7c82014-10-02 21:13:54 +0200581
Ian Campbelle24ea552014-05-05 14:42:31 +0100582 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200583 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
584 if (!mmc0)
585 return -1;
586
Hans de Goede2ccfac02014-10-02 20:43:50 +0200587#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
Ian Campbelle24ea552014-05-05 14:42:31 +0100588 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200589 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
590 if (!mmc1)
591 return -1;
592#endif
593
Ian Campbelle24ea552014-05-05 14:42:31 +0100594 return 0;
595}
Samuel Holland1011ebc2021-04-18 22:16:21 -0500596
597#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
598int mmc_get_env_dev(void)
599{
600 switch (sunxi_get_boot_device()) {
601 case BOOT_DEVICE_MMC1:
602 return 0;
603 case BOOT_DEVICE_MMC2:
604 return 1;
605 default:
606 return CONFIG_SYS_MMC_ENV_DEV;
607 }
608}
609#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100610#endif
611
Ian Campbellcba69ee2014-05-05 11:52:26 +0100612#ifdef CONFIG_SPL_BUILD
Andre Przywara57766102018-10-25 17:23:07 +0800613
614static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
615{
616 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
617
618 if (spl == INVALID_SPL_HEADER)
619 return;
620
621 /* Promote the header version for U-Boot proper, if needed. */
622 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
623 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
624
625 spl->dram_size = dram_size >> 20;
626}
627
Ian Campbellcba69ee2014-05-05 11:52:26 +0100628void sunxi_board_init(void)
629{
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200630 int power_failed = 0;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100631
Arnaud Ferraris8f872bb2021-09-08 21:14:19 +0200632#ifdef CONFIG_LED_STATUS
633 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
634 status_led_init();
635#endif
636
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100637#ifdef CONFIG_SY8106A_POWER
638 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
639#endif
640
vishnupatekar95ab8fe2015-11-29 01:07:22 +0800641#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
Jernej Skrabecfbd37d82021-01-11 21:11:33 +0100642 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
643 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200644 power_failed = axp_init();
645
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800646#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
647 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200648 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
Hans de Goede24289202014-06-13 22:55:51 +0200649#endif
Jernej Skrabecfbd37d82021-01-11 21:11:33 +0100650#if !defined(CONFIG_AXP305_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200651 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
652 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
Jernej Skrabecfbd37d82021-01-11 21:11:33 +0100653#endif
vishnupatekar95ab8fe2015-11-29 01:07:22 +0800654#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200655 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200656#endif
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800657#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
658 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200659 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200660#endif
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200661
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800662#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
663 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200664 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
665#endif
Jernej Skrabecfbd37d82021-01-11 21:11:33 +0100666#if !defined(CONFIG_AXP305_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200667 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
Jernej Skrabecfbd37d82021-01-11 21:11:33 +0100668#endif
669#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200670 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
671#endif
672#ifdef CONFIG_AXP209_POWER
673 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
674#endif
675
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800676#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
677 defined(CONFIG_AXP818_POWER)
Chen-Yu Tsai3517a272016-01-12 14:42:37 +0800678 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
679 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800680#if !defined CONFIG_AXP809_POWER
Chen-Yu Tsai3517a272016-01-12 14:42:37 +0800681 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
682 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800683#endif
Hans de Goede6944aff2015-10-03 15:18:33 +0200684 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
685 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
686 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
687#endif
Chen-Yu Tsai38491d92016-03-30 00:26:48 +0800688
689#ifdef CONFIG_AXP818_POWER
690 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
691 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
692 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800693#endif
694
695#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Chen-Yu Tsai15278cc2016-05-02 10:28:12 +0800696 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
Chen-Yu Tsai38491d92016-03-30 00:26:48 +0800697#endif
Hans de Goede6944aff2015-10-03 15:18:33 +0200698#endif
From: Karl Palsson44c214d2018-12-19 13:00:39 +0000699 printf("DRAM:");
700 gd->ram_size = sunxi_dram_init();
701 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
702 if (!gd->ram_size)
703 hang();
704
705 sunxi_spl_store_dram_size(gd->ram_size);
Andre Przywara57766102018-10-25 17:23:07 +0800706
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200707 /*
708 * Only clock up the CPU to full speed if we are reasonably
709 * assured it's being powered with suitable core voltage
710 */
711 if (!power_failed)
Iain Patone71b4222015-03-28 10:26:38 +0000712 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200713 else
From: Karl Palsson44c214d2018-12-19 13:00:39 +0000714 printf("Failed to set core voltage! Can't set CPU frequency\n");
Ian Campbellcba69ee2014-05-05 11:52:26 +0100715}
716#endif
Jonathan Liub41d7d02014-06-14 08:59:09 +0200717
Paul Kocialkowskif1df7582015-03-22 18:07:13 +0100718#ifdef CONFIG_USB_GADGET
719int g_dnl_board_usb_cable_connected(void)
720{
Jagan Teki237050f2018-05-07 13:03:36 +0530721 struct udevice *dev;
722 struct phy phy;
723 int ret;
724
Jean-Jacques Hiblot01311622018-11-29 10:52:46 +0100725 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
Jagan Teki237050f2018-05-07 13:03:36 +0530726 if (ret) {
727 pr_err("%s: Cannot find USB device\n", __func__);
728 return ret;
729 }
730
731 ret = generic_phy_get_by_name(dev, "usb", &phy);
732 if (ret) {
733 pr_err("failed to get %s USB PHY\n", dev->name);
734 return ret;
735 }
736
737 ret = generic_phy_init(&phy);
738 if (ret) {
Patrick Delaunayf286e372020-07-03 17:36:41 +0200739 pr_debug("failed to init %s USB PHY\n", dev->name);
Jagan Teki237050f2018-05-07 13:03:36 +0530740 return ret;
741 }
742
743 ret = sun4i_usb_phy_vbus_detect(&phy);
744 if (ret == 1) {
745 pr_err("A charger is plugged into the OTG\n");
746 return -ENODEV;
747 }
748
749 return ret;
Paul Kocialkowskif1df7582015-03-22 18:07:13 +0100750}
751#endif
752
Paul Kocialkowski9f852212015-03-28 18:35:36 +0100753#ifdef CONFIG_SERIAL_TAG
754void get_board_serial(struct tag_serialnr *serialnr)
755{
756 char *serial_string;
757 unsigned long long serial;
758
Simon Glass00caae62017-08-03 12:22:12 -0600759 serial_string = env_get("serial#");
Paul Kocialkowski9f852212015-03-28 18:35:36 +0100760
761 if (serial_string) {
762 serial = simple_strtoull(serial_string, NULL, 16);
763
764 serialnr->high = (unsigned int) (serial >> 32);
765 serialnr->low = (unsigned int) (serial & 0xffffffff);
766 } else {
767 serialnr->high = 0;
768 serialnr->low = 0;
769 }
770}
771#endif
772
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200773/*
774 * Check the SPL header for the "sunxi" variant. If found: parse values
775 * that might have been passed by the loader ("fel" utility), and update
776 * the environment accordingly.
777 */
778static void parse_spl_header(const uint32_t spl_addr)
779{
Andre Przywaracff5c132018-10-25 17:23:04 +0800780 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200781
Andre Przywaracff5c132018-10-25 17:23:04 +0800782 if (spl == INVALID_SPL_HEADER)
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200783 return;
Andre Przywaracff5c132018-10-25 17:23:04 +0800784
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200785 if (!spl->fel_script_address)
786 return;
787
788 if (spl->fel_uEnv_length != 0) {
789 /*
790 * data is expected in uEnv.txt compatible format, so "env
791 * import -t" the string(s) at fel_script_address right away.
792 */
Andre Przywara5a74a392016-09-05 01:32:41 +0100793 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200794 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
795 return;
796 }
797 /* otherwise assume .scr format (mkimage-type script) */
Simon Glass018f5302017-08-03 12:22:10 -0600798 env_set_hex("fel_scriptaddr", spl->fel_script_address);
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200799}
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200800
Andre Heider928f4f42021-10-01 19:29:00 +0100801static bool get_unique_sid(unsigned int *sid)
802{
803 if (sunxi_get_sid(sid) != 0)
804 return false;
805
806 if (!sid[0])
807 return false;
808
809 /*
810 * The single words 1 - 3 of the SID have quite a few bits
811 * which are the same on many models, so we take a crc32
812 * of all 3 words, to get a more unique value.
813 *
814 * Note we only do this on newer SoCs as we cannot change
815 * the algorithm on older SoCs since those have been using
816 * fixed mac-addresses based on only using word 3 for a
817 * long time and changing a fixed mac-address with an
818 * u-boot update is not good.
819 */
820#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
821 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
822 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
823 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
824#endif
825
826 /* Ensure the NIC specific bytes of the mac are not all 0 */
827 if ((sid[3] & 0xffffff) == 0)
828 sid[3] |= 0x800000;
829
830 return true;
831}
832
Hans de Goedef2219612016-06-26 13:34:42 +0200833/*
834 * Note this function gets called multiple times.
835 * It must not make any changes to env variables which already exist.
836 */
837static void setup_environment(const void *fdt)
Jonathan Liub41d7d02014-06-14 08:59:09 +0200838{
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100839 char serial_string[17] = { 0 };
Hans de Goedecac5b1c2014-11-26 00:04:24 +0100840 unsigned int sid[4];
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100841 uint8_t mac_addr[6];
Hans de Goedef2219612016-06-26 13:34:42 +0200842 char ethaddr[16];
Andre Heider928f4f42021-10-01 19:29:00 +0100843 int i;
Hans de Goedef2219612016-06-26 13:34:42 +0200844
Andre Heider928f4f42021-10-01 19:29:00 +0100845 if (!get_unique_sid(sid))
846 return;
Hans de Goede3f8ea3b2016-07-29 11:47:03 +0200847
Andre Heider928f4f42021-10-01 19:29:00 +0100848 for (i = 0; i < 4; i++) {
849 sprintf(ethaddr, "ethernet%d", i);
850 if (!fdt_get_alias(fdt, ethaddr))
851 continue;
Hans de Goede97322c32016-07-27 17:58:06 +0200852
Andre Heider928f4f42021-10-01 19:29:00 +0100853 if (i == 0)
854 strcpy(ethaddr, "ethaddr");
855 else
856 sprintf(ethaddr, "eth%daddr", i);
Hans de Goedef2219612016-06-26 13:34:42 +0200857
Andre Heider928f4f42021-10-01 19:29:00 +0100858 if (env_get(ethaddr))
859 continue;
Hans de Goedef2219612016-06-26 13:34:42 +0200860
Andre Heider928f4f42021-10-01 19:29:00 +0100861 /* Non OUI / registered MAC address */
862 mac_addr[0] = (i << 4) | 0x02;
863 mac_addr[1] = (sid[0] >> 0) & 0xff;
864 mac_addr[2] = (sid[3] >> 24) & 0xff;
865 mac_addr[3] = (sid[3] >> 16) & 0xff;
866 mac_addr[4] = (sid[3] >> 8) & 0xff;
867 mac_addr[5] = (sid[3] >> 0) & 0xff;
Hans de Goedef2219612016-06-26 13:34:42 +0200868
Andre Heider928f4f42021-10-01 19:29:00 +0100869 eth_env_set_enetaddr(ethaddr, mac_addr);
870 }
Hans de Goedef2219612016-06-26 13:34:42 +0200871
Andre Heider928f4f42021-10-01 19:29:00 +0100872 if (!env_get("serial#")) {
873 snprintf(serial_string, sizeof(serial_string),
874 "%08x%08x", sid[0], sid[3]);
Hans de Goedef2219612016-06-26 13:34:42 +0200875
Andre Heider928f4f42021-10-01 19:29:00 +0100876 env_set("serial#", serial_string);
Hans de Goedef2219612016-06-26 13:34:42 +0200877 }
878}
879
Hans de Goedef2219612016-06-26 13:34:42 +0200880int misc_init_r(void)
881{
Samuel Holland20f3ee32020-10-24 10:21:54 -0500882 const char *spl_dt_name;
Maxime Ripardf4c35232017-08-23 10:08:29 +0200883 uint boot;
Jonathan Liub41d7d02014-06-14 08:59:09 +0200884
Simon Glass382bee52017-08-03 12:22:09 -0600885 env_set("fel_booted", NULL);
886 env_set("fel_scriptaddr", NULL);
Maxime Ripardde86fc32017-08-23 10:12:22 +0200887 env_set("mmc_bootdev", NULL);
Maxime Ripardf4c35232017-08-23 10:08:29 +0200888
889 boot = sunxi_get_boot_device();
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200890 /* determine if we are running in FEL mode */
Maxime Ripardf4c35232017-08-23 10:08:29 +0200891 if (boot == BOOT_DEVICE_BOARD) {
Simon Glass382bee52017-08-03 12:22:09 -0600892 env_set("fel_booted", "1");
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200893 parse_spl_header(SPL_ADDR);
Maxime Ripardde86fc32017-08-23 10:12:22 +0200894 /* or if we booted from MMC, and which one */
895 } else if (boot == BOOT_DEVICE_MMC1) {
896 env_set("mmc_bootdev", "0");
897 } else if (boot == BOOT_DEVICE_MMC2) {
898 env_set("mmc_bootdev", "1");
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200899 }
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200900
Samuel Holland20f3ee32020-10-24 10:21:54 -0500901 /* Set fdtfile to match the FIT configuration chosen in SPL. */
902 spl_dt_name = get_spl_dt_name();
903 if (spl_dt_name) {
904 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
905 char str[64];
906
907 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
908 env_set("fdtfile", str);
909 }
910
Hans de Goedef2219612016-06-26 13:34:42 +0200911 setup_environment(gd->fdt_blob);
Jonathan Liub41d7d02014-06-14 08:59:09 +0200912
Andy Shevchenko92600ed2020-12-08 17:45:31 +0200913 return 0;
914}
915
916int board_late_init(void)
917{
Icenowy Zhenge6ee85a2017-09-28 22:16:38 +0800918#ifdef CONFIG_USB_ETHER
Maxime Ripard90dd2f12017-09-06 22:25:03 +0200919 usb_ether_init();
Icenowy Zhenge6ee85a2017-09-28 22:16:38 +0800920#endif
Maxime Ripard90dd2f12017-09-06 22:25:03 +0200921
Jonathan Liub41d7d02014-06-14 08:59:09 +0200922 return 0;
923}
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200924
Andre Heider9267ff82021-10-01 19:29:00 +0100925static void bluetooth_dt_fixup(void *blob)
926{
927 /* Some devices ship with a Bluetooth controller default address.
928 * Set a valid address through the device tree.
929 */
930 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
931 unsigned int sid[4];
932 int i;
933
934 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
935 return;
936
937 if (eth_env_get_enetaddr("bdaddr", tmp)) {
938 /* Convert between the binary formats of the corresponding stacks */
939 for (i = 0; i < ETH_ALEN; ++i)
940 bdaddr[i] = tmp[ETH_ALEN - i - 1];
941 } else {
942 if (!get_unique_sid(sid))
943 return;
944
945 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
946 bdaddr[1] = (sid[3] >> 8) & 0xff;
947 bdaddr[2] = (sid[3] >> 16) & 0xff;
948 bdaddr[3] = (sid[3] >> 24) & 0xff;
949 bdaddr[4] = (sid[0] >> 0) & 0xff;
950 bdaddr[5] = 0x02;
951 }
952
953 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
954 "local-bd-address", bdaddr, ETH_ALEN, 1);
955}
956
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900957int ft_board_setup(void *blob, struct bd_info *bd)
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200958{
Hans de Goeded75111a2016-03-22 22:51:52 +0100959 int __maybe_unused r;
960
Hans de Goedef2219612016-06-26 13:34:42 +0200961 /*
962 * Call setup_environment again in case the boot fdt has
963 * ethernet aliases the u-boot copy does not have.
964 */
965 setup_environment(blob);
966
Andre Heider9267ff82021-10-01 19:29:00 +0100967 bluetooth_dt_fixup(blob);
968
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200969#ifdef CONFIG_VIDEO_DT_SIMPLEFB
Hans de Goeded75111a2016-03-22 22:51:52 +0100970 r = sunxi_simplefb_setup(blob);
971 if (r)
972 return r;
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200973#endif
Hans de Goeded75111a2016-03-22 22:51:52 +0100974 return 0;
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200975}
Andre Przywara9ea3c352017-04-26 01:32:44 +0100976
977#ifdef CONFIG_SPL_LOAD_FIT
Samuel Holland41530cf2020-10-24 10:21:53 -0500978
979static void set_spl_dt_name(const char *name)
980{
981 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
982
983 if (spl == INVALID_SPL_HEADER)
984 return;
985
986 /* Promote the header version for U-Boot proper, if needed. */
987 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
988 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
989
990 strcpy((char *)&spl->string_pool, name);
991 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
992}
993
Andre Przywara9ea3c352017-04-26 01:32:44 +0100994int board_fit_config_name_match(const char *name)
995{
Samuel Holland467b7e52020-10-24 10:21:50 -0500996 const char *best_dt_name = get_spl_dt_name();
Samuel Holland41530cf2020-10-24 10:21:53 -0500997 int ret;
Andre Przywara9ea3c352017-04-26 01:32:44 +0100998
999#ifdef CONFIG_DEFAULT_DEVICE_TREE
Samuel Holland467b7e52020-10-24 10:21:50 -05001000 if (best_dt_name == NULL)
Samuel Holland2fcd7482020-10-24 10:21:49 -05001001 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
Andre Przywara9ea3c352017-04-26 01:32:44 +01001002#endif
1003
Samuel Holland467b7e52020-10-24 10:21:50 -05001004 if (best_dt_name == NULL) {
1005 /* No DT name was provided, so accept the first config. */
1006 return 0;
1007 }
Icenowy Zhengc6c2c852018-10-25 17:23:02 +08001008#ifdef CONFIG_PINE64_DT_SELECTION
Samuel Holland54ac5aa2020-10-24 10:21:51 -05001009 if (strstr(best_dt_name, "-pine64-plus")) {
1010 /* Differentiate the Pine A64 boards by their DRAM size. */
1011 if ((gd->ram_size == 512 * 1024 * 1024))
1012 best_dt_name = "sun50i-a64-pine64";
Andre Przywara9ea3c352017-04-26 01:32:44 +01001013 }
Icenowy Zhengc6c2c852018-10-25 17:23:02 +08001014#endif
Samuel Holland8a8b73b2020-10-24 10:21:52 -05001015#ifdef CONFIG_PINEPHONE_DT_SELECTION
1016 if (strstr(best_dt_name, "-pinephone")) {
1017 /* Differentiate the PinePhone revisions by GPIO inputs. */
1018 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1019 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1020 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1021 udelay(100);
1022
1023 /* PL6 is pulled low by the modem on v1.2. */
1024 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1025 best_dt_name = "sun50i-a64-pinephone-1.2";
1026 else
1027 best_dt_name = "sun50i-a64-pinephone-1.1";
1028
1029 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1030 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1031 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1032 }
1033#endif
1034
Samuel Holland41530cf2020-10-24 10:21:53 -05001035 ret = strcmp(name, best_dt_name);
1036
1037 /*
1038 * If one of the FIT configurations matches the most accurate DT name,
1039 * update the SPL header to provide that DT name to U-Boot proper.
1040 */
1041 if (ret == 0)
1042 set_spl_dt_name(best_dt_name);
1043
1044 return ret;
Andre Przywara9ea3c352017-04-26 01:32:44 +01001045}
1046#endif