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Cyril Chemparathy2b629972012-07-24 12:22:16 +00001/*
2 * CPSW Ethernet Switch Driver
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _CPSW_H_
17#define _CPSW_H_
18
Faiz Abbas0229c932019-03-18 13:54:37 +053019/* reg offset */
20#define CPSW_HOST_PORT_OFFSET 0x108
21#define CPSW_SLAVE0_OFFSET 0x208
22#define CPSW_SLAVE1_OFFSET 0x308
23#define CPSW_SLAVE_SIZE 0x100
24#define CPSW_CPDMA_OFFSET 0x800
25#define CPSW_HW_STATS 0x900
26#define CPSW_STATERAM_OFFSET 0xa00
27#define CPSW_CPTS_OFFSET 0xc00
28#define CPSW_ALE_OFFSET 0xd00
29#define CPSW_SLIVER0_OFFSET 0xd80
30#define CPSW_SLIVER1_OFFSET 0xdc0
31#define CPSW_BD_OFFSET 0x2000
32#define CPSW_MDIO_DIV 0xff
33
34#define AM335X_GMII_SEL_OFFSET 0x630
35
Cyril Chemparathy2b629972012-07-24 12:22:16 +000036struct cpsw_slave_data {
37 u32 slave_reg_ofs;
38 u32 sliver_reg_ofs;
Mugunthan V N9c653aa2014-02-18 07:31:52 -050039 int phy_addr;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000040 int phy_if;
Dan Murphycb386222016-05-02 15:45:56 -050041 int phy_of_handle;
Grygorii Strashko3c57b622019-09-19 11:16:39 +030042 int max_speed;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000043};
44
45enum {
46 CPSW_CTRL_VERSION_1 = 0,
47 CPSW_CTRL_VERSION_2 /* am33xx like devices */
48};
49
50struct cpsw_platform_data {
51 u32 mdio_base;
52 u32 cpsw_base;
Mugunthan V N4cc77892015-09-07 14:22:21 +053053 u32 mac_id;
54 u32 gmii_sel;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000055 int mdio_div;
56 int channels; /* number of cpdma channels (symmetric) */
57 u32 cpdma_reg_ofs; /* cpdma register offset */
58 int slaves; /* number of slave cpgmac ports */
59 u32 ale_reg_ofs; /* address lookup engine reg offset */
60 int ale_entries; /* ale table size */
61 u32 host_port_reg_ofs; /* cpdma host port registers */
62 u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
Mugunthan V N2bf36ac2013-07-08 16:04:37 +053063 u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */
Cyril Chemparathy2b629972012-07-24 12:22:16 +000064 u32 mac_control;
65 struct cpsw_slave_data *slave_data;
66 void (*control)(int enabled);
67 u32 host_port_num;
Mugunthan V N7a022752014-05-22 14:37:10 +053068 u32 active_slave;
Mugunthan V Nab971532016-10-13 19:33:38 +053069 bool rmii_clock_external;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000070 u8 version;
Faiz Abbase50f8782019-03-18 13:54:32 +053071 const char *phy_sel_compat;
Faiz Abbasa58d2222019-03-18 13:54:34 +053072 u32 syscon_addr;
73 const char *macid_sel_compat;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000074};
75
76int cpsw_register(struct cpsw_platform_data *data);
Faiz Abbasa58d2222019-03-18 13:54:34 +053077int ti_cm_get_macid_addr(struct udevice *dev, int slave,
78 struct cpsw_platform_data *data);
79void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
80 u8 *mac_addr);
Sekhar Norie2597be2018-08-23 17:11:29 +053081int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
Cyril Chemparathy2b629972012-07-24 12:22:16 +000082
83#endif /* _CPSW_H_ */