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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
Michal Simekf4c7a4a2018-06-04 14:57:34 +020016static long do_fpga_get_device(char *arg)
17{
18 long dev = FPGA_INVALID_DEVICE;
19 char *devstr = env_get("fpga");
20
21 if (devstr)
22 /* Should be strtol to handle -1 cases */
23 dev = simple_strtol(devstr, NULL, 16);
24
25 if (arg)
26 dev = simple_strtol(arg, NULL, 16);
27
28 debug("%s: device = %ld\n", __func__, dev);
29
30 return dev;
31}
32
Michal Simek85754792018-06-04 15:51:23 +020033static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
34 cmd_tbl_t *cmdtp, int argc, char *const argv[])
35{
36 size_t local_data_size;
37 long local_fpga_data;
38
39 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
40
41 if (argc != cmdtp->maxargs) {
42 debug("fpga: incorrect parameters passed\n");
43 return CMD_RET_USAGE;
44 }
45
46 *dev = do_fpga_get_device(argv[0]);
47
48 local_fpga_data = simple_strtol(argv[1], NULL, 16);
49 if (!local_fpga_data) {
50 debug("fpga: zero fpga_data address\n");
51 return CMD_RET_USAGE;
52 }
53 *fpga_data = local_fpga_data;
54
55 local_data_size = simple_strtoul(argv[2], NULL, 16);
56 if (!local_data_size) {
57 debug("fpga: zero size\n");
58 return CMD_RET_USAGE;
59 }
60 *data_size = local_data_size;
61
62 return 0;
63}
64
wdenk4a9cbbe2002-08-27 09:48:53 +000065/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010066enum {
67 FPGA_NONE = -1,
Michal Simek5cf22282017-01-06 11:20:54 +010068 FPGA_LOADMK,
Michal Simek5cf22282017-01-06 11:20:54 +010069 FPGA_LOADFS,
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053070 FPGA_LOADS,
Michal Simek5cf22282017-01-06 11:20:54 +010071};
wdenk4a9cbbe2002-08-27 09:48:53 +000072
Michal Simek323fe382018-05-30 10:00:40 +020073/*
74 * Map op to supported operations. We don't use a table since we
75 * would just have to relocate it from flash anyway.
76 */
77static int fpga_get_op(char *opstr)
78{
79 int op = FPGA_NONE;
80
Michal Simek323fe382018-05-30 10:00:40 +020081#if defined(CONFIG_CMD_FPGA_LOADFS)
Michal Simek85754792018-06-04 15:51:23 +020082 if (!strcmp("loadfs", opstr))
Michal Simek323fe382018-05-30 10:00:40 +020083 op = FPGA_LOADFS;
84#endif
85#if defined(CONFIG_CMD_FPGA_LOADMK)
86 else if (!strcmp("loadmk", opstr))
87 op = FPGA_LOADMK;
88#endif
Michal Simek323fe382018-05-30 10:00:40 +020089#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
90 else if (!strcmp("loads", opstr))
91 op = FPGA_LOADS;
92#endif
93
94 return op;
95}
96
wdenk4a9cbbe2002-08-27 09:48:53 +000097/* ------------------------------------------------------------------------- */
98/* command form:
99 * fpga <op> <device number> <data addr> <datasize>
100 * where op is 'load', 'dump', or 'info'
101 * If there is no device number field, the fpga environment variable is used.
102 * If there is no data addr field, the fpgadata environment variable is used.
103 * The info command requires no data address field.
104 */
Michal Simekfc598412013-04-26 13:10:07 +0200105int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000106{
wdenkd4ca31c2004-01-02 14:00:00 +0000107 int op, dev = FPGA_INVALID_DEVICE;
108 size_t data_size = 0;
109 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -0600110 char *devstr = env_get("fpga");
111 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +0000112 int rc = FPGA_FAIL;
Michal Simekfc598412013-04-26 13:10:07 +0200113#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100114 const char *fit_uname = NULL;
115 ulong fit_addr;
116#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530117#if defined(CONFIG_CMD_FPGA_LOADFS)
118 fpga_fs_info fpga_fsinfo;
119 fpga_fsinfo.fstype = FS_TYPE_ANY;
120#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530121#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
122 struct fpga_secure_info fpga_sec_info;
123
124 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
125#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000126
wdenkd4ca31c2004-01-02 14:00:00 +0000127 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +0200128 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +0000129 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +0200130 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000131
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530132 if (argc > 9 || argc < 2) {
133 debug("%s: Too many or too few args (%d)\n", __func__, argc);
134 return CMD_RET_USAGE;
135 }
136
Michal Simek323fe382018-05-30 10:00:40 +0200137 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530138
139 switch (op) {
Michal Simek55010962018-05-30 09:57:42 +0200140 case FPGA_NONE:
141 printf("Unknown fpga operation \"%s\"\n", argv[1]);
142 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530143#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530144 case FPGA_LOADFS:
145 if (argc < 9)
146 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530147 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530148 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530149 fpga_fsinfo.interface = argv[6];
150 fpga_fsinfo.dev_part = argv[7];
151 fpga_fsinfo.filename = argv[8];
Michal Simek44d839b2018-05-30 11:18:38 +0200152
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530153 argc = 5;
154 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530155#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530156#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
157 case FPGA_LOADS:
158 if (argc < 7)
159 return CMD_RET_USAGE;
160 if (argc == 8)
161 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
162 simple_strtoull(argv[7],
163 NULL, 16);
164 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
165 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +0200166
167 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
168 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
169 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
170 return CMD_RET_USAGE;
171 }
172
173 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
174 !fpga_sec_info.userkey_addr) {
175 puts("ERR: User key not provided\n");
176 return CMD_RET_USAGE;
177 }
178
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530179 argc = 5;
180 break;
181#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530182 default:
183 break;
184 }
185
186 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +0000187 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +0200188 data_size = simple_strtoul(argv[4], NULL, 16);
Michal Simek5cadab62018-05-30 11:28:57 +0200189 if (!data_size) {
190 puts("Zero data_size\n");
191 return CMD_RET_USAGE;
192 }
wdenkd4ca31c2004-01-02 14:00:00 +0000193 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100194#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200195 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
196 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100197 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200198 debug("* fpga: subimage '%s' from FIT image ",
199 fit_uname);
200 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100201 } else
202#endif
203 {
Michal Simekfc598412013-04-26 13:10:07 +0200204 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000205 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200206 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100207 }
Michal Simek455ad582016-01-05 13:51:48 +0100208 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Michal Simek5cadab62018-05-30 11:28:57 +0200209 if (!fpga_data) {
210 puts("Zero fpga_data address\n");
211 return CMD_RET_USAGE;
212 }
wdenkd4ca31c2004-01-02 14:00:00 +0000213 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200214 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000215 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000216 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000217
Stefano Babica790b5b2010-10-19 09:22:52 +0200218 if (dev == FPGA_INVALID_DEVICE) {
219 puts("FPGA device not specified\n");
Michal Simekccd65202018-05-30 10:04:34 +0200220 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200221 }
222
223 switch (op) {
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530224#if defined(CONFIG_CMD_FPGA_LOADFS)
225 case FPGA_LOADFS:
226 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
227 break;
228#endif
229
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530230#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
231 case FPGA_LOADS:
232 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
233 break;
234#endif
235
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530236#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200237 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200238 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200239#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100240 case IMAGE_FORMAT_LEGACY:
241 {
Michal Simekfc598412013-04-26 13:10:07 +0200242 image_header_t *hdr =
243 (image_header_t *)fpga_data;
244 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200245 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200246
Michal Simek32d7cdd2013-10-04 10:51:01 +0200247 comp = image_get_comp(hdr);
248 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200249#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200250 ulong image_buf = image_get_data(hdr);
251 data = image_get_load(hdr);
252 ulong image_size = ~0UL;
253
254 if (gunzip((void *)data, ~0UL,
255 (void *)image_buf,
256 &image_size) != 0) {
257 puts("GUNZIP: error\n");
258 return 1;
259 }
260 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200261#else
262 puts("Gunzip image is not supported\n");
263 return 1;
264#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200265 } else {
266 data = (ulong)image_get_data(hdr);
267 data_size = image_get_data_size(hdr);
268 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200269 rc = fpga_load(dev, (void *)data, data_size,
270 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200271 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100272 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200273#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100274#if defined(CONFIG_FIT)
275 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100276 {
277 const void *fit_hdr = (const void *)fpga_data;
278 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000279 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100280
281 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200282 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100283 return 1;
284 }
285
Michal Simekfc598412013-04-26 13:10:07 +0200286 if (!fit_check_format(fit_hdr)) {
287 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100288 return 1;
289 }
290
291 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200292 noffset = fit_image_get_node(fit_hdr,
293 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100294 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200295 printf("Can't find '%s' FIT subimage\n",
296 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100297 return 1;
298 }
299
300 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000301 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100302 puts ("Bad Data Hash\n");
303 return 1;
304 }
305
306 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200307 if (fit_image_get_data(fit_hdr, noffset,
308 &fit_data, &data_size)) {
309 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100310 return 1;
311 }
312
Michal Simek7a78bd22014-05-02 14:09:30 +0200313 rc = fpga_load(dev, fit_data, data_size,
314 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100315 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100316 break;
317#endif
318 default:
Michal Simekfc598412013-04-26 13:10:07 +0200319 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100320 rc = FPGA_FAIL;
321 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200322 }
323 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530324#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200325
wdenkd4ca31c2004-01-02 14:00:00 +0000326 default:
Michal Simekfc598412013-04-26 13:10:07 +0200327 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000328 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000329 }
Michal Simekfc598412013-04-26 13:10:07 +0200330 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000331}
332
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200333static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
334 char * const argv[])
335{
336 long dev = do_fpga_get_device(argv[0]);
337
338 return fpga_info(dev);
339}
340
Michal Simek85754792018-06-04 15:51:23 +0200341static int do_fpga_dump(cmd_tbl_t *cmdtp, int flag, int argc,
342 char * const argv[])
343{
344 size_t data_size = 0;
345 long fpga_data, dev;
346 int ret;
347
348 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
349 cmdtp, argc, argv);
350 if (ret)
351 return ret;
352
353 return fpga_dump(dev, (void *)fpga_data, data_size);
354}
355
356static int do_fpga_load(cmd_tbl_t *cmdtp, int flag, int argc,
357 char * const argv[])
358{
359 size_t data_size = 0;
360 long fpga_data, dev;
361 int ret;
362
363 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
364 cmdtp, argc, argv);
365 if (ret)
366 return ret;
367
368 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
369}
370
371static int do_fpga_loadb(cmd_tbl_t *cmdtp, int flag, int argc,
372 char * const argv[])
373{
374 size_t data_size = 0;
375 long fpga_data, dev;
376 int ret;
377
378 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
379 cmdtp, argc, argv);
380 if (ret)
381 return ret;
382
383 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
384}
385
386#if defined(CONFIG_CMD_FPGA_LOADP)
387static int do_fpga_loadp(cmd_tbl_t *cmdtp, int flag, int argc,
388 char * const argv[])
389{
390 size_t data_size = 0;
391 long fpga_data, dev;
392 int ret;
393
394 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
395 cmdtp, argc, argv);
396 if (ret)
397 return ret;
398
399 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
400}
401#endif
402
403#if defined(CONFIG_CMD_FPGA_LOADBP)
404static int do_fpga_loadbp(cmd_tbl_t *cmdtp, int flag, int argc,
405 char * const argv[])
406{
407 size_t data_size = 0;
408 long fpga_data, dev;
409 int ret;
410
411 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
412 cmdtp, argc, argv);
413 if (ret)
414 return ret;
415
416 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
417 BIT_PARTIAL);
418}
419#endif
420
Michal Simek9657d972018-06-04 14:55:20 +0200421static cmd_tbl_t fpga_commands[] = {
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200422 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek85754792018-06-04 15:51:23 +0200423 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
424 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
425 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
426#if defined(CONFIG_CMD_FPGA_LOADP)
427 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
428#endif
429#if defined(CONFIG_CMD_FPGA_LOADBP)
430 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
431#endif
Michal Simek9657d972018-06-04 14:55:20 +0200432};
433
434static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
435 char *const argv[])
436{
437 cmd_tbl_t *fpga_cmd;
438 int ret;
439
440 if (argc < 2)
441 return CMD_RET_USAGE;
442
443 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
444 ARRAY_SIZE(fpga_commands));
445
446 /* This should be removed when all functions are converted */
447 if (!fpga_cmd)
448 return do_fpga(cmdtp, flag, argc, argv);
449
450 /* FIXME This can't be reached till all functions are converted */
451 if (!fpga_cmd) {
452 debug("fpga: non existing command\n");
453 return CMD_RET_USAGE;
454 }
455
456 argc -= 2;
457 argv += 2;
458
459 if (argc > fpga_cmd->maxargs) {
460 debug("fpga: more parameters passed\n");
461 return CMD_RET_USAGE;
462 }
463
464 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
465
466 return cmd_process_error(fpga_cmd, ret);
467}
468
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530469#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9657d972018-06-04 14:55:20 +0200470U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530471#else
Michal Simek9657d972018-06-04 14:55:20 +0200472U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530473#endif
Michal Simekfc598412013-04-26 13:10:07 +0200474 "loadable FPGA image support",
475 "[operation type] [device number] [image address] [image size]\n"
476 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100477 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200478 " info\t[dev]\t\t\tlist known device information\n"
479 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200480#if defined(CONFIG_CMD_FPGA_LOADP)
481 " loadp\t[dev] [address] [size]\t"
482 "Load device from memory buffer with partial bitstream\n"
483#endif
Michal Simekfc598412013-04-26 13:10:07 +0200484 " loadb\t[dev] [address] [size]\t"
485 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200486#if defined(CONFIG_CMD_FPGA_LOADBP)
487 " loadbp\t[dev] [address] [size]\t"
488 "Load device from bitstream buffer with partial bitstream"
489 "(Xilinx only)\n"
490#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530491#if defined(CONFIG_CMD_FPGA_LOADFS)
492 "Load device from filesystem (FAT by default) (Xilinx only)\n"
493 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
494 " [<dev[:part]>] <filename>\n"
495#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530496#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200497 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100498#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200499 "\n"
500 "\tFor loadmk operating on FIT format uImage address must include\n"
501 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100502#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530503#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530504#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
505 "Load encrypted bitstream (Xilinx only)\n"
506 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
507 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
508 "Loads the secure bistreams(authenticated/encrypted/both\n"
509 "authenticated and encrypted) of [size] from [address].\n"
510 "The auth-OCM/DDR flag specifies to perform authentication\n"
511 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
512 "The enc flag specifies which key to be used for decryption\n"
513 "0-device key, 1-user key, 2-no encryption.\n"
514 "The optional Userkey address specifies from which address key\n"
515 "has to be used for decryption if user key is selected.\n"
516 "NOTE: the sceure bitstream has to be created using xilinx\n"
517 "bootgen tool only.\n"
518#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100519);