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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8/*
9 * FPGA support
10 */
11#include <common.h>
12#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000013#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local functions */
Michal Simekfc598412013-04-26 13:10:07 +020017static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000018
19/* Local defines */
20#define FPGA_NONE -1
21#define FPGA_INFO 0
22#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000023#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000024#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020025#define FPGA_LOADMK 4
Michal Simek67193862014-05-02 13:43:39 +020026#define FPGA_LOADP 5
27#define FPGA_LOADBP 6
wdenk4a9cbbe2002-08-27 09:48:53 +000028
29/* ------------------------------------------------------------------------- */
30/* command form:
31 * fpga <op> <device number> <data addr> <datasize>
32 * where op is 'load', 'dump', or 'info'
33 * If there is no device number field, the fpga environment variable is used.
34 * If there is no data addr field, the fpgadata environment variable is used.
35 * The info command requires no data address field.
36 */
Michal Simekfc598412013-04-26 13:10:07 +020037int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000038{
wdenkd4ca31c2004-01-02 14:00:00 +000039 int op, dev = FPGA_INVALID_DEVICE;
40 size_t data_size = 0;
41 void *fpga_data = NULL;
Michal Simekfc598412013-04-26 13:10:07 +020042 char *devstr = getenv("fpga");
43 char *datastr = getenv("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +000044 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +020045 int wrong_parms = 0;
Michal Simekfc598412013-04-26 13:10:07 +020046#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010047 const char *fit_uname = NULL;
48 ulong fit_addr;
49#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000050
wdenkd4ca31c2004-01-02 14:00:00 +000051 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +020052 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +000053 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +020054 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000055
wdenkd4ca31c2004-01-02 14:00:00 +000056 switch (argc) {
57 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +020058 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010059
wdenkd4ca31c2004-01-02 14:00:00 +000060 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010061#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +020062 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
63 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010064 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +020065 debug("* fpga: subimage '%s' from FIT image ",
66 fit_uname);
67 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010068 } else
69#endif
70 {
Michal Simekfc598412013-04-26 13:10:07 +020071 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +000072 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +020073 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010074 }
Michal Simekfc598412013-04-26 13:10:07 +020075 debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010076
wdenkd4ca31c2004-01-02 14:00:00 +000077 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +020078 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +000079 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +000080 /* FIXME - this is a really weak test */
Michal Simekfc598412013-04-26 13:10:07 +020081 if ((argc == 3) && (dev > fpga_count())) {
82 /* must be buffer ptr */
Stefano Babic06297db2011-12-28 06:47:01 +000083 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simekfc598412013-04-26 13:10:07 +020084 __func__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010085
86#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +020087 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
88 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010089 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +020090 debug("* fpga: subimage '%s' from FIT image ",
91 fit_uname);
92 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010093 } else
94#endif
95 {
Michal Simekfc598412013-04-26 13:10:07 +020096 fpga_data = (void *)dev;
97 debug("* fpga: cmdline image addr = 0x%08lx\n",
98 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010099 }
100
Stefano Babic06297db2011-12-28 06:47:01 +0000101 debug("%s: fpga_data = 0x%x\n",
Michal Simekfc598412013-04-26 13:10:07 +0200102 __func__, (uint)fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000103 dev = FPGA_INVALID_DEVICE; /* reset device num */
104 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100105
wdenkd4ca31c2004-01-02 14:00:00 +0000106 case 2: /* fpga <op> */
Michal Simekfc598412013-04-26 13:10:07 +0200107 op = (int)fpga_get_op(argv[1]);
wdenkd4ca31c2004-01-02 14:00:00 +0000108 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100109
wdenkd4ca31c2004-01-02 14:00:00 +0000110 default:
Michal Simekfc598412013-04-26 13:10:07 +0200111 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000112 op = FPGA_NONE; /* force usage display */
113 break;
114 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000115
Stefano Babica790b5b2010-10-19 09:22:52 +0200116 if (dev == FPGA_INVALID_DEVICE) {
117 puts("FPGA device not specified\n");
118 op = FPGA_NONE;
119 }
120
121 switch (op) {
122 case FPGA_NONE:
123 case FPGA_INFO:
124 break;
125 case FPGA_LOAD:
Michal Simek67193862014-05-02 13:43:39 +0200126 case FPGA_LOADP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200127 case FPGA_LOADB:
Michal Simek67193862014-05-02 13:43:39 +0200128 case FPGA_LOADBP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200129 case FPGA_DUMP:
130 if (!fpga_data || !data_size)
131 wrong_parms = 1;
132 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530133#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babica790b5b2010-10-19 09:22:52 +0200134 case FPGA_LOADMK:
135 if (!fpga_data)
136 wrong_parms = 1;
137 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530138#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200139 }
140
141 if (wrong_parms) {
142 puts("Wrong parameters for FPGA request\n");
143 op = FPGA_NONE;
144 }
145
wdenkd4ca31c2004-01-02 14:00:00 +0000146 switch (op) {
147 case FPGA_NONE:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000148 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000149
wdenkd4ca31c2004-01-02 14:00:00 +0000150 case FPGA_INFO:
Michal Simekfc598412013-04-26 13:10:07 +0200151 rc = fpga_info(dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000152 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000153
wdenkd4ca31c2004-01-02 14:00:00 +0000154 case FPGA_LOAD:
Michal Simek7a78bd22014-05-02 14:09:30 +0200155 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenkd4ca31c2004-01-02 14:00:00 +0000156 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000157
Michal Simek67193862014-05-02 13:43:39 +0200158#if defined(CONFIG_CMD_FPGA_LOADP)
159 case FPGA_LOADP:
160 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
161 break;
162#endif
163
wdenk30ce5ab2005-01-09 18:12:51 +0000164 case FPGA_LOADB:
Michal Simek7a78bd22014-05-02 14:09:30 +0200165 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk30ce5ab2005-01-09 18:12:51 +0000166 break;
167
Michal Simek67193862014-05-02 13:43:39 +0200168#if defined(CONFIG_CMD_FPGA_LOADBP)
169 case FPGA_LOADBP:
170 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
171 break;
172#endif
173
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530174#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200175 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200176 switch (genimg_get_format(fpga_data)) {
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100177 case IMAGE_FORMAT_LEGACY:
178 {
Michal Simekfc598412013-04-26 13:10:07 +0200179 image_header_t *hdr =
180 (image_header_t *)fpga_data;
181 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200182 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200183
Michal Simek32d7cdd2013-10-04 10:51:01 +0200184 comp = image_get_comp(hdr);
185 if (comp == IH_COMP_GZIP) {
186 ulong image_buf = image_get_data(hdr);
187 data = image_get_load(hdr);
188 ulong image_size = ~0UL;
189
190 if (gunzip((void *)data, ~0UL,
191 (void *)image_buf,
192 &image_size) != 0) {
193 puts("GUNZIP: error\n");
194 return 1;
195 }
196 data_size = image_size;
197 } else {
198 data = (ulong)image_get_data(hdr);
199 data_size = image_get_data_size(hdr);
200 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200201 rc = fpga_load(dev, (void *)data, data_size,
202 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200203 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100204 break;
205#if defined(CONFIG_FIT)
206 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100207 {
208 const void *fit_hdr = (const void *)fpga_data;
209 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000210 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100211
212 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200213 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100214 return 1;
215 }
216
Michal Simekfc598412013-04-26 13:10:07 +0200217 if (!fit_check_format(fit_hdr)) {
218 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100219 return 1;
220 }
221
222 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200223 noffset = fit_image_get_node(fit_hdr,
224 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100225 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200226 printf("Can't find '%s' FIT subimage\n",
227 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100228 return 1;
229 }
230
231 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000232 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100233 puts ("Bad Data Hash\n");
234 return 1;
235 }
236
237 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200238 if (fit_image_get_data(fit_hdr, noffset,
239 &fit_data, &data_size)) {
240 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100241 return 1;
242 }
243
Michal Simek7a78bd22014-05-02 14:09:30 +0200244 rc = fpga_load(dev, fit_data, data_size,
245 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100246 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100247 break;
248#endif
249 default:
Michal Simekfc598412013-04-26 13:10:07 +0200250 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100251 rc = FPGA_FAIL;
252 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200253 }
254 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530255#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200256
wdenkd4ca31c2004-01-02 14:00:00 +0000257 case FPGA_DUMP:
Michal Simekfc598412013-04-26 13:10:07 +0200258 rc = fpga_dump(dev, fpga_data, data_size);
wdenkd4ca31c2004-01-02 14:00:00 +0000259 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000260
wdenkd4ca31c2004-01-02 14:00:00 +0000261 default:
Michal Simekfc598412013-04-26 13:10:07 +0200262 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000263 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000264 }
Michal Simekfc598412013-04-26 13:10:07 +0200265 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000266}
267
wdenk4a9cbbe2002-08-27 09:48:53 +0000268/*
269 * Map op to supported operations. We don't use a table since we
270 * would just have to relocate it from flash anyway.
271 */
Michal Simekfc598412013-04-26 13:10:07 +0200272static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000273{
274 int op = FPGA_NONE;
275
Michal Simekfc598412013-04-26 13:10:07 +0200276 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000277 op = FPGA_INFO;
Michal Simekfc598412013-04-26 13:10:07 +0200278 else if (!strcmp("loadb", opstr))
wdenk30ce5ab2005-01-09 18:12:51 +0000279 op = FPGA_LOADB;
Michal Simekfc598412013-04-26 13:10:07 +0200280 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000281 op = FPGA_LOAD;
Michal Simek67193862014-05-02 13:43:39 +0200282#if defined(CONFIG_CMD_FPGA_LOADP)
283 else if (!strcmp("loadp", opstr))
284 op = FPGA_LOADP;
285#endif
286#if defined(CONFIG_CMD_FPGA_LOADBP)
287 else if (!strcmp("loadbp", opstr))
288 op = FPGA_LOADBP;
289#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530290#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200291 else if (!strcmp("loadmk", opstr))
Stefan Roesef0ff4692006-08-15 14:15:51 +0200292 op = FPGA_LOADMK;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530293#endif
Michal Simekfc598412013-04-26 13:10:07 +0200294 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000295 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000296
Michal Simekfc598412013-04-26 13:10:07 +0200297 if (op == FPGA_NONE)
298 printf("Unknown fpga operation \"%s\"\n", opstr);
299
wdenk4a9cbbe2002-08-27 09:48:53 +0000300 return op;
301}
302
Michal Simekfc598412013-04-26 13:10:07 +0200303U_BOOT_CMD(fpga, 6, 1, do_fpga,
304 "loadable FPGA image support",
305 "[operation type] [device number] [image address] [image size]\n"
306 "fpga operations:\n"
307 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
308 " info\t[dev]\t\t\tlist known device information\n"
309 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200310#if defined(CONFIG_CMD_FPGA_LOADP)
311 " loadp\t[dev] [address] [size]\t"
312 "Load device from memory buffer with partial bitstream\n"
313#endif
Michal Simekfc598412013-04-26 13:10:07 +0200314 " loadb\t[dev] [address] [size]\t"
315 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200316#if defined(CONFIG_CMD_FPGA_LOADBP)
317 " loadbp\t[dev] [address] [size]\t"
318 "Load device from bitstream buffer with partial bitstream"
319 "(Xilinx only)\n"
320#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530321#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200322 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100323#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200324 "\n"
325 "\tFor loadmk operating on FIT format uImage address must include\n"
326 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100327#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530328#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100329);