blob: 4dc4dee0e0a61e1fc44ed6ab1510efeb89dcab21 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkdd7d41f2002-09-18 20:04:01 +00002/*
3 * (C) Copyright 2001
4 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
wdenkdd7d41f2002-09-18 20:04:01 +00005 */
6
7/*
8 * MII Utilities
9 */
10
11#include <common.h>
12#include <command.h>
wdenke35745b2004-04-18 23:32:11 +000013#include <miiphy.h>
14
wdenk24711112004-04-18 22:57:51 +000015typedef struct _MII_field_desc_t {
16 ushort hi;
17 ushort lo;
18 ushort mask;
Trent Piepho4ef32312019-05-09 19:23:39 +000019 const char *name;
wdenk24711112004-04-18 22:57:51 +000020} MII_field_desc_t;
21
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040022static const MII_field_desc_t reg_0_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000023 { 15, 15, 0x01, "reset" },
24 { 14, 14, 0x01, "loopback" },
25 { 13, 6, 0x81, "speed selection" }, /* special */
26 { 12, 12, 0x01, "A/N enable" },
27 { 11, 11, 0x01, "power-down" },
28 { 10, 10, 0x01, "isolate" },
29 { 9, 9, 0x01, "restart A/N" },
30 { 8, 8, 0x01, "duplex" }, /* special */
31 { 7, 7, 0x01, "collision test enable" },
32 { 5, 0, 0x3f, "(reserved)" }
33};
34
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040035static const MII_field_desc_t reg_1_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000036 { 15, 15, 0x01, "100BASE-T4 able" },
37 { 14, 14, 0x01, "100BASE-X full duplex able" },
38 { 13, 13, 0x01, "100BASE-X half duplex able" },
39 { 12, 12, 0x01, "10 Mbps full duplex able" },
40 { 11, 11, 0x01, "10 Mbps half duplex able" },
41 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
42 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
43 { 8, 8, 0x01, "extended status" },
44 { 7, 7, 0x01, "(reserved)" },
45 { 6, 6, 0x01, "MF preamble suppression" },
46 { 5, 5, 0x01, "A/N complete" },
47 { 4, 4, 0x01, "remote fault" },
48 { 3, 3, 0x01, "A/N able" },
49 { 2, 2, 0x01, "link status" },
50 { 1, 1, 0x01, "jabber detect" },
51 { 0, 0, 0x01, "extended capabilities" },
52};
53
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040054static const MII_field_desc_t reg_2_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000055 { 15, 0, 0xffff, "OUI portion" },
56};
57
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040058static const MII_field_desc_t reg_3_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000059 { 15, 10, 0x3f, "OUI portion" },
60 { 9, 4, 0x3f, "manufacturer part number" },
61 { 3, 0, 0x0f, "manufacturer rev. number" },
62};
63
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040064static const MII_field_desc_t reg_4_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000065 { 15, 15, 0x01, "next page able" },
Stephan Bauroth57d33d42013-08-08 13:44:41 +020066 { 14, 14, 0x01, "(reserved)" },
wdenk24711112004-04-18 22:57:51 +000067 { 13, 13, 0x01, "remote fault" },
Stephan Bauroth57d33d42013-08-08 13:44:41 +020068 { 12, 12, 0x01, "(reserved)" },
wdenk24711112004-04-18 22:57:51 +000069 { 11, 11, 0x01, "asymmetric pause" },
70 { 10, 10, 0x01, "pause enable" },
71 { 9, 9, 0x01, "100BASE-T4 able" },
72 { 8, 8, 0x01, "100BASE-TX full duplex able" },
73 { 7, 7, 0x01, "100BASE-TX able" },
74 { 6, 6, 0x01, "10BASE-T full duplex able" },
75 { 5, 5, 0x01, "10BASE-T able" },
Trent Piepho4ef32312019-05-09 19:23:39 +000076 { 4, 0, 0x1f, "selector" },
wdenk24711112004-04-18 22:57:51 +000077};
78
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040079static const MII_field_desc_t reg_5_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000080 { 15, 15, 0x01, "next page able" },
81 { 14, 14, 0x01, "acknowledge" },
82 { 13, 13, 0x01, "remote fault" },
83 { 12, 12, 0x01, "(reserved)" },
84 { 11, 11, 0x01, "asymmetric pause able" },
85 { 10, 10, 0x01, "pause able" },
86 { 9, 9, 0x01, "100BASE-T4 able" },
87 { 8, 8, 0x01, "100BASE-X full duplex able" },
88 { 7, 7, 0x01, "100BASE-TX able" },
89 { 6, 6, 0x01, "10BASE-T full duplex able" },
90 { 5, 5, 0x01, "10BASE-T able" },
Trent Piepho4ef32312019-05-09 19:23:39 +000091 { 4, 0, 0x1f, "partner selector" },
wdenk24711112004-04-18 22:57:51 +000092};
Trent Piepho4ef32312019-05-09 19:23:39 +000093
94typedef struct _MII_reg_desc_t {
95 ushort regno;
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040096 const MII_field_desc_t *pdesc;
wdenk24711112004-04-18 22:57:51 +000097 ushort len;
Trent Piepho4ef32312019-05-09 19:23:39 +000098 const char *name;
99} MII_reg_desc_t;
wdenk24711112004-04-18 22:57:51 +0000100
Trent Piepho4ef32312019-05-09 19:23:39 +0000101static const MII_reg_desc_t mii_reg_desc_tbl[] = {
102 { MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
103 "PHY control register" },
104 { MII_BMSR, reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
105 "PHY status register" },
106 { MII_PHYSID1, reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
107 "PHY ID 1 register" },
108 { MII_PHYSID2, reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
109 "PHY ID 2 register" },
110 { MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
111 "Autonegotiation advertisement register" },
112 { MII_LPA, reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
113 "Autonegotiation partner abilities register" },
wdenk24711112004-04-18 22:57:51 +0000114};
115
116static void dump_reg(
117 ushort regval,
Trent Piepho4ef32312019-05-09 19:23:39 +0000118 const MII_reg_desc_t *prd);
wdenk24711112004-04-18 22:57:51 +0000119
Trent Piepho4ef32312019-05-09 19:23:39 +0000120static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
121 ushort regval);
wdenk24711112004-04-18 22:57:51 +0000122
Trent Piepho4ef32312019-05-09 19:23:39 +0000123static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
wdenk24711112004-04-18 22:57:51 +0000124{
125 ulong i;
126
Trent Piepho4ef32312019-05-09 19:23:39 +0000127 for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
128 const uchar reg = mii_reg_desc_tbl[i].regno;
129
130 if (reg >= reglo && reg <= reghi)
131 dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
wdenk24711112004-04-18 22:57:51 +0000132 }
133}
134
Trent Piepho4ef32312019-05-09 19:23:39 +0000135/* Print out field position, value, name */
136static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
137{
138 if (pdesc->hi == pdesc->lo)
139 printf("%2u ", pdesc->lo);
140 else
141 printf("%2u-%2u", pdesc->hi, pdesc->lo);
142
143 printf(" = %5u %s", (regval >> pdesc->lo) & pdesc->mask,
144 pdesc->name);
145}
146
wdenk24711112004-04-18 22:57:51 +0000147static void dump_reg(
148 ushort regval,
Trent Piepho4ef32312019-05-09 19:23:39 +0000149 const MII_reg_desc_t *prd)
wdenk24711112004-04-18 22:57:51 +0000150{
151 ulong i;
152 ushort mask_in_place;
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400153 const MII_field_desc_t *pdesc;
wdenk24711112004-04-18 22:57:51 +0000154
155 printf("%u. (%04hx) -- %s --\n",
156 prd->regno, regval, prd->name);
157
Trent Piepho4ef32312019-05-09 19:23:39 +0000158 for (i = 0; i < prd->len; i++) {
159 pdesc = &prd->pdesc[i];
wdenk24711112004-04-18 22:57:51 +0000160
161 mask_in_place = pdesc->mask << pdesc->lo;
162
Jeroen Hofsteec68112f2014-07-13 23:44:21 +0200163 printf(" (%04hx:%04x) %u.",
164 mask_in_place,
165 regval & mask_in_place,
166 prd->regno);
wdenk24711112004-04-18 22:57:51 +0000167
Trent Piepho4ef32312019-05-09 19:23:39 +0000168 if (!special_field(prd->regno, pdesc, regval))
169 dump_field(pdesc, regval);
wdenk24711112004-04-18 22:57:51 +0000170 printf("\n");
171
172 }
173 printf("\n");
174}
175
176/* Special fields:
177** 0.6,13
178** 0.8
179** 2.15-0
180** 3.15-0
181** 4.4-0
182** 5.4-0
183*/
184
Trent Piepho4ef32312019-05-09 19:23:39 +0000185static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
186 ushort regval)
wdenk24711112004-04-18 22:57:51 +0000187{
Trent Piepho4ef32312019-05-09 19:23:39 +0000188 const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
189
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500190 if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
191 ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100);
wdenk24711112004-04-18 22:57:51 +0000192 printf("%2u,%2u = b%u%u speed selection = %s Mbps",
193 6, 13,
194 (regval >> 6) & 1,
195 (regval >> 13) & 1,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500196 speed_bits == BMCR_SPEED1000 ? "1000" :
197 speed_bits == BMCR_SPEED100 ? "100" :
198 "10");
wdenk24711112004-04-18 22:57:51 +0000199 return 1;
200 }
201
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500202 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000203 dump_field(pdesc, regval);
204 printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
wdenk24711112004-04-18 22:57:51 +0000205 return 1;
206 }
207
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500208 else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000209 dump_field(pdesc, regval);
210 printf(" = %s",
211 sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
212 sel_bits == PHY_ANLPAR_PSB_802_9 ?
213 "IEEE 802.9 ISLAN-16T" : "???");
wdenk24711112004-04-18 22:57:51 +0000214 return 1;
215 }
216
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500217 else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000218 dump_field(pdesc, regval);
219 printf(" = %s",
220 sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
221 sel_bits == PHY_ANLPAR_PSB_802_9 ?
222 "IEEE 802.9 ISLAN-16T" : "???");
wdenk24711112004-04-18 22:57:51 +0000223 return 1;
224 }
225
226 return 0;
227}
228
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400229static char last_op[2];
230static uint last_data;
231static uint last_addr_lo;
232static uint last_addr_hi;
233static uint last_reg_lo;
234static uint last_reg_hi;
Tim Jamesa095f042015-03-25 11:55:15 +0000235static uint last_mask;
wdenk24711112004-04-18 22:57:51 +0000236
237static void extract_range(
238 char * input,
239 unsigned char * plo,
240 unsigned char * phi)
241{
242 char * end;
243 *plo = simple_strtoul(input, &end, 16);
244 if (*end == '-') {
245 end++;
246 *phi = simple_strtoul(end, NULL, 16);
247 }
248 else {
249 *phi = *plo;
250 }
251}
252
wdenk5cf91d62004-04-23 20:32:05 +0000253/* ---------------------------------------------------------------- */
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400254static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk24711112004-04-18 22:57:51 +0000255{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200256 char op[2];
wdenk24711112004-04-18 22:57:51 +0000257 unsigned char addrlo, addrhi, reglo, reghi;
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200258 unsigned char addr, reg;
Tim Jamesa095f042015-03-25 11:55:15 +0000259 unsigned short data, mask;
wdenk24711112004-04-18 22:57:51 +0000260 int rcode = 0;
Mike Frysinger5700bb62010-07-27 18:35:08 -0400261 const char *devname;
wdenk24711112004-04-18 22:57:51 +0000262
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200263 if (argc < 2)
Simon Glass4c12eeb2011-12-10 08:44:01 +0000264 return CMD_RET_USAGE;
Shinya Kuribayashib9173af2007-12-27 15:39:54 +0900265
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500266#if defined(CONFIG_MII_INIT)
wdenk24711112004-04-18 22:57:51 +0000267 mii_init ();
268#endif
269
270 /*
271 * We use the last specified parameters, unless new ones are
272 * entered.
273 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200274 op[0] = last_op[0];
275 op[1] = last_op[1];
wdenk24711112004-04-18 22:57:51 +0000276 addrlo = last_addr_lo;
277 addrhi = last_addr_hi;
278 reglo = last_reg_lo;
279 reghi = last_reg_hi;
280 data = last_data;
Tim Jamesa095f042015-03-25 11:55:15 +0000281 mask = last_mask;
wdenk24711112004-04-18 22:57:51 +0000282
283 if ((flag & CMD_FLAG_REPEAT) == 0) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200284 op[0] = argv[1][0];
285 if (strlen(argv[1]) > 1)
286 op[1] = argv[1][1];
287 else
288 op[1] = '\0';
289
wdenk24711112004-04-18 22:57:51 +0000290 if (argc >= 3)
291 extract_range(argv[2], &addrlo, &addrhi);
292 if (argc >= 4)
293 extract_range(argv[3], &reglo, &reghi);
294 if (argc >= 5)
Tim Jamesa095f042015-03-25 11:55:15 +0000295 data = simple_strtoul(argv[4], NULL, 16);
296 if (argc >= 6)
297 mask = simple_strtoul(argv[5], NULL, 16);
wdenk24711112004-04-18 22:57:51 +0000298 }
299
Hector Palaciosfb265a72018-08-17 13:06:40 +0200300 if (addrhi > 31 && strncmp(op, "de", 2)) {
Michal Simekbdaeb8f2015-10-19 15:13:34 +0200301 printf("Incorrect PHY address. Range should be 0-31\n");
302 return CMD_RET_USAGE;
303 }
304
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200305 /* use current device */
306 devname = miiphy_get_current_dev();
307
wdenk24711112004-04-18 22:57:51 +0000308 /*
309 * check info/read/write.
310 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200311 if (op[0] == 'i') {
wdenk24711112004-04-18 22:57:51 +0000312 unsigned char j, start, end;
313 unsigned int oui;
314 unsigned char model;
315 unsigned char rev;
316
317 /*
318 * Look for any and all PHYs. Valid addresses are 0..31.
319 */
320 if (argc >= 3) {
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200321 start = addrlo; end = addrhi;
wdenk24711112004-04-18 22:57:51 +0000322 } else {
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200323 start = 0; end = 31;
wdenk24711112004-04-18 22:57:51 +0000324 }
325
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200326 for (j = start; j <= end; j++) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200327 if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
wdenk24711112004-04-18 22:57:51 +0000328 printf("PHY 0x%02X: "
329 "OUI = 0x%04X, "
330 "Model = 0x%02X, "
331 "Rev = 0x%02X, "
Larry Johnson71bc6e62007-11-01 08:46:50 -0500332 "%3dbase%s, %s\n",
wdenk24711112004-04-18 22:57:51 +0000333 j, oui, model, rev,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200334 miiphy_speed (devname, j),
Larry Johnson71bc6e62007-11-01 08:46:50 -0500335 miiphy_is_1000base_x (devname, j)
336 ? "X" : "T",
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200337 (miiphy_duplex (devname, j) == FULL)
338 ? "FDX" : "HDX");
wdenk24711112004-04-18 22:57:51 +0000339 }
340 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200341 } else if (op[0] == 'r') {
wdenk24711112004-04-18 22:57:51 +0000342 for (addr = addrlo; addr <= addrhi; addr++) {
343 for (reg = reglo; reg <= reghi; reg++) {
344 data = 0xffff;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200345 if (miiphy_read (devname, addr, reg, &data) != 0) {
wdenk24711112004-04-18 22:57:51 +0000346 printf(
347 "Error reading from the PHY addr=%02x reg=%02x\n",
348 addr, reg);
349 rcode = 1;
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200350 } else {
wdenk24711112004-04-18 22:57:51 +0000351 if ((addrlo != addrhi) || (reglo != reghi))
352 printf("addr=%02x reg=%02x data=",
353 (uint)addr, (uint)reg);
354 printf("%04X\n", data & 0x0000FFFF);
355 }
356 }
357 if ((addrlo != addrhi) && (reglo != reghi))
358 printf("\n");
359 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200360 } else if (op[0] == 'w') {
wdenk24711112004-04-18 22:57:51 +0000361 for (addr = addrlo; addr <= addrhi; addr++) {
362 for (reg = reglo; reg <= reghi; reg++) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200363 if (miiphy_write (devname, addr, reg, data) != 0) {
wdenk24711112004-04-18 22:57:51 +0000364 printf("Error writing to the PHY addr=%02x reg=%02x\n",
365 addr, reg);
366 rcode = 1;
367 }
368 }
369 }
Tim Jamesa095f042015-03-25 11:55:15 +0000370 } else if (op[0] == 'm') {
371 for (addr = addrlo; addr <= addrhi; addr++) {
372 for (reg = reglo; reg <= reghi; reg++) {
373 unsigned short val = 0;
374 if (miiphy_read(devname, addr,
375 reg, &val)) {
376 printf("Error reading from the PHY");
377 printf(" addr=%02x", addr);
378 printf(" reg=%02x\n", reg);
379 rcode = 1;
380 } else {
381 val = (val & ~mask) | (data & mask);
382 if (miiphy_write(devname, addr,
383 reg, val)) {
384 printf("Error writing to the PHY");
385 printf(" addr=%02x", addr);
386 printf(" reg=%02x\n", reg);
387 rcode = 1;
388 }
389 }
390 }
391 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200392 } else if (strncmp(op, "du", 2) == 0) {
wdenk24711112004-04-18 22:57:51 +0000393 ushort regs[6];
394 int ok = 1;
395 if ((reglo > 5) || (reghi > 5)) {
396 printf(
397 "The MII dump command only formats the "
398 "standard MII registers, 0-5.\n");
399 return 1;
400 }
401 for (addr = addrlo; addr <= addrhi; addr++) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000402 for (reg = reglo; reg <= reghi; reg++) {
403 if (miiphy_read(devname, addr, reg,
404 &regs[reg - reglo]) != 0) {
wdenk24711112004-04-18 22:57:51 +0000405 ok = 0;
406 printf(
407 "Error reading from the PHY addr=%02x reg=%02x\n",
408 addr, reg);
409 rcode = 1;
410 }
411 }
412 if (ok)
Trent Piepho4ef32312019-05-09 19:23:39 +0000413 MII_dump(regs, reglo, reghi);
wdenk24711112004-04-18 22:57:51 +0000414 printf("\n");
415 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200416 } else if (strncmp(op, "de", 2) == 0) {
417 if (argc == 2)
418 miiphy_listdev ();
419 else
420 miiphy_set_current_dev (argv[2]);
wdenk24711112004-04-18 22:57:51 +0000421 } else {
Simon Glass4c12eeb2011-12-10 08:44:01 +0000422 return CMD_RET_USAGE;
wdenk24711112004-04-18 22:57:51 +0000423 }
424
425 /*
426 * Save the parameters for repeats.
427 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200428 last_op[0] = op[0];
429 last_op[1] = op[1];
wdenk24711112004-04-18 22:57:51 +0000430 last_addr_lo = addrlo;
431 last_addr_hi = addrhi;
432 last_reg_lo = reglo;
433 last_reg_hi = reghi;
434 last_data = data;
Tim Jamesa095f042015-03-25 11:55:15 +0000435 last_mask = mask;
wdenk24711112004-04-18 22:57:51 +0000436
437 return rcode;
438}
439
440/***************************************************/
441
442U_BOOT_CMD(
Tim Jamesa095f042015-03-25 11:55:15 +0000443 mii, 6, 1, do_mii,
Peter Tyser2fb26042009-01-27 18:03:12 -0600444 "MII utility commands",
Tim Jamesa095f042015-03-25 11:55:15 +0000445 "device - list available devices\n"
446 "mii device <devname> - set current device\n"
447 "mii info <addr> - display MII PHY info\n"
448 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
449 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
450 "mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
451 " updating bits identified in <mask>\n"
452 "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200453 "Addr and/or reg may be ranges, e.g. 2-7."
wdenk24711112004-04-18 22:57:51 +0000454);