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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010017enum {
18 FPGA_NONE = -1,
19 FPGA_INFO,
20 FPGA_LOAD,
21 FPGA_LOADB,
22 FPGA_DUMP,
23 FPGA_LOADMK,
24 FPGA_LOADP,
25 FPGA_LOADBP,
26 FPGA_LOADFS,
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053027 FPGA_LOADS,
Michal Simek5cf22282017-01-06 11:20:54 +010028};
wdenk4a9cbbe2002-08-27 09:48:53 +000029
Michal Simek323fe382018-05-30 10:00:40 +020030/*
31 * Map op to supported operations. We don't use a table since we
32 * would just have to relocate it from flash anyway.
33 */
34static int fpga_get_op(char *opstr)
35{
36 int op = FPGA_NONE;
37
38 if (!strcmp("info", opstr))
39 op = FPGA_INFO;
40 else if (!strcmp("loadb", opstr))
41 op = FPGA_LOADB;
42 else if (!strcmp("load", opstr))
43 op = FPGA_LOAD;
44#if defined(CONFIG_CMD_FPGA_LOADP)
45 else if (!strcmp("loadp", opstr))
46 op = FPGA_LOADP;
47#endif
48#if defined(CONFIG_CMD_FPGA_LOADBP)
49 else if (!strcmp("loadbp", opstr))
50 op = FPGA_LOADBP;
51#endif
52#if defined(CONFIG_CMD_FPGA_LOADFS)
53 else if (!strcmp("loadfs", opstr))
54 op = FPGA_LOADFS;
55#endif
56#if defined(CONFIG_CMD_FPGA_LOADMK)
57 else if (!strcmp("loadmk", opstr))
58 op = FPGA_LOADMK;
59#endif
60 else if (!strcmp("dump", opstr))
61 op = FPGA_DUMP;
62#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
63 else if (!strcmp("loads", opstr))
64 op = FPGA_LOADS;
65#endif
66
67 return op;
68}
69
wdenk4a9cbbe2002-08-27 09:48:53 +000070/* ------------------------------------------------------------------------- */
71/* command form:
72 * fpga <op> <device number> <data addr> <datasize>
73 * where op is 'load', 'dump', or 'info'
74 * If there is no device number field, the fpga environment variable is used.
75 * If there is no data addr field, the fpgadata environment variable is used.
76 * The info command requires no data address field.
77 */
Michal Simekfc598412013-04-26 13:10:07 +020078int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000079{
wdenkd4ca31c2004-01-02 14:00:00 +000080 int op, dev = FPGA_INVALID_DEVICE;
81 size_t data_size = 0;
82 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -060083 char *devstr = env_get("fpga");
84 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +000085 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +020086 int wrong_parms = 0;
Michal Simekfc598412013-04-26 13:10:07 +020087#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010088 const char *fit_uname = NULL;
89 ulong fit_addr;
90#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053091#if defined(CONFIG_CMD_FPGA_LOADFS)
92 fpga_fs_info fpga_fsinfo;
93 fpga_fsinfo.fstype = FS_TYPE_ANY;
94#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053095#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
96 struct fpga_secure_info fpga_sec_info;
97
98 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
99#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000100
wdenkd4ca31c2004-01-02 14:00:00 +0000101 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +0200102 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +0000103 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +0200104 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000105
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530106 if (argc > 9 || argc < 2) {
107 debug("%s: Too many or too few args (%d)\n", __func__, argc);
108 return CMD_RET_USAGE;
109 }
110
Michal Simek323fe382018-05-30 10:00:40 +0200111 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530112
113 switch (op) {
Michal Simek55010962018-05-30 09:57:42 +0200114 case FPGA_NONE:
115 printf("Unknown fpga operation \"%s\"\n", argv[1]);
116 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530117#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530118 case FPGA_LOADFS:
119 if (argc < 9)
120 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530121 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530122 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530123 fpga_fsinfo.interface = argv[6];
124 fpga_fsinfo.dev_part = argv[7];
125 fpga_fsinfo.filename = argv[8];
Michal Simek44d839b2018-05-30 11:18:38 +0200126
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530127 argc = 5;
128 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530129#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530130#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
131 case FPGA_LOADS:
132 if (argc < 7)
133 return CMD_RET_USAGE;
134 if (argc == 8)
135 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
136 simple_strtoull(argv[7],
137 NULL, 16);
138 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
139 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +0200140
141 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
142 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
143 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
144 return CMD_RET_USAGE;
145 }
146
147 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
148 !fpga_sec_info.userkey_addr) {
149 puts("ERR: User key not provided\n");
150 return CMD_RET_USAGE;
151 }
152
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530153 argc = 5;
154 break;
155#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530156 default:
157 break;
158 }
159
160 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +0000161 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +0200162 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100163
wdenkd4ca31c2004-01-02 14:00:00 +0000164 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100165#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200166 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
167 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100168 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200169 debug("* fpga: subimage '%s' from FIT image ",
170 fit_uname);
171 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100172 } else
173#endif
174 {
Michal Simekfc598412013-04-26 13:10:07 +0200175 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000176 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200177 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100178 }
Michal Simek455ad582016-01-05 13:51:48 +0100179 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100180
wdenkd4ca31c2004-01-02 14:00:00 +0000181 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200182 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000183 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000184 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000185
Stefano Babica790b5b2010-10-19 09:22:52 +0200186 if (dev == FPGA_INVALID_DEVICE) {
187 puts("FPGA device not specified\n");
Michal Simekccd65202018-05-30 10:04:34 +0200188 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200189 }
190
191 switch (op) {
Stefano Babica790b5b2010-10-19 09:22:52 +0200192 case FPGA_INFO:
193 break;
194 case FPGA_LOAD:
Michal Simek67193862014-05-02 13:43:39 +0200195 case FPGA_LOADP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200196 case FPGA_LOADB:
Michal Simek67193862014-05-02 13:43:39 +0200197 case FPGA_LOADBP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200198 case FPGA_DUMP:
199 if (!fpga_data || !data_size)
200 wrong_parms = 1;
201 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530202#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babica790b5b2010-10-19 09:22:52 +0200203 case FPGA_LOADMK:
204 if (!fpga_data)
205 wrong_parms = 1;
206 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530207#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200208 }
209
210 if (wrong_parms) {
211 puts("Wrong parameters for FPGA request\n");
Michal Simekccd65202018-05-30 10:04:34 +0200212 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200213 }
214
wdenkd4ca31c2004-01-02 14:00:00 +0000215 switch (op) {
wdenkd4ca31c2004-01-02 14:00:00 +0000216 case FPGA_INFO:
Michal Simekfc598412013-04-26 13:10:07 +0200217 rc = fpga_info(dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000218 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000219
wdenkd4ca31c2004-01-02 14:00:00 +0000220 case FPGA_LOAD:
Michal Simek7a78bd22014-05-02 14:09:30 +0200221 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenkd4ca31c2004-01-02 14:00:00 +0000222 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000223
Michal Simek67193862014-05-02 13:43:39 +0200224#if defined(CONFIG_CMD_FPGA_LOADP)
225 case FPGA_LOADP:
226 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
227 break;
228#endif
229
wdenk30ce5ab2005-01-09 18:12:51 +0000230 case FPGA_LOADB:
Michal Simek7a78bd22014-05-02 14:09:30 +0200231 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk30ce5ab2005-01-09 18:12:51 +0000232 break;
233
Michal Simek67193862014-05-02 13:43:39 +0200234#if defined(CONFIG_CMD_FPGA_LOADBP)
235 case FPGA_LOADBP:
236 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
237 break;
238#endif
239
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530240#if defined(CONFIG_CMD_FPGA_LOADFS)
241 case FPGA_LOADFS:
242 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
243 break;
244#endif
245
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530246#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
247 case FPGA_LOADS:
248 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
249 break;
250#endif
251
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530252#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200253 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200254 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200255#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100256 case IMAGE_FORMAT_LEGACY:
257 {
Michal Simekfc598412013-04-26 13:10:07 +0200258 image_header_t *hdr =
259 (image_header_t *)fpga_data;
260 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200261 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200262
Michal Simek32d7cdd2013-10-04 10:51:01 +0200263 comp = image_get_comp(hdr);
264 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200265#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200266 ulong image_buf = image_get_data(hdr);
267 data = image_get_load(hdr);
268 ulong image_size = ~0UL;
269
270 if (gunzip((void *)data, ~0UL,
271 (void *)image_buf,
272 &image_size) != 0) {
273 puts("GUNZIP: error\n");
274 return 1;
275 }
276 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200277#else
278 puts("Gunzip image is not supported\n");
279 return 1;
280#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200281 } else {
282 data = (ulong)image_get_data(hdr);
283 data_size = image_get_data_size(hdr);
284 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200285 rc = fpga_load(dev, (void *)data, data_size,
286 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200287 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100288 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200289#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100290#if defined(CONFIG_FIT)
291 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100292 {
293 const void *fit_hdr = (const void *)fpga_data;
294 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000295 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100296
297 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200298 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100299 return 1;
300 }
301
Michal Simekfc598412013-04-26 13:10:07 +0200302 if (!fit_check_format(fit_hdr)) {
303 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100304 return 1;
305 }
306
307 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200308 noffset = fit_image_get_node(fit_hdr,
309 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100310 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200311 printf("Can't find '%s' FIT subimage\n",
312 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100313 return 1;
314 }
315
316 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000317 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100318 puts ("Bad Data Hash\n");
319 return 1;
320 }
321
322 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200323 if (fit_image_get_data(fit_hdr, noffset,
324 &fit_data, &data_size)) {
325 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100326 return 1;
327 }
328
Michal Simek7a78bd22014-05-02 14:09:30 +0200329 rc = fpga_load(dev, fit_data, data_size,
330 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100331 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100332 break;
333#endif
334 default:
Michal Simekfc598412013-04-26 13:10:07 +0200335 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100336 rc = FPGA_FAIL;
337 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200338 }
339 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530340#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200341
wdenkd4ca31c2004-01-02 14:00:00 +0000342 case FPGA_DUMP:
Michal Simekfc598412013-04-26 13:10:07 +0200343 rc = fpga_dump(dev, fpga_data, data_size);
wdenkd4ca31c2004-01-02 14:00:00 +0000344 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000345
wdenkd4ca31c2004-01-02 14:00:00 +0000346 default:
Michal Simekfc598412013-04-26 13:10:07 +0200347 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000348 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000349 }
Michal Simekfc598412013-04-26 13:10:07 +0200350 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000351}
352
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530353#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530354U_BOOT_CMD(fpga, 9, 1, do_fpga,
355#else
Michal Simekfc598412013-04-26 13:10:07 +0200356U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530357#endif
Michal Simekfc598412013-04-26 13:10:07 +0200358 "loadable FPGA image support",
359 "[operation type] [device number] [image address] [image size]\n"
360 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100361 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200362 " info\t[dev]\t\t\tlist known device information\n"
363 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200364#if defined(CONFIG_CMD_FPGA_LOADP)
365 " loadp\t[dev] [address] [size]\t"
366 "Load device from memory buffer with partial bitstream\n"
367#endif
Michal Simekfc598412013-04-26 13:10:07 +0200368 " loadb\t[dev] [address] [size]\t"
369 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200370#if defined(CONFIG_CMD_FPGA_LOADBP)
371 " loadbp\t[dev] [address] [size]\t"
372 "Load device from bitstream buffer with partial bitstream"
373 "(Xilinx only)\n"
374#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530375#if defined(CONFIG_CMD_FPGA_LOADFS)
376 "Load device from filesystem (FAT by default) (Xilinx only)\n"
377 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
378 " [<dev[:part]>] <filename>\n"
379#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530380#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200381 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100382#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200383 "\n"
384 "\tFor loadmk operating on FIT format uImage address must include\n"
385 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100386#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530387#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530388#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
389 "Load encrypted bitstream (Xilinx only)\n"
390 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
391 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
392 "Loads the secure bistreams(authenticated/encrypted/both\n"
393 "authenticated and encrypted) of [size] from [address].\n"
394 "The auth-OCM/DDR flag specifies to perform authentication\n"
395 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
396 "The enc flag specifies which key to be used for decryption\n"
397 "0-device key, 1-user key, 2-no encryption.\n"
398 "The optional Userkey address specifies from which address key\n"
399 "has to be used for decryption if user key is selected.\n"
400 "NOTE: the sceure bitstream has to be created using xilinx\n"
401 "bootgen tool only.\n"
402#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100403);