Bo Lv | 72d0e90 | 2023-01-02 14:27:34 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2023 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #define MESON_CPU_MAJOR_ID_M6 0x16 |
| 7 | #define MESON_CPU_MAJOR_ID_M6TV 0x17 |
| 8 | #define MESON_CPU_MAJOR_ID_M6TVL 0x18 |
| 9 | #define MESON_CPU_MAJOR_ID_M8 0x19 |
| 10 | #define MESON_CPU_MAJOR_ID_MTVD 0x1A |
| 11 | #define MESON_CPU_MAJOR_ID_M8B 0x1B |
| 12 | #define MESON_CPU_MAJOR_ID_MG9TV 0x1C |
| 13 | #define MESON_CPU_MAJOR_ID_M8M2 0x1D |
| 14 | #define MESON_CPU_MAJOR_ID_GXBB 0x1F |
| 15 | #define MESON_CPU_MAJOR_ID_GXTVBB 0x20 |
| 16 | #define MESON_CPU_MAJOR_ID_GXL 0x21 |
| 17 | #define MESON_CPU_MAJOR_ID_GXM 0x22 |
| 18 | #define MESON_CPU_MAJOR_ID_TXL 0x23 |
| 19 | #define MESON_CPU_MAJOR_ID_TXLX 0x24 |
| 20 | #define MESON_CPU_MAJOR_ID_AXG 0x25 |
| 21 | #define MESON_CPU_MAJOR_ID_GXLX 0x26 |
| 22 | #define MESON_CPU_MAJOR_ID_TXHD 0x27 |
| 23 | #define MESON_CPU_MAJOR_ID_G12A 0x28 |
| 24 | #define MESON_CPU_MAJOR_ID_G12B 0x29 |
| 25 | #define MESON_CPU_MAJOR_ID_SM1 0x2B |
| 26 | #define MESON_CPU_MAJOR_ID_A1 0x2C |
| 27 | #define MESON_CPU_MAJOR_ID_TL1 0x2E |
| 28 | #define MESON_CPU_MAJOR_ID_TM2 0x2F |
| 29 | #define MESON_CPU_MAJOR_ID_C1 0x30 |
| 30 | #define MESON_CPU_MAJOR_ID_SC2 0x32 |
| 31 | #define MESON_CPU_MAJOR_ID_C2 0x33 |
| 32 | #define MESON_CPU_MAJOR_ID_T5 0x34 |
| 33 | #define MESON_CPU_MAJOR_ID_T5D 0x35 |
| 34 | #define MESON_CPU_MAJOR_ID_T7 0x36 |
| 35 | #define MESON_CPU_MAJOR_ID_S4 0x37 |
| 36 | #define MESON_CPU_MAJOR_ID_T3 0x38 |
| 37 | #define MESON_CPU_MAJOR_ID_P1 0x39 |
| 38 | #define MESON_CPU_MAJOR_ID_S4D 0x3A |
| 39 | #define MESON_CPU_MAJOR_ID_T5W 0x3B |
| 40 | #define MESON_CPU_MAJOR_ID_C3 0x3D |
| 41 | #define MESON_CPU_MAJOR_ID_S5 0x3E |
| 42 | #define MESON_CPU_MAJOR_ID_T5M 0x41 |
| 43 | |
| 44 | #define MESON_CPU_PACKAGE_ID_905D 0X00 |
| 45 | #define MESON_CPU_PACKAGE_ID_905M 0x20 |
| 46 | #define MESON_CPU_PACKAGE_ID_905X 0X80 |
| 47 | #define MESON_CPU_PACKAGE_ID_905L 0XC0 |
| 48 | #define MESON_CPU_PACKAGE_ID_905M2 0XE0 |
| 49 | |
| 50 | #define MESON_CPU_PACKAGE_ID_T962X 0x10 |
| 51 | #define MESON_CPU_PACKAGE_ID_T962E 0x20 |
| 52 | |
| 53 | #define MESON_CPU_PACKAGE_ID_A113X 0x37 |
| 54 | #define MESON_CPU_PACKAGE_ID_A113D 0xD0 |
| 55 | |
| 56 | #define MESON_CPU_CHIP_REVISION_A 0xA |
| 57 | #define MESON_CPU_CHIP_REVISION_B 0xB |
| 58 | #define MESON_CPU_CHIP_REVISION_C 0xC |
| 59 | #define MESON_CPU_CHIP_REVISION_D 0xD |
| 60 | |
| 61 | typedef struct cpu_id { |
| 62 | unsigned int family_id:8; |
| 63 | unsigned int package_id:8; |
| 64 | unsigned int chip_rev:8; //RevA/RevB etc. |
| 65 | unsigned int reserve:4; |
| 66 | unsigned int layout_ver:4; |
| 67 | } cpu_id_t; |
| 68 | |
| 69 | typedef struct chip_id { |
| 70 | unsigned int version; |
| 71 | unsigned char chipid[16]; |
| 72 | } chip_id_t; |
| 73 | |
| 74 | cpu_id_t get_cpu_id(void); |
| 75 | |
| 76 | extern chip_id_t aml_chip_id; |
| 77 | int get_chip_id(unsigned char *buff, unsigned int size); |
| 78 | |
| 79 | /** |
| 80 | * TODO: Remove this API after move static system information to RO |
| 81 | * register or SRAM |
| 82 | * |
| 83 | * Should *NOT* call this API directly, always use get_chip_id() |
| 84 | */ |
| 85 | int __get_chip_id(unsigned char *buff, unsigned int size); |