| Bo Lv | 72d0e90 | 2023-01-02 14:27:34 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MESON_SARADC_H__ |
| 7 | #define __MESON_SARADC_H__ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <adc.h> |
| 11 | #include <clk.h> |
| 12 | |
| 13 | enum ADC_CHANNEL_TYPE { |
| 14 | MESON_SARADC_CH0 = 0, |
| 15 | MESON_SARADC_CH1, |
| 16 | MESON_SARADC_CH2, |
| 17 | MESON_SARADC_CH3, |
| 18 | MESON_SARADC_CH4, |
| 19 | MESON_SARADC_CH5, |
| 20 | MESON_SARADC_CH6, |
| 21 | MESON_SARADC_CH7, |
| 22 | MESON_SARADC_CH_MAX, |
| 23 | }; |
| 24 | |
| 25 | enum MESON_SARADC_AVG_MODE { |
| 26 | NO_AVERAGING = 0x0, |
| 27 | MEAN_AVERAGING = 0x1, |
| 28 | MEDIAN_AVERAGING = 0x2, |
| 29 | }; |
| 30 | |
| 31 | enum MESON_SARADC_NUM_SAMPLES { |
| 32 | ONE_SAMPLE = 0x0, |
| 33 | TWO_SAMPLES = 0x1, |
| 34 | FOUR_SAMPLES = 0x2, |
| 35 | EIGHT_SAMPLES = 0x3, |
| 36 | }; |
| 37 | |
| 38 | enum MESON_SARADC_RESOLUTION { |
| 39 | SARADC_10BIT = 10, |
| 40 | SARADC_12BIT = 12, |
| 41 | SARADC_22BIT = 22, |
| 42 | }; |
| 43 | |
| 44 | enum MESON_SARADC_BIT_STATE { |
| 45 | BIT_LOW = 0, |
| 46 | BIT_HIGH = 1, |
| 47 | }; |
| 48 | |
| 49 | struct meson_saradc; |
| 50 | |
| 51 | struct meson_saradc_diff_ops { |
| 52 | void (*extra_init)(struct meson_saradc *priv); |
| 53 | void (*set_ch7_mux)(struct meson_saradc *priv, int ch, int mux); |
| 54 | void (*enable_decim_filter)(struct meson_saradc *priv, |
| 55 | int ch, unsigned int mode); |
| 56 | void (*set_ref_voltage)(struct meson_saradc *priv, unsigned int mode, |
| 57 | int ch); |
| 58 | int (*get_fifo_channel)(int val); |
| 59 | int (*get_fifo_data)(struct meson_saradc *priv, |
| 60 | struct adc_uclass_platdata *uc_pdata, int val); |
| 61 | }; |
| 62 | |
| 63 | /* |
| 64 | * struct meson_saradc_data - describe the differences of different platform |
| 65 | * |
| 66 | * @reg3_ring_counter_disable: to disable continuous ring counter. |
| 67 | * gxl and later: 1; others(gxtvbb etc): 0 |
| 68 | * @reg11_vref_en: g12a and later: 0; others(axg etc): 1 |
| 69 | * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1 |
| 70 | * @reg11_eoc: g12a and later: 1; others(axg etc): 0 |
| 71 | * @has_bl30_integration: |
| 72 | * @update_vref_conf: only for C2 & A5; C2: 0; A5: 1 |
| 73 | * @num_channels: the number of adc channels |
| 74 | * @self_test_channel: channel of self-test |
| 75 | * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit |
| 76 | * @clock_rate: saradc clock rate |
| 77 | */ |
| 78 | struct meson_saradc_data { |
| 79 | bool reg3_ring_counter_disable; |
| 80 | bool reg11_vref_en; |
| 81 | bool reg11_cmv_sel; |
| 82 | bool reg11_eoc; |
| 83 | bool has_bl30_integration; |
| 84 | bool update_vref_conf; |
| 85 | unsigned char self_test_channel; |
| 86 | unsigned char num_channels; |
| 87 | unsigned int resolution; |
| 88 | const struct meson_saradc_diff_ops *dops; |
| 89 | unsigned int capacity; |
| 90 | unsigned long clock_rate; |
| 91 | }; |
| 92 | |
| 93 | struct meson_saradc { |
| 94 | phys_addr_t base; |
| 95 | int active_channel; |
| 96 | unsigned int current_mode; |
| 97 | struct clk xtal; |
| 98 | struct clk adc_mux; |
| 99 | struct clk adc_div; |
| 100 | struct clk adc_gate; |
| 101 | struct meson_saradc_data *data; |
| 102 | }; |
| 103 | |
| 104 | extern const struct adc_ops meson_saradc_ops; |
| 105 | int meson_saradc_probe(struct udevice *dev); |
| 106 | int meson_saradc_remove(struct udevice *dev); |
| 107 | int meson_saradc_ofdata_to_platdata(struct udevice *dev); |
| 108 | |
| 109 | #define SARADC_CH_SELF_TEST MESON_SARADC_CH7 |
| 110 | |
| 111 | #endif /*_MESON_SARADC_H_*/ |