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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
30
31#define SD_VERSION_SD 0x20000
32#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
33#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
34#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
35#define MMC_VERSION_MMC 0x10000
36#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
37#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
38#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
39#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
40#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
41#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
42
43#define MMC_MODE_HS 0x001
44#define MMC_MODE_HS_52MHz 0x010
45#define MMC_MODE_4BIT 0x100
46#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000047#define MMC_MODE_SPI 0x400
Andy Fleming272cc702008-10-30 16:41:01 -050048
49#define SD_DATA_4BIT 0x00040000
50
Albin Tonnerre79b91de2009-08-22 14:21:53 +020051#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050052
53#define MMC_DATA_READ 1
54#define MMC_DATA_WRITE 2
55
56#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
57#define UNUSABLE_ERR -17 /* Unusable Card */
58#define COMM_ERR -18 /* Communications Error */
59#define TIMEOUT -19
60
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020061#define MMC_CMD_GO_IDLE_STATE 0
62#define MMC_CMD_SEND_OP_COND 1
63#define MMC_CMD_ALL_SEND_CID 2
64#define MMC_CMD_SET_RELATIVE_ADDR 3
65#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050066#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020067#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050068#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020069#define MMC_CMD_SEND_CSD 9
70#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050071#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020072#define MMC_CMD_SEND_STATUS 13
73#define MMC_CMD_SET_BLOCKLEN 16
74#define MMC_CMD_READ_SINGLE_BLOCK 17
75#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050076#define MMC_CMD_WRITE_SINGLE_BLOCK 24
77#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020078#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000079#define MMC_CMD_SPI_READ_OCR 58
80#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020081
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020082#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050083#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020084#define SD_CMD_SEND_IF_COND 8
85
86#define SD_CMD_APP_SET_BUS_WIDTH 6
87#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050088#define SD_CMD_APP_SEND_SCR 51
89
90/* SCR definitions in different words */
91#define SD_HIGHSPEED_BUSY 0x00020000
92#define SD_HIGHSPEED_SUPPORTED 0x00020000
93
94#define MMC_HS_TIMING 0x00000100
95#define MMC_HS_52MHZ 0x2
96
Rabin Vincent0b453ff2009-04-05 13:30:55 +053097#define OCR_BUSY 0x80000000
Andy Fleming272cc702008-10-30 16:41:01 -050098#define OCR_HCS 0x40000000
99
100#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
101#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
102#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
103#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
104#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
105#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
106#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
107#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
108#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
109#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
110#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
111#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
112#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
113#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
114#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
115#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
116#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
117
118#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
119#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
120 addressed by index which are
121 1 in value field */
122#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
123 addressed by index, which are
124 1 in value field */
125#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
126
127#define SD_SWITCH_CHECK 0
128#define SD_SWITCH_SWITCH 1
129
130/*
131 * EXT_CSD fields
132 */
133
134#define EXT_CSD_BUS_WIDTH 183 /* R/W */
135#define EXT_CSD_HS_TIMING 185 /* R/W */
136#define EXT_CSD_CARD_TYPE 196 /* RO */
137#define EXT_CSD_REV 192 /* RO */
138#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
139
140/*
141 * EXT_CSD field definitions
142 */
143
144#define EXT_CSD_CMD_SET_NORMAL (1<<0)
145#define EXT_CSD_CMD_SET_SECURE (1<<1)
146#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
147
148#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
149#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
150
151#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
152#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
153#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200154
Andy Fleming1de97f92008-10-30 16:31:39 -0500155#define R1_ILLEGAL_COMMAND (1 << 22)
156#define R1_APP_CMD (1 << 5)
157
Andy Fleming272cc702008-10-30 16:41:01 -0500158#define MMC_RSP_PRESENT (1 << 0)
159#define MMC_RSP_136 (1 << 1) /* 136 bit response */
160#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
161#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
162#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
163
164#define MMC_RSP_NONE (0)
165#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
166#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
167 MMC_RSP_BUSY)
168#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
169#define MMC_RSP_R3 (MMC_RSP_PRESENT)
170#define MMC_RSP_R4 (MMC_RSP_PRESENT)
171#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
172#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
173#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
174
wdenk71f95112003-06-15 22:40:42 +0000175
Andy Fleming1de97f92008-10-30 16:31:39 -0500176struct mmc_cid {
177 unsigned long psn;
178 unsigned short oid;
179 unsigned char mid;
180 unsigned char prv;
181 unsigned char mdt;
182 char pnm[7];
183};
184
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200185/*
186 * WARNING!
187 *
188 * This structure is used by atmel_mci.c only.
189 * It works for the AVR32 architecture but NOT
190 * for ARM/AT91 architectures.
191 * Its use is highly depreciated.
192 * After the atmel_mci.c driver for AVR32 has
193 * been replaced this structure will be removed.
194 */
Andy Fleming1de97f92008-10-30 16:31:39 -0500195struct mmc_csd
196{
197 u8 csd_structure:2,
198 spec_vers:4,
199 rsvd1:2;
200 u8 taac;
201 u8 nsac;
202 u8 tran_speed;
203 u16 ccc:12,
204 read_bl_len:4;
205 u64 read_bl_partial:1,
206 write_blk_misalign:1,
207 read_blk_misalign:1,
208 dsr_imp:1,
209 rsvd2:2,
210 c_size:12,
211 vdd_r_curr_min:3,
212 vdd_r_curr_max:3,
213 vdd_w_curr_min:3,
214 vdd_w_curr_max:3,
215 c_size_mult:3,
216 sector_size:5,
217 erase_grp_size:5,
218 wp_grp_size:5,
219 wp_grp_enable:1,
220 default_ecc:2,
221 r2w_factor:3,
222 write_bl_len:4,
223 write_bl_partial:1,
224 rsvd3:5;
225 u8 file_format_grp:1,
226 copy:1,
227 perm_write_protect:1,
228 tmp_write_protect:1,
229 file_format:2,
230 ecc:2;
231 u8 crc:7;
232 u8 one:1;
233};
234
Andy Fleming272cc702008-10-30 16:41:01 -0500235struct mmc_cmd {
236 ushort cmdidx;
237 uint resp_type;
238 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530239 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500240 uint flags;
241};
242
243struct mmc_data {
244 union {
245 char *dest;
246 const char *src; /* src buffers don't get written to */
247 };
248 uint flags;
249 uint blocks;
250 uint blocksize;
251};
252
253struct mmc {
254 struct list_head link;
255 char name[32];
256 void *priv;
257 uint voltages;
258 uint version;
259 uint f_min;
260 uint f_max;
261 int high_capacity;
262 uint bus_width;
263 uint clock;
264 uint card_caps;
265 uint host_caps;
266 uint ocr;
267 uint scr[2];
268 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530269 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500270 ushort rca;
271 uint tran_speed;
272 uint read_bl_len;
273 uint write_bl_len;
274 u64 capacity;
275 block_dev_desc_t block_dev;
276 int (*send_cmd)(struct mmc *mmc,
277 struct mmc_cmd *cmd, struct mmc_data *data);
278 void (*set_ios)(struct mmc *mmc);
279 int (*init)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500280#ifdef CONFIG_MMC_MBLOCK
281 uint b_max;
282#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500283};
284
285int mmc_register(struct mmc *mmc);
286int mmc_initialize(bd_t *bis);
287int mmc_init(struct mmc *mmc);
288int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000289void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500290struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700291int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500292void print_mmc_devices(char separator);
Stefano Babic11fdade2010-02-05 15:04:43 +0100293int board_mmc_getcd(u8 *cd, struct mmc *mmc);
Andy Fleming272cc702008-10-30 16:41:01 -0500294
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200295#ifdef CONFIG_GENERIC_MMC
296int atmel_mci_init(void *regs);
Thomas Choud52ebf12010-12-24 13:12:21 +0000297#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
298struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200299#else
Andy Fleming272cc702008-10-30 16:41:01 -0500300int mmc_legacy_init(int verbose);
301#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200302
wdenk71f95112003-06-15 22:40:42 +0000303#endif /* _MMC_H_ */