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git.odroid.com / yocto / uboot / refs/heads/odroidc5-v2023.01 / . / cmd / amlogic / cmd_ddr_test.c
blob: e024c2e8dbd651054b5ed615ab1c9bf760633ab6 [file] [log] [blame]
Bo Lv72d0e902023-01-02 14:27:34 +0000[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <common.h>
7//#include <asm/arch/secure_apb.h>
8
9
10//#include<stdio.h>
11
12//#include <asm/io.h>
13//#include <asm/arch/io.h>
14//#include <asm/arch/register.h>
15//#include <asm/arch-g9tv/mmc.h> //jiaxing debug
16
17//extern void aml_cache_disable(void);
18//#ifndef char* itoa(intnum,char*str,intradix)
19
20
21#define DWC_AC_PINMUX_TOTAL 28
22#define DWC_DFI_PINMUX_TOTAL 26
23
24//#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
25#define DDR_STICKY_MAGIC_NUMBER 0x20180000
26#define DDR_CHIP_ID 0x30
27#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
28#define DDR_STICKY_SOURCE_SRAM 0x2
29
30#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
31#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
32
33#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
34#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
35#define CONFIG_DDR_TYPE_DDR3 0
36#define CONFIG_DDR_TYPE_DDR4 1
37#define CONFIG_DDR_TYPE_LPDDR4 2
38#define CONFIG_DDR_TYPE_LPDDR3 3
39#define CONFIG_DDR_TYPE_LPDDR2 4
40//#define CONFIG_DDR_TYPE_LPDDR4X 5
41#define CONFIG_DDR_TYPE_AUTO 0xf
42#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
43
44#define CONFIG_DDR0_16BIT_CH0 0x1
45#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
46#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
47#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
48#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
49#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
50#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
51#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
52
53/*
54static uint32_t ddr_rd_16bit_on_32reg(uint32_t addr)
55{
56uint32_t read_value=0;
57uint32_t addr_t=((addr>>2) << 2);
58read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
59read_value=(read_value>>((addr%4)<<3))&0xffff;
60return read_value;
61
62}
63static uint32_t ddr_wr_16bit_on_32reg(uint32_t addr,uint32_t value)
64{
65uint32_t read_value=0;
66uint32_t write_value=0;
67uint32_t addr_t=((addr>>2) << 2);
68uint32_t offset=((addr%4)<<3);
69read_value= *(volatile uint32_t *)(( unsigned long )(addr_t));
70write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
71 *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
72
73return write_value;
74
75}
76*/
77static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
78{
79 uint32_t read_value=0;
80 uint32_t addr_t=0;
81 uint32_t offset=0;
82 if (size == 8) {
83 offset=((offset_index%4)<<3);
84 addr_t=(base_addr+((offset_index>>2) << 2));
85 read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
86 read_value=(read_value>>offset)&0xff;
87
88 }
89 if (size == 16) {
90 offset=((offset_index%2)<<4);
91 addr_t=(base_addr+((offset_index>>1) << 2));
92 read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
93 read_value=(read_value>>offset)&0xffff;
94 }
95 return read_value;
96
97}
98static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
99{
100 uint32_t read_value=0;
101 uint32_t write_value=0;
102 uint32_t addr_t=0;
103 uint32_t offset=0;
104 if (size == 8) {
105 offset=((offset_index%4)<<3);
106 addr_t=(base_addr+((offset_index>>2) << 2));
107 read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
108 write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
109 }
110 if (size == 16) {
111 offset=((offset_index%2)<<4);
112 addr_t=(base_addr+((offset_index>>1) << 2));
113 read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
114 write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
115 }
116 *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
117 return write_value;
118}
119typedef struct ddr_set{
120 unsigned int magic;
121 unsigned int rsv_int0;
122 unsigned char board_id;
123 //board id reserve,,do not modify
124 unsigned char version;
125 // firmware reserve version,,do not modify
126 unsigned char DramType;
127 //support DramType should confirm with amlogic
128 //#define CONFIG_DDR_TYPE_DDR3 0
129 //#define CONFIG_DDR_TYPE_DDR4 1
130 //#define CONFIG_DDR_TYPE_LPDDR4 2
131 //#define CONFIG_DDR_TYPE_LPDDR3 3
132 //#define CONFIG_DDR_TYPE_LPDDR2 4
133 unsigned char DisabledDbyte;
134 //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
135 //bit 0 ---use byte 0 ,1 disable byte 0,
136 //bit 1 ---use byte 1 ,1 disable byte 1,
137 //bit 2 ---use byte 2 ,1 disable byte 2,
138 //bit 3 ---use byte 3 ,1 disable byte 3,
139 unsigned char Is2Ttiming;
140 //ddr3/ddr3 use 2t timing,now only support 2t timming
141 unsigned char HdtCtrl;
142 //training information control,do not modify
143 unsigned char dram_rank_config;
144 //support Dram connection type should confirm with amlogic
145 //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
146 //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
147 //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
148 //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use channel a cs0 cs1 channel b cs0 cs1
149 //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
150 //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
151 //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
152 //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use channel a cs0 channel b cs0
153
154 /* rsv_char0. update for diagnose type define */
155 unsigned char diagnose;
156
157 /* imem/dmem define */
158 unsigned int imem_load_addr;
159 //system reserve,do not modify
160 unsigned int dmem_load_addr;
161 //system reserve,do not modify
162 unsigned short imem_load_size;
163 //system reserve,do not modify
164 unsigned short dmem_load_size;
165 //system reserve,do not modify
166 unsigned int ddr_base_addr;
167 //system reserve,do not modify
168 unsigned int ddr_start_offset;
169 //system reserve,do not modify
170
171 unsigned short dram_cs0_size_MB;
172 //config cs0 dram size ,like 1G DRAM ,setting 1024
173 unsigned short dram_cs1_size_MB;
174 //config cs1 dram size,like 512M DRAM ,setting 512
175 /* align8 */
176
177 unsigned short training_SequenceCtrl[2];
178 //system reserve,do not modify
179 unsigned char phy_odt_config_rank[4];
180 //training odt config ,only use for training
181 // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
182 // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
183 unsigned int dfi_odt_config;
184 //normal go status od config,use for normal status
185 //bit 12. rank1 ODT default. default value for ODT[1] pins if theres no read/write activity.
186 //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
187 //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
188 //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
189 //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
190 //bit 4. rank0 ODT default. default value for ODT[0] pins if theres no read/write activity.
191 //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
192 //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
193 //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
194 //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
195 unsigned short DRAMFreq[4];
196 //config dram frequency,use DRAMFreq[0],other reserve
197 unsigned char PllBypassEn;
198 //system reserve,do not modify
199 unsigned char ddr_rdbi_wr_enable;
200 //system reserve,do not modify
201 unsigned char ddr_rfc_type;
202 //config dram rfc type,according dram type,also can use same dram type max config
203 //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
204 //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
205 //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
206 //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
207 //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
208 //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
209 //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
210 //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
211 //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
212 //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
213 //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
214 //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
215 unsigned char enable_lpddr4x_mode;
216 //system reserve,do not modify
217 /* align8 */
218
219 unsigned int pll_ssc_mode;
220 //
221 /* pll ssc config:
222 *
223 * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
224 * ppm = strength * 500
225 * mode: 0=center, 1=up, 2=down
226 *
227 * eg:
228 * 1. config 1000ppm center ss. then mode=0, strength=2
229 * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
230 * 2. config 3000ppm down ss. then mode=2, strength=6
231 * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
232 */
233 unsigned short clk_drv_ohm;
234 //config soc clk pin signal driver strength ,select 20,30,40,60ohm
235 unsigned short cs_drv_ohm;
236 //config soc cs0 cs1 pin signal driver strength ,select 20,30,40,60ohm
237 unsigned short ac_drv_ohm;
238 //config soc normal address command pin driver strength ,select 20,30,40,60ohm
239 unsigned short soc_data_drv_ohm_p;
240 //config soc data pin pull up driver strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
241 unsigned short soc_data_drv_ohm_n;
242 //config soc data pin pull down driver strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
243 unsigned short soc_data_odt_ohm_p;
244 //config soc data pin odt pull up strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
245 unsigned short soc_data_odt_ohm_n;
246 //config soc data pin odt pull down strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
247 unsigned short dram_data_drv_ohm;
248 //config dram data pin pull up pull down driver strength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
249 unsigned short dram_data_odt_ohm;
250 //config dram data pin odt pull up down strength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
251 unsigned short dram_ac_odt_ohm;
252 //config dram ac pin odt pull up down strength,use for lpddr4, select 40,48,60,80,120,240ohm
253 unsigned short soc_clk_slew_rate;
254 //system reserve,do not modify
255 unsigned short soc_cs_slew_rate;
256 //system reserve,do not modify
257 unsigned short soc_ac_slew_rate;
258 //system reserve,do not modify
259 unsigned short soc_data_slew_rate;
260 //system reserve,do not modify
261 unsigned short vref_output_permil; //phy
262 //setting same with vref_dram_permil
263 unsigned short vref_receiver_permil; //soc
264 //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
265 unsigned short vref_dram_permil;
266 //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
267 unsigned short vref_reverse;
268 //system reserve,do not modify
269 /* align8 */
270
271 unsigned char ac_trace_delay[12];
272 //system reserve,do not modify ,take care ,please follow SI
273 unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
274 //use for lpddr3 /lpddr4 ca pinmux remap
275 unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
276 unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
277 //system reserve,do not modify
278 unsigned short dq_bdlr_org;
279 unsigned char rsv_char1[2];
280 //system reserve,do not modify
281 /* align8 */
282
283 unsigned int ddr_dmc_remap[5];
284 //system reserve,do not modify
285 /* align8 */
286 unsigned char ddr_lpddr34_ca_remap[4];
287 ////use for lpddr3 /lpddr4 ca training data byte lane remap
288 unsigned char ddr_lpddr34_dq_remap[32];
289 ////use for lpddr3 /lpddr4 ca pinmux remap
290 unsigned int dram_rtt_nom_wr_park[2];
291 //system reserve,do not modify
292 unsigned int ddr_func;
293 //system reserve,do not modify
294 /* align8 */
295
296 unsigned long rsv_long0[2];
297 /* v1 end */
298 unsigned char dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
299 /* v2 start */
300 unsigned char dq_bit_delay[72];
301 //override read bit delay
302// unsigned short dq_bdlr_org[2];
303// unsigned char dqs_adjust_line[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
304}ddr_set_t;
305
306ddr_set_t p_ddr_set_t;
307
308char* itoa_ddr_test(int num,char*str,int radix)
309{/*������*/
310 printf("\nitoa_ddr_test 1\n");
311 char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
312 unsigned unum;/*����*/
313 char temp;
314 int i=0,j,k;
315 /*ȷ��unum��ֵ*/
316 if (radix == 10 && num<0) /*ʮ���Ƹ���*/
317 {
318 unum = (unsigned)-num;
319 str[i++] = '-';
320 }
321 else
322 unum = (unsigned)num;/*�������*/
323 /*ת��*/
324 printf("\nitoa_ddr_test 2\n");
325 printf("\nunum=0x%08x\n",unum);
326 printf("\nunum2=0x%08x\n",(unum%(unsigned)radix));
327 printf("\nradix=0x%08x\n",radix);
328 str[0] = index[0];
329 printf("\nitoa_ddr_test 22\n");
330 unum /= radix;
331 printf("\nitoa_ddr_test 23\n");
332 do {
333 str[i++] = index[unum%(unsigned)radix];
334 unum /= radix;
335 }while(unum);
336 printf("\nitoa_ddr_test 3\n");
337 str[i] = '\0';
338 /*����*/
339 if (str[0] == '-')
340 k = 1;/*ʮ���Ƹ���*/
341 else
342 k = 0;
343 printf("\nitoa_ddr_test 4\n");
344 for (j = k;j <= (i-1)/2;j++)
345 {
346 temp = str[j];
347 str[j] = str[i-1+k-j];
348 str[i-1+k-j] = temp;
349 }
350 return str;
351}
352//#endif
353
354/*
355char *strsep(char **stringp, const char *delim)
356{
357 char *s;
358 const char *span;
359 int c, sc;
360 char *tok;
361 if ((s = *stringp)== NULL)
362 return (NULL);
363 for (tok = s;;) {
364 c = *s++;
365 span = delim;
366 do {
367 if ((sc =*span++) == c) {
368 if (c == 0)
369 s = NULL;
370 else
371 s[-1] = 0;
372 *stringp = s;
373 return (tok);
374 }
375 } while (sc != 0);
376 }
377
378}
379*/
380int TOLOWER(int ch)
381{
382
383 if ((unsigned int)(ch - 'A') < 26u )
384 ch += 'a' - 'A';
385
386 return ch;
387}//��д��ĸת��ΪСд��ĸ��
388
389int isxdigit(int ch)
390{
391 return (unsigned int)( ch - '0') < 10u ||
392 (unsigned int)((ch | 0x20) - 'a') < 6u;
393}//�ж��ַ�c�Ƿ�Ϊʮ���������֡�
394//��cΪA-F,a-f��0-9֮���ʮ����������ʱ�����ط���ֵ�����򷵻��㡣
395int isdigit(int ch)
396{
397 return (unsigned int)(ch - '0') < 10u;
398}//�ж��ַ�c�Ƿ�Ϊ����
399unsigned int simple_guess_base(const char *cp)
400{
401 if (cp[0] == '0') {
402 if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
403 return 16;
404 else
405 // return 8;
406 return 10;
407 } else {
408 return 10;
409 }
410}
411unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
412{
413 unsigned int result = 0;
414 //printf("test sizeof(str_buf)==%d\n",1);
415 if (cp == NULL) //jiaxing add 20170616
416 return 0;
417 if (!base)
418 base = simple_guess_base(cp);
419 if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
420 cp += 2;
421 if (base == 10) {
422 while ((*cp)== '0')
423 cp++;
424 }
425 while (isxdigit(*cp)) {//��鵱ǰcp�Ƿ��Ǹ�ʮ��������ֵ������ֱ�ӷ���0
426 unsigned int value;
427 value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
428 if (value >= base)
429 break;
430 result = result * base + value;
431 cp++;
432 }
433 if (endp)
434 *endp = (char *)cp;
435 return result;
436}
437unsigned int env_to_a_num(const char *env_name)
438{
439 char *str_buf = NULL;
440 char buf[48];
441 str_buf = (char *)(&buf);
442 memset(str_buf, 0, sizeof(buf));
443 printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
444 str_buf = env_get(env_name);
445 unsigned int a_num = 0;
446 char *endp;
447
448 printf("str==%s\n",str_buf);
449
450 a_num=simple_strtoull_ddr(str_buf, &endp, 0);
451 printf("%s==0x%08x\n",str_buf,a_num);
452
453 return a_num;
454}
455unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num)
456{
457 char *str_buf=NULL;
458 char buf[1024];
459 //unsigned int str_to_numarry[48];
460 //str_buf = (char *)malloc(sizeof(char)*1024);
461 str_buf = (char *)(&buf);
462 memset(str_buf, 0, sizeof(buf));
463 printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
464 str_buf = env_get(env_name);
465
466 printf("str==%s\n",str_buf);
467
468 sprintf(buf, "0x%08x", *a_num);
469
470 printf( "%s==0x%08x", buf,*a_num);
471 env_set(env_name, buf);
472
473 run_command("save",0);
474 return 1;
475}
476unsigned int env_to_num(const char *env_name,unsigned int *num_arry)
477{
478 char *str_buf = NULL;
479 char buf[1024];
480 unsigned int str_to_numarry[48];
481 //str_buf = (char *)malloc(sizeof(char)*1024);
482 str_buf = (char *)(&buf);
483 memset(str_buf, 0, sizeof(buf));
484 printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
485 str_buf = env_get(env_name);
486
487 char * str[48];
488 char *endp;
489 int i;
490 for (i = 0; i < 48; i++)
491 str_to_numarry[i] = 0;
492 printf("str==%s\n",str_buf);
493 for (i = 0; i < 48; i++) {
494 str[i] = strsep(&str_buf, ";");
495 //str[i] = strsep(&str_buf, " ");
496 if (str[i] == NULL)
497 break;
498 str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
499 //printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
500 //num_arry[i]=str_to_numarry[i];
501 }
502 for (i = 0; i < 48; i++) {
503 printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
504 num_arry[i] = str_to_numarry[i];
505 }
506 //num_arry=(unsigned int *)(&str_to_numarry);
507 return 1;
508}
509
510unsigned int num_to_env(const char *env_name,unsigned int *num_arry)
511{
512 char *str_buf=NULL;
513 char buf[1024];
514 int i;
515 //unsigned int str_to_numarry[48];
516 //str_buf = (char *)malloc(sizeof(char)*1024);
517 str_buf = (char *)(&buf);
518 memset(str_buf, 0, sizeof(buf));
519 printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
520 str_buf = env_get(env_name);
521
522 //char * str[48];
523 printf("str==%s\n",str_buf);
524
525
526 sprintf(buf, "0x%08x", num_arry[0]);
527 for (i = 1; i < 48; i++) {
528 //num_arry[i]=0;
529 sprintf(buf, "%s;0x%08x", buf,num_arry[i]);
530 printf("%d %d\n", i,num_arry[i]);
531 }
532 //sprintf(str, "%lx", value);
533 printf( "%s", buf);
534 env_set(env_name, buf);
535
536 run_command("save",0);
537 //num_arry=(unsigned int *)(&str_to_numarry);
538 return 1;
539}
540
541#define TDATA32F 0xffffffff
542#define TDATA32A 0xaaaaaaaa
543#define TDATA325 0x55555555
544#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2))
545//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567
546#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
547#define DMC_STICKY_G12A_0 ((0x0000 << 2) + 0xff638800)
548#define DMC_STICKY_MAGIC_0 0x12345678
549#define DMC_STICKY_MAGIC_1 0xabcdbead
550#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
551#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
552unsigned int dmc_sticky[64];
553unsigned int sticky_reg_base_add=0;
554
555//#define DDR_TEST_ACLCDLR
556unsigned int global_boot_times= 0;
557unsigned int watchdog_time_s= 20;
558unsigned int global_ddr_clk=1;
559unsigned int bdlr_100step=0;
560unsigned int ui_1_32_100step=0;
561unsigned int error_count =0;
562unsigned int error_outof_count_flag=0;
563unsigned int copy_test_flag = 0;
564unsigned int training_pattern_flag = 0;
565unsigned int test_start_addr=0x1080000;
566
567unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
568unsigned int dq_lcd_bdl_value_bdlr0_org_a;
569unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
570unsigned int dq_lcd_bdl_value_bdlr0_min_a;
571unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
572unsigned int dq_lcd_bdl_value_bdlr0_max_a;
573unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
574unsigned int dq_lcd_bdl_value_bdlr0_status_a;
575
576unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
577unsigned int dq_lcd_bdl_value_bdlr0_org_b;
578unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
579unsigned int dq_lcd_bdl_value_bdlr0_min_b;
580unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
581unsigned int dq_lcd_bdl_value_bdlr0_max_b;
582
583unsigned int dq_lcd_bdl_value_wdq_org_a[4];
584unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
585unsigned int dq_lcd_bdl_value_wdq_min_a[4];
586unsigned int dq_lcd_bdl_value_wdq_max_a[4];
587unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
588unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
589unsigned int dq_lcd_bdl_value_wdq_status_a[4];
590unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
591
592unsigned int dq_lcd_bdl_value_wdq_org_b[4];
593unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
594unsigned int dq_lcd_bdl_value_wdq_min_b[4];
595unsigned int dq_lcd_bdl_value_wdq_max_b[4];
596unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
597unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
598unsigned int dq_lcd_bdl_value_wdq_status_b[4];
599unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
600unsigned int acbdlr0_9_reg_org[10];
601unsigned int acbdlr0_9_reg_setup_max[40];
602unsigned int acbdlr0_9_reg_hold_max[40];
603unsigned int acbdlr0_9_reg_setup_time[40];
604unsigned int acbdlr0_9_reg_hold_time[40];
605// unsigned int data_bdlr0_5_reg_org[6];
606unsigned int data_bdlr0_5_reg_org[28];//4//4lane
607unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr
608unsigned int bdlr0_9_reg_hold_max[24*4];
609unsigned int bdlr0_9_reg_setup_time[24*4];
610unsigned int bdlr0_9_reg_hold_time[24*4];
611
612#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
613#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
614
615#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
616#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
617
618//#define CONFIG_DDR_CMD_BDL_TUNE
619//#define CONFIG_CMD_DDR_TEST
620
621#ifndef CONFIG_CHIP
622//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
623#define CHIP_OLD 0
624#define CHIP_TXLX 1
625#define CHIP_A113 2
626#define CHIP_G12 3
627#define CONFIG_CHIP CHIP_G12// CHIP_OLD//
628#endif
629
630#define P_DDR_PHY_DEFAULT 0
631#define P_DDR_PHY_GX_BABY 1
632#define P_DDR_PHY_GX_TV_BABY 2
633#define P_DDR_PHY_905X 3
634
635//#define P_DDR_PHY_OLD_TAG 0
636#define P_DDR_PHY_G12 4
637
638#if (CONFIG_CHIP>=CHIP_G12)
639#define CONFIG_DDR_PHY P_DDR_PHY_G12
640#else
641//#define CONFIG_CHIP CHIP_OLD//
642//#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
643//#define CONFIG_DDR_PHY P_DDR_PHY_G12//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
644#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
645//#define CONFIG_DDR_PHY_NEW_TAG1 P_DDR_PHY_G12
646#endif
647
648#define G12_AM_DDR_PLL_CNTL0 0xff638c00
649
650#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
651#include <asm/arch/secure_apb.h>
652#endif
653
654#define PATTERN_USE_DDR_DES
655#define USE_64BIT_POINTER
656//#define USE_32BIT_POINTER
657#ifdef USE_64BIT_POINTER
658#define p_convter_int(a) ( unsigned int )( unsigned long )(a)
659#define int_convter_p(a) ( unsigned long )(a)
660
661#else
662#define p_convter_int(a) ( unsigned int )(a)
663#define int_convter_p(a) ( unsigned int )(a)
664#endif
665
666#ifdef PATTERN_USE_DDR_DES
667#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d])
668#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d])))
669#define des_xor_pattern(a,b) ( a^b)
670//des[temp_i]^pattern_2[temp_k][temp_i]
671#else
672#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d]
673#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d])
674#define des_xor_pattern(a,b) (a&0+b)
675#endif
676
677
678#define DDR_LCDLR_CK_USE_FAST_PATTERN
679#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
680#define DDR_PREFETCH_CACHE
681#endif
682#ifdef DDR_PREFETCH_CACHE
683#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
684#else
685#define ddr_pld_cache(P)
686#endif
687
688#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
689#define DDR0_PUB_REG_BASE 0xc8836000
690#define DDR1_PUB_REG_BASE 0xc8836000
691#define CHANNEL_A_REG_BASE 0
692#define CHANNEL_B_REG_BASE 0x2000
693#define P_DDR0_CLK_CTRL 0xc8836c00
694#define P_DDR1_CLK_CTRL 0xc8836c00
695#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
696#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8836c00))
697#define CLOSE_CHANNEL_A_PHY_CLK() (writel((5), 0xc8836c00))
698#define CLOSE_CHANNEL_B_PHY_CLK() (writel((5), 0xc8836c00))
699// #define P_ISA_TIMERE 0xc1109988
700// #define get_us_time() (readl(P_ISA_TIMERE))
701#define AM_DDR_PLL_CNTL 0xc8836800
702#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
703#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
704#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
705
706#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
707#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
708#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
709
710#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
711#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
712#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
713//0x98 reserved)
714#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
715#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
716#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
717//0x9c reserved)
718#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
719#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
720#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
721#define ACBDLR_MAX 0X1F
722#define ACLCDLR_MAX 0XFF
723#define DQBDLR_MAX 0X1F
724#define DQLCDLR_MAX 0XFF
725#define DXNGTR_MAX 0X7
726#define ACBDLR_NUM 10
727#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
728#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
729#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
730#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
731
732
733#define DMC_REG_BASE 0xc8838000
734#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
735 //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
736 //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
737 //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
738 //bit 19:16. qos monitor channel select. select one at one time only.
739 //bit 15:0. port select for the selected channel.
740#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
741 // qos_mon_clk_timer. How long to measure the bandwidth.
742
743
744#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
745 // at the test period, the whole MMC request time.
746#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
747 // at the test period, the whole MMC granted data cycles. 64bits unit.
748#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
749
750
751#elif (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY)
752#define DDR0_PUB_REG_BASE 0xc8836000
753#define DDR1_PUB_REG_BASE 0xc8837000
754#define CHANNEL_A_REG_BASE 0
755#define CHANNEL_B_REG_BASE 0x1000
756#define P_DDR0_CLK_CTRL 0xc8836c00
757#define P_DDR1_CLK_CTRL 0xc8836c00
758#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
759#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8837c00))
760#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8836c00))
761#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8837c00))
762// #define P_ISA_TIMERE 0xc1109988
763// #define get_us_time() (readl(P_ISA_TIMERE) )
764#define AM_DDR_PLL_CNTL 0xc8836800
765#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
766#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
767#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
768#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
769#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
770#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
771
772#define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2))
773//0x94 reserved)
774#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
775#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
776#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
777//0x98 reserved)
778#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
779#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
780#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
781//0x9c reserved)
782#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
783#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
784#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
785#define ACBDLR_MAX 0X1F
786#define ACLCDLR_MAX 0XFF
787#define DQBDLR_MAX 0X1F
788#define DQLCDLR_MAX 0XFF
789#define DXNGTR_MAX 0X7
790#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
791#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
792#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
793#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
794#define DMC_REG_BASE 0xc8838000
795#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
796 //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
797 //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
798 //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
799 //bit 19:16. qos monitor channel select. select one at one time only.
800 //bit 15:0. port select for the selected channel.
801#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
802 // qos_mon_clk_timer. How long to measure the bandwidth.
803
804
805#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
806 // at the test period, the whole MMC request time.
807#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
808 // at the test period, the whole MMC granted data cycles. 64bits unit.
809#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
810 // at the test period, the granted data cycles for the selected channel and ports.
811
812#elif (CONFIG_DDR_PHY == P_DDR_PHY_905X)
813
814 // #define P_ISA_TIMERE 0xc1109988
815 // #define get_us_time() (readl(P_ISA_TIMERE) )
816#if CONFIG_CHIP >=CHIP_TXLX
817#define DDR0_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
818#define DDR1_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
819#define CHANNEL_A_REG_BASE 0
820#define CHANNEL_B_REG_BASE 0//0x1000
821#define MMC_REG_BASE ((0x0000 << 2) + 0xff637000) // #define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xff637000) 0xc8837000
822#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
823#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
824#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
825#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
826#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
827#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
828#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
829
830#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
831#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
832#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
833#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
834#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
835#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
836
837#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
838#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
839#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
840
841#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
842#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
843#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
844
845#define DDR0_PUB_DX0GCR0 ((0x01c0 << 2) + DDR0_PUB_REG_BASE)
846#define DDR0_PUB_DX1GCR0 ((0x0200 << 2) + DDR0_PUB_REG_BASE)
847#define DDR0_PUB_DX2GCR0 ((0x0240 << 2) + DDR0_PUB_REG_BASE)
848#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
849
850#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
851#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
852#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
853
854#define ACBDLR_MAX 0X3F
855#define ACLCDLR_MAX 0X1FF
856#define DQBDLR_MAX 0X3F
857#define DQLCDLR_MAX 0X1FF
858#define DXNGTR_MAX 0X1F
859
860 // #define DMC_REG_BASE MMC_REG_BASE
861
862#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
863 //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
864 //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
865 //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
866 //bit 19:16. qos monitor channel select. select one at one time only.
867 //bit 15:0. port select for the selected channel.
868#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
869// qos_mon_clk_timer. How long to measure the bandwidth.
870
871
872#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
873 // at the test period, the whole MMC request time.
874#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
875 // at the test period, the whole MMC granted data cycles. 64bits unit.
876#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
877 // at the test period, the granted data cycles for the selected channel and ports.
878
879#else
880#define DDR0_PUB_REG_BASE 0xc8836000
881#define DDR1_PUB_REG_BASE 0xc8836000
882#define CHANNEL_A_REG_BASE 0
883#define CHANNEL_B_REG_BASE 0//0x1000
884#define MMC_REG_BASE 0xc8837000
885#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
886#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
887#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
888#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
889#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
890#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
891#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
892
893#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
894#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
895#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
896#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
897#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
898#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
899
900#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
901#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
902#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
903
904#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
905#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
906#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
907
908#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
909#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
910#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
911
912#define ACBDLR_MAX 0X3F
913#define ACLCDLR_MAX 0X1FF
914#define DQBDLR_MAX 0X3F
915#define DQLCDLR_MAX 0X1FF
916#define DXNGTR_MAX 0X1F
917#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
918#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
919#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
920#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
921#ifndef DMC_REG_BASE
922#define DMC_REG_BASE MMC_REG_BASE
923#endif
924#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
925//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
926//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
927//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
928//bit 19:16. qos monitor channel select. select one at one time only.
929//bit 15:0. port select for the selected channel.
930#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
931// qos_mon_clk_timer. How long to measure the bandwidth.
932
933#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
934// at the test period, the whole MMC request time.
935#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
936// at the test period, the whole MMC granted data cycles. 64bits unit.
937#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
938// at the test period, the granted data cycles for the selected channel and ports.
939#endif
940
941#elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
942
943#define DDR0_PUB_REG_BASE 0xc8001000 //0xc8836000
944#define DDR1_PUB_REG_BASE 0xc8001000 // 0xc8836000
945#define CHANNEL_A_REG_BASE 0
946#define CHANNEL_B_REG_BASE 0x2000
947#define P_DDR0_CLK_CTRL 0xc8000800
948#define P_DDR1_CLK_CTRL 0xc8002800
949#define OPEN_CHANNEL_A_PHY_CLK() (writel((0x12b), 0xc8000800))
950#define OPEN_CHANNEL_B_PHY_CLK() (writel((0x12b), 0xc8002800))
951#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8000800))
952#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8002800))
953// #define P_ISA_TIMERE 0xc1109988
954// #define get_us_time() (readl(P_ISA_TIMERE))
955
956#define PREG_STICKY_REG0 0xc1100000+(0x207c<<2)
957#define PREG_STICKY_REG1 0xc1100000+(0x207d<<2)
958#define WATCHDOG_TC 0xc1100000+(0x2640<<2)// 0x2640
959
960#define AM_DDR_PLL_CNTL 0xc8000400
961#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
962#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
963#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
964#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x91<<2))
965#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x92<<2))
966#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x91<<2))
967#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x92<<2))
968#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
969#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
970#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
971#define ACBDLR_MAX 0X1F
972#define ACLCDLR_MAX 0XFF
973#define DQBDLR_MAX 0X1F
974#define DQLCDLR_MAX 0XFF
975#define DXNGTR_MAX 0X7
976#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
977#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
978#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
979#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
980#define DMC_REG_BASE 0xc8006000
981#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
982//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
983//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
984//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
985//bit 19:16. qos monitor channel select. select one at one time only.
986//bit 15:0. port select for the selected channel.
987#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
988// qos_mon_clk_timer. How long to measure the bandwidth.
989
990#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
991// at the test period, the whole MMC request time.
992#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
993// at the test period, the whole MMC granted data cycles. 64bits unit.
994#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
995// at the test period, the granted data cycles for the selected channel and ports.
996
997
998
999#elif (CONFIG_DDR_PHY == P_DDR_PHY_G12)
1000#define DDR0_PUB_REG_BASE 0xff636000
1001#define DDR1_PUB_REG_BASE 0xff636000
1002#define CHANNEL_A_REG_BASE 0
1003#define CHANNEL_B_REG_BASE 0//0x1000
1004#define MMC_REG_BASE 0xff637000
1005#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
1006#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
1007#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
1008#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
1009#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
1010#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
1011#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
1012
1013#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
1014#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
1015#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
1016#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
1017#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
1018#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
1019
1020#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
1021#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
1022#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
1023
1024#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
1025#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
1026#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
1027
1028#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
1029#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
1030#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
1031
1032#define ACBDLR_MAX 0X3F
1033#define ACLCDLR_MAX 0X1FF
1034#define DQBDLR_MAX 0X3F
1035#define DQLCDLR_MAX 0X1FF
1036#define DXNGTR_MAX 0X1F
1037#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
1038#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
1039#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
1040#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
1041#ifndef DMC_REG_BASE
1042#define DMC_REG_BASE MMC_REG_BASE
1043#endif
1044#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
1045//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
1046//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
1047//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
1048//bit 19:16. qos monitor channel select. select one at one time only.
1049//bit 15:0. port select for the selected channel.
1050#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
1051// qos_mon_clk_timer. How long to measure the bandwidth.
1052
1053
1054#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
1055// at the test period, the whole MMC request time.
1056#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
1057 // at the test period, the whole MMC granted data cycles. 64bits unit.
1058#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
1059 // at the test period, the granted data cycles for the selected channel and ports.
1060#endif
1061
1062#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
1063#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
1064#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 ))// R/W - PHY General Configuration Register 0
1065#define DDR0_PUB_PGCR1 ( DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
1066#define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
1067#define DDR0_PUB_PGCR3 ( DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
1068#define DDR0_PUB_PGCR4 ( DDR0_PUB_REG_BASE + ( 0x008 << 2 )) // R/W - PHY General Configuration Register 4
1069#define DDR0_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
1070#define DDR0_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
1071#define DDR0_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
1072#define DDR0_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 )) // R/W - PHY General Configuration Register 8
1073
1074#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
1075#define DDR1_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 )) // R/W - PHY General Configuration Register 0
1076#define DDR1_PUB_PGCR1 (DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
1077#define DDR1_PUB_PGCR2 ( DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
1078#define DDR1_PUB_PGCR3 (DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
1079#define DDR1_PUB_PGCR4 (DDR0_PUB_REG_BASE + ( 0x008 << 2 ) )// R/W - PHY General Configuration Register 4
1080#define DDR1_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
1081#define DDR1_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
1082#define DDR1_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
1083#define DDR1_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 ) )// R/W - PHY General Configuration Register 8
1084
1085#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE + ( 0x1d0 << 2 ))
1086#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE + ( 0x1d1 << 2 ))
1087#define DDR0_PUB_DX0BDLR2 ( DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
1088#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
1089#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2 ))
1090#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2 ))
1091#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2 ))
1092#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE + ( 0x1e0 << 2 ))
1093#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
1094#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE + ( 0x1e2 << 2 ))
1095#define DDR0_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
1096#define DDR0_PUB_DX0LCDLR4 (DDR0_PUB_REG_BASE + ( 0x1e4 << 2 ))
1097#define DDR0_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
1098#define DDR0_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
1099#define DDR0_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2) )
1100#define DDR0_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
1101#define DDR0_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
1102#define DDR0_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
1103#define DDR0_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
1104
1105#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2) )
1106#define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2) )
1107#define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2) )
1108#define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2) )
1109#define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2) )
1110#define DDR0_PUB_DX1BDLR5 ( DDR0_PUB_REG_BASE + ( 0x216 << 2) )
1111#define DDR0_PUB_DX1BDLR6 ( DDR0_PUB_REG_BASE + ( 0x218 << 2) )
1112#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2) )
1113#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2) )
1114#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE + ( 0x222 << 2) )
1115#define DDR0_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2) )
1116#define DDR0_PUB_DX1LCDLR4 (DDR0_PUB_REG_BASE + ( 0x224 << 2) )
1117#define DDR0_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2) )
1118#define DDR0_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2) )
1119#define DDR0_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2) )
1120#define DDR0_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
1121#define DDR0_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2) )
1122#define DDR0_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2) )
1123#define DDR0_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2) )
1124
1125#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2) )
1126#define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2) )
1127#define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2) )
1128#define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2) )
1129#define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2) )
1130#define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2) )
1131#define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2) )
1132#define DDR0_PUB_DX2LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x260 << 2) )
1133#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2) )
1134#define DDR0_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2) )
1135#define DDR0_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2) )
1136#define DDR0_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2) )
1137#define DDR0_PUB_DX2LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x265 << 2) )
1138#define DDR0_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2) )
1139#define DDR0_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2) )
1140#define DDR0_PUB_DX2GTR0 ( DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
1141#define DDR0_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2) )
1142#define DDR0_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2) )
1143#define DDR0_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2) )
1144
1145#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2) )
1146#define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2) )
1147#define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2) )
1148#define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2) )
1149#define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2) )
1150#define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2) )
1151#define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2) )
1152#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2) )
1153#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2) )
1154#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE + ( 0x2a2 << 2) )
1155#define DDR0_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2) )
1156#define DDR0_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2) )
1157#define DDR0_PUB_DX3LCDLR5 (DDR0_PUB_REG_BASE + ( 0x2a5 << 2) )
1158#define DDR0_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2) )
1159#define DDR0_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2) )
1160#define DDR0_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
1161#define DDR0_PUB_DX3GTR1 ( DDR0_PUB_REG_BASE + ( 0x2b1 << 2) )
1162#define DDR0_PUB_DX3GTR2 ( DDR0_PUB_REG_BASE + ( 0x2b2 << 2) )
1163#define DDR0_PUB_DX3GTR3 ( DDR0_PUB_REG_BASE + ( 0x2b3 << 2) )
1164
1165#define DDR1_PUB_DX0BDLR0 ( DDR0_PUB_REG_BASE + ( 0x1d0 << 2) )
1166#define DDR1_PUB_DX0BDLR1 ( DDR0_PUB_REG_BASE + ( 0x1d1 << 2) )
1167#define DDR1_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
1168#define DDR1_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
1169#define DDR1_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2) )
1170#define DDR1_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2) )
1171#define DDR1_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2) )
1172#define DDR1_PUB_DX0LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x1e0 << 2) )
1173#define DDR1_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
1174#define DDR1_PUB_DX0LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x1e2 << 2) )
1175#define DDR1_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
1176#define DDR1_PUB_DX0LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x1e4 << 2) )
1177#define DDR1_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
1178#define DDR1_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
1179#define DDR1_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2 ))
1180#define DDR1_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
1181#define DDR1_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
1182#define DDR1_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
1183#define DDR1_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
1184
1185#define DDR1_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2 ))
1186#define DDR1_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2 ))
1187#define DDR1_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2 ))
1188#define DDR1_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2 ))
1189#define DDR1_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2 ))
1190#define DDR1_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE + ( 0x216 << 2 ))
1191#define DDR1_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE + ( 0x218 << 2 ))
1192#define DDR1_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2 ))
1193#define DDR1_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2 ))
1194#define DDR1_PUB_DX1LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x222 << 2 ))
1195#define DDR1_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2 ))
1196#define DDR1_PUB_DX1LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x224 << 2 ))
1197#define DDR1_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2 ))
1198#define DDR1_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2 ))
1199#define DDR1_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2 ))
1200#define DDR1_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
1201#define DDR1_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2 ))
1202#define DDR1_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2 ))
1203#define DDR1_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2 ))
1204
1205#define DDR1_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2 ))
1206#define DDR1_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2 ))
1207#define DDR1_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2 ))
1208#define DDR1_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2 ))
1209#define DDR1_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2 ))
1210#define DDR1_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2 ))
1211#define DDR1_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2 ))
1212#define DDR1_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE + ( 0x260 << 2 ))
1213#define DDR1_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2 ))
1214#define DDR1_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2 ))
1215#define DDR1_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2 ))
1216#define DDR1_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2 ))
1217#define DDR1_PUB_DX2LCDLR5 (DDR0_PUB_REG_BASE + ( 0x265 << 2 ))
1218#define DDR1_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2 ))
1219#define DDR1_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2 ))
1220#define DDR1_PUB_DX2GTR0 (DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
1221#define DDR1_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2 ))
1222#define DDR1_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2 ))
1223#define DDR1_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2 ))
1224
1225#define DDR1_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2 ))
1226#define DDR1_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2 ))
1227#define DDR1_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2 ))
1228#define DDR1_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2 ))
1229#define DDR1_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2 ))
1230#define DDR1_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2 ))
1231#define DDR1_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2 ))
1232#define DDR1_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2 ))
1233#define DDR1_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2 ))
1234#define DDR1_PUB_DX3LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x2a2 << 2 ))
1235#define DDR1_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2 ))
1236#define DDR1_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2 ))
1237#define DDR1_PUB_DX3LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x2a5 << 2 ))
1238#define DDR1_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2 ))
1239#define DDR1_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2 ))
1240#define DDR1_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
1241#define DDR1_PUB_DX3GTR1 (DDR0_PUB_REG_BASE + ( 0x2b1 << 2 ))
1242#define DDR1_PUB_DX3GTR2 (DDR0_PUB_REG_BASE + ( 0x2b2 << 2 ))
1243#define DDR1_PUB_DX3GTR3 (DDR0_PUB_REG_BASE + ( 0x2b3 << 2 ))
1244
1245
1246#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 )) // R/W - LC Delay Line Present Register
1247#define DDR0_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
1248#define DDR0_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
1249#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE + ( 0x150 << 2 )) // R/W - AC Bit Delay Line Register 0
1250#define DDR0_PUB_ACBDLR3 ( DDR0_PUB_REG_BASE + ( 0x153 << 2 ) ) // R/W - AC Bit Delay Line Register 3
1251
1252#define DDR1_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 ) )// R/W - LC Delay Line Present Register
1253#define DDR1_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
1254#define DDR1_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
1255#define DDR1_PUB_ACBDLR0 ( DDR0_PUB_REG_BASE + ( 0x150 << 2 ) )// R/W - AC Bit Delay Line Register 0
1256
1257
1258#define DDR0_PUB_ACMDLR DDR0_PUB_ACMDLR0
1259#define DDR1_PUB_ACMDLR DDR1_PUB_ACMDLR0
1260#define DDR0_PUB_DX0GTR DDR0_PUB_DX0GTR0
1261#define DDR0_PUB_DX1GTR DDR0_PUB_DX1GTR0
1262#define DDR0_PUB_DX2GTR DDR0_PUB_DX2GTR0
1263#define DDR0_PUB_DX3GTR DDR0_PUB_DX3GTR0
1264#define DDR1_PUB_DX0GTR DDR0_PUB_DX0GTR0
1265#define DDR1_PUB_DX1GTR DDR0_PUB_DX1GTR0
1266#define DDR1_PUB_DX2GTR DDR0_PUB_DX2GTR0
1267#define DDR1_PUB_DX3GTR DDR0_PUB_DX3GTR0
1268
1269
1270#define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
1271#define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
1272#define DDR0_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 ) )// R/W - VREF Training Control Register 0
1273#define DDR0_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
1274#define DDR1_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
1275#define DDR1_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
1276#define DDR1_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 )) // R/W - VREF Training Control Register 0
1277#define DDR1_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
1278
1279//#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
1280//#define DDR1_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
1281#define DDR0_PUB_DX0GCR6 ( DDR0_PUB_REG_BASE + ( 0x1c6 << 2 ) )
1282#define DDR0_PUB_DX1GCR6 ( DDR0_PUB_REG_BASE + ( 0x206 << 2 ) )
1283#define DDR0_PUB_DX2GCR6 ( DDR0_PUB_REG_BASE + ( 0x246 << 2 ) )
1284#define DDR0_PUB_DX3GCR6 ( DDR0_PUB_REG_BASE + ( 0x286 << 2 ) )
1285#define DDR0_PUB_DCR ( DDR0_PUB_REG_BASE + ( 0x040 << 2 ) ) // R/W - DRAM Configuration Register
1286#define DDR0_PUB_MR0 ( DDR0_PUB_REG_BASE + ( 0x060 << 2 ) ) // R/W - Mode Register
1287#define DDR0_PUB_MR1 ( DDR0_PUB_REG_BASE + ( 0x061 << 2 ) ) // R/W - Extended Mode Register
1288#define DDR0_PUB_MR2 ( DDR0_PUB_REG_BASE + ( 0x062 << 2 ) ) // R/W - Extended Mode Register 2
1289#define DDR0_PUB_MR3 ( DDR0_PUB_REG_BASE + ( 0x063 << 2 ) ) // R/W - Extended Mode Register 3
1290#define DDR0_PUB_MR4 ( DDR0_PUB_REG_BASE + ( 0x064 << 2 ) ) // R/W - Extended Mode Register 4
1291#define DDR0_PUB_MR5 ( DDR0_PUB_REG_BASE + ( 0x065 << 2 ) ) // R/W - Extended Mode Register 5
1292#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
1293#define DDR0_PUB_MR7 ( DDR0_PUB_REG_BASE + ( 0x067 << 2 ) ) // R/W - Extended Mode Register 7
1294#define DDR0_PUB_MR11 ( DDR0_PUB_REG_BASE + ( 0x06B << 2 ) ) // R/W - Extended Mode Register 11
1295#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x137 << 2 ) ) // R/W - Rank ID Register
1296#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0x080 << 2 ) ) // R/W - Data Training Configuration Register
1297#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x08C << 2 ) ) // R/W - Data Training Eye Data Register 0
1298#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x08D << 2 ) ) // R/W - Data Training Eye Data Register 1
1299#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x08E << 2 ) ) // R/W - Data Training Eye Data Register 2
1300#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x08F << 2 ) ) // R/W - Vref Training Data Register
1301#else
1302
1303#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
1304#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2))
1305#define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2))
1306
1307#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
1308#define DDR1_PUB_PGCR0 (DDR1_PUB_REG_BASE+(0x02<<2))
1309#define DDR1_PUB_PGCR1 (DDR1_PUB_REG_BASE+(0x03<<2))
1310
1311#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2))
1312#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2))
1313#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2))
1314#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2))
1315
1316#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2))
1317#define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2))
1318#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2))
1319#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2))
1320#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2))
1321#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2))
1322
1323#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2))
1324#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2))
1325#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2))
1326#define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2))
1327#define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2))
1328#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2))
1329#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2))
1330#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2))
1331#define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2))
1332#define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2))
1333#define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2))
1334#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2))
1335#define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2))
1336#define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2))
1337#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2))
1338#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2))
1339#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2))
1340#define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2))
1341#define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2))
1342
1343#define DDR1_PUB_DX0LCDLR0 (DDR1_PUB_REG_BASE+(0xAE<<2))
1344#define DDR1_PUB_DX0LCDLR1 (DDR1_PUB_REG_BASE+(0xAF<<2))
1345#define DDR1_PUB_DX0LCDLR2 (DDR1_PUB_REG_BASE+(0xB0<<2))
1346#define DDR1_PUB_DX0MDLR (DDR1_PUB_REG_BASE+(0xB1<<2))
1347#define DDR1_PUB_DX0GTR (DDR1_PUB_REG_BASE+(0xB2<<2))
1348#define DDR1_PUB_DX1LCDLR0 (DDR1_PUB_REG_BASE+(0xCE<<2))
1349#define DDR1_PUB_DX1LCDLR1 (DDR1_PUB_REG_BASE+(0xCF<<2))
1350#define DDR1_PUB_DX1LCDLR2 (DDR1_PUB_REG_BASE+(0xD0<<2))
1351#define DDR1_PUB_DX1MDLR (DDR1_PUB_REG_BASE+(0xD1<<2))
1352#define DDR1_PUB_DX1GTR (DDR1_PUB_REG_BASE+(0xD2<<2))
1353#define DDR1_PUB_DX2LCDLR0 (DDR1_PUB_REG_BASE+(0xEE<<2))
1354#define DDR1_PUB_DX2LCDLR1 (DDR1_PUB_REG_BASE+(0xEF<<2))
1355#define DDR1_PUB_DX2LCDLR2 (DDR1_PUB_REG_BASE+(0xF0<<2))
1356#define DDR1_PUB_DX2MDLR (DDR1_PUB_REG_BASE+(0xF1<<2))
1357#define DDR1_PUB_DX3LCDLR0 (DDR1_PUB_REG_BASE+(0x10E<<2))
1358#define DDR1_PUB_DX3LCDLR1 (DDR1_PUB_REG_BASE+(0x10F<<2))
1359#define DDR1_PUB_DX3LCDLR2 (DDR1_PUB_REG_BASE+(0x110<<2))
1360#define DDR1_PUB_DX3MDLR (DDR1_PUB_REG_BASE+(0x111<<2))
1361#define DDR1_PUB_DX3GTR (DDR1_PUB_REG_BASE+(0x112<<2))
1362
1363
1364#define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2))
1365#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2))
1366#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2))
1367#define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2))
1368#define DDR1_PUB_ACMDLR (DDR1_PUB_REG_BASE+(0x0E<<2))
1369#define DDR1_PUB_ACLCDLR (DDR1_PUB_REG_BASE+(0x0F<<2))
1370#define DDR1_PUB_ACBDLR0 (DDR1_PUB_REG_BASE+(0x10<<2))
1371
1372#define DDR0_PUB_ACMDLR0 DDR0_PUB_ACMDLR
1373#define DDR1_PUB_ACMDLR0 DDR1_PUB_ACMDLR
1374#define DDR0_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
1375#define DDR0_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
1376#define DDR0_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
1377#define DDR0_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
1378#define DDR1_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
1379#define DDR1_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
1380#define DDR1_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
1381#define DDR1_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
1382#define DDR0_PUB_DCR (DDR0_PUB_REG_BASE+(0x22<<2))
1383#define DDR0_PUB_MR0 (DDR0_PUB_REG_BASE+(0x27<<2))
1384#define DDR0_PUB_MR1 (DDR0_PUB_REG_BASE+(0x28<<2))
1385#define DDR0_PUB_MR2 (DDR0_PUB_REG_BASE+(0x29<<2))
1386#define DDR0_PUB_MR3 (DDR0_PUB_REG_BASE+(0x2A<<2))
1387#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Rank ID Register
1388#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0<< 2 ) ) // R/W - Data Training Configuration Register
1389#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 0
1390#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Data Training Eye Data Register 1
1391#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 2
1392#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Vref Training Data Register
1393
1394#ifndef P_DDR0_CLK_CTRL
1395#define P_DDR0_CLK_CTRL 0xc8000800
1396#endif
1397#ifndef P_DDR1_CLK_CTRL
1398#define P_DDR1_CLK_CTRL 0xc8002800
1399#endif
1400
1401#define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2))
1402#define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2))
1403#endif
1404
1405#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
1406//unsigned int des[8];
1407/*
1408 unsigned int pattern_1[4][8]=
1409 {
1410 0xff00ff00 ,
14110xff00ff00 ,
14120xff00ff00 ,
14130xff00ff00 ,
14140xff00ff00 ,
14150xff00ff00 ,
14160xff00ff00 ,
14170xff00ff00 ,
14180xff00ff00 ,
14190xff00ff00 ,
14200xff00ff00 ,
14210xff00ff00 ,
14220xff00ff00 ,
14230xff00ff00 ,
14240xff00ff00 ,
14250xff00ff00 ,
14260xff00ff00 ,
14270xff00ff00 ,
14280xff00ff00 ,
14290xff00ff00 ,
14300xff00ff00 ,
14310xff00ff00 ,
14320xff00ff00 ,
14330xff00ff00 ,
14340xff00ff00 ,
14350xff00ff00 ,
14360xff00ff00 ,
14370xff00ff00 ,
14380xff00ff00 ,
14390xff00ff00 ,
14400xff00ff00 ,
14410xff00ff00 ,
1442
1443};
1444unsigned int pattern_2[4][8]={
14450x0001fe00 ,
14460x0000ff00 ,
14470x0000ff00 ,
14480x0000ff00 ,
14490x0002fd00 ,
14500x0000ff00 ,
14510x0000ff00 ,
14520x0000ff00 ,
14530x0004fb00 ,
14540x0000ff00 ,
14550x0000ff00 ,
14560x0000ff00 ,
14570x0008f700 ,
14580x0000ff00 ,
14590x0000ff00 ,
14600x0000ff00 ,
14610x0010ef00 ,
14620x0000ff00 ,
14630x0000ff00 ,
14640x0000ff00 ,
14650x0020df00 ,
14660x0000ff00 ,
14670x0000ff00 ,
14680x0000ff00 ,
14690x0040bf00 ,
14700x0000ff00 ,
14710x0000ff00 ,
14720x0000ff00 ,
14730x00807f00 ,
14740x0000ff00 ,
14750x0000ff00 ,
14760x0000ff00 ,
1477
1478};
1479unsigned int pattern_3[4][8]={
1480 0x00010000 ,
1481 0x00000000 ,
1482 0x00000000 ,
1483 0x00000000 ,
1484 0x00020000 ,
1485 0x00000000 ,
1486 0x00000000 ,
1487 0x00000000 ,
1488 0x00040000 ,
1489 0x00000000 ,
1490 0x00000000 ,
1491 0x00000000 ,
1492 0x00080000 ,
1493 0x00000000 ,
1494 0x00000000 ,
1495 0x00000000 ,
1496 0x00100000 ,
1497 0x00000000 ,
1498 0x00000000 ,
1499 0x00000000 ,
1500 0x00200000 ,
1501 0x00000000 ,
1502 0x00000000 ,
1503 0x00000000 ,
1504 0x00400000 ,
1505 0x00000000 ,
1506 0x00000000 ,
1507 0x00000000 ,
1508 0x00800000 ,
1509 0x00000000 ,
1510 0x00000000 ,
1511 0x00000000 ,
1512};
1513unsigned int pattern_4[4][8]={
1514 0x51c8c049 ,
1515 0x2d43592c ,
1516 0x0777b50b ,
1517 0x9cd2ebe5 ,
1518 0xc04199d5 ,
1519 0xdc968dc0 ,
1520 0xb8ba8a33 ,
1521 0x35e4327f ,
1522 0x51c8c049 ,
1523 0x2d43592c ,
1524 0x0777b50b ,
1525 0x9cd2ebe5 ,
1526 0xc04199d5 ,
1527 0xdc968dc0 ,
1528 0xb8ba8a33 ,
1529 0x35e4327f ,
1530 0x51c8c049 ,
1531 0x2d43592c ,
1532 0x0777b50b ,
1533 0x9cd2ebe5 ,
1534 0xc04199d5 ,
1535 0xdc968dc0 ,
1536 0xb8ba8a33 ,
1537 0x35e4327f ,
1538 0x51c8c049 ,
1539 0x2d43592c ,
1540 0x0777b50b ,
1541 0x9cd2ebe5 ,
1542 0xc04199d5 ,
1543 0xdc968dc0 ,
1544 0xb8ba8a33 ,
1545 0x35e4327f ,
1546};
1547unsigned int pattern_5[4][8]={
1548 0xaec9c149 ,
1549 0xd243592c ,
1550 0xf877b50b ,
1551 0x63d2ebe5 ,
1552 0x3f439bd5 ,
1553 0x23968dc0 ,
1554 0x47ba8a33 ,
1555 0xcae4327f ,
1556 0xaeccc449 ,
1557 0xd243592c ,
1558 0xf877b50b ,
1559 0x63d2ebe5 ,
1560 0x3f4991d5 ,
1561 0x23968dc0 ,
1562 0x47ba8a33 ,
1563 0xcae4327f ,
1564 0xaed8d049 ,
1565 0xd243592c ,
1566 0xf877b50b ,
1567 0x63d2ebe5 ,
1568 0x3f61b9d5 ,
1569 0x23968dc0 ,
1570 0x47ba8a33 ,
1571 0xcae4327f ,
1572 0xae888049 ,
1573 0xd243592c ,
1574 0xf877b50b ,
1575 0x63d2ebe5 ,
1576 0x3fc119d5 ,
1577 0x23968dc0 ,
1578 0x47ba8a33 ,
1579 0xcae4327f ,
1580};
1581unsigned int pattern_6[4][8]={
1582 0xaec9c149 ,
1583 0xd243a62c ,
1584 0xf8774a0b ,
1585 0x63d214e5 ,
1586 0x3f4366d5 ,
1587 0x239672c0 ,
1588 0x47ba7533 ,
1589 0xcae4cd7f ,
1590 0xaecc3f49 ,
1591 0xd243a62c ,
1592 0xf8774a0b ,
1593 0x63d214e5 ,
1594 0x3f4966d5 ,
1595 0x239672c0 ,
1596 0x47ba7533 ,
1597 0xcae4cd7f ,
1598 0xaed83f49 ,
1599 0xd243a62c ,
1600 0xf8774a0b ,
1601 0x63d214e5 ,
1602 0x3f6166d5 ,
1603 0x239672c0 ,
1604 0x47ba7533 ,
1605 0xcae4cd7f ,
1606 0xae883f49 ,
1607 0xd243a62c ,
1608 0xf8774a0b ,
1609 0x63d214e5 ,
1610 0x3fc166d5 ,
1611 0x239672c0 ,
1612 0x47ba7533 ,
1613 0xcae4cd7f ,
1614
1615};
1616unsigned int des[8] ={
1617 0xaec83f49,
1618 0xd243a62c,
1619 0xf8774a0b,
1620 0x63d214e5,
1621 0x3f4166d5,
1622 0x239672c0,
1623 0x47ba7533,
1624 0xcae4cd7f,
1625};
1626*/
1627/*
1628 unsigned int des[8] ;
1629 des[0] = 0xaec83f49;
1630 des[1] = 0xd243a62c;
1631 des[2] = 0xf8774a0b;
1632 des[3] = 0x63d214e5;
1633 des[4] = 0x3f4166d5;
1634 des[5] = 0x239672c0;
1635 des[6] = 0x47ba7533;
1636 des[7] = 0xcae4cd7f;
1637 pattern_1[0][0] = 0xff00ff00;
1638 pattern_1[0][1] = 0xff00ff00;
1639 pattern_1[0][2] = 0xff00ff00;
1640 pattern_1[0][3] = 0xff00ff00;
1641 pattern_1[0][4] = 0xff00ff00;
1642 pattern_1[0][5] = 0xff00ff00;
1643 pattern_1[0][6] = 0xff00ff00;
1644 pattern_1[0][7] = 0xff00ff00;
1645
1646 pattern_1[1][0] = 0xff00ff00;
1647 pattern_1[1][1] = 0xff00ff00;
1648 pattern_1[1][2] = 0xff00ff00;
1649 pattern_1[1][3] = 0xff00ff00;
1650 pattern_1[1][4] = 0xff00ff00;
1651 pattern_1[1][5] = 0xff00ff00;
1652 pattern_1[1][6] = 0xff00ff00;
1653 pattern_1[1][7] = 0xff00ff00;
1654
1655 pattern_1[2][0] = 0xff00ff00;
1656 pattern_1[2][1] = 0xff00ff00;
1657 pattern_1[2][2] = 0xff00ff00;
1658 pattern_1[2][3] = 0xff00ff00;
1659 pattern_1[2][4] = 0xff00ff00;
1660 pattern_1[2][5] = 0xff00ff00;
1661 pattern_1[2][6] = 0xff00ff00;
1662 pattern_1[2][7] = 0xff00ff00;
1663
1664 pattern_1[3][0] = 0xff00ff00;
1665 pattern_1[3][1] = 0xff00ff00;
1666 pattern_1[3][2] = 0xff00ff00;
1667 pattern_1[3][3] = 0xff00ff00;
1668 pattern_1[3][4] = 0xff00ff00;
1669 pattern_1[3][5] = 0xff00ff00;
1670 pattern_1[3][6] = 0xff00ff00;
1671 pattern_1[3][7] = 0xff00ff00;
1672
1673 pattern_2[0][0] = 0x0001fe00;
1674 pattern_2[0][1] = 0x0000ff00;
1675 pattern_2[0][2] = 0x0000ff00;
1676 pattern_2[0][3] = 0x0000ff00;
1677 pattern_2[0][4] = 0x0002fd00;
1678 pattern_2[0][5] = 0x0000ff00;
1679 pattern_2[0][6] = 0x0000ff00;
1680 pattern_2[0][7] = 0x0000ff00;
1681
1682 pattern_2[1][0] = 0x0004fb00;
1683 pattern_2[1][1] = 0x0000ff00;
1684 pattern_2[1][2] = 0x0000ff00;
1685 pattern_2[1][3] = 0x0000ff00;
1686 pattern_2[1][4] = 0x0008f700;
1687 pattern_2[1][5] = 0x0000ff00;
1688 pattern_2[1][6] = 0x0000ff00;
1689 pattern_2[1][7] = 0x0000ff00;
1690
1691 pattern_2[2][0] = 0x0010ef00;
1692 pattern_2[2][1] = 0x0000ff00;
1693 pattern_2[2][2] = 0x0000ff00;
1694 pattern_2[2][3] = 0x0000ff00;
1695 pattern_2[2][4] = 0x0020df00;
1696 pattern_2[2][5] = 0x0000ff00;
1697 pattern_2[2][6] = 0x0000ff00;
1698pattern_2[2][7] = 0x0000ff00;
1699
1700pattern_2[3][0] = 0x0040bf00;
1701pattern_2[3][1] = 0x0000ff00;
1702pattern_2[3][2] = 0x0000ff00;
1703pattern_2[3][3] = 0x0000ff00;
1704pattern_2[3][4] = 0x00807f00;
1705pattern_2[3][5] = 0x0000ff00;
1706pattern_2[3][6] = 0x0000ff00;
1707pattern_2[3][7] = 0x0000ff00;
1708
1709pattern_3[0][0] = 0x00010000;
1710pattern_3[0][1] = 0x00000000;
1711pattern_3[0][2] = 0x00000000;
1712pattern_3[0][3] = 0x00000000;
1713pattern_3[0][4] = 0x00020000;
1714pattern_3[0][5] = 0x00000000;
1715pattern_3[0][6] = 0x00000000;
1716pattern_3[0][7] = 0x00000000;
1717
1718pattern_3[1][0] = 0x00040000;
1719pattern_3[1][1] = 0x00000000;
1720pattern_3[1][2] = 0x00000000;
1721pattern_3[1][3] = 0x00000000;
1722pattern_3[1][4] = 0x00080000;
1723 pattern_3[1][5] = 0x00000000;
1724 pattern_3[1][6] = 0x00000000;
1725 pattern_3[1][7] = 0x00000000;
1726
1727 pattern_3[2][0] = 0x00100000;
1728 pattern_3[2][1] = 0x00000000;
1729 pattern_3[2][2] = 0x00000000;
1730 pattern_3[2][3] = 0x00000000;
1731 pattern_3[2][4] = 0x00200000;
1732 pattern_3[2][5] = 0x00000000;
1733 pattern_3[2][6] = 0x00000000;
1734 pattern_3[2][7] = 0x00000000;
1735
1736 pattern_3[3][0] = 0x00400000;
1737 pattern_3[3][1] = 0x00000000;
1738 pattern_3[3][2] = 0x00000000;
1739 pattern_3[3][3] = 0x00000000;
1740 pattern_3[3][4] = 0x00800000;
1741 pattern_3[3][5] = 0x00000000;
1742 pattern_3[3][6] = 0x00000000;
1743 pattern_3[3][7] = 0x00000000;
1744
1745pattern_4[0][0] = 0x51c8c049 ;
1746pattern_4[0][1] = 0x2d43592c ;
1747pattern_4[0][2] = 0x0777b50b ;
1748pattern_4[0][3] = 0x9cd2ebe5 ;
1749pattern_4[0][4] = 0xc04199d5 ;
1750pattern_4[0][5] = 0xdc968dc0 ;
1751pattern_4[0][6] = 0xb8ba8a33 ;
1752pattern_4[0][7] = 0x35e4327f ;
1753
1754pattern_4[1][0] = 0x51c8c049 ;
1755pattern_4[1][1] = 0x2d43592c ;
1756pattern_4[1][2] = 0x0777b50b ;
1757pattern_4[1][3] = 0x9cd2ebe5 ;
1758pattern_4[1][4] = 0xc04199d5 ;
1759pattern_4[1][5] = 0xdc968dc0 ;
1760pattern_4[1][6] = 0xb8ba8a33 ;
1761pattern_4[1][7] = 0x35e4327f ;
1762
1763pattern_4[2][0] = 0x51c8c049 ;
1764pattern_4[2][1] = 0x2d43592c ;
1765pattern_4[2][2] = 0x0777b50b ;
1766pattern_4[2][3] = 0x9cd2ebe5 ;
1767pattern_4[2][4] = 0xc04199d5 ;
1768pattern_4[2][5] = 0xdc968dc0 ;
1769pattern_4[2][6] = 0xb8ba8a33 ;
1770pattern_4[2][7] = 0x35e4327f ;
1771
1772pattern_4[3][0] = 0x51c8c049 ;
1773pattern_4[3][1] = 0x2d43592c ;
1774pattern_4[3][2] = 0x0777b50b ;
1775pattern_4[3][3] = 0x9cd2ebe5 ;
1776pattern_4[3][4] = 0xc04199d5 ;
1777pattern_4[3][5] = 0xdc968dc0 ;
1778pattern_4[3][6] = 0xb8ba8a33 ;
1779pattern_4[3][7] = 0x35e4327f ;
1780
1781pattern_5[0][0] = 0xaec9c149 ;
1782pattern_5[0][1] = 0xd243592c ;
1783pattern_5[0][2] = 0xf877b50b ;
1784pattern_5[0][3] = 0x63d2ebe5 ;
1785pattern_5[0][4] = 0x3f439bd5 ;
1786pattern_5[0][5] = 0x23968dc0 ;
1787pattern_5[0][6] = 0x47ba8a33 ;
1788pattern_5[0][7] = 0xcae4327f ;
1789pattern_5[1][0] = 0xaeccc449 ;
1790pattern_5[1][1] = 0xd243592c ;
1791pattern_5[1][2] = 0xf877b50b ;
1792pattern_5[1][3] = 0x63d2ebe5 ;
1793pattern_5[1][4] = 0x3f4991d5 ;
1794pattern_5[1][5] = 0x23968dc0 ;
1795pattern_5[1][6] = 0x47ba8a33 ;
1796pattern_5[1][7] = 0xcae4327f ;
1797pattern_5[2][0] = 0xaed8d049 ;
1798pattern_5[2][1] = 0xd243592c ;
1799pattern_5[2][2] = 0xf877b50b ;
1800pattern_5[2][3] = 0x63d2ebe5 ;
1801pattern_5[2][4] = 0x3f61b9d5 ;
1802pattern_5[2][5] = 0x23968dc0 ;
1803pattern_5[2][6] = 0x47ba8a33 ;
1804pattern_5[2][7] = 0xcae4327f ;
1805pattern_5[3][0] = 0xae888049 ;
1806pattern_5[3][1] = 0xd243592c ;
1807pattern_5[3][2] = 0xf877b50b ;
1808pattern_5[3][3] = 0x63d2ebe5 ;
1809pattern_5[3][4] = 0x3fc119d5 ;
1810pattern_5[3][5] = 0x23968dc0 ;
1811pattern_5[3][6] = 0x47ba8a33 ;
1812pattern_5[3][7] = 0xcae4327f ;
1813
1814pattern_6[0][1] = 0xd243a62c ;
1815pattern_6[0][2] = 0xf8774a0b ;
1816pattern_6[0][3] = 0x63d214e5 ;
1817pattern_6[0][4] = 0x3f4366d5 ;
1818pattern_6[0][5] = 0x239672c0 ;
1819pattern_6[0][6] = 0x47ba7533 ;
1820pattern_6[0][7] = 0xcae4cd7f ;
1821pattern_6[1][0] = 0xaecc3f49 ;
1822pattern_6[1][1] = 0xd243a62c ;
1823pattern_6[1][2] = 0xf8774a0b ;
1824pattern_6[1][3] = 0x63d214e5 ;
1825pattern_6[1][4] = 0x3f4966d5 ;
1826pattern_6[1][5] = 0x239672c0 ;
1827pattern_6[1][6] = 0x47ba7533 ;
1828pattern_6[1][7] = 0xcae4cd7f ;
1829pattern_6[2][0] = 0xaed83f49 ;
1830pattern_6[2][1] = 0xd243a62c ;
1831pattern_6[2][2] = 0xf8774a0b ;
1832pattern_6[2][3] = 0x63d214e5 ;
1833pattern_6[2][4] = 0x3f6166d5 ;
1834pattern_6[2][5] = 0x239672c0 ;
1835pattern_6[2][6] = 0x47ba7533 ;
1836pattern_6[2][7] = 0xcae4cd7f ;
1837pattern_6[3][0] = 0xae883f49 ;
1838pattern_6[3][1] = 0xd243a62c ;
1839pattern_6[3][2] = 0xf8774a0b ;
1840pattern_6[3][3] = 0x63d214e5 ;
1841pattern_6[3][4] = 0x3fc166d5 ;
1842pattern_6[3][5] = 0x239672c0 ;
1843pattern_6[3][6] = 0x47ba7533 ;
1844pattern_6[3][7] = 0xcae4cd7f ;
1845*/
1846#endif
1847
1848#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START
1849#define DDR_TEST_SIZE 0x2000000
1850//#define DDR_TEST_SIZE 0x2000
1851
1852#if (CONFIG_CHIP>=CHIP_TXLX)
1853
1854#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000)
1855
1856///*
1857//#ifndef P_PIN_MUX_REG1
1858// Pin Mux (9)
1859// ----------------------------
1860#if (CONFIG_CHIP==CHIP_TXLX)
1861#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
1862#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
1863#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x2c << 2))
1864#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
1865#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
1866#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x2d << 2))
1867#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
1868#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
1869#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x2e << 2))
1870#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
1871#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
1872#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x2f << 2))
1873#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
1874#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
1875#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x30 << 2))
1876#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
1877#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
1878#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x31 << 2))
1879#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
1880#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
1881#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x32 << 2))
1882#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
1883#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
1884#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x33 << 2))
1885#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
1886#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
1887#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x34 << 2))
1888#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
1889#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
1890#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x35 << 2))
1891#define PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
1892#define SEC_PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
1893#define P_PERIPHS_PIN_MUX_10 (volatile uint32_t *)(0xff634400 + (0x36 << 2))
1894#define PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
1895#define SEC_PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
1896#define P_PERIPHS_PIN_MUX_11 (volatile uint32_t *)(0xff634400 + (0x37 << 2))
1897#define PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
1898#define SEC_PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
1899#define P_PERIPHS_PIN_MUX_12 (volatile uint32_t *)(0xff634400 + (0x38 << 2))
1900#endif
1901#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
1902#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
1903#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
1904#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2))))
1905//#endif
1906
1907//#ifndef P_PWM_MISC_REG_AB
1908//#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
1909//#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
1910//#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
1911//#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
1912//#endif
1913//*/
1914//#define PWM_MISC_REG_AB (0x6c02)
1915//#define P_PWM_MISC_REG_AB (volatile unsigned int *)((0x6c02 << 2) + 0xffd00000)
1916//#define WATCHDOG_CNTL ((0x3c34 << 2) + 0xffd00000)
1917//#define WATCHDOG_CNTL1 ((0x3c35 << 2) + 0xffd00000)
1918//#define WATCHDOG_TCNT ((0x3c36 << 2) + 0xffd00000)
1919//#define WATCHDOG_RESET ((0x3c37 << 2) + 0xffd00000)
1920#else
1921//#define ddr_udelay(a) do{}while((a<<5)--);
1922#define P_EE_TIMER_E (volatile unsigned int *)(((0x2662 << 2) + 0xc1100000))
1923//#define WATCHDOG_CNTL 0xc11098d0
1924//#define WATCHDOG_CNTL1 0xc11098d4
1925//#define WATCHDOG_TCNT 0xc11098d8
1926//#define WATCHDOG_RESET 0xc11098dc
1927#ifndef P_WATCHDOG_CNTL
1928#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
1929#define P_WATCHDOG_CNTL (volatile unsigned int *)0xc11098d0
1930#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
1931#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
1932#define P_WATCHDOG_RESET (volatile unsigned int *) 0xc11098dc
1933#else
1934#define P_WATCHDOG_CNTL (volatile unsigned int *)(0xc1100000+(0x2640<<2))
1935//#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
1936//#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
1937#define P_WATCHDOG_RESET (volatile unsigned int *)(0xc1100000+(0x2641<<2))
1938#endif
1939#endif
1940
1941
1942#ifndef P_PIN_MUX_REG1
1943#define P_PIN_MUX_REG1 (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
1944#define P_PIN_MUX_REG2 (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
1945#define P_PIN_MUX_REG3 (((volatile unsigned *)(0xda834400 + (0x2f << 2))))
1946#define P_PIN_MUX_REG7 (((volatile unsigned *)(0xda834400 + (0x33 << 2))))
1947#endif
1948
1949#ifndef P_PWM_MISC_REG_AB
1950#define P_PWM_MISC_REG_AB (((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
1951#define P_PWM_PWM_B (((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
1952#define P_PWM_MISC_REG_CD (((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
1953#define P_PWM_PWM_D (((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
1954#endif
1955
1956#ifndef P_EE_TIMER_E
1957#define P_EE_TIMER_E (((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
1958#endif
1959
1960#endif
1961
1962#define get_us_time() (*P_EE_TIMER_E)// (readl(P_ISA_TIMERE))
1963
1964// #define P_ISA_TIMERE 0xc1109988
1965// #define get_us_time() (readl(P_ISA_TIMERE))
1966
1967/*
1968#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
1969#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
1970
1971#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xff807000 + (0x02 << 2))))
1972#define P_PWM_PWM_A (*((volatile unsigned *)((0x6c00 << 2) + 0xffd00000)))
1973
1974#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
1975*/
1976
1977#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))=((uint16_t)dat)
1978#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))
1979#define ACX_MAX 0x80
1980
1981void ddr_udelay(unsigned int us)
1982{
1983//#ifndef CONFIG_PXP_EMULATOR
1984 unsigned int t0 = (*((P_EE_TIMER_E)));
1985
1986 while ((*((P_EE_TIMER_E))) - t0 <= us)
1987 ;
1988//#endif
1989}
1990
1991#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
1992#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
1993#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
1994#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
1995
1996#define DDR_PARAMETER_READ 1
1997#define DDR_PARAMETER_WRITE 2
1998#define DDR_PARAMETER_LEFT 1
1999#define DDR_PARAMETER_RIGHT 2
2000
2001typedef struct ddr_test_struct {
2002 unsigned int ddr_data_source ;
2003 unsigned int ddr_data_test_size ;
2004 unsigned int ddr_address_test_size ;
2005 unsigned int ddr_test_watchdog_times_s ;
2006 unsigned int ddr_test_lane_disable ;
2007
2008 unsigned int ddr_test_window_flag[8] ;
2009 unsigned int ddr_test_window_data[100] ;
2010} ddr_test_struct_t;
2011ddr_test_struct_t *g_ddr_test_struct;
2012
2013unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
2014{
2015
2016 if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
2017 {
2018 sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
2019
2020 if (read_write_flag == DDR_PARAMETER_WRITE)
2021 wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
2022 if (read_write_flag == DDR_PARAMETER_READ)
2023 parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
2024 }
2025
2026 if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
2027 {
2028 char *pre_env_name = "ddr_test_data_num";
2029 char *env_name = "ddr_test_data_num_0000";
2030 char *str_buf = NULL;
2031 char *temp_s = NULL;
2032 char *endp = NULL;
2033 char buf[1024];
2034 str_buf = (char *)(&buf);
2035 memset(str_buf, 0, sizeof(buf));
2036 sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
2037 sprintf(buf, "0x%08x", parameter_value);
2038
2039 if (read_write_flag == DDR_PARAMETER_WRITE)
2040 {
2041 env_set(env_name, buf);
2042 run_command("save",0);
2043 }
2044 if (read_write_flag == DDR_PARAMETER_READ)
2045 {
2046 temp_s = env_get(env_name);
2047 if (temp_s)
2048 parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
2049 else
2050 parameter_value = 0;
2051 }
2052 }
2053
2054 if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
2055 {
2056 sticky_reg_base_add=(PREG_STICKY_REG0);
2057
2058 if (read_write_flag == DDR_PARAMETER_WRITE)
2059 wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
2060 if (read_write_flag == DDR_PARAMETER_READ)
2061 parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
2062 }
2063 return parameter_value;
2064}
2065
2066
2067unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
2068{
2069
2070 if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
2071 {
2072 sticky_reg_base_add = PREG_STICKY_REG0;
2073
2074 if (read_write_flag == DDR_PARAMETER_WRITE)
2075 wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
2076 if (read_write_flag == DDR_PARAMETER_READ)
2077 parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
2078 }
2079
2080 if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
2081 {
2082 sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
2083
2084 if (read_write_flag == DDR_PARAMETER_WRITE)
2085 wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
2086 if (read_write_flag == DDR_PARAMETER_READ)
2087 parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
2088 }
2089
2090 if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
2091 {
2092 char *pre_env_name = "ddr_test_data_num";
2093 char *env_name = "ddr_test_data_num_0000";
2094 char *str_buf = NULL;
2095 char *temp_s = NULL;
2096 char *endp = NULL;
2097 char buf[1024];
2098 str_buf = (char *)(&buf);
2099 memset(str_buf, 0, sizeof(buf));
2100 sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
2101 sprintf(buf, "0x%08x", parameter_value);
2102
2103 if (read_write_flag == DDR_PARAMETER_WRITE)
2104 {
2105 env_set(env_name, buf);
2106 run_command("save",0);
2107 }
2108 if (read_write_flag == DDR_PARAMETER_READ)
2109 {
2110 temp_s = env_get(env_name);
2111 if (temp_s)
2112 parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
2113 else
2114 parameter_value = 0;
2115 }
2116 }
2117
2118 return parameter_value;
2119}
2120
2121void ddr_test_watchdog_init(uint32_t msec)
2122{
2123
2124 // src: 24MHz
2125 // div: 24000 for 1ms
2126 // reset ao-22 and ee-21
2127 // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
2128#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
2129 *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1);
2130
2131 // set timeout
2132 //*P_WATCHDOG_TCNT = msec;
2133 // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
2134 *P_WATCHDOG_TCNT = msec;
2135 //writel(0,(unsigned int )P_WATCHDOG_RESET);
2136 *P_WATCHDOG_RESET = 0;
2137 //*P_WATCHDOG_RESET = 0;
2138
2139 // enable
2140 *P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18);
2141 //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
2142 //*P_WATCHDOG_CNTL |= (1<<18);
2143#else
2144 *P_WATCHDOG_CNTL = (0<<24)|(msec*8-1);
2145 //*P_WATCHDOG_TCNT=msec;
2146#endif
2147}
2148
2149void ddr_test_watchdog_enable(uint32_t sec)
2150{
2151
2152 // src: 24MHz
2153 // div: 24000 for 1ms
2154 // reset ao-22 and ee-21
2155 // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
2156#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
2157 *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
2158 // set timeout
2159 //*P_WATCHDOG_TCNT = msec;
2160 // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
2161 if (sec*100>0xffff)
2162 *P_WATCHDOG_TCNT=0xffff;
2163 else
2164 *P_WATCHDOG_TCNT=sec*100; //max 655s
2165 //writel(0,(unsigned int )P_WATCHDOG_RESET);
2166 *P_WATCHDOG_RESET=0;
2167 //*P_WATCHDOG_RESET = 0;
2168
2169 // enable
2170 *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
2171 //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
2172 //*P_WATCHDOG_CNTL |= (1<<18);
2173#else
2174 //*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1);
2175 *P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff);
2176 printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n");
2177#endif
2178 printf("\nP_WATCHDOG_ENABLE\n");
2179}
2180
2181void ddr_test_watchdog_disable(void )
2182{
2183
2184 // src: 24MHz
2185 // div: 24000 for 1ms
2186 // reset ao-22 and ee-21
2187 // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
2188#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
2189 *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
2190 // set timeout
2191 //*P_WATCHDOG_TCNT = msec;
2192 // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
2193 //*P_WATCHDOG_TCNT=sec*100;
2194 //writel(0,(unsigned int )P_WATCHDOG_RESET);
2195 *P_WATCHDOG_RESET=0;
2196 //*P_WATCHDOG_RESET = 0;
2197
2198 // enable
2199 *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
2200 //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
2201 //*P_WATCHDOG_CNTL |= (1<<18);
2202#else
2203 *P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1);
2204#endif
2205 printf("\nP_WATCHDOG_DISABLE\n");
2206}
2207
2208
2209void ddr_test_watchdog_clear(void )
2210{
2211
2212 // src: 24MHz
2213 // div: 24000 for 1ms
2214 // reset ao-22 and ee-21
2215 // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
2216 //*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
2217 // set timeout
2218 //*P_WATCHDOG_TCNT = msec;
2219 // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
2220 //*P_WATCHDOG_TCNT=sec*100;
2221 //writel(0,(unsigned int )P_WATCHDOG_RESET);
2222 *P_WATCHDOG_RESET=0;
2223 //*P_WATCHDOG_RESET = 0;
2224
2225 // enable
2226 //*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
2227 //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
2228 //*P_WATCHDOG_CNTL |= (1<<18);
2229 //printf("\nP_WATCHDOG_CLEAR,reg=0x%8x\n",(P_WATCHDOG_RESET));
2230}
2231
2232void ddr_test_watchdog_reset_system(void)
2233{
2234 //#define P_WATCHDOG_CNTL 0xc11098d0
2235 //#define P_WATCHDOG_CNTL1 0xc11098d4
2236 //#define P_WATCHDOG_TCNT 0xc11098d8
2237 //#define P_WATCHDOG_RESET 0xc11098dc
2238#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
2239 int i;
2240
2241 while (1) {
2242 /*
2243 writel( 0x3 | (1 << 21) // sys reset en ao ee 3
2244 | (1 << 23) // interrupt en
2245 | (1 << 24) // clk en
2246 | (1 << 25) // clk div en
2247 | (1 << 26) // sys reset now ao ee 3
2248 , (unsigned int )P_WATCHDOG_CNTL);
2249 */
2250 *P_WATCHDOG_CNTL=
2251 0x3 | (1 << 21) // sys reset en ao ee 3
2252 | (1 << 23) // interrupt en
2253 | (1 << 24) // clk en
2254 | (1 << 25) // clk div en
2255 | (1 << 26); // sys reset now ao ee 3;
2256 //printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL));
2257 //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
2258 //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
2259 printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL,
2260 *P_WATCHDOG_CNTL);
2261 //writel(0, (unsigned int )P_WATCHDOG_RESET);
2262 *P_WATCHDOG_RESET=0;
2263
2264 // writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en
2265 //(unsigned int )P_WATCHDOG_CNTL);
2266 *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
2267 for (i=0; i<100; i++)
2268 *P_WATCHDOG_CNTL;
2269 //readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
2270 }
2271
2272#else
2273 //WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
2274 *P_WATCHDOG_CNTL=(0xf080000 | 2000);
2275#endif
2276 while (1) ;
2277}
2278
2279
2280//just tune for lcdlr
2281
2282#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
2283#else
2284int do_ddr_fine_tune_lcdlr_env1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
2285{
2286 printf("\nEnter ddr_fine_tune_lcdlr_env function\n");
2287 // if(!argc)
2288 // goto DDR_TUNE_DQS_START;
2289 int i = 0;
2290 printf("\nargc== 0x%08x\n", argc);
2291 for (i = 0; i<argc; i++)
2292 {
2293 printf("\nargv[%d]=%s\n",i,argv[i]);
2294 }
2295
2296 //writel((0), 0xc8836c00);
2297 OPEN_CHANNEL_A_PHY_CLK();
2298
2299 OPEN_CHANNEL_B_PHY_CLK();
2300 //writel((0), 0xc8836c00);
2301
2302 char *endp;
2303 // unsigned int *p_start_addr;
2304
2305#define WR_RD_ADJ_USE_ENV 1
2306#define WR_RD_ADJ_USE_UART_INPUT 2
2307 unsigned int wr_rd_adj_input_src=1;
2308 int wr_adj_per[12]={
2309 100 ,
2310 1000,
2311 100 ,
2312 100 ,
2313 100 ,
2314 100 ,
2315 100 ,
2316 100 ,
2317 100 ,
2318 100 ,
2319 100 ,
2320 100 ,
2321 };
2322 int rd_adj_per[12]={
2323 100 ,
2324 100 ,
2325 80 ,
2326 80 ,
2327 80 ,
2328 80 ,
2329 100 ,
2330 100 ,
2331 100 ,
2332 100 ,
2333 100 ,
2334 100 ,
2335 };
2336 if (argc == 1)
2337 printf("\nplease read help\n");
2338
2339 if (argc >= 2)
2340 {
2341 wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
2342
2343 unsigned int i=0;
2344 if (wr_rd_adj_input_src == WR_RD_ADJ_USE_UART_INPUT)
2345 {
2346 printf("\ntune ddr lcdlr use uart input\n");
2347 if (argc>24+2)
2348 argc=24+2;
2349
2350 for (i = 2;i<argc;i++)
2351 {
2352 if (i<(2+12))
2353 wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
2354 else
2355 rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
2356 }
2357 }
2358
2359 // unsigned int = 0, max = 0xff, min = 0x00;
2360 if (wr_rd_adj_input_src == WR_RD_ADJ_USE_ENV)
2361 {
2362 printf("\ntune ddr lcdlr use uboot env\n");
2363 //char str[24];
2364 const char *s;
2365
2366 // char *varname;
2367 int value=0;
2368
2369 //*varname="env_ddrtest";
2370 s = env_get("env_wr_lcdlr_pr");
2371 if (s)
2372 {//i=0;
2373 //while(s_temp)
2374 {
2375 printf("%s",s);
2376 //sscanf(s,"d%,",wr_adj_per);
2377 //sprintf(str,"d%",s);
2378 //getc
2379 }
2380 value = simple_strtoull_ddr(s, &endp, 16);
2381 printf("%d",value);
2382 }
2383 s = env_get("env_rd_lcdlr_pr");
2384
2385 if (s)
2386 {//i=0;
2387 //while(s_temp)
2388 {
2389 printf("%s",s);
2390 //sscanf(s,"d%,",rd_adj_per);
2391
2392 }
2393 //value = simple_strtoull_ddr(s, &endp, 16);
2394 }
2395
2396 //sprintf(str, "%lx", value);
2397 // env_set("env_ddrtest", str);
2398 //run_command("save",0);
2399
2400 if (argc>24+2)
2401 argc=24+2;
2402 for (i = 2;i<argc;i++)
2403 {
2404 if (i<(2+12))
2405 wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
2406 else
2407 rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
2408 }
2409 }
2410 printf(" int wr_adj_per[12]={\n");
2411 for (i = 0;i<12;i++)
2412 printf("%04d ,\n",wr_adj_per[i]);
2413 printf("};\n");
2414 printf(" int rd_adj_per[12]={\n");
2415 for (i = 0;i<12;i++)
2416 printf("%04d ,\n",rd_adj_per[i]);
2417 printf("};\n");
2418
2419#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
2420 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
2421 wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))|(1<<0));
2422 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
2423 wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))|(1<<0));
2424#else
2425 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
2426 wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))|(1<<26));
2427 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
2428 wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))|(1<<26));
2429#endif
2430
2431 int lcdlr_w=0,lcdlr_r=0;
2432 unsigned temp_reg=0;
2433 int temp_count=0;
2434 for ( temp_count=0;temp_count<2;temp_count++)
2435 { temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
2436 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
2437 lcdlr_w=lcdlr_w?lcdlr_w:1;
2438 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2439 if (temp_count == 1)
2440 lcdlr_w=lcdlr_w&ACBDLR_MAX;
2441 wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
2442 }
2443#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
2444 for ( temp_count=2;temp_count<6;temp_count++)
2445 { temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
2446 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
2447 lcdlr_w=lcdlr_w?lcdlr_w:1;
2448 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
2449 lcdlr_r=lcdlr_r?lcdlr_r:1;
2450 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2451 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
2452 wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
2453 wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
2454 wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
2455 }
2456#else
2457 for ( temp_count=2;temp_count<6;temp_count++) {
2458 temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
2459 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
2460 lcdlr_w=lcdlr_w?lcdlr_w:1;
2461 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&DQLCDLR_MAX);
2462 lcdlr_r=lcdlr_r?lcdlr_r:1;
2463 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2464 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
2465 wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
2466 }
2467#endif
2468 for ( temp_count=6;temp_count<8;temp_count++) {
2469 temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
2470
2471 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
2472 lcdlr_w=lcdlr_w?lcdlr_w:1;
2473 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2474 if (temp_count == 7)
2475 lcdlr_w=lcdlr_w&ACBDLR_MAX;
2476 wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
2477 }
2478#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
2479 for ( temp_count=8;temp_count<12;temp_count++) {
2480 temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
2481 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
2482 lcdlr_w=lcdlr_w?lcdlr_w:1;
2483 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
2484 lcdlr_r=lcdlr_r?lcdlr_r:1;
2485 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2486 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
2487 wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
2488 wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
2489 wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
2490 }
2491#else
2492 for ( temp_count=8;temp_count<12;temp_count++) {
2493 temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
2494 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
2495 lcdlr_w=lcdlr_w?lcdlr_w:1;
2496 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&0xff);
2497 lcdlr_r=lcdlr_r?lcdlr_r:1;
2498 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
2499 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
2500 wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
2501 }
2502#endif
2503
2504#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
2505 wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
2506 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
2507
2508 wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))&(~(1<<0)));
2509 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
2510#else
2511 wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))&(~(1<<26)));
2512 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
2513
2514 wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))&(~(1<<26)));
2515 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
2516#endif
2517 printf("\nend adjust lcdlr\n");
2518
2519 CLOSE_CHANNEL_A_PHY_CLK();
2520 CLOSE_CHANNEL_B_PHY_CLK();
2521 }
2522
2523 return 1;
2524}
2525U_BOOT_CMD(
2526 ddr_test_tune_dqs_env, 30, 1, do_ddr_fine_tune_lcdlr_env1,
2527 "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3...",
2528 "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
2529);
2530
2531#endif
2532//*/
2533static void ddr_write(void *buff, unsigned int m_length)
2534{
2535 unsigned int *p;
2536 unsigned int i, j, n;
2537 unsigned int m_len = m_length;
2538
2539 p = ( unsigned int *)buff;
2540
2541 while (m_len)
2542 {
2543 for (j=0;j<32;j++)
2544 {
2545
2546 if (m_len >= 128)
2547 n = 32;
2548 else
2549 n = m_len>>2;
2550
2551 for (i = 0; i < n; i++)
2552 {
2553#ifdef DDR_PREFETCH_CACHE
2554 ddr_pld_cache(p) ;
2555#endif
2556 switch (i)
2557 {
2558 case 0:
2559 case 9:
2560 case 14:
2561 case 25:
2562 case 30:
2563 *(p+i) = TDATA32F;
2564 break;
2565 case 1:
2566 case 6:
2567 case 8:
2568 case 17:
2569 case 22:
2570 *(p+i) = 0;
2571 break;
2572 case 16:
2573 case 23:
2574 case 31:
2575 *(p+i) = TDATA32A;
2576 break;
2577 case 7:
2578 case 15:
2579 case 24:
2580 *(p+i) = TDATA325;
2581 break;
2582 case 2:
2583 case 4:
2584 case 10:
2585 case 12:
2586 case 19:
2587 case 21:
2588 case 27:
2589 case 29:
2590 *(p+i) = 1<<j;
2591 break;
2592 case 3:
2593 case 5:
2594 case 11:
2595 case 13:
2596 case 18:
2597 case 20:
2598 case 26:
2599 case 28:
2600 *(p+i) = ~(1<<j);
2601 break;
2602 }
2603 }
2604
2605 if (m_len > 128)
2606 {
2607 m_len -= 128;
2608 p += 32;
2609 }
2610 else
2611 {
2612 p += (m_len>>2);
2613 m_len = 0;
2614 break;
2615 }
2616 }
2617 }
2618}
2619
2620static void ddr_read(void *buff, unsigned int m_length)
2621{
2622 unsigned int *p;
2623 unsigned int i, j, n;
2624 unsigned int m_len = m_length;
2625
2626 p = ( unsigned int *)buff;
2627
2628 while (m_len)
2629 {
2630 for (j=0;j<32;j++)
2631 {
2632
2633 if (m_len >= 128)
2634 n = 32;
2635 else
2636 n = m_len>>2;
2637
2638 for (i = 0; i < n; i++)
2639 {
2640#ifdef DDR_PREFETCH_CACHE
2641 ddr_pld_cache(p) ;
2642#endif
2643 if ((error_outof_count_flag) && (error_count))
2644 {
2645 printf("Error data out of count");
2646 m_len=0;
2647 break;
2648 }
2649 switch (i)
2650 {
2651
2652 case 0:
2653 case 9:
2654 case 14:
2655 case 25:
2656 case 30:
2657 if (*(p+i) != TDATA32F)
2658 {error_count++;
2659 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2660 }
2661 break;
2662 case 1:
2663 case 6:
2664 case 8:
2665 case 17:
2666 case 22:
2667 if (*(p+i) != 0) {error_count++;
2668 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
2669 }break;
2670 case 16:
2671 case 23:
2672 case 31:
2673 if (*(p+i) != TDATA32A) {error_count++;
2674 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
2675 } break;
2676 case 7:
2677 case 15:
2678 case 24:
2679 if (*(p+i) != TDATA325) {error_count++;
2680 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
2681 } break;
2682 case 2:
2683 case 4:
2684 case 10:
2685 case 12:
2686 case 19:
2687 case 21:
2688 case 27:
2689 case 29:
2690 if (*(p+i) != 1<<j) {error_count++;
2691 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j);
2692 } break;
2693 case 3:
2694 case 5:
2695 case 11:
2696 case 13:
2697 case 18:
2698 case 20:
2699 case 26:
2700 case 28:
2701 if (*(p+i) != ~(1<<j)) {error_count++;
2702 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j));
2703 } break;
2704 }
2705 }
2706
2707 if (m_len > 128)
2708 {
2709 m_len -= 128;
2710 p += 32;
2711 }
2712 else
2713 {
2714 p += (m_len>>2);
2715 m_len = 0;
2716 break;
2717 }
2718 }
2719 }
2720}
2721
2722
2723static void ddr_write4(void *buff, unsigned int m_length)
2724{
2725 unsigned int *p;
2726 unsigned int i, j, n;
2727 unsigned int m_len = m_length;
2728
2729 p = ( unsigned int *)buff;
2730
2731 while (m_len)
2732 {
2733 for (j=0;j<32;j++)
2734 {
2735
2736 if (m_len >= 128)
2737 n = 32;
2738 else
2739 n = m_len>>2;
2740
2741 for (i = 0; i < n; i++)
2742 {
2743#ifdef DDR_PREFETCH_CACHE
2744 ddr_pld_cache(p) ;
2745#endif
2746 switch (i)
2747 {
2748 case 0:
2749 case 1:
2750 case 2:
2751 case 3:
2752
2753 *(p+i) = 0xff00ff00;
2754 break;
2755 case 4:
2756 case 5:
2757 case 6:
2758 case 7:
2759
2760 *(p+i) = ~0xff00ff00;
2761 break;
2762 case 8:
2763 case 9:
2764 case 10:
2765 case 11:
2766 *(p+i) = 0xaa55aa55;
2767 break;
2768 case 12:
2769 case 13:
2770 case 14:
2771 case 15:
2772 *(p+i) = ~0xaa55aa55;
2773 break;
2774 case 16:
2775 case 17:
2776 case 18:
2777 case 19:
2778
2779 case 24:
2780 case 25:
2781 case 26:
2782 case 27:
2783
2784 *(p+i) = 1<<j;
2785 break;
2786
2787 case 20:
2788 case 21:
2789 case 22:
2790 case 23:
2791 case 28:
2792 case 29:
2793 case 30:
2794 case 31:
2795 *(p+i) = ~(1<<j);
2796 break;
2797 }
2798 }
2799
2800 if (m_len > 128)
2801 {
2802 m_len -= 128;
2803 p += 32;
2804 }
2805 else
2806 {
2807 p += (m_len>>2);
2808 m_len = 0;
2809 break;
2810 }
2811 }
2812 }
2813}
2814
2815static void ddr_read4(void *buff, unsigned int m_length)
2816{
2817 unsigned int *p;
2818 unsigned int i, j, n;
2819 unsigned int m_len = m_length;
2820
2821 p = ( unsigned int *)buff;
2822
2823 while (m_len)
2824 {
2825 for (j=0;j<32;j++)
2826 {
2827
2828 if (m_len >= 128)
2829 n = 32;
2830 else
2831 n = m_len>>2;
2832
2833 for (i = 0; i < n; i++)
2834 {
2835#ifdef DDR_PREFETCH_CACHE
2836 ddr_pld_cache(p) ;
2837#endif
2838 if ((error_outof_count_flag) && (error_count))
2839 {
2840 printf("Error data out of count");
2841 m_len=0;
2842 break;
2843 }
2844 switch (i)
2845 {
2846
2847 case 0:
2848 case 1:
2849 case 2:
2850 case 3:
2851
2852 // *(p+i) = 0xff00ff00;
2853 if (*(p+i) != 0xff00ff00)
2854 {error_count++;
2855 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2856 }
2857 break;
2858 case 4:
2859 case 5:
2860 case 6:
2861 case 7:
2862
2863 // *(p+i) = ~0xff00ff00;
2864 if (*(p+i) != ~0xff00ff00)
2865 {error_count++;
2866 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2867 }
2868 break;
2869 case 8:
2870 case 9:
2871 case 10:
2872 case 11:
2873 // *(p+i) = 0xaa55aa55;
2874 if (*(p+i) != 0xaa55aa55)
2875 {error_count++;
2876 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2877 }
2878 break;
2879 case 12:
2880 case 13:
2881 case 14:
2882 case 15:
2883 // *(p+i) = ~0xaa55aa55;
2884 if (*(p+i) != ~0xaa55aa55)
2885 {error_count++;
2886 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2887 }
2888 break;
2889 case 16:
2890 case 17:
2891 case 18:
2892 case 19:
2893
2894 case 24:
2895 case 25:
2896 case 26:
2897 case 27:
2898
2899 // *(p+i) = 1<<j;
2900 if (*(p+i) != (1<<j))
2901 {error_count++;
2902 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2903 }
2904 break;
2905
2906 case 20:
2907 case 21:
2908 case 22:
2909 case 23:
2910 case 28:
2911 case 29:
2912 case 30:
2913 case 31:
2914 // *(p+i) = ~(1<<j);
2915 if (*(p+i) !=~( 1<<j))
2916 {error_count++;
2917 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
2918 }
2919 break;
2920 }
2921 }
2922
2923 if (m_len > 128)
2924 {
2925 m_len -= 128;
2926 p += 32;
2927 }
2928 else
2929 {
2930 p += (m_len>>2);
2931 m_len = 0;
2932 break;
2933 }
2934 }
2935 }
2936}
2937
2938static void ddr_read_full(void *buff, unsigned int m_length,unsigned int start_pattern,
2939 unsigned int pattern_offset)
2940{
2941 unsigned int *p;
2942 unsigned int i=0;
2943 unsigned int m_len = m_length&0xfffffffc;
2944
2945 p = ( unsigned int *)buff;
2946 //*(p)=start_pattern;
2947 while (m_len)
2948 {
2949 m_len=m_len-4;
2950
2951 // *(p+i) = (*(p))+pattern_offset;
2952
2953#ifdef DDR_PREFETCH_CACHE
2954 ddr_pld_cache(p+i) ;
2955#endif
2956 if ((error_outof_count_flag) && (error_count))
2957 {
2958 printf("Error data out of count");
2959 m_len=0;
2960 break;
2961 }
2962 if ((*(p+i)) !=(start_pattern+pattern_offset*i))
2963 {error_count++;
2964 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
2965 (start_pattern+pattern_offset*i));
2966 }
2967 break;
2968
2969 i++;
2970 }
2971}
2972
2973static void ddr_write_full(void *buff, unsigned int m_length,unsigned int start_pattern,
2974 unsigned int pattern_offset)
2975{
2976 unsigned int *p;
2977 unsigned int i=0;
2978 unsigned int m_len = m_length&0xfffffffc;
2979
2980 p = ( unsigned int *)buff;
2981 //*(p)=start_pattern;
2982 while (m_len)
2983 {
2984 m_len=m_len-4;
2985 *(p+i) = start_pattern+pattern_offset*i;
2986 i++;
2987 }
2988}
2989
2990///*
2991static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size)
2992{
2993 unsigned int *p_dest;
2994 unsigned int *p_src;
2995
2996 unsigned int m_len = memcpy_size;
2997
2998 p_dest = ( unsigned int *)addr_dest;
2999 p_src = ( unsigned int *)addr_src;
3000 m_len = m_len/4; //assume it's multiple of 4
3001 while (m_len--) {
3002 ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
3003 *p_dest++ = *p_src++;
3004 *p_dest++ = *p_src++;
3005 *p_dest++ = *p_src++;
3006 *p_dest++ = *p_src++;
3007 }
3008}
3009//*/
3010int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
3011{
3012 char *endp;
3013 unsigned long loop = 1;
3014 unsigned int print_flag =1;
3015 // unsigned int start_addr = DDR_TEST_START_ADDR;
3016 unsigned int src_addr = DDR_TEST_START_ADDR;
3017 unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000;
3018 unsigned int test_size = DDR_TEST_SIZE;
3019
3020
3021 print_flag=1;
3022
3023 printf("\nargc== 0x%08x\n", argc);
3024 int i ;
3025 for (i = 0;i<argc;i++)
3026 printf("\nargv[%d]=%s\n",i,argv[i]);
3027
3028 // printf("\nLINE== 0x%08x\n", __LINE__);
3029 if (argc ==1) {
3030 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
3031 // if (*argv[2] == 0 || *endp != 0)
3032 src_addr = DDR_TEST_START_ADDR;
3033 loop = 1;
3034 }
3035 if (argc > 2) {
3036 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
3037 if (*argv[2] == 0 || *endp != 0)
3038 src_addr = DDR_TEST_START_ADDR;
3039 }
3040 if (argc > 3) {
3041 src_addr = simple_strtoull_ddr(argv[1], &endp, 16);
3042 dec_addr = simple_strtoull_ddr(argv[2], &endp, 16);
3043 test_size = simple_strtoull_ddr(argv[3], &endp, 16);
3044 loop = 1;
3045 if (*argv[3] == 0 || *endp != 0)
3046 test_size = DDR_TEST_SIZE;
3047
3048 }
3049 if (test_size<0x1000)
3050 test_size = DDR_TEST_SIZE;
3051 if (argc > 4) {
3052 loop = simple_strtoull_ddr(argv[4], &endp, 16);
3053 if (*argv[4] == 0 || *endp != 0)
3054 loop = 1;
3055 }
3056 if (argc > 5) {
3057 print_flag = simple_strtoull_ddr(argv[5], &endp, 16);
3058 if (*argv[5] == 0 || *endp != 0)
3059 print_flag = 1;
3060 }
3061 //COPY_TEST_START:
3062
3063 ///*
3064 unsigned long time_start, time_end,test_loops;
3065 test_loops=loop;
3066 unsigned long size_count=0;
3067 size_count=loop*test_size;
3068 time_start = get_us_time();//us
3069
3070 do {
3071 // loop = 1;
3072 ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size);
3073 //bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
3074 //mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
3075 if (print_flag)
3076 {
3077 printf("\nloop==0x%08x", ( unsigned int )loop);
3078 printf("\n \n");
3079 }
3080 }while(--loop);
3081 //*/
3082 time_end = get_us_time();//us
3083 printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start));
3084
3085 printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
3086 printf("\rEnd ddr test. \n");
3087
3088 unsigned int m_len=0,counter=0;
3089 unsigned int *p_dest;
3090 p_dest= (void *)(int_convter_p(dec_addr));
3091 m_len = test_size/4; //assume it's multiple of 4
3092 counter=(unsigned int)test_loops;
3093 size_count=counter*test_size;
3094 time_start = get_us_time();//us
3095 do {
3096 loop = 1;
3097 m_len = test_size/4;
3098 while (m_len--) {
3099 ddr_pld_cache(p_dest) ;
3100 *p_dest++ = 0x12345678;
3101 *p_dest++ = 0x12345678;
3102 *p_dest++ = 0x12345678;
3103 *p_dest++ = 0x12345678;
3104 }
3105 }while(--counter);
3106 time_end = get_us_time();//us
3107 printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start));
3108
3109 printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
3110
3111 unsigned int *p_src;
3112 p_src= (void *)(int_convter_p(src_addr));
3113 m_len = test_size/4; //assume it's multiple of 4
3114 unsigned int temp0=0;
3115 //unsigned int temp1=0;
3116 //unsigned int temp2=0;
3117 //unsigned int temp3=0;
3118 counter=(unsigned int)test_loops;
3119 size_count=counter*test_size;
3120
3121 // #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
3122 //writel((1000000<<0), DMC_MON_CTRL1);
3123 //writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
3124 //writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
3125 time_start = get_us_time();//us
3126 do {
3127 loop = 1;
3128 m_len = test_size/4;
3129 while (m_len--) {
3130 // ddr_pld_cache(p_src++) ;
3131#ifdef DDR_PREFETCH_CACHE
3132 __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src));
3133#endif
3134 p_src++;
3135 temp0 =( *p_src);
3136 m_len--;
3137 m_len--;
3138 m_len--;
3139 m_len--;
3140 m_len--;
3141 m_len--;
3142 m_len--;
3143 }
3144 }while(--counter);
3145 *p_dest++ = temp0;
3146 *p_dest++ = *p_src;
3147 *p_dest++ = *p_src;
3148 *p_dest++ = *p_src;
3149 time_end = get_us_time();//us
3150
3151 printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start));
3152 printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
3153
3154 return 0;
3155}
3156
3157U_BOOT_CMD(
3158 ddr_test_copy, 7, 1, do_ddr_test_copy,
3159 "ddr_test_copy function",
3160 "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n"
3161);
3162
3163///*
3164#define DDR_PATTERN_LOOP_1 32
3165#define DDR_PATTERN_LOOP_2 64
3166#define DDR_PATTERN_LOOP_3 96
3167/*
3168__asm
3169{
3170.Global memcpy_pld
3171.type memcpy_pld ,%function
3172.align 8
3173memcpy_pld:
3174mov x4,x0
3175subs x2,x2,#8
3176b.mi 2f
31771: ldr x3,[x1],#8
3178 subs x2,x2,#8
3179 str x3,[x4],#8
3180 prfm PLDL1KEEP,[x1,#376]
3181 b.pl 1b
3182
31832: adds x2,x2,#4
3184 b.mi 3f
3185 ldr w3,[x1],#4
3186 sub x2,x2,#4
3187 str w3,[x4],#4
3188
31893: adds x2,x2,#2
3190 b.mi 4f
3191 ldr w3,[x1],#2
3192 sub x2,x2,#4
3193 str w3,[x4],#4
3194
31954: adds x2,x2,#1
3196 b.mi 5f
3197 ldr w3,[x1],#2
3198 sub x2,x2,#4
3199 str w3,[x4],#4
3200
32015: ret
3202}
3203*/
3204//static void ddr_memcpy_pld(void *addr_dest, void *addr_src, unsigned int m_length)
3205//{
3206/*
3207asm
3208{
3209//.Global memcpy_pld
3210.type memcpy_pld ,%function
3211.align 8
3212memcpy_pld:
3213mov x4,x0
3214subs x2,x2,#8
3215b.mi 2f
32161: ldr x3,[x1],#8
3217 subs x2,x2,#8
3218 str x3,[x4],#8
3219 prfm PLDL1KEEP,[x1,#376]
3220 b.pl 1b
3221
32222: adds x2,x2,#4
3223 b.mi 3f
3224 ldr w3,[x1],#4
3225 sub x2,x2,#4
3226 str w3,[x4],#4
3227
32283: adds x2,x2,#2
3229 b.mi 4f
3230 ldr w3,[x1],#2
3231 sub x2,x2,#4
3232 str w3,[x4],#4
3233
32344: adds x2,x2,#1
3235 b.mi 5f
3236 ldr w3,[x1],#2
3237 sub x2,x2,#4
3238 str w3,[x4],#4
3239
32405: ret
3241}
3242memcpy_pld(addr_dest,addr_src,m_length);
3243*/
3244//}
3245
3246
3247
3248#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
3249
3250///*
3251
3252int ddr_test_gx_cross_talk_pattern(int ddr_test_size)
3253{
3254 unsigned int start_addr = 0x10000000;
3255 error_outof_count_flag=1;
3256 error_count=0;
3257
3258 unsigned int des[8] ;
3259 unsigned int pattern_1[4][8] ;
3260 unsigned int pattern_2[4][8] ;
3261 unsigned int pattern_3[4][8] ;
3262 unsigned int pattern_4[4][8] ;
3263 unsigned int pattern_5[4][8] ;
3264 unsigned int pattern_6[4][8] ;
3265
3266 des[0] = 0xaec83f49;
3267 des[1] = 0xd243a62c;
3268 des[2] = 0xf8774a0b;
3269 des[3] = 0x63d214e5;
3270 des[4] = 0x3f4166d5;
3271 des[5] = 0x239672c0;
3272 des[6] = 0x47ba7533;
3273 des[7] = 0xcae4cd7f;
3274 pattern_1[0][0] = 0xff00ff00;
3275 pattern_1[0][1] = 0xff00ff00;
3276 pattern_1[0][2] = 0xff00ff00;
3277 pattern_1[0][3] = 0xff00ff00;
3278 pattern_1[0][4] = 0xff00ff00;
3279 pattern_1[0][5] = 0xff00ff00;
3280 pattern_1[0][6] = 0xff00ff00;
3281 pattern_1[0][7] = 0xff00ff00;
3282
3283 pattern_1[1][0] = 0x00ffff00;
3284 pattern_1[1][1] = 0x00ffff00;
3285 pattern_1[1][2] = 0x00ffff00;
3286 pattern_1[1][3] = 0x00ffff00;
3287 pattern_1[1][4] = 0x00ffff00;
3288 pattern_1[1][5] = 0x00ffff00;
3289 pattern_1[1][6] = 0x00ffff00;
3290 pattern_1[1][7] = 0x00ffff00;
3291
3292 pattern_1[2][0] = 0xffff0000;
3293 pattern_1[2][1] = 0xffff0000;
3294 pattern_1[2][2] = 0xffff0000;
3295 pattern_1[2][3] = 0xffff0000;
3296 pattern_1[2][4] = 0xffff0000;
3297 pattern_1[2][5] = 0xffff0000;
3298 pattern_1[2][6] = 0xffff0000;
3299 pattern_1[2][7] = 0xffff0000;
3300 pattern_1[3][0] = 0xff00ff00;
3301 pattern_1[3][1] = 0xff00ff00;
3302 pattern_1[3][2] = 0xff00ff00;
3303 pattern_1[3][3] = 0xff00ff00;
3304 pattern_1[3][4] = 0xff00ff00;
3305 pattern_1[3][5] = 0xff00ff00;
3306 pattern_1[3][6] = 0xff00ff00;
3307 pattern_1[3][7] = 0xff00ff00;
3308
3309 pattern_2[0][0] = 0x0001fe00;
3310 pattern_2[0][1] = 0x0000ff00;
3311 pattern_2[0][2] = 0x0000ff00;
3312 pattern_2[0][3] = 0x0000ff00;
3313 pattern_2[0][4] = 0x0002fd00;
3314 pattern_2[0][5] = 0x0000ff00;
3315 pattern_2[0][6] = 0x0000ff00;
3316 pattern_2[0][7] = 0x0000ff00;
3317
3318 pattern_2[1][0] = 0x0004fb00;
3319 pattern_2[1][1] = 0x0000ff00;
3320 pattern_2[1][2] = 0x0000ff00;
3321 pattern_2[1][3] = 0x0000ff00;
3322 pattern_2[1][4] = 0x0008f700;
3323 pattern_2[1][5] = 0x0000ff00;
3324 pattern_2[1][6] = 0x0000ff00;
3325 pattern_2[1][7] = 0x0000ff00;
3326
3327 pattern_2[2][0] = 0x0010ef00;
3328 pattern_2[2][1] = 0x0000ff00;
3329 pattern_2[2][2] = 0x0000ff00;
3330 pattern_2[2][3] = 0x0000ff00;
3331 pattern_2[2][4] = 0x0020df00;
3332 pattern_2[2][5] = 0x0000ff00;
3333 pattern_2[2][6] = 0x0000ff00;
3334 pattern_2[2][7] = 0x0000ff00;
3335
3336 pattern_2[3][0] = 0x0040bf00;
3337 pattern_2[3][1] = 0x0000ff00;
3338 pattern_2[3][2] = 0x0000ff00;
3339 pattern_2[3][3] = 0x0000ff00;
3340 pattern_2[3][4] = 0x00807f00;
3341 pattern_2[3][5] = 0x0000ff00;
3342 pattern_2[3][6] = 0x0000ff00;
3343 pattern_2[3][7] = 0x0000ff00;
3344
3345 pattern_3[0][0] = 0x00010000;
3346 pattern_3[0][1] = 0x00000000;
3347 pattern_3[0][2] = 0x00000000;
3348 pattern_3[0][3] = 0x00000000;
3349 pattern_3[0][4] = 0x00020000;
3350 pattern_3[0][5] = 0x00000000;
3351 pattern_3[0][6] = 0x00000000;
3352 pattern_3[0][7] = 0x00000000;
3353
3354 pattern_3[1][0] = 0x00040000;
3355 pattern_3[1][1] = 0x00000000;
3356 pattern_3[1][2] = 0x00000000;
3357 pattern_3[1][3] = 0x00000000;
3358 pattern_3[1][4] = 0x00080000;
3359 pattern_3[1][5] = 0x00000000;
3360 pattern_3[1][6] = 0x00000000;
3361 pattern_3[1][7] = 0x00000000;
3362
3363 pattern_3[2][0] = 0x00100000;
3364 pattern_3[2][1] = 0x00000000;
3365 pattern_3[2][2] = 0x00000000;
3366 pattern_3[2][3] = 0x00000000;
3367 pattern_3[2][4] = 0x00200000;
3368 pattern_3[2][5] = 0x00000000;
3369 pattern_3[2][6] = 0x00000000;
3370 pattern_3[2][7] = 0x00000000;
3371
3372 pattern_3[3][0] = 0x00400000;
3373 pattern_3[3][1] = 0x00000000;
3374 pattern_3[3][2] = 0x00000000;
3375 pattern_3[3][3] = 0x00000000;
3376 pattern_3[3][4] = 0x00800000;
3377 pattern_3[3][5] = 0x00000000;
3378 pattern_3[3][6] = 0x00000000;
3379 pattern_3[3][7] = 0x00000000;
3380
3381 ///*
3382 pattern_4[0][0] = 0x51c8c049 ;
3383 pattern_4[0][1] = 0x2d43592c ;
3384 pattern_4[0][2] = 0x0777b50b ;
3385 pattern_4[0][3] = 0x9cd2ebe5 ;
3386 pattern_4[0][4] = 0xc04199d5 ;
3387 pattern_4[0][5] = 0xdc968dc0 ;
3388 pattern_4[0][6] = 0xb8ba8a33 ;
3389 pattern_4[0][7] = 0x35e4327f ;
3390
3391 pattern_4[1][0] = 0xae37c049 ;
3392 pattern_4[1][1] = 0xd2bc592c ;
3393 pattern_4[1][2] = 0xf888b50b ;
3394 pattern_4[1][3] = 0x632debe5 ;
3395 pattern_4[1][4] = 0x3fbe99d5 ;
3396 pattern_4[1][5] = 0x23698dc0 ;
3397 pattern_4[1][6] = 0x47458a33 ;
3398 pattern_4[1][7] = 0xca1b327f ;
3399
3400 pattern_4[2][0] = 0x51373f49 ;
3401 pattern_4[2][1] = 0x2dbca62c ;
3402 pattern_4[2][2] = 0x07884a0b ;
3403 pattern_4[2][3] = 0x9c2d14e5 ;
3404 pattern_4[2][4] = 0xc0be66d5 ;
3405 pattern_4[2][5] = 0xdc6972c0 ;
3406 pattern_4[2][6] = 0xb8457533 ;
3407 pattern_4[2][7] = 0x351bcd7f ;
3408
3409
3410 pattern_4[3][0] = 0x51c8c049 ;
3411 pattern_4[3][1] = 0x2d43592c ;
3412 pattern_4[3][2] = 0x0777b50b ;
3413 pattern_4[3][3] = 0x9cd2ebe5 ;
3414 pattern_4[3][4] = 0xc04199d5 ;
3415 pattern_4[3][5] = 0xdc968dc0 ;
3416 pattern_4[3][6] = 0xb8ba8a33 ;
3417 pattern_4[3][7] = 0x35e4327f ;
3418
3419 pattern_5[0][0] = 0xaec9c149 ;
3420 pattern_5[0][1] = 0xd243592c ;
3421 pattern_5[0][2] = 0xf877b50b ;
3422 pattern_5[0][3] = 0x63d2ebe5 ;
3423 pattern_5[0][4] = 0x3f439bd5 ;
3424 pattern_5[0][5] = 0x23968dc0 ;
3425 pattern_5[0][6] = 0x47ba8a33 ;
3426 pattern_5[0][7] = 0xcae4327f ;
3427 pattern_5[1][0] = 0xaeccc449 ;
3428 pattern_5[1][1] = 0xd243592c ;
3429 pattern_5[1][2] = 0xf877b50b ;
3430 pattern_5[1][3] = 0x63d2ebe5 ;
3431 pattern_5[1][4] = 0x3f4991d5 ;
3432 pattern_5[1][5] = 0x23968dc0 ;
3433 pattern_5[1][6] = 0x47ba8a33 ;
3434 pattern_5[1][7] = 0xcae4327f ;
3435 pattern_5[2][0] = 0xaed8d049 ;
3436 pattern_5[2][1] = 0xd243592c ;
3437 pattern_5[2][2] = 0xf877b50b ;
3438 pattern_5[2][3] = 0x63d2ebe5 ;
3439 pattern_5[2][4] = 0x3f61b9d5 ;
3440 pattern_5[2][5] = 0x23968dc0 ;
3441 pattern_5[2][6] = 0x47ba8a33 ;
3442 pattern_5[2][7] = 0xcae4327f ;
3443 pattern_5[3][0] = 0xae888049 ;
3444 pattern_5[3][1] = 0xd243592c ;
3445 pattern_5[3][2] = 0xf877b50b ;
3446 pattern_5[3][3] = 0x63d2ebe5 ;
3447 pattern_5[3][4] = 0x3fc119d5 ;
3448 pattern_5[3][5] = 0x23968dc0 ;
3449 pattern_5[3][6] = 0x47ba8a33 ;
3450 pattern_5[3][7] = 0xcae4327f ;
3451
3452 pattern_6[0][0] = 0xaec93f49 ;
3453 pattern_6[0][1] = 0xd243a62c ;
3454 pattern_6[0][2] = 0xf8774a0b ;
3455 pattern_6[0][3] = 0x63d214e5 ;
3456 pattern_6[0][4] = 0x3f4366d5 ;
3457 pattern_6[0][5] = 0x239672c0 ;
3458 pattern_6[0][6] = 0x47ba7533 ;
3459 pattern_6[0][7] = 0xcae4cd7f ;
3460 pattern_6[1][0] = 0xaecc3f49 ;
3461 pattern_6[1][1] = 0xd243a62c ;
3462 pattern_6[1][2] = 0xf8774a0b ;
3463 pattern_6[1][3] = 0x63d214e5 ;
3464 pattern_6[1][4] = 0x3f4966d5 ;
3465 pattern_6[1][5] = 0x239672c0 ;
3466 pattern_6[1][6] = 0x47ba7533 ;
3467 pattern_6[1][7] = 0xcae4cd7f ;
3468 pattern_6[2][0] = 0xaed83f49 ;
3469 pattern_6[2][1] = 0xd243a62c ;
3470 pattern_6[2][2] = 0xf8774a0b ;
3471 pattern_6[2][3] = 0x63d214e5 ;
3472 pattern_6[2][4] = 0x3f6166d5 ;
3473 pattern_6[2][5] = 0x239672c0 ;
3474 pattern_6[2][6] = 0x47ba7533 ;
3475 pattern_6[2][7] = 0xcae4cd7f ;
3476 pattern_6[3][0] = 0xae883f49 ;
3477 pattern_6[3][1] = 0xd243a62c ;
3478 pattern_6[3][2] = 0xf8774a0b ;
3479 pattern_6[3][3] = 0x63d214e5 ;
3480 pattern_6[3][4] = 0x3fc166d5 ;
3481 pattern_6[3][5] = 0x239672c0 ;
3482 pattern_6[3][6] = 0x47ba7533 ;
3483 pattern_6[3][7] = 0xcae4cd7f ;
3484 //*/
3485 //*/
3486 start_addr=0x10000000;
3487 unsigned int test_size = 0x20;
3488 unsigned int test_addr;
3489 unsigned int temp_i=0;
3490 unsigned int temp_k=0;
3491 unsigned int pattern_o[8];
3492 unsigned int pattern_d[8];
3493 {
3494 // if(lflag)
3495 // loop = 888;
3496
3497 //if(old_pattern_flag==1)
3498 {
3499
3500 printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
3501
3502 /*
3503 for ((temp_k=0);(temp_k<4);(temp_k++)) {
3504 {
3505
3506 for ((temp_i=0);(temp_i<8);(temp_i++))
3507 {
3508 test_addr=start_addr+(temp_i<<2);
3509 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3510 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3511 //des[temp_i]^pattern_2[temp_k][temp_i]
3512 }
3513 // _clean_dcache_addr(0x10000000);
3514 flush_dcache_range(start_addr,start_addr + test_size);
3515
3516 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3517 test_addr=start_addr+(temp_i<<2);
3518 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3519 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
3520 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3521 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
3522 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
3523 {error_count++;
3524 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
3525 }
3526 }
3527 }
3528 }
3529 */
3530 //if(pattern_flag1==1)
3531 {
3532 for ((temp_k=0);(temp_k<4);(temp_k++))
3533 {
3534 {
3535 ddr_udelay(10000);
3536 for ((temp_i=0);(temp_i<8);(temp_i++))
3537 {
3538 test_addr=start_addr+(temp_i<<2);
3539 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3540 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3541 //des[temp_i]^pattern_2[temp_k][temp_i]
3542 }
3543 // _clean_dcache_addr(0x10000000);
3544#ifdef DDR_PREFETCH_CACHE
3545 flush_dcache_range(start_addr,start_addr + test_size);
3546#endif
3547 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3548 test_addr=start_addr+(temp_i<<2);
3549 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3550 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
3551 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3552 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
3553 if (pattern_o[temp_i] != pattern_4[temp_k][temp_i])
3554 {error_count++;
3555 printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
3556 }
3557
3558 }
3559 }
3560 }
3561 for ((temp_k=0);(temp_k<4);(temp_k++))
3562 {
3563 {
3564 ddr_udelay(10000);
3565 for ((temp_i=0);(temp_i<8);(temp_i++))
3566 {
3567 test_addr=start_addr+(temp_i<<2);
3568 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3569 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3570 //des[temp_i]^pattern_2[temp_k][temp_i]
3571 }
3572 // _clean_dcache_addr(0x10000000);
3573#ifdef DDR_PREFETCH_CACHE
3574 flush_dcache_range(start_addr,start_addr + test_size);
3575#endif
3576 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3577 test_addr=start_addr+(temp_i<<2);
3578 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3579 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
3580 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3581 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
3582 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
3583 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
3584 {error_count++;
3585 printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]);
3586 }
3587
3588 }
3589 }
3590 }
3591 }
3592 //if(pattern_flag2==1)
3593 {
3594 for ((temp_k=0);(temp_k<4);(temp_k++)) {
3595 {
3596 ddr_udelay(10000);
3597 for ((temp_i=0);(temp_i<8);(temp_i++))
3598 {
3599 test_addr=start_addr+(temp_i<<2);
3600 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3601 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3602 //des[temp_i]^pattern_2[temp_k][temp_i]
3603 }
3604 // _clean_dcache_addr(0x10000000);
3605#ifdef DDR_PREFETCH_CACHE
3606 flush_dcache_range(start_addr,start_addr + test_size);
3607#endif
3608 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3609 test_addr=start_addr+(temp_i<<2);
3610 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3611 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
3612 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3613 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
3614 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
3615 {error_count++;
3616 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
3617 }
3618 }
3619 }
3620 }
3621 for ((temp_k=0);(temp_k<4);(temp_k++))
3622 {
3623 {
3624 ddr_udelay(10000);
3625 for ((temp_i=0);(temp_i<8);(temp_i++))
3626 {
3627 test_addr=start_addr+(temp_i<<2);
3628 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3629 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3630 //des[temp_i]^pattern_2[temp_k][temp_i]
3631 }
3632 // _clean_dcache_addr(0x10000000);
3633#ifdef DDR_PREFETCH_CACHE
3634 flush_dcache_range(start_addr,start_addr + test_size);
3635#endif
3636 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3637 test_addr=start_addr+(temp_i<<2);
3638 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3639 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
3640 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3641 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
3642 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
3643 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
3644 {error_count++;
3645 printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]);
3646 }
3647 }
3648 }
3649 }
3650
3651 }
3652
3653 // if(pattern_flag3==1)
3654 {
3655 for ((temp_k=0);(temp_k<4);(temp_k++)) {
3656 {
3657 ddr_udelay(10000);
3658 for ((temp_i=0);(temp_i<8);(temp_i++))
3659 {
3660 test_addr=start_addr+(temp_i<<2);
3661 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3662 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3663 //des[temp_i]^pattern_2[temp_k][temp_i]
3664 }
3665 // _clean_dcache_addr(0x10000000);
3666#ifdef DDR_PREFETCH_CACHE
3667 flush_dcache_range(start_addr,start_addr + test_size);
3668#endif
3669 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3670 test_addr=start_addr+(temp_i<<2);
3671 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3672 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
3673 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3674 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
3675 if (pattern_o[temp_i] != pattern_6[temp_k][temp_i])
3676 {error_count++;
3677 printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]);
3678 }
3679 }
3680 }
3681 }
3682 for ((temp_k=0);(temp_k<4);(temp_k++))
3683 {
3684 {
3685 ddr_udelay(10000);
3686 for ((temp_i=0);(temp_i<8);(temp_i++))
3687 {
3688 test_addr=start_addr+(temp_i<<2);
3689 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
3690 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
3691 //des[temp_i]^pattern_2[temp_k][temp_i]
3692 }
3693 // _clean_dcache_addr(0x10000000);
3694#ifdef DDR_PREFETCH_CACHE
3695 flush_dcache_range(start_addr,start_addr + test_size);
3696#endif
3697 for ((temp_i=0);(temp_i<8);(temp_i++)) {
3698 test_addr=start_addr+(temp_i<<2);
3699 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
3700 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
3701 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
3702 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
3703 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
3704 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
3705 {error_count++;
3706 printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]);
3707 }
3708 }
3709 }
3710 }
3711 }
3712
3713
3714
3715 }
3716
3717 printf("\Error count==0x%08x", error_count);
3718 printf("\n \n");
3719 }
3720
3721 if (error_count)
3722 return 1;
3723 else
3724 return 0;
3725}
3726
3727int ddr_test_gx_training_pattern(int ddr_test_size)
3728{
3729 unsigned int start_addr = 0x10000000;
3730 error_outof_count_flag=1;
3731 error_count=0;
3732
3733 unsigned int des[8] ;
3734 unsigned int pattern_1[4][8] ;
3735 // unsigned int pattern_2[4][8] ;
3736 // unsigned int pattern_3[4][8] ;
3737 // unsigned int pattern_4[4][8] ;
3738 // unsigned int pattern_5[4][8] ;
3739 //unsigned int pattern_6[4][8] ;
3740
3741 des[0] = 0xaec83f49;
3742 des[1] = 0xd243a62c;
3743 des[2] = 0xf8774a0b;
3744 des[3] = 0x63d214e5;
3745 des[4] = 0x3f4166d5;
3746 des[5] = 0x239672c0;
3747 des[6] = 0x47ba7533;
3748 des[7] = 0xcae4cd7f;
3749 /*
3750 pattern_1[0][0] = 0x55005500;
3751 pattern_1[0][1] = 0xaa00aa00;
3752 pattern_1[0][2] = 0x55005500;
3753 pattern_1[0][3] = 0xaa00aa00;
3754 pattern_1[0][4] = 0x55005500;
3755 pattern_1[0][5] = 0xaa00aa00;
3756 pattern_1[0][6] = 0x55005500;
3757 pattern_1[0][7] = 0xaa00aa00;
3758
3759 pattern_1[1][0] = 0x55005500;
3760 pattern_1[1][1] = 0xaa00aa00;
3761 pattern_1[1][2] = 0x55005500;
3762 pattern_1[1][3] = 0xaa00aa00;
3763 pattern_1[1][4] = 0x55005500;
3764 pattern_1[1][5] = 0xaa00aa00;
3765 pattern_1[1][6] = 0x55005500;
3766 pattern_1[1][7] = 0xaa00aa00;
3767
3768 pattern_1[2][0] = 0x55005500;
3769 pattern_1[2][1] = 0xaa00aa00;
3770 pattern_1[2][2] = 0x55005500;
3771 pattern_1[2][3] = 0xaa00aa00;
3772 pattern_1[2][4] = 0x55005500;
3773 pattern_1[2][5] = 0xaa00aa00;
3774 pattern_1[2][6] = 0x55005500;
3775 pattern_1[2][7] = 0xaa00aa00;
3776
3777 pattern_1[3][0] = 0x55005500;
3778 pattern_1[3][1] = 0xaa00aa00;
3779 pattern_1[3][2] = 0x55005500;
3780 pattern_1[3][3] = 0xaa00aa00;
3781 pattern_1[3][4] = 0x55005500;
3782 pattern_1[3][5] = 0xaa00aa00;
3783 pattern_1[3][6] = 0x55005500;
3784 pattern_1[3][7] = 0xaa00aa00;
3785 */
3786 // /*
3787 pattern_1[0][0] = 0x55aa5500;
3788 pattern_1[0][1] = 0x55aa5500;
3789 pattern_1[0][2] = 0x55aa5500;
3790 pattern_1[0][3] = 0x55aa5500;
3791 pattern_1[0][4] = 0xaa00ff00;
3792 pattern_1[0][5] = 0xaa00ff00;
3793 pattern_1[0][6] = 0xaa00ff00;
3794 pattern_1[0][7] = 0xaa00ff00;
3795
3796 pattern_1[1][0] = 0x55005500;
3797 pattern_1[1][1] = 0xaa00aa00;
3798 pattern_1[1][2] = 0x55005500;
3799 pattern_1[1][3] = 0xaa00aa00;
3800 pattern_1[1][4] = 0x55005500;
3801 pattern_1[1][5] = 0xaa00aa00;
3802 pattern_1[1][6] = 0x55005500;
3803 pattern_1[1][7] = 0xaa00aa00;
3804
3805 pattern_1[2][0] = 0x0001fe00;
3806 pattern_1[2][1] = 0x0000ff00;
3807 pattern_1[2][2] = 0x0000ff00;
3808 pattern_1[2][3] = 0x0000ff00;
3809 pattern_1[2][4] = 0x0002fd00;
3810 pattern_1[2][5] = 0x0000ff00;
3811 pattern_1[2][6] = 0x0000ff00;
3812 pattern_1[2][7] = 0x0000ff00;
3813
3814 pattern_1[3][0] = 0x0004fb00;
3815 pattern_1[3][1] = 0x0000ff00;
3816 pattern_1[3][2] = 0x0000ff00;
3817 pattern_1[3][3] = 0x0000ff00;
3818 pattern_1[3][4] = 0x0008f700;
3819 pattern_1[3][5] = 0x0000ff00;
3820 pattern_1[3][6] = 0x0000ff00;
3821 pattern_1[3][7] = 0x0000ff00;
3822 //*/
3823 /*
3824 pattern_2[0][0] = 0x0001fe00;
3825 pattern_2[0][1] = 0x0000ff00;
3826 pattern_2[0][2] = 0x0000ff00;
3827 pattern_2[0][3] = 0x0000ff00;
3828 pattern_2[0][4] = 0x0002fd00;
3829 pattern_2[0][5] = 0x0000ff00;
3830 pattern_2[0][6] = 0x0000ff00;
3831 pattern_2[0][7] = 0x0000ff00;
3832
3833 pattern_2[1][0] = 0x0004fb00;
3834 pattern_2[1][1] = 0x0000ff00;
3835 pattern_2[1][2] = 0x0000ff00;
3836 pattern_2[1][3] = 0x0000ff00;
3837 pattern_2[1][4] = 0x0008f700;
3838 pattern_2[1][5] = 0x0000ff00;
3839 pattern_2[1][6] = 0x0000ff00;
3840 pattern_2[1][7] = 0x0000ff00;
3841
3842 pattern_2[2][0] = 0x0010ef00;
3843 pattern_2[2][1] = 0x0000ff00;
3844 pattern_2[2][2] = 0x0000ff00;
3845 pattern_2[2][3] = 0x0000ff00;
3846 pattern_2[2][4] = 0x0020df00;
3847 pattern_2[2][5] = 0x0000ff00;
3848 pattern_2[2][6] = 0x0000ff00;
3849 pattern_2[2][7] = 0x0000ff00;
3850
3851 pattern_2[3][0] = 0x0040bf00;
3852 pattern_2[3][1] = 0x0000ff00;
3853 pattern_2[3][2] = 0x0000ff00;
3854 pattern_2[3][3] = 0x0000ff00;
3855 pattern_2[3][4] = 0x00807f00;
3856 pattern_2[3][5] = 0x0000ff00;
3857 pattern_2[3][6] = 0x0000ff00;
3858 pattern_2[3][7] = 0x0000ff00;
3859
3860 pattern_3[0][0] = 0x00010000;
3861 pattern_3[0][1] = 0x00000000;
3862 pattern_3[0][2] = 0x00000000;
3863 pattern_3[0][3] = 0x00000000;
3864 pattern_3[0][4] = 0x00020000;
3865 pattern_3[0][5] = 0x00000000;
3866 pattern_3[0][6] = 0x00000000;
3867 pattern_3[0][7] = 0x00000000;
3868
3869 pattern_3[1][0] = 0x00040000;
3870 pattern_3[1][1] = 0x00000000;
3871 pattern_3[1][2] = 0x00000000;
3872 pattern_3[1][3] = 0x00000000;
3873 pattern_3[1][4] = 0x00080000;
3874 pattern_3[1][5] = 0x00000000;
3875 pattern_3[1][6] = 0x00000000;
3876 pattern_3[1][7] = 0x00000000;
3877
3878 pattern_3[2][0] = 0x00100000;
3879 pattern_3[2][1] = 0x00000000;
3880 pattern_3[2][2] = 0x00000000;
3881 pattern_3[2][3] = 0x00000000;
3882 pattern_3[2][4] = 0x00200000;
3883 pattern_3[2][5] = 0x00000000;
3884 pattern_3[2][6] = 0x00000000;
3885 pattern_3[2][7] = 0x00000000;
3886
3887 pattern_3[3][0] = 0x00400000;
3888 pattern_3[3][1] = 0x00000000;
3889 pattern_3[3][2] = 0x00000000;
3890 pattern_3[3][3] = 0x00000000;
3891 pattern_3[3][4] = 0x00800000;
3892 pattern_3[3][5] = 0x00000000;
3893 pattern_3[3][6] = 0x00000000;
3894 pattern_3[3][7] = 0x00000000;
3895
3896
3897 pattern_4[0][0] = 0x51c8c049 ;
3898 pattern_4[0][1] = 0x2d43592c ;
3899 pattern_4[0][2] = 0x0777b50b ;
3900 pattern_4[0][3] = 0x9cd2ebe5 ;
3901 pattern_4[0][4] = 0xc04199d5 ;
3902 pattern_4[0][5] = 0xdc968dc0 ;
3903 pattern_4[0][6] = 0xb8ba8a33 ;
3904 pattern_4[0][7] = 0x35e4327f ;
3905
3906 pattern_4[1][0] = 0xae37c049 ;
3907 pattern_4[1][1] = 0xd2bc592c ;
3908 pattern_4[1][2] = 0xf888b50b ;
3909 pattern_4[1][3] = 0x632debe5 ;
3910 pattern_4[1][4] = 0x3fbe99d5 ;
3911 pattern_4[1][5] = 0x23698dc0 ;
3912 pattern_4[1][6] = 0x47458a33 ;
3913 pattern_4[1][7] = 0xca1b327f ;
3914
3915 pattern_4[2][0] = 0x51373f49 ;
3916 pattern_4[2][1] = 0x2dbca62c ;
3917 pattern_4[2][2] = 0x07884a0b ;
3918 pattern_4[2][3] = 0x9c2d14e5 ;
3919 pattern_4[2][4] = 0xc0be66d5 ;
3920 pattern_4[2][5] = 0xdc6972c0 ;
3921 pattern_4[2][6] = 0xb8457533 ;
3922 pattern_4[2][7] = 0x351bcd7f ;
3923
3924
3925 pattern_4[3][0] = 0x51c8c049 ;
3926 pattern_4[3][1] = 0x2d43592c ;
3927 pattern_4[3][2] = 0x0777b50b ;
3928 pattern_4[3][3] = 0x9cd2ebe5 ;
3929 pattern_4[3][4] = 0xc04199d5 ;
3930 pattern_4[3][5] = 0xdc968dc0 ;
3931 pattern_4[3][6] = 0xb8ba8a33 ;
3932 pattern_4[3][7] = 0x35e4327f ;
3933
3934 pattern_5[0][0] = 0xaec9c149 ;
3935 pattern_5[0][1] = 0xd243592c ;
3936 pattern_5[0][2] = 0xf877b50b ;
3937 pattern_5[0][3] = 0x63d2ebe5 ;
3938 pattern_5[0][4] = 0x3f439bd5 ;
3939 pattern_5[0][5] = 0x23968dc0 ;
3940 pattern_5[0][6] = 0x47ba8a33 ;
3941 pattern_5[0][7] = 0xcae4327f ;
3942 pattern_5[1][0] = 0xaeccc449 ;
3943 pattern_5[1][1] = 0xd243592c ;
3944 pattern_5[1][2] = 0xf877b50b ;
3945 pattern_5[1][3] = 0x63d2ebe5 ;
3946 pattern_5[1][4] = 0x3f4991d5 ;
3947 pattern_5[1][5] = 0x23968dc0 ;
3948 pattern_5[1][6] = 0x47ba8a33 ;
3949 pattern_5[1][7] = 0xcae4327f ;
3950 pattern_5[2][0] = 0xaed8d049 ;
3951 pattern_5[2][1] = 0xd243592c ;
3952 pattern_5[2][2] = 0xf877b50b ;
3953 pattern_5[2][3] = 0x63d2ebe5 ;
3954 pattern_5[2][4] = 0x3f61b9d5 ;
3955 pattern_5[2][5] = 0x23968dc0 ;
3956 pattern_5[2][6] = 0x47ba8a33 ;
3957 pattern_5[2][7] = 0xcae4327f ;
3958 pattern_5[3][0] = 0xae888049 ;
3959 pattern_5[3][1] = 0xd243592c ;
3960 pattern_5[3][2] = 0xf877b50b ;
3961 pattern_5[3][3] = 0x63d2ebe5 ;
3962 pattern_5[3][4] = 0x3fc119d5 ;
3963 pattern_5[3][5] = 0x23968dc0 ;
3964 pattern_5[3][6] = 0x47ba8a33 ;
3965 pattern_5[3][7] = 0xcae4327f ;
3966
3967 pattern_6[0][0] = 0xaec93f49 ;
3968 pattern_6[0][1] = 0xd243a62c ;
3969 pattern_6[0][2] = 0xf8774a0b ;
3970 pattern_6[0][3] = 0x63d214e5 ;
3971 pattern_6[0][4] = 0x3f4366d5 ;
3972 pattern_6[0][5] = 0x239672c0 ;
3973 pattern_6[0][6] = 0x47ba7533 ;
3974 pattern_6[0][7] = 0xcae4cd7f ;
3975 pattern_6[1][0] = 0xaecc3f49 ;
3976 pattern_6[1][1] = 0xd243a62c ;
3977 pattern_6[1][2] = 0xf8774a0b ;
3978 pattern_6[1][3] = 0x63d214e5 ;
3979 pattern_6[1][4] = 0x3f4966d5 ;
3980 pattern_6[1][5] = 0x239672c0 ;
3981 pattern_6[1][6] = 0x47ba7533 ;
3982 pattern_6[1][7] = 0xcae4cd7f ;
3983 pattern_6[2][0] = 0xaed83f49 ;
3984 pattern_6[2][1] = 0xd243a62c ;
3985 pattern_6[2][2] = 0xf8774a0b ;
3986 pattern_6[2][3] = 0x63d214e5 ;
3987 pattern_6[2][4] = 0x3f6166d5 ;
3988 pattern_6[2][5] = 0x239672c0 ;
3989 pattern_6[2][6] = 0x47ba7533 ;
3990 pattern_6[2][7] = 0xcae4cd7f ;
3991 pattern_6[3][0] = 0xae883f49 ;
3992 pattern_6[3][1] = 0xd243a62c ;
3993 pattern_6[3][2] = 0xf8774a0b ;
3994 pattern_6[3][3] = 0x63d214e5 ;
3995 pattern_6[3][4] = 0x3fc166d5 ;
3996 pattern_6[3][5] = 0x239672c0 ;
3997 pattern_6[3][6] = 0x47ba7533 ;
3998 pattern_6[3][7] = 0xcae4cd7f ;
3999 */
4000 //*/
4001 //*/
4002 start_addr=0x10000000;
4003 unsigned int test_size = 0x20;
4004 unsigned int test_addr;
4005 unsigned int temp_i=0;
4006 unsigned int temp_k=0;
4007 unsigned int pattern_o[8];
4008 unsigned int pattern_d[8];
4009 {
4010 // if(lflag)
4011 // loop = 888;
4012
4013 //if(old_pattern_flag==1)
4014 {
4015
4016 printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
4017
4018 /*
4019 for ((temp_k=0);(temp_k<4);(temp_k++)) {
4020 {
4021
4022 for ((temp_i=0);(temp_i<8);(temp_i++))
4023 {
4024 test_addr=start_addr+(temp_i<<2);
4025 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
4026 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
4027 //des[temp_i]^pattern_2[temp_k][temp_i]
4028 }
4029 // _clean_dcache_addr(0x10000000);
4030 flush_dcache_range(start_addr,start_addr + test_size);
4031
4032 for ((temp_i=0);(temp_i<8);(temp_i++)) {
4033 test_addr=start_addr+(temp_i<<2);
4034 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
4035 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
4036 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
4037 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
4038 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
4039 {error_count++;
4040 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
4041 }
4042 }
4043 }
4044 }
4045 */
4046 //if(pattern_flag1==1)
4047 {
4048 for ((temp_k=0);(temp_k<4);(temp_k++))
4049 {
4050 {
4051 ddr_udelay(10000);
4052 for ((temp_i=0);(temp_i<8);(temp_i++))
4053 {
4054 test_addr=start_addr+(temp_i<<2);
4055 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
4056 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
4057 //des[temp_i]^pattern_2[temp_k][temp_i]
4058 }
4059 // _clean_dcache_addr(0x10000000);
4060#ifdef DDR_PREFETCH_CACHE
4061 flush_dcache_range(start_addr,start_addr + test_size);
4062#endif
4063 for ((temp_i=0);(temp_i<8);(temp_i++)) {
4064 test_addr=start_addr+(temp_i<<2);
4065 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
4066 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
4067 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
4068 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
4069 if ((pattern_o[temp_i]) != (des_pattern(temp_i,1,temp_k,temp_i)))
4070 {error_count++;
4071 // printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
4072 printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,1,temp_k,temp_i),pattern_1[temp_k][temp_i]);
4073 }
4074
4075
4076 }
4077 }
4078 }
4079
4080 for ((temp_k=0);(temp_k<4);(temp_k++))
4081 {
4082 {
4083 ddr_udelay(10000);
4084 for ((temp_i=0);(temp_i<8);(temp_i++))
4085 {
4086 test_addr=start_addr+(temp_i<<2);
4087 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
4088 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
4089 //des[temp_i]^pattern_2[temp_k][temp_i]
4090 }
4091 // _clean_dcache_addr(0x10000000);
4092#ifdef DDR_PREFETCH_CACHE
4093 flush_dcache_range(start_addr,start_addr + test_size);
4094#endif
4095 for ((temp_i=0);(temp_i<8);(temp_i++)) {
4096 test_addr=start_addr+(temp_i<<2);
4097 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
4098 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
4099 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
4100 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
4101 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
4102 if ((des_xor_pattern((des[temp_i]),des_inv_pattern(temp_i,1,temp_k,temp_i))) != pattern_d[temp_i])
4103 {error_count++;
4104 printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",
4105 pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_1[temp_k][temp_i]),pattern_d[temp_i]);
4106 }
4107
4108 }
4109 }
4110 }
4111
4112 }
4113 }
4114
4115 printf("\Error count==0x%08x", error_count);
4116 printf("\n \n");
4117 }
4118 if (error_count)
4119 return 1;
4120 else
4121 return 0;
4122}
4123
4124#endif
4125
4126static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length)
4127{
4128 unsigned int *p;
4129 // unsigned int i, j, n;
4130 unsigned int i, n;
4131 unsigned int m_len = m_length;
4132 //#define ddr_pattern_loop 32
4133 p = ( unsigned int *)buff;
4134
4135 while (m_len)
4136 {
4137 // for(j=0;j<32;j++)
4138 {
4139 if (m_len >= 128*4)
4140 n = 32*4;
4141 else
4142 n = m_len>>2;
4143
4144 for (i = 0; i < n; i++)
4145 {
4146#ifdef DDR_PREFETCH_CACHE
4147 ddr_pld_cache(p) ;
4148#endif
4149 switch (i)
4150 {
4151 case 0:
4152 case 1:
4153 case 2:
4154 case 3:
4155 case 8:
4156 case 9:
4157 case 10:
4158 case 11:
4159 case 16:
4160 case 17:
4161 case 18:
4162 case 19:
4163 case 24:
4164 case 25:
4165 case 26:
4166 case 27:
4167 // case 30:
4168 *(p+i) = TDATA32F;
4169 break;
4170 case 4:
4171 case 5:
4172 case 6:
4173 case 7:
4174 case 12:
4175 case 13:
4176 case 14:
4177 case 15:
4178 case 20:
4179 case 21:
4180 case 22:
4181 case 23:
4182 case 28:
4183 case 29:
4184 case 30:
4185 case 31:
4186 // case 22:
4187 *(p+i) = 0;
4188 break;
4189 case DDR_PATTERN_LOOP_1+0:
4190 case DDR_PATTERN_LOOP_1+1:
4191 case DDR_PATTERN_LOOP_1+2:
4192 case DDR_PATTERN_LOOP_1+3:
4193 case DDR_PATTERN_LOOP_1+8:
4194 case DDR_PATTERN_LOOP_1+9:
4195 case DDR_PATTERN_LOOP_1+10:
4196 case DDR_PATTERN_LOOP_1+11:
4197 case DDR_PATTERN_LOOP_1+16:
4198 case DDR_PATTERN_LOOP_1+17:
4199 case DDR_PATTERN_LOOP_1+18:
4200 case DDR_PATTERN_LOOP_1+19:
4201 case DDR_PATTERN_LOOP_1+24:
4202 case DDR_PATTERN_LOOP_1+25:
4203 case DDR_PATTERN_LOOP_1+26:
4204 case DDR_PATTERN_LOOP_1+27:
4205 // case 30:
4206 *(p+i) = TDATA32A;
4207 break;
4208 case DDR_PATTERN_LOOP_1+4:
4209 case DDR_PATTERN_LOOP_1+5:
4210 case DDR_PATTERN_LOOP_1+6:
4211 case DDR_PATTERN_LOOP_1+7:
4212 case DDR_PATTERN_LOOP_1+12:
4213 case DDR_PATTERN_LOOP_1+13:
4214 case DDR_PATTERN_LOOP_1+14:
4215 case DDR_PATTERN_LOOP_1+15:
4216 case DDR_PATTERN_LOOP_1+20:
4217 case DDR_PATTERN_LOOP_1+21:
4218 case DDR_PATTERN_LOOP_1+22:
4219 case DDR_PATTERN_LOOP_1+23:
4220 case DDR_PATTERN_LOOP_1+28:
4221 case DDR_PATTERN_LOOP_1+29:
4222 case DDR_PATTERN_LOOP_1+30:
4223 case DDR_PATTERN_LOOP_1+31:
4224 *(p+i) = TDATA325;
4225
4226
4227 break;
4228 case DDR_PATTERN_LOOP_2+0:
4229 case DDR_PATTERN_LOOP_2+1:
4230 case DDR_PATTERN_LOOP_2+2:
4231 case DDR_PATTERN_LOOP_2+3:
4232 *(p+i) =0xfe01fe01;
4233 break;
4234 case DDR_PATTERN_LOOP_2+4:
4235 case DDR_PATTERN_LOOP_2+5:
4236 case DDR_PATTERN_LOOP_2+6:
4237 case DDR_PATTERN_LOOP_2+7:
4238 *(p+i) =0xfd02fd02;
4239 break;
4240 case DDR_PATTERN_LOOP_2+8:
4241 case DDR_PATTERN_LOOP_2+9:
4242 case DDR_PATTERN_LOOP_2+10:
4243 case DDR_PATTERN_LOOP_2+11:
4244 *(p+i) =0xfb04fb04;
4245 break;
4246 case DDR_PATTERN_LOOP_2+12:
4247 case DDR_PATTERN_LOOP_2+13:
4248 case DDR_PATTERN_LOOP_2+14:
4249 case DDR_PATTERN_LOOP_2+15:
4250 *(p+i) =0xf708f708;
4251 break;
4252 case DDR_PATTERN_LOOP_2+16:
4253 case DDR_PATTERN_LOOP_2+17:
4254 case DDR_PATTERN_LOOP_2+18:
4255 case DDR_PATTERN_LOOP_2+19:
4256 *(p+i) =0xef10ef10;
4257 break;
4258 case DDR_PATTERN_LOOP_2+20:
4259 case DDR_PATTERN_LOOP_2+21:
4260 case DDR_PATTERN_LOOP_2+22:
4261 case DDR_PATTERN_LOOP_2+23:
4262 *(p+i) =0xdf20df20;
4263 break;
4264 case DDR_PATTERN_LOOP_2+24:
4265 case DDR_PATTERN_LOOP_2+25:
4266 case DDR_PATTERN_LOOP_2+26:
4267 case DDR_PATTERN_LOOP_2+27:
4268 *(p+i) =0xbf40bf40;
4269 break;
4270 case DDR_PATTERN_LOOP_2+28:
4271 case DDR_PATTERN_LOOP_2+29:
4272 case DDR_PATTERN_LOOP_2+30:
4273 case DDR_PATTERN_LOOP_2+31:
4274 *(p+i) =0x7f807f80;
4275 break;
4276 case DDR_PATTERN_LOOP_3+0:
4277 case DDR_PATTERN_LOOP_3+1:
4278 case DDR_PATTERN_LOOP_3+2:
4279 case DDR_PATTERN_LOOP_3+3:
4280 *(p+i) =0x00000100;
4281 break;
4282 case DDR_PATTERN_LOOP_3+4:
4283 case DDR_PATTERN_LOOP_3+5:
4284 case DDR_PATTERN_LOOP_3+6:
4285 case DDR_PATTERN_LOOP_3+7:
4286 *(p+i) =0x00000200;
4287 break;
4288 case DDR_PATTERN_LOOP_3+8:
4289 case DDR_PATTERN_LOOP_3+9:
4290 case DDR_PATTERN_LOOP_3+10:
4291 case DDR_PATTERN_LOOP_3+11:
4292 *(p+i) =0x00000400;
4293 break;
4294 case DDR_PATTERN_LOOP_3+12:
4295 case DDR_PATTERN_LOOP_3+13:
4296 case DDR_PATTERN_LOOP_3+14:
4297 case DDR_PATTERN_LOOP_3+15:
4298 *(p+i) =0x00000800;
4299 break;
4300 case DDR_PATTERN_LOOP_3+16:
4301 case DDR_PATTERN_LOOP_3+17:
4302 case DDR_PATTERN_LOOP_3+18:
4303 case DDR_PATTERN_LOOP_3+19:
4304 *(p+i) =0x00001000;
4305 break;
4306 case DDR_PATTERN_LOOP_3+20:
4307 case DDR_PATTERN_LOOP_3+21:
4308 case DDR_PATTERN_LOOP_3+22:
4309 case DDR_PATTERN_LOOP_3+23:
4310 *(p+i) =0x00002000;
4311 break;
4312 case DDR_PATTERN_LOOP_3+24:
4313 case DDR_PATTERN_LOOP_3+25:
4314 case DDR_PATTERN_LOOP_3+26:
4315 case DDR_PATTERN_LOOP_3+27:
4316 *(p+i) =0x00004000;
4317 break;
4318 case DDR_PATTERN_LOOP_3+28:
4319 case DDR_PATTERN_LOOP_3+29:
4320 case DDR_PATTERN_LOOP_3+30:
4321 case DDR_PATTERN_LOOP_3+31:
4322 *(p+i) =0x00008000;
4323 break;
4324
4325
4326 }
4327 }
4328
4329 if (m_len >( 128*4))
4330 {
4331 m_len -=( 128*4);
4332 p += 32*4;
4333 }
4334 else
4335 {
4336 p += (m_len>>2);
4337 m_len = 0;
4338 break;
4339 }
4340 }
4341 }
4342}
4343
4344static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
4345{
4346 unsigned int *p;
4347 // unsigned int i, j, n;
4348 unsigned int i, n;
4349 unsigned int m_len = m_length;
4350 //#define ddr_pattern_loop 32
4351 p = ( unsigned int *)buff;
4352
4353 while (m_len)
4354 {
4355 // for(j=0;j<32;j++)
4356 {
4357 if (m_len >= 128*4)
4358 n = 32*4;
4359 else
4360 n = m_len>>2;
4361
4362 for (i = 0; i < n; i++)
4363 {
4364#ifdef DDR_PREFETCH_CACHE
4365 ddr_pld_cache(p) ;
4366#endif
4367
4368 switch (i)
4369 {
4370
4371 case 0:
4372 case DDR_PATTERN_LOOP_1+1:
4373 case DDR_PATTERN_LOOP_2+2:
4374 case DDR_PATTERN_LOOP_3+3:
4375 *(p+i) = 0xfe01fe01;
4376 break;
4377 case 4:
4378 case DDR_PATTERN_LOOP_1+5:
4379 case DDR_PATTERN_LOOP_2+6:
4380 case DDR_PATTERN_LOOP_3+7:
4381 *(p+i) = 0xfd02fd02;
4382 break;
4383
4384 case 8:
4385 case DDR_PATTERN_LOOP_1+9:
4386 case DDR_PATTERN_LOOP_2+10:
4387 case DDR_PATTERN_LOOP_3+11:
4388 *(p+i) = 0xfb04fb04;
4389 break;
4390
4391 case 12:
4392 case DDR_PATTERN_LOOP_1+13:
4393 case DDR_PATTERN_LOOP_2+14:
4394 case DDR_PATTERN_LOOP_3+15:
4395 *(p+i) = 0xf708f708;
4396 break;
4397
4398 case 16:
4399 case DDR_PATTERN_LOOP_1+17:
4400 case DDR_PATTERN_LOOP_2+18:
4401 case DDR_PATTERN_LOOP_3+19:
4402 *(p+i) = 0xef10ef10;
4403 break;
4404
4405 case 20:
4406 case DDR_PATTERN_LOOP_1+21:
4407 case DDR_PATTERN_LOOP_2+22:
4408 case DDR_PATTERN_LOOP_3+23:
4409 *(p+i) = 0xdf20df20;
4410 break;
4411
4412 case 24:
4413 case DDR_PATTERN_LOOP_1+25:
4414 case DDR_PATTERN_LOOP_2+26:
4415 case DDR_PATTERN_LOOP_3+27:
4416 *(p+i) = 0xbf40bf40;
4417 break;
4418
4419 case 28:
4420 case DDR_PATTERN_LOOP_1+29:
4421 case DDR_PATTERN_LOOP_2+30:
4422 case DDR_PATTERN_LOOP_3+31:
4423 *(p+i) = 0x7f807f80;
4424 break;
4425
4426
4427 default:
4428
4429 *(p+i) = 0xff00ff00;
4430 break;
4431
4432 break;
4433
4434
4435 }
4436 }
4437
4438 if (m_len >( 128*4))
4439 {
4440 m_len -=( 128*4);
4441 p += 32*4;
4442 }
4443 else
4444 {
4445 p += (m_len>>2);
4446 m_len = 0;
4447 break;
4448 }
4449 }
4450 }
4451}
4452static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length)
4453{
4454 unsigned int *p;
4455 // unsigned int i, j, n;
4456 unsigned int i, n;
4457 unsigned int m_len = m_length;
4458
4459 p = ( unsigned int *)buff;
4460
4461 while (m_len)
4462 {
4463 // for(j=0;j<32;j++)
4464 {
4465 if (m_len >= 128*4)
4466 n = 32*4;
4467 else
4468 n = m_len>>2;
4469
4470 for (i = 0; i < n; i++)
4471 {
4472#ifdef DDR_PREFETCH_CACHE
4473 ddr_pld_cache(p) ;
4474#endif
4475 if ((error_outof_count_flag) && (error_count))
4476 {
4477 printf("Error data out of count");
4478 m_len=0;
4479 break;
4480 }
4481
4482 switch (i)
4483 {
4484
4485 case 0:
4486 case 1:
4487 case 2:
4488 case 3:
4489 case 8:
4490 case 9:
4491 case 10:
4492 case 11:
4493 case 16:
4494 case 17:
4495 case 18:
4496 case 19:
4497 case 24:
4498 case 25:
4499 case 26:
4500 case 27:
4501 // case 30:
4502 // *(p+i) = TDATA32F;
4503 if (*(p+i) != TDATA32F)
4504 {error_count++;
4505 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
4506 break;
4507 }
4508 break;
4509 case 4:
4510 case 5:
4511 case 6:
4512 case 7:
4513 case 12:
4514 case 13:
4515 case 14:
4516 case 15:
4517 case 20:
4518 case 21:
4519 case 22:
4520 case 23:
4521 case 28:
4522 case 29:
4523 case 30:
4524 case 31:
4525 // case 22:
4526 // *(p+i) = 0;
4527 if (*(p+i) != 0)
4528 {error_count++;
4529 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
4530 break;}
4531 break;
4532 case DDR_PATTERN_LOOP_1+0:
4533 case DDR_PATTERN_LOOP_1+1:
4534 case DDR_PATTERN_LOOP_1+2:
4535 case DDR_PATTERN_LOOP_1+3:
4536 case DDR_PATTERN_LOOP_1+8:
4537 case DDR_PATTERN_LOOP_1+9:
4538 case DDR_PATTERN_LOOP_1+10:
4539 case DDR_PATTERN_LOOP_1+11:
4540 case DDR_PATTERN_LOOP_1+16:
4541 case DDR_PATTERN_LOOP_1+17:
4542 case DDR_PATTERN_LOOP_1+18:
4543 case DDR_PATTERN_LOOP_1+19:
4544 case DDR_PATTERN_LOOP_1+24:
4545 case DDR_PATTERN_LOOP_1+25:
4546 case DDR_PATTERN_LOOP_1+26:
4547 case DDR_PATTERN_LOOP_1+27:
4548 // case 30:
4549 // *(p+i) = TDATA32A;
4550 if (*(p+i) != TDATA32A)
4551 {error_count++;
4552 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
4553 break;
4554 }
4555 break;
4556 case DDR_PATTERN_LOOP_1+4:
4557 case DDR_PATTERN_LOOP_1+5:
4558 case DDR_PATTERN_LOOP_1+6:
4559 case DDR_PATTERN_LOOP_1+7:
4560 case DDR_PATTERN_LOOP_1+12:
4561 case DDR_PATTERN_LOOP_1+13:
4562 case DDR_PATTERN_LOOP_1+14:
4563 case DDR_PATTERN_LOOP_1+15:
4564 case DDR_PATTERN_LOOP_1+20:
4565 case DDR_PATTERN_LOOP_1+21:
4566 case DDR_PATTERN_LOOP_1+22:
4567 case DDR_PATTERN_LOOP_1+23:
4568 case DDR_PATTERN_LOOP_1+28:
4569 case DDR_PATTERN_LOOP_1+29:
4570 case DDR_PATTERN_LOOP_1+30:
4571 case DDR_PATTERN_LOOP_1+31:
4572 // *(p+i) = TDATA325;
4573 if (*(p+i) != TDATA325)
4574 {error_count++;
4575 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
4576 break;
4577 }
4578 break;
4579 case DDR_PATTERN_LOOP_2+0:
4580 case DDR_PATTERN_LOOP_2+1:
4581 case DDR_PATTERN_LOOP_2+2:
4582 case DDR_PATTERN_LOOP_2+3:
4583 // *(p+i) =0xfe01fe01;
4584 if (*(p+i) !=0xfe01fe01)
4585 {error_count++;
4586 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
4587 break;
4588 }
4589 break;
4590 case DDR_PATTERN_LOOP_2+4:
4591 case DDR_PATTERN_LOOP_2+5:
4592 case DDR_PATTERN_LOOP_2+6:
4593 case DDR_PATTERN_LOOP_2+7:
4594 // *(p+i) =0xfd02fd02;
4595 if (*(p+i) != 0xfd02fd02)
4596 {error_count++;
4597 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
4598 break;
4599 }
4600 break;
4601 case DDR_PATTERN_LOOP_2+8:
4602 case DDR_PATTERN_LOOP_2+9:
4603 case DDR_PATTERN_LOOP_2+10:
4604 case DDR_PATTERN_LOOP_2+11:
4605 // *(p+i) =0xfb04fb04;
4606 if (*(p+i) != 0xfb04fb04)
4607 {error_count++;
4608 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
4609 break;
4610 }
4611 break;
4612 case DDR_PATTERN_LOOP_2+12:
4613 case DDR_PATTERN_LOOP_2+13:
4614 case DDR_PATTERN_LOOP_2+14:
4615 case DDR_PATTERN_LOOP_2+15:
4616 // *(p+i) =0xf7b08f708;
4617 if (*(p+i) != 0xf708f708)
4618 {error_count++;
4619 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
4620 break;
4621 }
4622 break;
4623 case DDR_PATTERN_LOOP_2+16:
4624 case DDR_PATTERN_LOOP_2+17:
4625 case DDR_PATTERN_LOOP_2+18:
4626 case DDR_PATTERN_LOOP_2+19:
4627 // *(p+i) =0xef10ef10;
4628 if (*(p+i) != 0xef10ef10)
4629 {error_count++;
4630 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
4631 break;
4632 }
4633 break;
4634 case DDR_PATTERN_LOOP_2+20:
4635 case DDR_PATTERN_LOOP_2+21:
4636 case DDR_PATTERN_LOOP_2+22:
4637 case DDR_PATTERN_LOOP_2+23:
4638 // *(p+i) =0xdf20df20;
4639 if (*(p+i) != 0xdf20df20)
4640 {error_count++;
4641 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
4642 break;
4643 }
4644 break;
4645 case DDR_PATTERN_LOOP_2+24:
4646 case DDR_PATTERN_LOOP_2+25:
4647 case DDR_PATTERN_LOOP_2+26:
4648 case DDR_PATTERN_LOOP_2+27:
4649 // *(p+i) =0xbf40bf40;
4650 if (*(p+i) != 0xbf40bf40)
4651 {error_count++;
4652 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
4653 break;
4654 }
4655 break;
4656 case DDR_PATTERN_LOOP_2+28:
4657 case DDR_PATTERN_LOOP_2+29:
4658 case DDR_PATTERN_LOOP_2+30:
4659 case DDR_PATTERN_LOOP_2+31:
4660 // *(p+i) =0x7f807f80;
4661 if (*(p+i) != 0x7f807f80)
4662 {error_count++;
4663 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
4664 break;
4665
4666 }
4667 break;
4668 case DDR_PATTERN_LOOP_3+0:
4669 case DDR_PATTERN_LOOP_3+1:
4670 case DDR_PATTERN_LOOP_3+2:
4671 case DDR_PATTERN_LOOP_3+3:
4672 // *(p+i) =0x00000100;
4673 if (*(p+i) != 0x00000100)
4674 {error_count++;
4675 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000100);
4676 break;
4677 }
4678 break;
4679 case DDR_PATTERN_LOOP_3+4:
4680 case DDR_PATTERN_LOOP_3+5:
4681 case DDR_PATTERN_LOOP_3+6:
4682 case DDR_PATTERN_LOOP_3+7:
4683 // *(p+i) =0x00000100;
4684 if (*(p+i) != 0x00000200)
4685 {error_count++;
4686 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000200);
4687 break;
4688 }
4689 break;
4690 case DDR_PATTERN_LOOP_3+8:
4691 case DDR_PATTERN_LOOP_3+9:
4692 case DDR_PATTERN_LOOP_3+10:
4693 case DDR_PATTERN_LOOP_3+11:
4694 // *(p+i) =0x00000100;
4695 if (*(p+i) != 0x00000400)
4696 {error_count++;
4697 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000400);
4698 break;
4699 }
4700 break;
4701 case DDR_PATTERN_LOOP_3+12:
4702 case DDR_PATTERN_LOOP_3+13:
4703 case DDR_PATTERN_LOOP_3+14:
4704 case DDR_PATTERN_LOOP_3+15:
4705 // *(p+i) =0x00000100;
4706 if (*(p+i) != 0x00000800)
4707 {error_count++;
4708 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000800);
4709 break;
4710 }
4711 break;
4712 case DDR_PATTERN_LOOP_3+16:
4713 case DDR_PATTERN_LOOP_3+17:
4714 case DDR_PATTERN_LOOP_3+18:
4715 case DDR_PATTERN_LOOP_3+19:
4716 // *(p+i) =0xfffffeff;
4717 if (*(p+i) != 0x00001000)
4718 {error_count++;
4719 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00001000);
4720 break;
4721 }
4722 break;
4723 case DDR_PATTERN_LOOP_3+20:
4724 case DDR_PATTERN_LOOP_3+21:
4725 case DDR_PATTERN_LOOP_3+22:
4726 case DDR_PATTERN_LOOP_3+23:
4727 // *(p+i) =0xfffffeff;
4728 if (*(p+i) != 0x00002000)
4729 {error_count++;
4730 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00002000);
4731
4732 } break;
4733 case DDR_PATTERN_LOOP_3+24:
4734 case DDR_PATTERN_LOOP_3+25:
4735 case DDR_PATTERN_LOOP_3+26:
4736 case DDR_PATTERN_LOOP_3+27:
4737 // *(p+i) =0xfffffeff;
4738 if (*(p+i) != 0x00004000)
4739 {error_count++;
4740 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00004000);
4741 break;
4742 }
4743 break;
4744 case DDR_PATTERN_LOOP_3+28:
4745 case DDR_PATTERN_LOOP_3+29:
4746 case DDR_PATTERN_LOOP_3+30:
4747 case DDR_PATTERN_LOOP_3+31:
4748 // *(p+i) =0xfffffeff;
4749 if (*(p+i) != 0x00008000)
4750 {error_count++;
4751 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00008000);
4752 break;
4753 }
4754 break;
4755
4756
4757
4758 }
4759 }
4760
4761 if (m_len > 128*4)
4762 {
4763 m_len -= 128*4;
4764 p += 32*4;
4765 }
4766 else
4767 {
4768 p += (m_len>>2);
4769 m_len = 0;
4770 break;
4771 }
4772 }
4773 }
4774}
4775//*/
4776static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
4777{
4778 unsigned int *p;
4779 // unsigned int i, j, n;
4780 unsigned int i, n;
4781 unsigned int m_len = m_length;
4782
4783 p = ( unsigned int *)buff;
4784
4785 while (m_len)
4786 {
4787 // for(j=0;j<32;j++)
4788 {
4789 if (m_len >= 128*4)
4790 n = 32*4;
4791 else
4792 n = m_len>>2;
4793
4794 for (i = 0; i < n; i++)
4795 {
4796#ifdef DDR_PREFETCH_CACHE
4797 ddr_pld_cache(p) ;
4798#endif
4799 if ((error_outof_count_flag) && (error_count))
4800 {
4801 printf("Error data out of count");
4802 m_len=0;
4803 break;
4804 }
4805
4806 switch (i)
4807 {
4808 case 0:
4809 case DDR_PATTERN_LOOP_1+1:
4810 case DDR_PATTERN_LOOP_2+2:
4811 case DDR_PATTERN_LOOP_3+3:
4812 // *(p+i) = 0xfe01fe01;
4813 if (*(p+i) != 0xfe01fe01)
4814 {error_count++;
4815 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
4816 break;
4817 }
4818 break;
4819 case 4:
4820 case DDR_PATTERN_LOOP_1+5:
4821 case DDR_PATTERN_LOOP_2+6:
4822 case DDR_PATTERN_LOOP_3+7:
4823 // *(p+i) = 0xfd02fd02;
4824 if (*(p+i) != 0xfd02fd02)
4825 {error_count++;
4826 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
4827 break;
4828 }
4829 break;
4830
4831 case 8:
4832 case DDR_PATTERN_LOOP_1+9:
4833 case DDR_PATTERN_LOOP_2+10:
4834 case DDR_PATTERN_LOOP_3+11:
4835 // *(p+i) = 0xfb04fb04;
4836 if (*(p+i) != 0xfb04fb04)
4837 {error_count++;
4838 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
4839 break;
4840 }
4841 break;
4842
4843 case 12:
4844 case DDR_PATTERN_LOOP_1+13:
4845 case DDR_PATTERN_LOOP_2+14:
4846 case DDR_PATTERN_LOOP_3+15:
4847 // *(p+i) = 0xf708f708;
4848 if (*(p+i) != 0xf708f708)
4849 {error_count++;
4850 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
4851 break;
4852 }
4853 break;
4854
4855 case 16:
4856 case DDR_PATTERN_LOOP_1+17:
4857 case DDR_PATTERN_LOOP_2+18:
4858 case DDR_PATTERN_LOOP_3+19:
4859 // *(p+i) = 0xef10ef10;
4860 if (*(p+i) != 0xef10ef10)
4861 {error_count++;
4862 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
4863 break;
4864 }
4865 break;
4866
4867 case 20:
4868 case DDR_PATTERN_LOOP_1+21:
4869 case DDR_PATTERN_LOOP_2+22:
4870 case DDR_PATTERN_LOOP_3+23:
4871 // *(p+i) = 0xdf20df20;
4872 if (*(p+i) != 0xdf20df20)
4873 {error_count++;
4874 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
4875 break;
4876 }
4877 break;
4878
4879 case 24:
4880 case DDR_PATTERN_LOOP_1+25:
4881 case DDR_PATTERN_LOOP_2+26:
4882 case DDR_PATTERN_LOOP_3+27:
4883 // *(p+i) = 0xbf40bf40;
4884 if (*(p+i) != 0xbf40bf40)
4885 {error_count++;
4886 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
4887 break;
4888 }
4889 break;
4890 case 28:
4891 case DDR_PATTERN_LOOP_1+29:
4892 case DDR_PATTERN_LOOP_2+30:
4893 case DDR_PATTERN_LOOP_3+31:
4894 // *(p+i) = 0x7f807f80;
4895 if (*(p+i) != 0x7f807f80)
4896 {error_count++;
4897 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
4898 break;
4899 }
4900 break;
4901
4902
4903 default:
4904
4905 // *(p+i) = 0xff00ff00;
4906 if (*(p+i) != 0xff00ff00)
4907 {error_count++;
4908 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
4909 break;
4910 }
4911 break;
4912
4913 break;
4914
4915
4916 }
4917 }
4918
4919 if (m_len > 128*4)
4920 {
4921 m_len -= 128*4;
4922 p += 32*4;
4923 }
4924 else
4925 {
4926 p += (m_len>>2);
4927 m_len = 0;
4928 break;
4929 }
4930 }
4931 }
4932}
4933
4934static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length)
4935{
4936 unsigned int *p;
4937 // unsigned int i, j, n;
4938 unsigned int i, n;
4939 unsigned int m_len = m_length;
4940 //#define ddr_pattern_loop 32
4941 p = ( unsigned int *)buff;
4942
4943 while (m_len)
4944 {
4945 // for(j=0;j<32;j++)
4946 {
4947 if (m_len >= 128*4)
4948 n = 32*4;
4949 else
4950 n = m_len>>2;
4951
4952 for (i = 0; i < n; i++)
4953 {
4954#ifdef DDR_PREFETCH_CACHE
4955 ddr_pld_cache(p) ;
4956#endif
4957 switch (i)
4958 {
4959 case 0:
4960 case 1:
4961 case 2:
4962 case 3:
4963 case 8:
4964 case 9:
4965 case 10:
4966 case 11:
4967 case 16:
4968 case 17:
4969 case 18:
4970 case 19:
4971 case 24:
4972 case 25:
4973 case 26:
4974 case 27:
4975 // case 30:
4976 *(p+i) = ~TDATA32F;
4977 break;
4978 case 4:
4979 case 5:
4980 case 6:
4981 case 7:
4982 case 12:
4983 case 13:
4984 case 14:
4985 case 15:
4986 case 20:
4987 case 21:
4988 case 22:
4989 case 23:
4990 case 28:
4991 case 29:
4992 case 30:
4993 case 31:
4994 // case 22:
4995 *(p+i) = ~0;
4996 break;
4997 case DDR_PATTERN_LOOP_1+0:
4998 case DDR_PATTERN_LOOP_1+1:
4999 case DDR_PATTERN_LOOP_1+2:
5000 case DDR_PATTERN_LOOP_1+3:
5001 case DDR_PATTERN_LOOP_1+8:
5002 case DDR_PATTERN_LOOP_1+9:
5003 case DDR_PATTERN_LOOP_1+10:
5004 case DDR_PATTERN_LOOP_1+11:
5005 case DDR_PATTERN_LOOP_1+16:
5006 case DDR_PATTERN_LOOP_1+17:
5007 case DDR_PATTERN_LOOP_1+18:
5008 case DDR_PATTERN_LOOP_1+19:
5009 case DDR_PATTERN_LOOP_1+24:
5010 case DDR_PATTERN_LOOP_1+25:
5011 case DDR_PATTERN_LOOP_1+26:
5012 case DDR_PATTERN_LOOP_1+27:
5013 // case 30:
5014 *(p+i) = ~TDATA32A;
5015 break;
5016 case DDR_PATTERN_LOOP_1+4:
5017 case DDR_PATTERN_LOOP_1+5:
5018 case DDR_PATTERN_LOOP_1+6:
5019 case DDR_PATTERN_LOOP_1+7:
5020 case DDR_PATTERN_LOOP_1+12:
5021 case DDR_PATTERN_LOOP_1+13:
5022 case DDR_PATTERN_LOOP_1+14:
5023 case DDR_PATTERN_LOOP_1+15:
5024 case DDR_PATTERN_LOOP_1+20:
5025 case DDR_PATTERN_LOOP_1+21:
5026 case DDR_PATTERN_LOOP_1+22:
5027 case DDR_PATTERN_LOOP_1+23:
5028 case DDR_PATTERN_LOOP_1+28:
5029 case DDR_PATTERN_LOOP_1+29:
5030 case DDR_PATTERN_LOOP_1+30:
5031 case DDR_PATTERN_LOOP_1+31:
5032 *(p+i) =~TDATA325;
5033
5034
5035 break;
5036 case DDR_PATTERN_LOOP_2+0:
5037 case DDR_PATTERN_LOOP_2+1:
5038 case DDR_PATTERN_LOOP_2+2:
5039 case DDR_PATTERN_LOOP_2+3:
5040 *(p+i) =~0xfe01fe01;
5041 break;
5042 case DDR_PATTERN_LOOP_2+4:
5043 case DDR_PATTERN_LOOP_2+5:
5044 case DDR_PATTERN_LOOP_2+6:
5045 case DDR_PATTERN_LOOP_2+7:
5046 *(p+i) =~0xfd02fd02;
5047 break;
5048 case DDR_PATTERN_LOOP_2+8:
5049 case DDR_PATTERN_LOOP_2+9:
5050 case DDR_PATTERN_LOOP_2+10:
5051 case DDR_PATTERN_LOOP_2+11:
5052 *(p+i) =~0xfb04fb04;
5053 break;
5054 case DDR_PATTERN_LOOP_2+12:
5055 case DDR_PATTERN_LOOP_2+13:
5056 case DDR_PATTERN_LOOP_2+14:
5057 case DDR_PATTERN_LOOP_2+15:
5058 *(p+i) =~0xf708f708;
5059 break;
5060 case DDR_PATTERN_LOOP_2+16:
5061 case DDR_PATTERN_LOOP_2+17:
5062 case DDR_PATTERN_LOOP_2+18:
5063 case DDR_PATTERN_LOOP_2+19:
5064 *(p+i) =~0xef10ef10;
5065 break;
5066 case DDR_PATTERN_LOOP_2+20:
5067 case DDR_PATTERN_LOOP_2+21:
5068 case DDR_PATTERN_LOOP_2+22:
5069 case DDR_PATTERN_LOOP_2+23:
5070 *(p+i) =~0xdf20df20;
5071 break;
5072 case DDR_PATTERN_LOOP_2+24:
5073 case DDR_PATTERN_LOOP_2+25:
5074 case DDR_PATTERN_LOOP_2+26:
5075 case DDR_PATTERN_LOOP_2+27:
5076 *(p+i) =~0xbf40bf40;
5077 break;
5078 case DDR_PATTERN_LOOP_2+28:
5079 case DDR_PATTERN_LOOP_2+29:
5080 case DDR_PATTERN_LOOP_2+30:
5081 case DDR_PATTERN_LOOP_2+31:
5082 *(p+i) =~0x7f807f80;
5083 break;
5084 case DDR_PATTERN_LOOP_3+0:
5085 case DDR_PATTERN_LOOP_3+1:
5086 case DDR_PATTERN_LOOP_3+2:
5087 case DDR_PATTERN_LOOP_3+3:
5088 *(p+i) =~0x00000100;
5089 break;
5090 case DDR_PATTERN_LOOP_3+4:
5091 case DDR_PATTERN_LOOP_3+5:
5092 case DDR_PATTERN_LOOP_3+6:
5093 case DDR_PATTERN_LOOP_3+7:
5094 *(p+i) =~0x00000200;
5095 break;
5096 case DDR_PATTERN_LOOP_3+8:
5097 case DDR_PATTERN_LOOP_3+9:
5098 case DDR_PATTERN_LOOP_3+10:
5099 case DDR_PATTERN_LOOP_3+11:
5100 *(p+i) =~0x00000400;
5101 break;
5102 case DDR_PATTERN_LOOP_3+12:
5103 case DDR_PATTERN_LOOP_3+13:
5104 case DDR_PATTERN_LOOP_3+14:
5105 case DDR_PATTERN_LOOP_3+15:
5106 *(p+i) =~0x00000800;
5107 break;
5108 case DDR_PATTERN_LOOP_3+16:
5109 case DDR_PATTERN_LOOP_3+17:
5110 case DDR_PATTERN_LOOP_3+18:
5111 case DDR_PATTERN_LOOP_3+19:
5112 *(p+i) =~0x00001000;
5113 break;
5114 case DDR_PATTERN_LOOP_3+20:
5115 case DDR_PATTERN_LOOP_3+21:
5116 case DDR_PATTERN_LOOP_3+22:
5117 case DDR_PATTERN_LOOP_3+23:
5118 *(p+i) =~0x00002000;
5119 break;
5120 case DDR_PATTERN_LOOP_3+24:
5121 case DDR_PATTERN_LOOP_3+25:
5122 case DDR_PATTERN_LOOP_3+26:
5123 case DDR_PATTERN_LOOP_3+27:
5124 *(p+i) =~0x00004000;
5125 break;
5126 case DDR_PATTERN_LOOP_3+28:
5127 case DDR_PATTERN_LOOP_3+29:
5128 case DDR_PATTERN_LOOP_3+30:
5129 case DDR_PATTERN_LOOP_3+31:
5130 *(p+i) =~0x00008000;
5131 break;
5132
5133
5134 }
5135 }
5136
5137 if (m_len >( 128*4))
5138 {
5139 m_len -=( 128*4);
5140 p += 32*4;
5141 }
5142 else
5143 {
5144 p += (m_len>>2);
5145 m_len = 0;
5146 break;
5147 }
5148 }
5149 }
5150}
5151
5152
5153static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
5154{
5155 unsigned int *p;
5156 // unsigned int i, j, n;
5157 unsigned int i, n;
5158 unsigned int m_len = m_length;
5159 //#define ddr_pattern_loop 32
5160 p = ( unsigned int *)buff;
5161
5162 while (m_len)
5163 {
5164 // for(j=0;j<32;j++)
5165 {
5166 if (m_len >= 128*4)
5167 n = 32*4;
5168 else
5169 n = m_len>>2;
5170
5171 for (i = 0; i < n; i++)
5172 {
5173#ifdef DDR_PREFETCH_CACHE
5174 ddr_pld_cache(p) ;
5175#endif
5176
5177 switch (i)
5178 {
5179 case 0:
5180 case DDR_PATTERN_LOOP_1+1:
5181 case DDR_PATTERN_LOOP_2+2:
5182 case DDR_PATTERN_LOOP_3+3:
5183 *(p+i) = ~0xfe01fe01;
5184 break;
5185 case 4:
5186 case DDR_PATTERN_LOOP_1+5:
5187 case DDR_PATTERN_LOOP_2+6:
5188 case DDR_PATTERN_LOOP_3+7:
5189 *(p+i) = ~0xfd02fd02;
5190 break;
5191
5192 case 8:
5193 case DDR_PATTERN_LOOP_1+9:
5194 case DDR_PATTERN_LOOP_2+10:
5195 case DDR_PATTERN_LOOP_3+11:
5196 *(p+i) = ~0xfb04fb04;
5197 break;
5198
5199 case 12:
5200 case DDR_PATTERN_LOOP_1+13:
5201 case DDR_PATTERN_LOOP_2+14:
5202 case DDR_PATTERN_LOOP_3+15:
5203 *(p+i) = ~0xf708f708;
5204 break;
5205
5206 case 16:
5207 case DDR_PATTERN_LOOP_1+17:
5208 case DDR_PATTERN_LOOP_2+18:
5209 case DDR_PATTERN_LOOP_3+19:
5210 *(p+i) = ~0xef10ef10;
5211 break;
5212
5213 case 20:
5214 case DDR_PATTERN_LOOP_1+21:
5215 case DDR_PATTERN_LOOP_2+22:
5216 case DDR_PATTERN_LOOP_3+23:
5217 *(p+i) = ~0xdf20df20;
5218 break;
5219
5220 case 24:
5221 case DDR_PATTERN_LOOP_1+25:
5222 case DDR_PATTERN_LOOP_2+26:
5223 case DDR_PATTERN_LOOP_3+27:
5224 *(p+i) =~0xbf40bf40;
5225 break;
5226 case 28:
5227 case DDR_PATTERN_LOOP_1+29:
5228 case DDR_PATTERN_LOOP_2+30:
5229 case DDR_PATTERN_LOOP_3+31:
5230 *(p+i) = ~0x7f807f80;
5231 break;
5232
5233
5234 default:
5235
5236 *(p+i) = ~0xff00ff00;
5237 break;
5238
5239 break;
5240
5241
5242 }
5243 }
5244
5245 if (m_len >( 128*4))
5246 {
5247 m_len -=( 128*4);
5248 p += 32*4;
5249 }
5250 else
5251 {
5252 p += (m_len>>2);
5253 m_len = 0;
5254 break;
5255 }
5256 }
5257 }
5258}
5259
5260static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length)
5261{
5262 unsigned int *p;
5263 // unsigned int i, j, n;
5264 unsigned int i, n;
5265 unsigned int m_len = m_length;
5266
5267 p = ( unsigned int *)buff;
5268
5269 while (m_len)
5270 {
5271 // for(j=0;j<32;j++)
5272 {
5273 if (m_len >= 128*4)
5274 n = 32*4;
5275 else
5276 n = m_len>>2;
5277
5278 for (i = 0; i < n; i++)
5279 {
5280#ifdef DDR_PREFETCH_CACHE
5281 ddr_pld_cache(p) ;
5282#endif
5283 if ((error_outof_count_flag) && (error_count))
5284 {
5285 printf("Error data out of count");
5286 m_len=0;
5287 break;
5288 }
5289 switch (i)
5290 {
5291 case 0:
5292 case 1:
5293 case 2:
5294 case 3:
5295 case 8:
5296 case 9:
5297 case 10:
5298 case 11:
5299 case 16:
5300 case 17:
5301 case 18:
5302 case 19:
5303 case 24:
5304 case 25:
5305 case 26:
5306 case 27:
5307 // case 30:
5308 // *(p+i) = TDATA32F;
5309 if (*(p+i) !=~TDATA32F)
5310 {error_count++;
5311 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA32F);
5312 break;
5313 }
5314 break;
5315 case 4:
5316 case 5:
5317 case 6:
5318 case 7:
5319 case 12:
5320 case 13:
5321 case 14:
5322 case 15:
5323 case 20:
5324 case 21:
5325 case 22:
5326 case 23:
5327 case 28:
5328 case 29:
5329 case 30:
5330 case 31:
5331 // case 22:
5332 // *(p+i) = 0;
5333 if (*(p+i) !=~0)
5334 {error_count++;
5335 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0);
5336 }
5337 break;
5338 case DDR_PATTERN_LOOP_1+0:
5339 case DDR_PATTERN_LOOP_1+1:
5340 case DDR_PATTERN_LOOP_1+2:
5341 case DDR_PATTERN_LOOP_1+3:
5342 case DDR_PATTERN_LOOP_1+8:
5343 case DDR_PATTERN_LOOP_1+9:
5344 case DDR_PATTERN_LOOP_1+10:
5345 case DDR_PATTERN_LOOP_1+11:
5346 case DDR_PATTERN_LOOP_1+16:
5347 case DDR_PATTERN_LOOP_1+17:
5348 case DDR_PATTERN_LOOP_1+18:
5349 case DDR_PATTERN_LOOP_1+19:
5350 case DDR_PATTERN_LOOP_1+24:
5351 case DDR_PATTERN_LOOP_1+25:
5352 case DDR_PATTERN_LOOP_1+26:
5353 case DDR_PATTERN_LOOP_1+27:
5354 // case 30:
5355 // *(p+i) = TDATA32A;
5356 if (*(p+i) != ~TDATA32A)
5357 {error_count++;
5358 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),~TDATA32A);
5359 }
5360 break;
5361 case DDR_PATTERN_LOOP_1+4:
5362 case DDR_PATTERN_LOOP_1+5:
5363 case DDR_PATTERN_LOOP_1+6:
5364 case DDR_PATTERN_LOOP_1+7:
5365 case DDR_PATTERN_LOOP_1+12:
5366 case DDR_PATTERN_LOOP_1+13:
5367 case DDR_PATTERN_LOOP_1+14:
5368 case DDR_PATTERN_LOOP_1+15:
5369 case DDR_PATTERN_LOOP_1+20:
5370 case DDR_PATTERN_LOOP_1+21:
5371 case DDR_PATTERN_LOOP_1+22:
5372 case DDR_PATTERN_LOOP_1+23:
5373 case DDR_PATTERN_LOOP_1+28:
5374 case DDR_PATTERN_LOOP_1+29:
5375 case DDR_PATTERN_LOOP_1+30:
5376 case DDR_PATTERN_LOOP_1+31:
5377 // *(p+i) = TDATA325;
5378 if (*(p+i) != ~TDATA325)
5379 {error_count++;
5380 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA325);
5381 }
5382 break;
5383 case DDR_PATTERN_LOOP_2+0:
5384 case DDR_PATTERN_LOOP_2+1:
5385 case DDR_PATTERN_LOOP_2+2:
5386 case DDR_PATTERN_LOOP_2+3:
5387 // *(p+i) =0xfe01fe01;
5388 if (*(p+i) !=~0xfe01fe01)
5389 {error_count++;
5390 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01);
5391 }
5392 break;
5393 case DDR_PATTERN_LOOP_2+4:
5394 case DDR_PATTERN_LOOP_2+5:
5395 case DDR_PATTERN_LOOP_2+6:
5396 case DDR_PATTERN_LOOP_2+7:
5397 // *(p+i) =0xfd02fd02;
5398 if (*(p+i) != ~0xfd02fd02)
5399 {error_count++;
5400 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02);
5401 }
5402 break;
5403
5404 case DDR_PATTERN_LOOP_2+8:
5405 case DDR_PATTERN_LOOP_2+9:
5406 case DDR_PATTERN_LOOP_2+10:
5407 case DDR_PATTERN_LOOP_2+11:
5408 // *(p+i) =0xfb04fb04;
5409 if (*(p+i) != ~0xfb04fb04)
5410 {error_count++;
5411 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04);
5412 }
5413 break;
5414 case DDR_PATTERN_LOOP_2+12:
5415 case DDR_PATTERN_LOOP_2+13:
5416 case DDR_PATTERN_LOOP_2+14:
5417 case DDR_PATTERN_LOOP_2+15:
5418 // *(p+i) =0xf7b08f708;
5419 if (*(p+i) != ~0xf708f708)
5420 {error_count++;
5421 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708);
5422 }
5423 break;
5424 case DDR_PATTERN_LOOP_2+16:
5425 case DDR_PATTERN_LOOP_2+17:
5426 case DDR_PATTERN_LOOP_2+18:
5427 case DDR_PATTERN_LOOP_2+19:
5428 // *(p+i) =0xef10ef10;
5429 if (*(p+i) != ~0xef10ef10)
5430 {error_count++;
5431 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10);
5432 }
5433 break;
5434 case DDR_PATTERN_LOOP_2+20:
5435 case DDR_PATTERN_LOOP_2+21:
5436 case DDR_PATTERN_LOOP_2+22:
5437 case DDR_PATTERN_LOOP_2+23:
5438 // *(p+i) =0xdf20df20;
5439 if (*(p+i) != ~0xdf20df20)
5440 {error_count++;
5441 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20);
5442 }
5443 break;
5444 case DDR_PATTERN_LOOP_2+24:
5445 case DDR_PATTERN_LOOP_2+25:
5446 case DDR_PATTERN_LOOP_2+26:
5447 case DDR_PATTERN_LOOP_2+27:
5448 // *(p+i) =0xbf40bf40;
5449 if (*(p+i) != ~0xbf40bf40)
5450 {error_count++;
5451 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40);
5452 }
5453 break;
5454 case DDR_PATTERN_LOOP_2+28:
5455 case DDR_PATTERN_LOOP_2+29:
5456 case DDR_PATTERN_LOOP_2+30:
5457 case DDR_PATTERN_LOOP_2+31:
5458 // *(p+i) =0x7f807f80;
5459 if (*(p+i) != ~0x7f807f80)
5460 {error_count++;
5461 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80);
5462 }
5463 break;
5464 break;
5465 case DDR_PATTERN_LOOP_3+0:
5466 case DDR_PATTERN_LOOP_3+1:
5467 case DDR_PATTERN_LOOP_3+2:
5468 case DDR_PATTERN_LOOP_3+3:
5469 // *(p+i) =0x00000100;
5470 if (*(p+i) != ~0x00000100)
5471 {error_count++;
5472 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000100);
5473 }
5474 break;
5475 case DDR_PATTERN_LOOP_3+4:
5476 case DDR_PATTERN_LOOP_3+5:
5477 case DDR_PATTERN_LOOP_3+6:
5478 case DDR_PATTERN_LOOP_3+7:
5479 // *(p+i) =0x00000100;
5480 if (*(p+i) != ~0x00000200)
5481 {error_count++;
5482 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000200);
5483 }
5484 break;
5485 case DDR_PATTERN_LOOP_3+8:
5486 case DDR_PATTERN_LOOP_3+9:
5487 case DDR_PATTERN_LOOP_3+10:
5488 case DDR_PATTERN_LOOP_3+11:
5489 // *(p+i) =0x00000100;
5490 if (*(p+i) != ~0x00000400)
5491 {error_count++;
5492 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000400);
5493 }
5494 break;
5495 case DDR_PATTERN_LOOP_3+12:
5496 case DDR_PATTERN_LOOP_3+13:
5497 case DDR_PATTERN_LOOP_3+14:
5498 case DDR_PATTERN_LOOP_3+15:
5499 // *(p+i) =0x00000100;
5500 if (*(p+i) != ~0x00000800)
5501 {error_count++;
5502 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000800);
5503 }
5504 break;
5505 case DDR_PATTERN_LOOP_3+16:
5506 case DDR_PATTERN_LOOP_3+17:
5507 case DDR_PATTERN_LOOP_3+18:
5508 case DDR_PATTERN_LOOP_3+19:
5509 // *(p+i) =0xfffffeff;
5510 if (*(p+i) != ~0x00001000)
5511 {error_count++;
5512 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00001000);
5513 }
5514 break;
5515 case DDR_PATTERN_LOOP_3+20:
5516 case DDR_PATTERN_LOOP_3+21:
5517 case DDR_PATTERN_LOOP_3+22:
5518 case DDR_PATTERN_LOOP_3+23:
5519 // *(p+i) =0xfffffeff;
5520 if (*(p+i) != ~0x00002000)
5521 {error_count++;
5522 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00002000);
5523 }
5524 break;
5525 case DDR_PATTERN_LOOP_3+24:
5526 case DDR_PATTERN_LOOP_3+25:
5527 case DDR_PATTERN_LOOP_3+26:
5528 case DDR_PATTERN_LOOP_3+27:
5529 // *(p+i) =0xfffffeff;
5530 if (*(p+i) != ~0x00004000)
5531 {error_count++;
5532 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00004000);
5533 }
5534 break;
5535 case DDR_PATTERN_LOOP_3+28:
5536 case DDR_PATTERN_LOOP_3+29:
5537 case DDR_PATTERN_LOOP_3+30:
5538 case DDR_PATTERN_LOOP_3+31:
5539 // *(p+i) =0xfffffeff;
5540 if (*(p+i) != ~0x00008000)
5541 {error_count++;
5542 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00008000);
5543 }
5544 break;
5545
5546
5547
5548 }
5549 }
5550
5551 if (m_len > 128*4)
5552 {
5553 m_len -= 128*4;
5554 p += 32*4;
5555 }
5556 else
5557 {
5558 p += (m_len>>2);
5559 m_len = 0;
5560 break;
5561 }
5562 }
5563 }
5564}
5565
5566
5567//*/
5568static void ddr_read_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
5569{
5570 unsigned int *p;
5571 // unsigned int i, j, n;
5572 unsigned int i, n;
5573 unsigned int m_len = m_length;
5574
5575 p = ( unsigned int *)buff;
5576
5577 while (m_len)
5578 {
5579 // for(j=0;j<32;j++)
5580 {
5581 if (m_len >= 128*4)
5582 n = 32*4;
5583 else
5584 n = m_len>>2;
5585
5586 for (i = 0; i < n; i++)
5587 {
5588#ifdef DDR_PREFETCH_CACHE
5589 ddr_pld_cache(p) ;
5590#endif
5591 if ((error_outof_count_flag) && (error_count))
5592 {
5593 printf("Error data out of count");
5594 m_len=0;
5595 break;
5596 }
5597
5598 switch (i)
5599 {
5600 case 0:
5601 case DDR_PATTERN_LOOP_1+1:
5602 case DDR_PATTERN_LOOP_2+2:
5603 case DDR_PATTERN_LOOP_3+3:
5604 // *(p+i) = 0xfe01fe01;
5605 if (*(p+i) != ~0xfe01fe01)
5606 {error_count++;
5607 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01);
5608 break;
5609 }
5610 break;
5611 case 4:
5612 case DDR_PATTERN_LOOP_1+5:
5613 case DDR_PATTERN_LOOP_2+6:
5614 case DDR_PATTERN_LOOP_3+7:
5615 // *(p+i) = 0xfd02fd02;
5616 if (*(p+i) != ~0xfd02fd02)
5617 {error_count++;
5618 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02);
5619 break;
5620 }
5621 break;
5622
5623 case 8:
5624 case DDR_PATTERN_LOOP_1+9:
5625 case DDR_PATTERN_LOOP_2+10:
5626 case DDR_PATTERN_LOOP_3+11:
5627 // *(p+i) = 0xfb04fb04;
5628 if (*(p+i) != ~0xfb04fb04)
5629 {error_count++;
5630 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04);
5631 break;
5632 }
5633 break;
5634
5635 case 12:
5636 case DDR_PATTERN_LOOP_1+13:
5637 case DDR_PATTERN_LOOP_2+14:
5638 case DDR_PATTERN_LOOP_3+15:
5639 // *(p+i) = 0xf708f708;
5640 if (*(p+i) != ~0xf708f708)
5641 {error_count++;
5642 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708);
5643 break;
5644 }
5645 break;
5646
5647 case 16:
5648 case DDR_PATTERN_LOOP_1+17:
5649 case DDR_PATTERN_LOOP_2+18:
5650 case DDR_PATTERN_LOOP_3+19:
5651 // *(p+i) = 0xef10ef10;
5652 if (*(p+i) != ~0xef10ef10)
5653 {error_count++;
5654 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10);
5655 break;
5656 }
5657 break;
5658
5659 case 20:
5660 case DDR_PATTERN_LOOP_1+21:
5661 case DDR_PATTERN_LOOP_2+22:
5662 case DDR_PATTERN_LOOP_3+23:
5663 // *(p+i) = 0xdf20df20;
5664 if (*(p+i) != ~0xdf20df20)
5665 {error_count++;
5666 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20);
5667 break;
5668 }
5669 break;
5670
5671 case 24:
5672 case DDR_PATTERN_LOOP_1+25:
5673 case DDR_PATTERN_LOOP_2+26:
5674 case DDR_PATTERN_LOOP_3+27:
5675 // *(p+i) = 0xbf40bf40;
5676 if (*(p+i) != ~0xbf40bf40)
5677 {error_count++;
5678 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40);
5679 break;
5680 }
5681 break;
5682 case 28:
5683 case DDR_PATTERN_LOOP_1+29:
5684 case DDR_PATTERN_LOOP_2+30:
5685 case DDR_PATTERN_LOOP_3+31:
5686 // *(p+i) = 0x7f807f80;
5687 if (*(p+i) != ~0x7f807f80)
5688 {error_count++;
5689 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80);
5690 break;
5691 }
5692 break;
5693
5694
5695 default:
5696
5697 // *(p+i) = 0xff00ff00;
5698 if (*(p+i) != ~0xff00ff00)
5699 {error_count++;
5700 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
5701 break;
5702 }
5703 break;
5704
5705 break;
5706
5707
5708 }
5709 }
5710
5711 if (m_len > 128*4)
5712 {
5713 m_len -= 128*4;
5714 p += 32*4;
5715 }
5716 else
5717 {
5718 p += (m_len>>2);
5719 m_len = 0;
5720 break;
5721 }
5722 }
5723 }
5724}
5725
5726static void ddr_write_pattern4_no_cross_talk(void *buff, unsigned int m_length)
5727{
5728 unsigned int *p;
5729 // unsigned int i, j, n;
5730 unsigned int i, n;
5731 unsigned int m_len = m_length;
5732 //#define ddr_pattern_loop 32
5733 p = ( unsigned int *)buff;
5734
5735 while (m_len)
5736 {
5737 // for(j=0;j<32;j++)
5738 {
5739 if (m_len >= 128*4)
5740 n = 32*4;
5741 else
5742 n = m_len>>2;
5743
5744 for (i = 0; i < n; i++)
5745 {
5746#ifdef DDR_PREFETCH_CACHE
5747 ddr_pld_cache(p) ;
5748#endif
5749 switch (i)
5750 {
5751 case 0:
5752 case 1:
5753 case 2:
5754 case 3:
5755 *(p+i) = 0xff00ff00;
5756 break;
5757 case 4:
5758 case 5:
5759 case 6:
5760 case 7:
5761 *(p+i) = 0xffff0000;
5762 break;
5763
5764 case 8:
5765 case 9:
5766 case 10:
5767 case 11:
5768 *(p+i) = 0xff000000;
5769 break;
5770 case 12:
5771 case 13:
5772 case 14:
5773 case 15:
5774 *(p+i) = 0xff00ffff;
5775 break;
5776
5777 case 16:
5778 case 17:
5779 case 18:
5780 case 19:
5781 *(p+i) = 0xff00ffff;
5782 break;
5783 case 20:
5784 case 21:
5785 case 22:
5786 case 23:
5787 *(p+i) = 0xff0000ff;
5788 break;
5789 case 24:
5790 case 25:
5791 case 26:
5792 case 27:
5793 *(p+i) = 0xffff0000;
5794 break;
5795
5796 case 28:
5797 case 29:
5798 case 30:
5799 case 31:
5800 *(p+i) = 0x00ff00ff;
5801 break;
5802 case DDR_PATTERN_LOOP_1+0:
5803 case DDR_PATTERN_LOOP_1+1:
5804 case DDR_PATTERN_LOOP_1+2:
5805 case DDR_PATTERN_LOOP_1+3:
5806 *(p+i) =~0xff00ff00;
5807 break;
5808 case DDR_PATTERN_LOOP_1+4:
5809 case DDR_PATTERN_LOOP_1+5:
5810 case DDR_PATTERN_LOOP_1+6:
5811 case DDR_PATTERN_LOOP_1+7:
5812 *(p+i) =~0xffff0000;
5813 break;
5814 case DDR_PATTERN_LOOP_1+8:
5815 case DDR_PATTERN_LOOP_1+9:
5816 case DDR_PATTERN_LOOP_1+10:
5817 case DDR_PATTERN_LOOP_1+11:
5818 *(p+i) =~0xff000000;
5819 break;
5820 case DDR_PATTERN_LOOP_1+12:
5821 case DDR_PATTERN_LOOP_1+13:
5822 case DDR_PATTERN_LOOP_1+14:
5823 case DDR_PATTERN_LOOP_1+15:
5824 *(p+i) =~0xff00ffff;
5825 break;
5826 case DDR_PATTERN_LOOP_1+16:
5827 case DDR_PATTERN_LOOP_1+17:
5828 case DDR_PATTERN_LOOP_1+18:
5829 case DDR_PATTERN_LOOP_1+19:
5830 *(p+i) =~0xff00ffff;
5831 break;
5832 case DDR_PATTERN_LOOP_1+20:
5833 case DDR_PATTERN_LOOP_1+21:
5834 case DDR_PATTERN_LOOP_1+22:
5835 case DDR_PATTERN_LOOP_1+23:
5836 *(p+i) =~0xff00ffff;
5837 break;
5838 case DDR_PATTERN_LOOP_1+24:
5839 case DDR_PATTERN_LOOP_1+25:
5840 case DDR_PATTERN_LOOP_1+26:
5841 case DDR_PATTERN_LOOP_1+27:
5842 *(p+i) =~0xffff0000;
5843 break;
5844 case DDR_PATTERN_LOOP_1+28:
5845 case DDR_PATTERN_LOOP_1+29:
5846 case DDR_PATTERN_LOOP_1+30:
5847 case DDR_PATTERN_LOOP_1+31:
5848 *(p+i) =~0x00ff00ff;
5849 break;
5850
5851 case DDR_PATTERN_LOOP_2+0:
5852 case DDR_PATTERN_LOOP_2+1:
5853 case DDR_PATTERN_LOOP_2+2:
5854 case DDR_PATTERN_LOOP_2+3:
5855 *(p+i) =0x00ff0000;
5856 break;
5857 case DDR_PATTERN_LOOP_2+4:
5858 case DDR_PATTERN_LOOP_2+5:
5859 case DDR_PATTERN_LOOP_2+6:
5860 case DDR_PATTERN_LOOP_2+7:
5861 *(p+i) =0xff000000;
5862 break;
5863 case DDR_PATTERN_LOOP_2+8:
5864 case DDR_PATTERN_LOOP_2+9:
5865 case DDR_PATTERN_LOOP_2+10:
5866 case DDR_PATTERN_LOOP_2+11:
5867 *(p+i) =0x0000ffff;
5868 break;
5869 case DDR_PATTERN_LOOP_2+12:
5870 case DDR_PATTERN_LOOP_2+13:
5871 case DDR_PATTERN_LOOP_2+14:
5872 case DDR_PATTERN_LOOP_2+15:
5873 *(p+i) =0x000000ff;
5874 break;
5875 case DDR_PATTERN_LOOP_2+16:
5876 case DDR_PATTERN_LOOP_2+17:
5877 case DDR_PATTERN_LOOP_2+18:
5878 case DDR_PATTERN_LOOP_2+19:
5879 *(p+i) =0x00ff00ff;
5880 break;
5881 case DDR_PATTERN_LOOP_2+20:
5882 case DDR_PATTERN_LOOP_2+21:
5883 case DDR_PATTERN_LOOP_2+22:
5884 case DDR_PATTERN_LOOP_2+23:
5885 *(p+i) =0xff00ff00;
5886 break;
5887 case DDR_PATTERN_LOOP_2+24:
5888 case DDR_PATTERN_LOOP_2+25:
5889 case DDR_PATTERN_LOOP_2+26:
5890 case DDR_PATTERN_LOOP_2+27:
5891 *(p+i) =0xff00ffff;
5892 break;
5893 case DDR_PATTERN_LOOP_2+28:
5894 case DDR_PATTERN_LOOP_2+29:
5895 case DDR_PATTERN_LOOP_2+30:
5896 case DDR_PATTERN_LOOP_2+31:
5897 *(p+i) =0xff00ff00;
5898 break;
5899 case DDR_PATTERN_LOOP_3+0:
5900 case DDR_PATTERN_LOOP_3+1:
5901 case DDR_PATTERN_LOOP_3+2:
5902 case DDR_PATTERN_LOOP_3+3:
5903 *(p+i) =~0x00ff0000;
5904 break;
5905 case DDR_PATTERN_LOOP_3+4:
5906 case DDR_PATTERN_LOOP_3+5:
5907 case DDR_PATTERN_LOOP_3+6:
5908 case DDR_PATTERN_LOOP_3+7:
5909 *(p+i) =~0xff000000;
5910 break;
5911 case DDR_PATTERN_LOOP_3+8:
5912 case DDR_PATTERN_LOOP_3+9:
5913 case DDR_PATTERN_LOOP_3+10:
5914 case DDR_PATTERN_LOOP_3+11:
5915 *(p+i) =~0x0000ffff;
5916 break;
5917 case DDR_PATTERN_LOOP_3+12:
5918 case DDR_PATTERN_LOOP_3+13:
5919 case DDR_PATTERN_LOOP_3+14:
5920 case DDR_PATTERN_LOOP_3+15:
5921 *(p+i) =~0x000000ff;
5922 break;
5923 case DDR_PATTERN_LOOP_3+16:
5924 case DDR_PATTERN_LOOP_3+17:
5925 case DDR_PATTERN_LOOP_3+18:
5926 case DDR_PATTERN_LOOP_3+19:
5927 *(p+i) =~0x00ff00ff;
5928 break;
5929 case DDR_PATTERN_LOOP_3+20:
5930 case DDR_PATTERN_LOOP_3+21:
5931 case DDR_PATTERN_LOOP_3+22:
5932 case DDR_PATTERN_LOOP_3+23:
5933 *(p+i) =~0xff00ff00;
5934 break;
5935 case DDR_PATTERN_LOOP_3+24:
5936 case DDR_PATTERN_LOOP_3+25:
5937 case DDR_PATTERN_LOOP_3+26:
5938 case DDR_PATTERN_LOOP_3+27:
5939 *(p+i) =~0xff00ffff;
5940 break;
5941 case DDR_PATTERN_LOOP_3+28:
5942 case DDR_PATTERN_LOOP_3+29:
5943 case DDR_PATTERN_LOOP_3+30:
5944 case DDR_PATTERN_LOOP_3+31:
5945 *(p+i) =~0xff00ff00;
5946 break;
5947
5948
5949 }
5950 }
5951
5952 if (m_len >( 128*4))
5953 {
5954 m_len -=( 128*4);
5955 p += 32*4;
5956 }
5957 else
5958 {
5959 p += (m_len>>2);
5960 m_len = 0;
5961 break;
5962 }
5963 }
5964 }
5965}
5966
5967static void ddr_read_pattern4_no_cross_talk(void *buff, unsigned int m_length)
5968{
5969 unsigned int *p;
5970 // unsigned int i, j, n;
5971 unsigned int i, n;
5972 unsigned int m_len = m_length;
5973
5974 p = ( unsigned int *)buff;
5975 while (m_len)
5976 {
5977 // for(j=0;j<32;j++)
5978 {
5979 if (m_len >= 128*4)
5980 n = 32*4;
5981 else
5982 n = m_len>>2;
5983
5984 for (i = 0; i < n; i++)
5985 {
5986#ifdef DDR_PREFETCH_CACHE
5987 ddr_pld_cache(p) ;
5988#endif
5989 if ((error_outof_count_flag) && (error_count))
5990 {
5991 printf("Error data out of count");
5992 m_len=0;
5993 break;
5994 }
5995 switch (i)
5996 {
5997 case 0:
5998 case 1:
5999 case 2:
6000 case 3:
6001 // if(*(p+i) !=~TDATA32F)
6002
6003 if ( *(p+i) != 0xff00ff00)
6004 {error_count++;
6005 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
6006 }
6007 break;
6008 case 4:
6009 case 5:
6010 case 6:
6011 case 7:
6012 if ( *(p+i) != 0xffff0000)
6013 {error_count++;
6014 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000);
6015 }
6016 break;
6017
6018 case 8:
6019 case 9:
6020 case 10:
6021 case 11:
6022 // *(p+i) = 0xff000000;
6023 if ( *(p+i) != 0xff000000)
6024 {error_count++;
6025 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000);
6026 }
6027 break;
6028 case 12:
6029 case 13:
6030 case 14:
6031 case 15:
6032 // *(p+i) = 0xff00ffff;
6033 if ( *(p+i) != 0xff00ffff)
6034 {error_count++;
6035 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
6036 }
6037 break;
6038
6039 case 16:
6040 case 17:
6041 case 18:
6042 case 19:
6043 // *(p+i) = 0xff00ffff;
6044 if ( *(p+i) != 0xff00ffff)
6045 {error_count++;
6046 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
6047 }
6048 break;
6049 case 20:
6050 case 21:
6051 case 22:
6052 case 23:
6053 // *(p+i) = 0xff0000ff;
6054 if ( *(p+i) != 0xff0000ff)
6055 {error_count++;
6056 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff0000ff);
6057 }
6058 break;
6059 case 24:
6060 case 25:
6061 case 26:
6062 case 27:
6063 // *(p+i) = 0xffff0000;
6064 if ( *(p+i) != 0xffff0000)
6065 {error_count++;
6066 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000);
6067 }
6068 break;
6069
6070 case 28:
6071 case 29:
6072 case 30:
6073 case 31:
6074 // *(p+i) = 0x00ff00ff;
6075 if ( *(p+i) != 0x00ff00ff)
6076 {error_count++;
6077 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff);
6078 }
6079 break;
6080 case DDR_PATTERN_LOOP_1+0:
6081 case DDR_PATTERN_LOOP_1+1:
6082 case DDR_PATTERN_LOOP_1+2:
6083 case DDR_PATTERN_LOOP_1+3:
6084 // *(p+i) =~0xff00ff00;
6085 if ( *(p+i) != ~0xff00ff00)
6086 {error_count++;
6087 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
6088 }
6089 break;
6090 case DDR_PATTERN_LOOP_1+4:
6091 case DDR_PATTERN_LOOP_1+5:
6092 case DDR_PATTERN_LOOP_1+6:
6093 case DDR_PATTERN_LOOP_1+7:
6094 // *(p+i) =~0xffff0000;
6095 if ( *(p+i) != ~0xffff0000)
6096 {error_count++;
6097 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000);
6098 }
6099 break;
6100 case DDR_PATTERN_LOOP_1+8:
6101 case DDR_PATTERN_LOOP_1+9:
6102 case DDR_PATTERN_LOOP_1+10:
6103 case DDR_PATTERN_LOOP_1+11:
6104 // *(p+i) =~0xff000000;
6105 if ( *(p+i) != ~0xff000000)
6106 {error_count++;
6107 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000);
6108 }
6109 break;
6110 case DDR_PATTERN_LOOP_1+12:
6111 case DDR_PATTERN_LOOP_1+13:
6112 case DDR_PATTERN_LOOP_1+14:
6113 case DDR_PATTERN_LOOP_1+15:
6114 // *(p+i) =~0xff00ffff;
6115 if ( *(p+i) != ~0xff00ffff)
6116 {error_count++;
6117 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
6118 }
6119 break;
6120 case DDR_PATTERN_LOOP_1+16:
6121 case DDR_PATTERN_LOOP_1+17:
6122 case DDR_PATTERN_LOOP_1+18:
6123 case DDR_PATTERN_LOOP_1+19:
6124 // *(p+i) =~0xff00ffff;
6125 if ( *(p+i) != ~0xff00ffff)
6126 {error_count++;
6127 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
6128 }
6129 break;
6130 case DDR_PATTERN_LOOP_1+20:
6131 case DDR_PATTERN_LOOP_1+21:
6132 case DDR_PATTERN_LOOP_1+22:
6133 case DDR_PATTERN_LOOP_1+23:
6134 // *(p+i) =~0xff00ffff;
6135 if ( *(p+i) != ~0xff00ffff)
6136 {error_count++;
6137 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
6138 }
6139 break;
6140 case DDR_PATTERN_LOOP_1+24:
6141 case DDR_PATTERN_LOOP_1+25:
6142 case DDR_PATTERN_LOOP_1+26:
6143 case DDR_PATTERN_LOOP_1+27:
6144 // *(p+i) =~0xffff0000;
6145 if ( *(p+i) != ~0xffff0000)
6146 {error_count++;
6147 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000);
6148 }
6149 break;
6150 case DDR_PATTERN_LOOP_1+28:
6151 case DDR_PATTERN_LOOP_1+29:
6152 case DDR_PATTERN_LOOP_1+30:
6153 case DDR_PATTERN_LOOP_1+31:
6154 // *(p+i) =~0x00ff00ff;
6155 if ( *(p+i) != ~0x00ff00ff)
6156 {error_count++;
6157 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff);
6158 }
6159 break;
6160
6161 case DDR_PATTERN_LOOP_2+0:
6162 case DDR_PATTERN_LOOP_2+1:
6163 case DDR_PATTERN_LOOP_2+2:
6164 case DDR_PATTERN_LOOP_2+3:
6165 // *(p+i) =0x00ff0000;
6166 if ( *(p+i) != 0x00ff0000)
6167 {error_count++;
6168 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff0000);
6169 }
6170 break;
6171 case DDR_PATTERN_LOOP_2+4:
6172 case DDR_PATTERN_LOOP_2+5:
6173 case DDR_PATTERN_LOOP_2+6:
6174 case DDR_PATTERN_LOOP_2+7:
6175 // *(p+i) =0xff000000;
6176 if ( *(p+i) != 0xff000000)
6177 {error_count++;
6178 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000);
6179 }
6180 break;
6181 case DDR_PATTERN_LOOP_2+8:
6182 case DDR_PATTERN_LOOP_2+9:
6183 case DDR_PATTERN_LOOP_2+10:
6184 case DDR_PATTERN_LOOP_2+11:
6185 // *(p+i) =0x0000ffff;
6186 if ( *(p+i) != 0x0000ffff)
6187 {error_count++;
6188 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x0000ffff);
6189 }
6190 break;
6191 case DDR_PATTERN_LOOP_2+12:
6192 case DDR_PATTERN_LOOP_2+13:
6193 case DDR_PATTERN_LOOP_2+14:
6194 case DDR_PATTERN_LOOP_2+15:
6195 // *(p+i) =0x000000ff;
6196 if ( *(p+i) != 0x000000ff)
6197 {error_count++;
6198 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x000000ff);
6199 }
6200 break;
6201 case DDR_PATTERN_LOOP_2+16:
6202 case DDR_PATTERN_LOOP_2+17:
6203 case DDR_PATTERN_LOOP_2+18:
6204 case DDR_PATTERN_LOOP_2+19:
6205 // *(p+i) =0x00ff00ff;
6206 if ( *(p+i) != 0x00ff00ff)
6207 {error_count++;
6208 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff);
6209 }
6210 break;
6211 case DDR_PATTERN_LOOP_2+20:
6212 case DDR_PATTERN_LOOP_2+21:
6213 case DDR_PATTERN_LOOP_2+22:
6214 case DDR_PATTERN_LOOP_2+23:
6215 // *(p+i) =0xff00ff00;
6216 if ( *(p+i) != 0xff00ff00)
6217 {error_count++;
6218 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
6219 }
6220 break;
6221 case DDR_PATTERN_LOOP_2+24:
6222 case DDR_PATTERN_LOOP_2+25:
6223 case DDR_PATTERN_LOOP_2+26:
6224 case DDR_PATTERN_LOOP_2+27:
6225 // *(p+i) =0xff00ffff;
6226 if ( *(p+i) != 0xff00ffff)
6227 {error_count++;
6228 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
6229 }
6230 break;
6231 case DDR_PATTERN_LOOP_2+28:
6232 case DDR_PATTERN_LOOP_2+29:
6233 case DDR_PATTERN_LOOP_2+30:
6234 case DDR_PATTERN_LOOP_2+31:
6235 // *(p+i) =0xff00ff00;
6236 if ( *(p+i) != 0xff00ff00)
6237 {error_count++;
6238 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
6239 }
6240 break;
6241 case DDR_PATTERN_LOOP_3+0:
6242 case DDR_PATTERN_LOOP_3+1:
6243 case DDR_PATTERN_LOOP_3+2:
6244 case DDR_PATTERN_LOOP_3+3:
6245 // *(p+i) =~0x00ff0000;
6246 if ( *(p+i) != ~0x00ff0000)
6247 {error_count++;
6248 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff0000);
6249 }
6250 break;
6251 case DDR_PATTERN_LOOP_3+4:
6252 case DDR_PATTERN_LOOP_3+5:
6253 case DDR_PATTERN_LOOP_3+6:
6254 case DDR_PATTERN_LOOP_3+7:
6255 // *(p+i) =~0xff000000;
6256 if ( *(p+i) != ~0xff000000)
6257 {error_count++;
6258 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000);
6259 }
6260 break;
6261 case DDR_PATTERN_LOOP_3+8:
6262 case DDR_PATTERN_LOOP_3+9:
6263 case DDR_PATTERN_LOOP_3+10:
6264 case DDR_PATTERN_LOOP_3+11:
6265 // *(p+i) =~0x0000ffff;
6266 if ( *(p+i) != ~0x0000ffff)
6267 {error_count++;
6268 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x0000ffff);
6269 }
6270 break;
6271 case DDR_PATTERN_LOOP_3+12:
6272 case DDR_PATTERN_LOOP_3+13:
6273 case DDR_PATTERN_LOOP_3+14:
6274 case DDR_PATTERN_LOOP_3+15:
6275 // *(p+i) =~0x000000ff;
6276 if ( *(p+i) != ~0x000000ff)
6277 {error_count++;
6278 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x000000ff);
6279 }
6280 break;
6281 case DDR_PATTERN_LOOP_3+16:
6282 case DDR_PATTERN_LOOP_3+17:
6283 case DDR_PATTERN_LOOP_3+18:
6284 case DDR_PATTERN_LOOP_3+19:
6285 // *(p+i) =~0x00ff00ff;
6286 if ( *(p+i) != ~0x00ff00ff)
6287 {error_count++;
6288 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff);
6289 }
6290 break;
6291 case DDR_PATTERN_LOOP_3+20:
6292 case DDR_PATTERN_LOOP_3+21:
6293 case DDR_PATTERN_LOOP_3+22:
6294 case DDR_PATTERN_LOOP_3+23:
6295 // *(p+i) =~0xff00ff00;
6296 if ( *(p+i) != ~0xff00ff00)
6297 {error_count++;
6298 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
6299 }
6300 break;
6301 case DDR_PATTERN_LOOP_3+24:
6302 case DDR_PATTERN_LOOP_3+25:
6303 case DDR_PATTERN_LOOP_3+26:
6304 case DDR_PATTERN_LOOP_3+27:
6305 // *(p+i) =~0xff00ffff;
6306 if ( *(p+i) != ~0xff00ffff)
6307 {error_count++;
6308 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
6309 }
6310 break;
6311 case DDR_PATTERN_LOOP_3+28:
6312 case DDR_PATTERN_LOOP_3+29:
6313 case DDR_PATTERN_LOOP_3+30:
6314 case DDR_PATTERN_LOOP_3+31:
6315 // *(p+i) =~0xff00ff00;
6316 if ( *(p+i) != ~0xff00ff00)
6317 {error_count++;
6318 printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
6319 }
6320 break;
6321
6322
6323 }
6324 }
6325
6326 if (m_len >( 128*4))
6327 {
6328 m_len -=( 128*4);
6329 p += 32*4;
6330 }
6331 else
6332 {
6333 p += (m_len>>2);
6334 m_len = 0;
6335 break;
6336 }
6337 }
6338 }
6339}
6340
6341
6342
6343int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
6344{
6345 char *endp;
6346 unsigned int loop = 1;
6347 unsigned int lflag = 0;
6348 unsigned int start_addr = DDR_TEST_START_ADDR;
6349 unsigned int test_size = DDR_TEST_SIZE;
6350 unsigned int simple_pattern_flag = 1;
6351 unsigned int cross_talk_pattern_flag = 1;
6352 unsigned int old_pattern_flag = 1;
6353
6354 unsigned int print_flag = 1;
6355 // copy_test_flag = 0;
6356 print_flag = 1;
6357 error_outof_count_flag =0;
6358 error_count =0;
6359 printf("\nargc== 0x%08x\n", argc);
6360 int i ;
6361 for (i = 0;i<argc;i++)
6362 {
6363 printf("\nargv[%d]=%s\n",i,argv[i]);
6364 }
6365 if (!argc)
6366 goto DDR_TEST_START;
6367 if (argc > 1) {
6368 if (strcmp(argv[1], "l") == 0) {
6369 lflag = 1;
6370 }
6371 else if (strcmp(argv[1], "h") == 0){
6372 goto usage;
6373 }
6374 else{
6375 loop = simple_strtoull_ddr(argv[1], &endp, 10);
6376 if (*argv[1] == 0 || *endp != 0)
6377 loop = 1;
6378 }
6379 }
6380 // printf("\nLINE== 0x%08x\n", __LINE__);
6381 if (argc ==1) {
6382 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
6383 // if (*argv[2] == 0 || *endp != 0)
6384 start_addr = DDR_TEST_START_ADDR;
6385 loop = 1;
6386
6387 }
6388 if (argc > 2) {
6389 start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
6390 if (*argv[2] == 0 || *endp != 0)
6391 start_addr = DDR_TEST_START_ADDR;
6392
6393 }
6394 if (argc > 3) {
6395 test_size = simple_strtoull_ddr(argv[3], &endp, 16);
6396 if (*argv[3] == 0 || *endp != 0)
6397 test_size = DDR_TEST_SIZE;
6398
6399 }
6400 if (test_size<0x1000)
6401 test_size = DDR_TEST_SIZE;
6402
6403 old_pattern_flag = 1;
6404 simple_pattern_flag = 1;
6405 cross_talk_pattern_flag = 1;
6406 //printf("\nLINE== 0x%08x\n", __LINE__);
6407 if (argc ==2) {
6408 if ( (strcmp(argv[1], "s") == 0))
6409 {
6410 simple_pattern_flag = 1;
6411 old_pattern_flag=0;
6412 cross_talk_pattern_flag = 0;
6413 }
6414 else if ((strcmp(argv[1], "c") == 0))
6415 {
6416 simple_pattern_flag = 0;
6417 old_pattern_flag=0;
6418 cross_talk_pattern_flag = 1;
6419 }
6420 else if ( (strcmp(argv[1], "e") == 0))
6421 {
6422 error_outof_count_flag=1;
6423 }
6424 }
6425 if (argc >2) {
6426 if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0))
6427 {
6428 print_flag = 0;
6429 }
6430 if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0))
6431 {
6432 copy_test_flag = 1;
6433 }
6434 if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0))
6435 {
6436 simple_pattern_flag = 1;
6437 old_pattern_flag=0;
6438 cross_talk_pattern_flag = 0;
6439 }
6440 else if ((strcmp(argv[1], "c") == 0)||(strcmp(argv[2], "c") == 0))
6441 {
6442 simple_pattern_flag = 0;
6443 old_pattern_flag=0;
6444 cross_talk_pattern_flag = 1;
6445 }
6446 else if ( (strcmp(argv[1], "e") == 0)||(strcmp(argv[2], "e") == 0))
6447 {
6448 error_outof_count_flag=1;
6449 }
6450 }
6451 //printf("\nLINE1== 0x%08x\n", __LINE__);
6452 if (argc > 3) {
6453 if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0) || (strcmp(argv[3], "p") == 0))
6454 {
6455 copy_test_flag = 1;
6456 }
6457 if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0) || (strcmp(argv[3], "n") == 0))
6458 {
6459 print_flag = 0;
6460 }
6461 if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0) || (strcmp(argv[3], "s") == 0))
6462 {
6463 simple_pattern_flag = 1;
6464 old_pattern_flag=0;
6465 cross_talk_pattern_flag = 0;
6466 }
6467 if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0) || (strcmp(argv[3], "c") == 0))
6468 {
6469 simple_pattern_flag = 0;
6470 old_pattern_flag=0;
6471 cross_talk_pattern_flag = 1;
6472 }
6473 if ( (strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0) || (strcmp(argv[3], "e") == 0))
6474 {
6475 error_outof_count_flag=1;
6476 }
6477 }
6478
6479 // printf("\nLINE2== 0x%08x\n", __LINE__);
6480 // printf("\nLINE3== 0x%08x\n", __LINE__);
6481 // printf("\nLINE== 0x%08x\n", __LINE__);
6482
6483DDR_TEST_START:
6484
6485 ///*
6486 do {
6487 if (lflag)
6488 loop = 888;
6489
6490 if (old_pattern_flag == 1)
6491 {
6492 {
6493 // printf("\nLINE== 0x%08x\n", __LINE__);
6494 //printf("\nLINE== 0x%08x\n", __LINE__);
6495 //printf("\nLINE== 0x%08x\n", __LINE__);
6496 if (print_flag)
6497 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
6498 ddr_write((void *)(int_convter_p(start_addr)), test_size);
6499 // flush_dcache_range(start_addr,start_addr + test_size);
6500 if (print_flag) {
6501 printf("\nEnd write. ");
6502 printf("\nStart 1st reading... ");
6503 }
6504 ddr_read((void *)(int_convter_p(start_addr)), test_size);
6505 if (print_flag) {
6506 printf("\nEnd 1st read. ");
6507 printf("\nStart 2nd reading... ");}
6508 ddr_read((void *)(int_convter_p(start_addr)), test_size);
6509 if (print_flag) {
6510 printf("\nEnd 2nd read. ");
6511 printf("\nStart 3rd reading... ");}
6512 ddr_read((void *)(int_convter_p(start_addr)), test_size);
6513 if (print_flag)
6514 printf("\nEnd 3rd read. \n");
6515
6516 if (copy_test_flag)
6517 {if(print_flag)
6518 printf("\n copy_test_flag = 1,start copy test. \n");
6519 ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
6520 ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6521 ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6522 }
6523
6524 }
6525 {
6526 // printf("\nLINE== 0x%08x\n", __LINE__);
6527 //printf("\nLINE== 0x%08x\n", __LINE__);
6528 //printf("\nLINE== 0x%08x\n", __LINE__);
6529 if (print_flag) {
6530 printf("\nStart *4 normal pattern. ");
6531 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
6532 }
6533 ddr_write4((void *)(int_convter_p(start_addr)), test_size);
6534 if (print_flag) {
6535 printf("\nEnd write. ");
6536 printf("\nStart 1st reading... ");}
6537 ddr_read4((void *)(int_convter_p(start_addr)), test_size);
6538 if (print_flag) {
6539 printf("\nEnd 1st read. ");
6540 printf("\nStart 2nd reading... ");}
6541 ddr_read4((void *)(int_convter_p(start_addr)), test_size);
6542 if (print_flag) {
6543 printf("\nEnd 2nd read. ");
6544 printf("\nStart 3rd reading... ");}
6545 ddr_read4((void *)(int_convter_p(start_addr)), test_size);
6546 if (print_flag)
6547 printf("\rEnd 3rd read. \n");
6548 if (copy_test_flag)
6549 {
6550
6551 ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
6552 ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6553 ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6554 }
6555
6556
6557 }
6558 }
6559
6560 if (simple_pattern_flag == 1)
6561 {
6562 if (print_flag) {
6563 printf("\nStart *4 no cross talk pattern. ");
6564 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
6565 }
6566 ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
6567 if (print_flag) {
6568 printf("\rEnd write. ");
6569 printf("\rStart 1st reading... ");}
6570 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
6571 if (print_flag) {
6572 printf("\rEnd 1st read. ");
6573 printf("\rStart 2nd reading... ");}
6574 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
6575 if (print_flag) {
6576 printf("\rEnd 2nd read. ");
6577 printf("\rStart 3rd reading... ");}
6578 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
6579 if (print_flag)
6580 printf("\rEnd 3rd read. \n");
6581
6582 if (copy_test_flag)
6583 {
6584 ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
6585 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6586 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6587 }
6588
6589 }
6590
6591 if (cross_talk_pattern_flag == 1)
6592 {if(print_flag){
6593 printf("\nStart *4 cross talk pattern p. ");
6594 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
6595 }
6596 ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
6597 if (print_flag) {
6598 printf("\rEnd write. ");
6599 printf("\rStart 1st reading... ");}
6600 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
6601 if (print_flag) {
6602 printf("\rEnd 1st read. ");
6603 printf("\rStart 2nd reading... ");}
6604 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
6605 if (print_flag) {
6606 printf("\rEnd 2nd read. ");
6607 printf("\rStart 3rd reading... ");}
6608 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
6609 if (print_flag) {
6610 printf("\rEnd 3rd read. \n");
6611
6612 printf("\nStart *4 cross talk pattern n. ");
6613 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
6614 ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
6615 if (print_flag) {
6616 printf("\rEnd write. ");
6617 printf("\rStart 1st reading... ");}
6618 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
6619 if (print_flag) {
6620 printf("\rEnd 1st read. ");
6621 printf("\rStart 2nd reading... ");}
6622 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
6623 if (print_flag) {
6624 printf("\rEnd 2nd read. ");
6625 printf("\rStart 3rd reading... ");}
6626 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
6627 if (print_flag) {
6628 printf("\rEnd 3rd read. \n");
6629
6630 ///*
6631 printf("\nStart *4 cross talk pattern p2. ");
6632 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
6633 ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
6634 if (print_flag) {
6635 printf("\rEnd write. ");
6636 printf("\rStart 1st reading... ");}
6637 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
6638 if (print_flag) {
6639 printf("\rEnd 1st read. ");
6640 printf("\rStart 2nd reading... ");}
6641 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
6642 if (print_flag) {
6643 printf("\rEnd 2nd read. ");
6644 printf("\rStart 3rd reading... ");}
6645 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
6646 if (print_flag) {
6647 printf("\rEnd 3rd read. \n");
6648
6649 printf("\nStart *4 cross talk pattern n2. ");
6650 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
6651 ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
6652 if (print_flag) {
6653 printf("\rEnd write. ");
6654 printf("\rStart 1st reading... ");}
6655 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
6656 if (print_flag) {
6657 printf("\rEnd 1st read. ");
6658 printf("\rStart 2nd reading... ");}
6659 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
6660 if (print_flag) {
6661 printf("\rEnd 2nd read. ");
6662 printf("\rStart 3rd reading... ");}
6663 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
6664 if (print_flag)
6665 printf("\rEnd 3rd read. \n");
6666
6667 if (copy_test_flag)
6668 {
6669 ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
6670 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6671 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
6672 }
6673 // */
6674
6675 }
6676
6677 if (print_flag)
6678 printf("\nError count==0x%08x", error_count);
6679
6680 }while(--loop);
6681 //*/
6682
6683 printf("\rEnd ddr test. \n");
6684
6685 return 0;
6686
6687usage:
6688 cmd_usage(cmdtp);
6689 return 1;
6690}
6691
6692U_BOOT_CMD(
6693 ddrtest, 5, 1, do_ddr_test,
6694 "DDR test function",
6695 "ddrtest [LOOP] [ADDR].Default address is 0x8d000000\n"
6696);
6697
6698int do_ddr_special_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
6699{
6700 char *endp;
6701 unsigned int loop = 1;
6702 unsigned int lflag = 0;
6703 unsigned int start_addr = DDR_TEST_START_ADDR;
6704 unsigned int test_addr = DDR_TEST_START_ADDR;
6705 unsigned int test_size = DDR_TEST_SIZE;
6706 unsigned int write_times = 1;
6707 unsigned int read_times = 3;
6708 // unsigned int old_pattern_flag = 1;
6709
6710 unsigned int print_flag = 1;
6711 // copy_test_flag = 0;
6712 print_flag = 1;
6713 error_outof_count_flag =0;
6714 error_count =0;
6715 printf("\nargc== 0x%08x\n", argc);
6716 int i ;
6717 for (i = 0;i<argc;i++)
6718 {
6719 printf("\nargv[%d]=%s\n",i,argv[i]);
6720 }
6721
6722 if (strcmp(argv[1], "l") == 0) {
6723 lflag = 1;
6724 }
6725 else if (strcmp(argv[1], "h") == 0){
6726 goto usage;
6727 }
6728 else{
6729 loop = simple_strtoull_ddr(argv[1], &endp, 10);
6730 if (*argv[1] == 0 || *endp != 0)
6731 loop = 1;
6732 }
6733
6734 // printf("\nLINE== 0x%08x\n", __LINE__);
6735 if (argc ==1) {
6736 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
6737 // if (*argv[2] == 0 || *endp != 0)
6738 start_addr = DDR_TEST_START_ADDR;
6739 loop = 1;
6740
6741 }
6742 if (argc > 2) {
6743 start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
6744 if (*argv[2] == 0 || *endp != 0)
6745 start_addr = DDR_TEST_START_ADDR;
6746
6747 }
6748 if (argc > 3) {
6749 test_size = simple_strtoull_ddr(argv[3], &endp, 16);
6750 if (*argv[3] == 0 || *endp != 0)
6751 test_size = DDR_TEST_SIZE;
6752
6753 }
6754 if (test_size<0x1000)
6755 test_size = DDR_TEST_SIZE;
6756 if (argc > 4) {
6757 write_times = simple_strtoull_ddr(argv[4], &endp, 16);
6758 if (*argv[4] == 0 || *endp != 0)
6759 write_times = 0;
6760
6761 }
6762 if (argc > 5) {
6763 read_times = simple_strtoull_ddr(argv[5], &endp, 16);
6764 if (*argv[5] == 0 || *endp != 0)
6765 read_times = 0;
6766
6767 }
6768 unsigned int base_pattern = 1;
6769 unsigned int inc_flag = 1;
6770 if (argc > 6) {
6771 base_pattern = simple_strtoull_ddr(argv[6], &endp, 16);
6772 if (*argv[6] == 0 || *endp != 0)
6773 base_pattern = 0;
6774
6775 }
6776 if (argc > 7) {
6777 inc_flag = simple_strtoull_ddr(argv[7], &endp, 16);
6778 if (*argv[7] == 0 || *endp != 0)
6779 inc_flag = 0;
6780
6781 }
6782
6783
6784 //printf("\nLINE== 0x%08x\n", __LINE__);
6785
6786 //printf("\nLINE1== 0x%08x\n", __LINE__);
6787
6788
6789 // printf("\nLINE2== 0x%08x\n", __LINE__);
6790 // printf("\nLINE3== 0x%08x\n", __LINE__);
6791 // printf("\nLINE== 0x%08x\n", __LINE__);
6792
6793
6794 unsigned int count = 1;
6795 unsigned int test_val = 1;
6796
6797 ///*
6798 do {
6799 if (lflag)
6800 loop = 888;
6801
6802 if (1)
6803 {
6804
6805 for (i=0;i<write_times;)
6806 {i++;
6807
6808 printf("\nwrite_times==0x%08x \n",((unsigned int)i));
6809 // serial_put_hex(((unsigned long)i),32);
6810 // count=count_max;
6811 // reg=reg_base;
6812 // val=val_base;
6813 test_addr=start_addr;
6814 test_val=base_pattern;
6815 count=(test_size>>2);
6816 do
6817 {
6818 writel(test_val,(unsigned long)test_addr);
6819 test_addr=test_addr+4;
6820 if (inc_flag)
6821 test_val=test_val+1;
6822
6823 }
6824 while (count--) ;
6825 }
6826
6827 for (i=0;i<read_times;)
6828 {i++;
6829 printf("\nread_times==0x%08x \n",((unsigned int)i));
6830 //serial_puts("\nread_times= ");
6831 // serial_put_hex(((unsigned long)i),32);
6832 test_addr=start_addr;
6833 test_val=base_pattern;
6834 count=(test_size>>2);
6835
6836 do
6837 {
6838
6839 //writel(val,(unsigned long)reg);
6840 if (test_val != (readl((unsigned long)test_addr))) {
6841
6842 printf("\nadd==0x%08x,pattern==0x%08x,read==0x%08x \n",((unsigned int)test_addr),((unsigned int)test_val),(readl((unsigned int)test_addr)));
6843 }
6844 test_addr=test_addr+4;
6845 if (inc_flag)
6846 test_val=test_val+1;
6847 }
6848 while (count--) ;
6849 }
6850 }
6851
6852
6853
6854 if (print_flag)
6855 printf("\nError count==0x%08x", error_count);
6856
6857 }while(--loop);
6858 //*/
6859
6860 printf("\rEnd ddr test. \n");
6861
6862 return 0;
6863
6864usage:
6865 cmd_usage(cmdtp);
6866 return 1;
6867}
6868U_BOOT_CMD(
6869 ddr_spec_test, 8, 1, do_ddr_special_test,
6870 "DDR test function",
6871 "ddrtest [LOOP] [ADDR] [size] [write_times] [read times] [pattern] [inc].ddr_spec_test 1 0x1080000 0x200000 1 3 1 1 \n"
6872);
6873/*
6874int do_mw_mask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
6875{
6876char *endp;
6877unsigned int reg_add=0;
6878unsigned int wr_reg_value=0;
6879unsigned int rd_reg_value=0;
6880unsigned int wr_reg_and_mask_1=0xffffffff;
6881if (argc == 1)
6882{ printf("\nplease read help\n");
6883printf("\nexample only change 0xc8836800 0x8c010226 0x000fffff bit20-bit31,no change pll od oc \n");
6884printf("\nmwm 0xc8836800 0x8c010226 0x000fffff\n");
6885}
6886else{
6887if (argc >= 2)
6888{
6889reg_add = simple_strtoull_ddr(argv[1], &endp, 10);
6890}
6891if (argc >= 3)
6892{
6893wr_reg_value = simple_strtoull_ddr(argv[2], &endp, 10);
6894}
6895if (argc >= 4)
6896{
6897wr_reg_and_mask_1 = simple_strtoull_ddr(argv[3], &endp, 10);
6898
6899}
6900rd_reg_value= (rd_reg(reg_add));
6901wr_reg(reg_add,(rd_reg_value&wr_reg_and_mask_1)|(wr_reg_value&(~wr_reg_and_mask_1)) );
6902
6903printf("\nmodify ok read==0x%08x\n",(rd_reg(reg_add)));
6904
6905}
6906return 1;
6907}
6908U_BOOT_CMD(
6909 mwm, 30, 1, do_mw_mask,
6910 "mw mask function",
6911 "mw 0xc8836800 0x8c82022c 0x000fffff\n"
6912);
6913*/
6914
6915///*
6916
6917int ddr_test_s_cross_talk_pattern(int ddr_test_size)
6918{
6919#define TEST_OFFSET 0//0X40000000
6920 // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET;
6921 unsigned int start_addr=test_start_addr;
6922
6923 error_outof_count_flag=1;
6924
6925 error_count=0;
6926
6927#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
6928 training_pattern_flag=0;
6929#endif
6930 ///*
6931 if (training_pattern_flag)
6932 {
6933#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
6934 ddr_test_gx_training_pattern(ddr_test_size);
6935#endif
6936 if (error_count)
6937 return 1;
6938 else
6939 return 0;
6940 }
6941 else
6942 {
6943#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
6944 ddr_test_gx_training_pattern(ddr_test_size);
6945#endif
6946
6947 }
6948 // */
6949 /*
6950 ddr_test_gx_cross_talk_pattern( ddr_test_size);
6951 if (error_count)
6952 return 1;
6953 else
6954 return 0;
6955 */
6956 {
6957 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
6958 ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
6959 printf("\nEnd write. ");
6960 printf("\nStart 1st reading... ");
6961 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
6962 printf("\nEnd 1st read. ");
6963 printf("\nStart 2nd reading... ");
6964 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
6965 if (error_count)
6966 return error_count;
6967 printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
6968 ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
6969 printf("\nEnd write. ");
6970 printf("\nStart 1st reading... ");
6971 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
6972 printf("\nEnd 1st read. ");
6973 printf("\nStart 2nd reading... ");
6974 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
6975
6976 if (error_count)
6977 return error_count;
6978 printf("\nStart *4 no cross talk pattern. ");
6979 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
6980 ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
6981 printf("\nEnd write. ");
6982 printf("\nStart 1st reading... ");
6983 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
6984 printf("\nEnd 1st read. ");
6985 printf("\nStart 2nd reading... ");
6986 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
6987 }
6988
6989 if (error_count)
6990 return error_count;
6991 //if(cross_talk_pattern_flag==1)
6992 {
6993 printf("\nStart *4 cross talk pattern p. ");
6994 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
6995 ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
6996 printf("\rEnd write. ");
6997 printf("\rStart 1st reading... ");
6998 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
6999 printf("\rEnd 1st read. ");
7000 printf("\rStart 2nd reading... ");
7001 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
7002 printf("\rEnd 2nd read. ");
7003
7004 // printf("\rStart 3rd reading... ");
7005 // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
7006 // printf("\rEnd 3rd read. \n");
7007
7008 if (error_count)
7009 return error_count;
7010 printf("\nStart *4 cross talk pattern n. ");
7011 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7012 ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7013 printf("\rEnd write. ");
7014 printf("\rStart 1st reading... ");
7015 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7016 printf("\rEnd 1st read. ");
7017 printf("\rStart 2nd reading... ");
7018 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7019 printf("\rEnd 2nd read. ");
7020 // printf("\rStart 3rd reading... ");
7021 // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
7022 // printf("\rEnd 3rd read. \n");
7023 }
7024 if (error_count)
7025 return error_count;
7026 {
7027 printf("\nStart *4 cross talk pattern p2. ");
7028 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7029 ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7030 printf("\rEnd write. ");
7031 printf("\rStart 1st reading... ");
7032 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7033 printf("\rEnd 1st read. ");
7034 printf("\rStart 2nd reading... ");
7035 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7036 printf("\rEnd 2nd read. ");
7037
7038 // printf("\rStart 3rd reading... ");
7039 // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
7040 // printf("\rEnd 3rd read. \n");
7041 if (error_count)
7042 return error_count;
7043 printf("\nStart *4 cross talk pattern n. ");
7044 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7045 ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7046 printf("\rEnd write. ");
7047 printf("\rStart 1st reading... ");
7048 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7049 printf("\rEnd 1st read. ");
7050 printf("\rStart 2nd reading... ");
7051 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7052 printf("\rEnd 2nd read. ");
7053 // printf("\rStart 3rd reading... ");
7054 // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
7055 // printf("\rEnd 3rd read. \n");
7056 if (copy_test_flag)
7057 {
7058 if (error_count)
7059 return error_count;
7060 printf("\n start copy test ... ");
7061 ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 );
7062 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
7063 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
7064 }
7065 }
7066
7067 if (error_count)
7068 return 1;
7069 else
7070 return 0;
7071 }
7072
7073
7074
7075int ddr_test_s_cross_talk_pattern_quick_retrun(int ddr_test_size)
7076{
7077 error_outof_count_flag =1;
7078 #define TEST_OFFSET 0//0X40000000
7079 // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET;
7080 unsigned int start_addr=test_start_addr;
7081
7082 error_outof_count_flag=1;
7083
7084 error_count=0;
7085
7086 #if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
7087 training_pattern_flag=0;
7088 #endif
7089 ///*
7090 if (training_pattern_flag)
7091 {
7092 #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
7093 ddr_test_gx_training_pattern(ddr_test_size);
7094 #endif
7095 if (error_count)
7096 return 1;
7097 else
7098 return 0;
7099 }
7100 else
7101 {
7102 #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
7103 ddr_test_gx_training_pattern(ddr_test_size);
7104 #endif
7105 }
7106 // */
7107 /*
7108 ddr_test_gx_cross_talk_pattern( ddr_test_size);
7109 if (error_count)
7110 return 1;
7111 else
7112 return 0;
7113 */
7114
7115 {
7116 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7117 ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
7118 printf("\nEnd write. ");
7119 printf("\nStart 1st reading... ");
7120 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
7121 printf("\nEnd 1st read. ");
7122 printf("\nStart 2nd reading... ");
7123 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
7124
7125 printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7126 ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
7127 printf("\nEnd write. ");
7128 printf("\nStart 1st reading... ");
7129 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
7130 printf("\nEnd 1st read. ");
7131 printf("\nStart 2nd reading... ");
7132 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
7133
7134 printf("\nStart *4 no cross talk pattern. ");
7135 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7136 ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
7137 printf("\nEnd write. ");
7138 printf("\nStart 1st reading... ");
7139 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
7140 printf("\nEnd 1st read. ");
7141 printf("\nStart 2nd reading... ");
7142 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
7143 }
7144 //if(cross_talk_pattern_flag==1)
7145 {
7146 printf("\nStart *4 cross talk pattern p. ");
7147 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7148 ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
7149 printf("\rEnd write. ");
7150 printf("\rStart 1st reading... ");
7151 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
7152 printf("\rEnd 1st read. ");
7153 printf("\rStart 2nd reading... ");
7154 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
7155 printf("\rEnd 2nd read. ");
7156
7157 // printf("\rStart 3rd reading... ");
7158 // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
7159 // printf("\rEnd 3rd read. \n");
7160
7161 printf("\nStart *4 cross talk pattern n. ");
7162 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7163 ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7164 printf("\rEnd write. ");
7165 printf("\rStart 1st reading... ");
7166 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7167 printf("\rEnd 1st read. ");
7168 printf("\rStart 2nd reading... ");
7169 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
7170 printf("\rEnd 2nd read. ");
7171 // printf("\rStart 3rd reading... ");
7172 // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
7173 // printf("\rEnd 3rd read. \n");
7174
7175
7176 }
7177
7178 {
7179 printf("\nStart *4 cross talk pattern p2. ");
7180 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7181 ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7182 printf("\rEnd write. ");
7183 printf("\rStart 1st reading... ");
7184 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7185 printf("\rEnd 1st read. ");
7186 printf("\rStart 2nd reading... ");
7187 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
7188 printf("\rEnd 2nd read. ");
7189
7190 // printf("\rStart 3rd reading... ");
7191 // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
7192 // printf("\rEnd 3rd read. \n");
7193
7194 printf("\nStart *4 cross talk pattern n. ");
7195 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
7196 ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7197 printf("\rEnd write. ");
7198 printf("\rStart 1st reading... ");
7199 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7200 printf("\rEnd 1st read. ");
7201 printf("\rStart 2nd reading... ");
7202 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
7203 printf("\rEnd 2nd read. ");
7204 // printf("\rStart 3rd reading... ");
7205 // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
7206 // printf("\rEnd 3rd read. \n");
7207 if (copy_test_flag)
7208 {
7209 printf("\n start copy test ... ");
7210 ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 );
7211 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
7212 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
7213 }
7214
7215 }
7216
7217 if (error_count)
7218 return 1;
7219 else
7220 return 0;
7221}
7222
7223#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
7224int do_ddr_test_dqs_window_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
7225{
7226 printf("\nEnter test ddr dqs window step function\n");
7227 // if(!argc)
7228 // goto DDR_TUNE_DQS_START;
7229 printf("\nargc== 0x%08x\n", argc);
7230
7231 unsigned int temp_test_error= 0;
7232
7233 char *endp;
7234 // unsigned int *p_start_addr;
7235 unsigned int test_lane_step=0;
7236 unsigned int testing_lane=0;
7237 unsigned int test_lane_step_rdqs_flag=0;
7238 unsigned int test_min_max_flag=0;
7239 unsigned int test_times=1;
7240 unsigned int reg_add=0;
7241 unsigned int reg_base_adj=0;
7242 unsigned int channel_a_en = 0;
7243 unsigned int channel_b_en = 0;
7244
7245 unsigned int dq_lcd_bdl_reg_org=0;
7246 unsigned int dq_lcd_bdl_reg_left=0;
7247 unsigned int dq_lcd_bdl_reg_right=0;
7248
7249 unsigned int dq_lcd_bdl_reg_left_min=0;
7250 unsigned int dq_lcd_bdl_reg_right_min=0;
7251
7252 unsigned int dq_lcd_bdl_temp_reg_value=0;
7253
7254 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
7255 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
7256 // unsigned int dq_lcd_bdl_temp_reg_lef;
7257 // unsigned int dq_lcd_bdl_temp_reg_rig;
7258
7259 unsigned int ddr_test_size= DDR_TEST_SIZE;//DDR_CROSS_TALK_TEST_SIZE;
7260
7261 if (argc == 2)
7262 {
7263 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
7264 {
7265 channel_a_en = 1;
7266 }
7267 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
7268 {
7269 channel_b_en = 1;
7270 }
7271 else
7272 {
7273 goto usage;
7274 }
7275 }
7276 if (argc > 2)
7277 {
7278 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
7279 {
7280 channel_a_en = 1;
7281 }
7282 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
7283 {
7284 channel_b_en = 1;
7285 }
7286 }
7287 ddr_test_size = DDR_TEST_SIZE;
7288 if (argc >3) {
7289 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
7290 if (*argv[3] == 0 || *endp != 0)
7291 {
7292 ddr_test_size = DDR_TEST_SIZE;
7293 }
7294 }
7295 if (argc >4) {
7296 test_lane_step = 0;
7297 test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
7298 if (*argv[4] == 0 || *endp != 0)
7299 {
7300 test_lane_step = 0;
7301 }
7302 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
7303 {
7304 test_lane_step = 0;
7305 }
7306 }
7307 if (test_lane_step >7)
7308 test_lane_step = 0;
7309 unsigned int test_loop=1;
7310 if (argc >5) {
7311 test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
7312 if (*argv[5] == 0 || *endp != 0)
7313 {
7314 test_min_max_flag = 0;
7315 }
7316 else
7317 {
7318 //test_min_max_flag =1;
7319 }
7320 }
7321 unsigned int test_temp_value_use_sticky_register=0;
7322 if (argc >6) {
7323 test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
7324 if (*argv[6] == 0 || *endp != 0)
7325 {
7326 test_temp_value_use_sticky_register = 0;
7327 }
7328 else
7329 {
7330 //test_min_max_flag =1;
7331 }
7332 }
7333 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
7334
7335 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
7336 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
7337 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
7338 printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
7339 printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
7340 printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
7341
7342 const char *temp_s;
7343 char *env_lcdlr_temp_count;
7344 char *buf;
7345 buf="";
7346 unsigned int lcdlr_temp_count=0;
7347 env_lcdlr_temp_count="lcdlr_temp_count";
7348
7349 if (test_temp_value_use_sticky_register)
7350 {
7351 lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
7352 }
7353 else
7354 {
7355 temp_s= env_get(env_lcdlr_temp_count);
7356 if (temp_s)
7357 {
7358 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
7359 }
7360 else
7361 {
7362 lcdlr_temp_count=0;
7363 }
7364 }
7365
7366 //if ( channel_a_en)
7367 {
7368 //writel((0), 0xc8836c00);
7369 OPEN_CHANNEL_A_PHY_CLK();
7370 }
7371 //if ( channel_b_en)
7372 {
7373 OPEN_CHANNEL_B_PHY_CLK();
7374 //writel((0), 0xc8836c00);
7375 }
7376
7377for (test_times=0;(test_times<test_loop);(test_times++))
7378{
7379 ////tune and save training dqs value
7380 if (channel_a_en || channel_b_en)
7381 {
7382 if (( channel_a_en) && ( channel_b_en == 0))
7383 {
7384 reg_base_adj=CHANNEL_A_REG_BASE;
7385 }
7386 else if(( channel_b_en)&&( channel_a_en==0))
7387 {
7388 reg_base_adj=CHANNEL_B_REG_BASE;
7389 }
7390 else if ((channel_a_en+channel_b_en)==2)
7391 {
7392 reg_base_adj=CHANNEL_A_REG_BASE;
7393 }
7394
7395 {
7396 printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR0_PUB_REG_BASE+4));
7397 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
7398 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
7399 if ( channel_b_en)
7400 {
7401 printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR1_PUB_REG_BASE+4));
7402 writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
7403 printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
7404 }
7405 if (test_lane_step>8)
7406 test_lane_step=0;
7407 printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
7408
7409 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_lane_step>>1);
7410 test_lane_step_rdqs_flag=test_lane_step%2;
7411 testing_lane=(test_lane_step>>1);
7412
7413 dq_lcd_bdl_temp_reg_value=readl(reg_add);
7414 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
7415 printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
7416
7417 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7418 if (test_lane_step_rdqs_flag)
7419 {
7420 dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0xff00)>>8);
7421 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
7422 }
7423 else
7424 {
7425 dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0x00ff)>>0);
7426 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
7427 }
7428 #endif
7429
7430 if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
7431 {
7432 while (dq_lcd_bdl_temp_reg_value>0)
7433 {
7434 ddr_test_watchdog_clear();
7435 temp_test_error=0;
7436 dq_lcd_bdl_temp_reg_value--;
7437
7438 {
7439 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
7440 sprintf(buf, "0x%08x", lcdlr_temp_count);
7441 printf( "%s\n", buf);
7442 if (test_temp_value_use_sticky_register)
7443 {
7444 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
7445 }
7446 else
7447 {
7448 env_set(env_lcdlr_temp_count, buf);
7449 run_command("save",0);
7450 }
7451 }
7452
7453 printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
7454 if (!test_lane_step_rdqs_flag)
7455 {
7456 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7457 writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
7458 #else
7459 writel(dq_lcd_bdl_temp_reg_value,reg_add);
7460 #endif
7461 }
7462 else
7463 {
7464 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7465 writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
7466 #endif
7467 }
7468 printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
7469 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
7470
7471 if (temp_test_error)
7472 {
7473 //printf("\nwdqd left edge detect \n");
7474 dq_lcd_bdl_temp_reg_value++;
7475 break;
7476 }
7477 }
7478 printf("\n left edge detect \n");
7479 printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
7480
7481 dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
7482 if (test_times == 0)
7483 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
7484 if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
7485 {
7486 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
7487 }
7488 }
7489 else
7490 {
7491 printf("\n left edge skip \n");
7492 }
7493
7494 if (!test_lane_step_rdqs_flag)
7495 {
7496 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7497 writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
7498 #else
7499 writel(dq_lcd_bdl_reg_org,reg_add);
7500 #endif
7501 // writel(dq_lcd_bdl_reg_org,reg_add);
7502 }
7503 else
7504 {
7505 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7506 writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
7507 #else
7508 #endif
7509 // writel(dq_lcd_bdl_reg_org,reg_add);
7510 // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
7511 }
7512
7513 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
7514
7515 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
7516
7517
7518 if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
7519 {
7520 while (dq_lcd_bdl_temp_reg_value<DQLCDLR_MAX)
7521 {
7522 ddr_test_watchdog_clear();
7523 temp_test_error=0;
7524 dq_lcd_bdl_temp_reg_value++;
7525
7526
7527 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
7528 sprintf(buf, "0x%08x", lcdlr_temp_count);
7529 printf( "%s\n", buf);
7530 if (test_temp_value_use_sticky_register)
7531 {
7532 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
7533 }
7534 else
7535 {
7536 env_set(env_lcdlr_temp_count, buf);
7537 run_command("save",0);
7538 }
7539
7540 printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
7541 if (!test_lane_step_rdqs_flag)
7542 {
7543 //writel(dq_lcd_bdl_temp_reg_value,reg_add);
7544 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7545 writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
7546 #else
7547 writel(dq_lcd_bdl_temp_reg_value,reg_add);
7548 #endif
7549 }
7550 else
7551 {
7552 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7553 writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
7554 #endif
7555 // writel(dq_lcd_bdl_temp_reg_value,reg_add);
7556 // writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
7557 }
7558 printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
7559 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
7560 if (temp_test_error)
7561 {
7562 //printf("\nwdqd right edge detect \n");
7563 dq_lcd_bdl_temp_reg_value--;
7564 break;
7565 }
7566 }
7567 printf("\n right edge detect \n");
7568 printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
7569
7570 dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
7571 if (test_times == 0)
7572 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
7573 if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
7574 {
7575 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
7576 }
7577 }
7578
7579 if (!test_lane_step_rdqs_flag)
7580 {
7581 // writel(dq_lcd_bdl_reg_org,reg_add);
7582 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7583 writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
7584 #else
7585 writel(dq_lcd_bdl_reg_org,reg_add);
7586 #endif
7587 }
7588 else
7589 {
7590 #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
7591 writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
7592 #endif
7593 // writel(dq_lcd_bdl_reg_org,reg_add);
7594 // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
7595 }
7596 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
7597 printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
7598 writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
7599 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
7600 }
7601 }
7602
7603}
7604
7605 dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
7606 if (!test_lane_step_rdqs_flag)
7607 {
7608 if (channel_a_en)
7609 {
7610 dq_lcd_bdl_value_wdq_org_a[testing_lane]=dq_lcd_bdl_reg_org;
7611 if (test_min_max_flag != 1)
7612 dq_lcd_bdl_value_wdq_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
7613 if (test_min_max_flag != 2)
7614 dq_lcd_bdl_value_wdq_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
7615 }
7616 if (channel_b_en)
7617 {
7618 dq_lcd_bdl_value_wdq_org_b[testing_lane]=dq_lcd_bdl_reg_org;
7619 if (test_min_max_flag != 1)
7620 dq_lcd_bdl_value_wdq_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
7621 if (test_min_max_flag != 2)
7622 dq_lcd_bdl_value_wdq_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
7623 }
7624 }
7625 else
7626 {
7627 if (channel_a_en) {
7628 dq_lcd_bdl_value_rdqs_org_a[testing_lane]=dq_lcd_bdl_reg_org;
7629 if (test_min_max_flag != 1)
7630 dq_lcd_bdl_value_rdqs_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
7631 if (test_min_max_flag != 2)
7632 dq_lcd_bdl_value_rdqs_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
7633 }
7634 if (channel_b_en) {
7635 dq_lcd_bdl_value_rdqs_org_b[testing_lane]=dq_lcd_bdl_reg_org;
7636 if (test_min_max_flag != 1)
7637 dq_lcd_bdl_value_rdqs_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
7638 if (test_min_max_flag != 2)
7639 dq_lcd_bdl_value_rdqs_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
7640 }
7641 }
7642
7643 return dq_lcd_bdl_temp_reg_value;
7644
7645usage:
7646 cmd_usage(cmdtp);
7647 return 1;
7648
7649}
7650U_BOOT_CMD(
7651 ddr_tune_dqs_step, 7, 1, do_ddr_test_dqs_window_step,
7652 "ddr_tune_dqs_step function",
7653 "ddr_tune_dqs_step a 0 0x80000 3 or ddr_tune_dqs_step b 0 0x80000 5 \n dcache off ? \n"
7654);
7655#else
7656
7657int do_ddr_test_fine_tune_dqs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
7658{
7659 printf("\nEnter Tune ddr dqs function\n");
7660 // if(!argc)
7661 // goto DDR_TUNE_DQS_START;
7662 printf("\nargc== 0x%08x\n", argc);
7663 // unsigned int loop = 1;
7664 unsigned int temp_count_i = 1;
7665 unsigned int temp_count_j= 1;
7666 unsigned int temp_count_k= 1;
7667 unsigned int temp_test_error= 0;
7668
7669
7670 char *endp;
7671 // unsigned int *p_start_addr;
7672 unsigned int test_loop=1;
7673 unsigned int test_times=1;
7674 unsigned int reg_add=0;
7675 unsigned int reg_base_adj=0;
7676 unsigned int channel_a_en = 0;
7677 unsigned int channel_b_en = 0;
7678 unsigned int testing_channel = 0;
7679
7680#define DATX8_DQ_LCD_BDL_REG_WIDTH 12
7681
7682#define DATX8_DQ_LANE_WIDTH 4
7683#define CHANNEL_CHANNEL_WIDTH 2
7684
7685#define CHANNEL_A 0
7686#define CHANNEL_B 1
7687
7688
7689
7690#define DATX8_DQ_LANE_LANE00 0
7691#define DATX8_DQ_LANE_LANE01 1
7692#define DATX8_DQ_LANE_LANE02 2
7693#define DATX8_DQ_LANE_LANE03 3
7694
7695#define DATX8_DQ_BDLR0 0
7696#define DATX8_DQ_BDLR1 1
7697#define DATX8_DQ_BDLR2 2
7698#define DATX8_DQ_BDLR3 3
7699#define DATX8_DQ_BDLR4 4
7700#define DATX8_DQ_BDLR5 5
7701#define DATX8_DQ_BDLR6 6
7702#define DATX8_DQ_DXNLCDLR0 7
7703#define DATX8_DQ_DXNLCDLR1 8
7704#define DATX8_DQ_DXNLCDLR2 9
7705#define DATX8_DQ_DXNMDLR 10
7706#define DATX8_DQ_DXNGTR 11
7707
7708
7709#define DDR_CROSS_TALK_TEST_SIZE 0x20000
7710
7711#define DQ_LCD_BDL_REG_NUM_PER_CHANNEL DATX8_DQ_LCD_BDL_REG_WIDTH*DATX8_DQ_LANE_WIDTH
7712#define DQ_LCD_BDL_REG_NUM DQ_LCD_BDL_REG_NUM_PER_CHANNEL*CHANNEL_CHANNEL_WIDTH
7713
7714 unsigned int dq_lcd_bdl_reg_org[DQ_LCD_BDL_REG_NUM];
7715 unsigned int dq_lcd_bdl_reg_left[DQ_LCD_BDL_REG_NUM];
7716 unsigned int dq_lcd_bdl_reg_right[DQ_LCD_BDL_REG_NUM];
7717 unsigned int dq_lcd_bdl_reg_index[DQ_LCD_BDL_REG_NUM];
7718
7719 unsigned int dq_lcd_bdl_reg_left_min[DQ_LCD_BDL_REG_NUM];
7720 unsigned int dq_lcd_bdl_reg_right_min[DQ_LCD_BDL_REG_NUM];
7721
7722 unsigned int dq_lcd_bdl_temp_reg_value;
7723 unsigned int dq_lcd_bdl_temp_reg_value_dqs;
7724 unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
7725 unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
7726 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsnd;
7727 unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
7728 unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
7729 // unsigned int dq_lcd_bdl_temp_reg_value_dqs;
7730 // unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
7731 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
7732
7733 unsigned int dq_lcd_bdl_temp_reg_lef;
7734 unsigned int dq_lcd_bdl_temp_reg_rig;
7735 unsigned int dq_lcd_bdl_temp_reg_center;
7736 unsigned int dq_lcd_bdl_temp_reg_windows;
7737 unsigned int dq_lcd_bdl_temp_reg_center_min;
7738 unsigned int dq_lcd_bdl_temp_reg_windows_min;
7739
7740 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
7741
7742
7743
7744 if (argc == 2)
7745 {
7746 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
7747
7748 {channel_a_en = 1;
7749 }
7750 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
7751
7752 {channel_b_en = 1;
7753 }
7754 else
7755 {
7756 goto usage;
7757 }
7758 }
7759 if (argc > 2)
7760 {
7761 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
7762
7763 {channel_a_en = 1;
7764 }
7765 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
7766
7767 {channel_b_en = 1;
7768 }
7769 }
7770 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
7771 if (argc >3) {
7772 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
7773 if (*argv[3] == 0 || *endp != 0)
7774 {
7775 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
7776 }
7777
7778 }
7779 if (argc >4) {
7780 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
7781 if (*argv[4] == 0 || *endp != 0)
7782 {
7783 test_loop = 1;
7784 }
7785 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
7786 {
7787 test_loop = 100000;
7788 }
7789 }
7790 if (argc >5) {
7791 training_pattern_flag = simple_strtoull_ddr(argv[5], &endp, 16);
7792 if (*argv[5] == 0 || *endp != 0)
7793 {
7794 training_pattern_flag = 0;
7795 }
7796 else if(training_pattern_flag)
7797 training_pattern_flag = 1;
7798
7799
7800 }
7801
7802
7803 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
7804 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
7805 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
7806 printf("\ntest_loop== 0x%08x\n", test_loop);
7807 printf("\training_pattern_flag== 0x%08x\n", training_pattern_flag);
7808 if ( channel_a_en)
7809 {
7810 //writel((0), 0xc8836c00);
7811 OPEN_CHANNEL_A_PHY_CLK();
7812 }
7813 if ( channel_b_en)
7814 {
7815 OPEN_CHANNEL_B_PHY_CLK();
7816 //writel((0), 0xc8836c00);
7817 }
7818
7819
7820 //save and print org training dqs value
7821 if (channel_a_en || channel_b_en)
7822 {
7823
7824
7825 //dcache_disable();
7826 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
7827
7828 {
7829 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
7830 {
7831 if (( channel_a_en) && ( channel_b_en == 0))
7832 {
7833 reg_base_adj=CHANNEL_A_REG_BASE;
7834 }
7835 else if(( channel_b_en)&&( channel_a_en==0))
7836 {
7837 reg_base_adj=CHANNEL_B_REG_BASE;
7838 }
7839 else if ((channel_a_en+channel_b_en)==2)
7840 {
7841 if ( testing_channel == CHANNEL_A)
7842 {
7843 reg_base_adj=CHANNEL_A_REG_BASE;
7844 }
7845 else if( testing_channel==CHANNEL_B)
7846 {
7847 reg_base_adj=CHANNEL_B_REG_BASE;
7848 }
7849 }
7850
7851 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
7852 {
7853
7854 if (temp_count_i == DATX8_DQ_LANE_LANE00)
7855 {
7856 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
7857
7858 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
7859 {
7860 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
7861
7862 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
7863 {
7864 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
7865 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
7866 {
7867 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
7868
7869
7870
7871 for ((temp_count_j=0);(temp_count_j<DATX8_DQ_LCD_BDL_REG_WIDTH);(temp_count_j++))
7872 {
7873 dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=readl(reg_add+4*temp_count_j);
7874 dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
7875 printf("\n org add 0x%08x reg== 0x%08x\n",(reg_add+4*temp_count_j), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]));
7876 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
7877 =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
7878 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
7879 =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
7880
7881 }
7882 }
7883
7884 }
7885
7886 }
7887
7888 }////save and print org training dqs value
7889
7890
7891 for (test_times=0;(test_times<test_loop);(test_times++))
7892 {
7893 ////tune and save training dqs value
7894 if (channel_a_en || channel_b_en)
7895
7896 {
7897 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
7898 {
7899
7900 if (( channel_a_en) && ( channel_b_en == 0))
7901 {
7902 reg_base_adj=CHANNEL_A_REG_BASE;
7903 }
7904 else if(( channel_b_en)&&( channel_a_en==0))
7905 {
7906 reg_base_adj=CHANNEL_B_REG_BASE;
7907 }
7908 else if ((channel_a_en+channel_b_en)==2)
7909 {
7910 if ( testing_channel == CHANNEL_A)
7911 {
7912 reg_base_adj=CHANNEL_A_REG_BASE;
7913 }
7914 else if( testing_channel==CHANNEL_B)
7915 {
7916 reg_base_adj=CHANNEL_B_REG_BASE;
7917 }
7918 }
7919
7920 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
7921 {
7922 { printf("\ntest lane==0x%08x\n ",temp_count_i);
7923
7924 if (temp_count_i == DATX8_DQ_LANE_LANE00)
7925 {
7926 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
7927
7928 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
7929 {
7930 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
7931
7932 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
7933 {
7934 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
7935 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
7936 {
7937 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
7938 }
7939
7940 for ((temp_count_k=0);(temp_count_k<2);(temp_count_k++))
7941 {
7942
7943 if (temp_count_k == 0)
7944 {
7945#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
7946 dq_lcd_bdl_temp_reg_value_dqs=(readl(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0));
7947 dq_lcd_bdl_temp_reg_value_wdqd=(readl(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0))&DQLCDLR_MAX;
7948 dq_lcd_bdl_temp_reg_value_rdqsd=(readl(reg_add+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0BDLR0))&DQLCDLR_MAX;
7949 // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
7950#else
7951 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
7952 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
7953 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
7954 // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
7955#endif
7956
7957 while (dq_lcd_bdl_temp_reg_value_wdqd>0)
7958 {
7959 temp_test_error=0;
7960 dq_lcd_bdl_temp_reg_value_wdqd--;
7961 printf("\nwdqd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
7962 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
7963#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
7964 writel(dq_lcd_bdl_temp_reg_value_wdqd,(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0));
7965#else
7966 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
7967#endif
7968 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
7969 if (temp_test_error)
7970 {
7971 //printf("\nwdqd left edge detect \n");
7972 dq_lcd_bdl_temp_reg_value_wdqd++;
7973 break;
7974 }
7975 }
7976 printf("\nwdqd left edge detect \n");
7977 printf("\nwdqd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
7978 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
7979 //only update dq_lcd_bdl_temp_reg_value_wdqd
7980 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
7981 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
7982 dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
7983
7984
7985 dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
7986 if (dq_lcd_bdl_temp_reg_value_wdqd>(dq_lcd_bdl_temp_reg_lef_min_value&0xff)) //update wdqd min value
7987 {
7988 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
7989 =((dq_lcd_bdl_temp_reg_lef_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
7990 }
7991
7992
7993 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
7994
7995 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
7996 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
7997 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
7998
7999
8000 while (dq_lcd_bdl_temp_reg_value_wdqd<0xff)
8001 {
8002 temp_test_error=0;
8003 dq_lcd_bdl_temp_reg_value_wdqd++;
8004 printf("\nwdqd rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
8005 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8006 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
8007 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
8008 if (temp_test_error)
8009 {
8010 //printf("\nwdqd right edge detect \n");
8011 dq_lcd_bdl_temp_reg_value_wdqd--;
8012 break;
8013 }
8014 }
8015 printf("\nwdqd right edge detect \n");
8016 printf("\nwdqd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
8017 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8018 //only update dq_lcd_bdl_temp_reg_value_wdqd
8019 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8020 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
8021
8022 dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
8023
8024 dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8025 if (dq_lcd_bdl_temp_reg_value_wdqd<(dq_lcd_bdl_temp_reg_rig_min_value&0xff)) //update wdqd min value
8026 {
8027 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
8028 =((dq_lcd_bdl_temp_reg_rig_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
8029 }
8030
8031
8032
8033 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
8034
8035
8036 }
8037 else if(temp_count_k==1)
8038 {
8039
8040 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
8041 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
8042 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
8043
8044 while (dq_lcd_bdl_temp_reg_value_rdqsd>0)
8045 {
8046 temp_test_error=0;
8047 dq_lcd_bdl_temp_reg_value_rdqsd--;
8048 printf("\nrdqsd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
8049 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8050 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
8051 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
8052 if (temp_test_error)
8053 {
8054 //printf("\nrdqsd left edge detect \n");
8055 dq_lcd_bdl_temp_reg_value_rdqsd++;
8056 break;
8057 }
8058 }
8059 printf("\nrdqsd left edge detect \n");
8060 printf("\nrdqsd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
8061 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8062 //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
8063 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8064 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8065
8066 dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
8067
8068
8069 dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8070 if (dq_lcd_bdl_temp_reg_value_rdqsd>((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)) //update wdqd min value
8071 {
8072 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
8073 =((dq_lcd_bdl_temp_reg_lef_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
8074 }
8075
8076
8077 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
8078
8079 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
8080 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
8081 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
8082
8083 while (dq_lcd_bdl_temp_reg_value_rdqsd<0xff)
8084 {
8085 temp_test_error=0;
8086 dq_lcd_bdl_temp_reg_value_rdqsd++;
8087 printf("\nrdqsd right temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
8088 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8089 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
8090 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
8091 if (temp_test_error)
8092 {
8093 //printf("\nrdqsd right edge detect \n");
8094 dq_lcd_bdl_temp_reg_value_rdqsd--;
8095 break;
8096 }
8097 }
8098 printf("\nrdqsd right edge detect \n");
8099 printf("\nrdqsd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
8100 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8101 //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
8102 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8103 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
8104 dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
8105
8106
8107 dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
8108 if (dq_lcd_bdl_temp_reg_value_rdqsd<((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)) //update wdqd min value
8109 {
8110 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
8111 =((dq_lcd_bdl_temp_reg_rig_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
8112 }
8113
8114
8115
8116 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
8117
8118
8119
8120
8121 }
8122
8123 }
8124 }
8125
8126 }
8127 }
8128
8129 ////tune and save training dqs value
8130
8131
8132
8133
8134 ////calculate and print dqs value
8135 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
8136 {
8137 if (( channel_a_en) && ( channel_b_en == 0))
8138 {
8139 reg_base_adj=CHANNEL_A_REG_BASE;
8140 }
8141 else if(( channel_b_en)&&( channel_a_en==0))
8142 {
8143 reg_base_adj=CHANNEL_B_REG_BASE;
8144 }
8145 else if ((channel_a_en+channel_b_en)==2)
8146 {
8147 if ( testing_channel == CHANNEL_A)
8148 {
8149 reg_base_adj=CHANNEL_A_REG_BASE;
8150 }
8151 else if( testing_channel==CHANNEL_B)
8152 {
8153 reg_base_adj=CHANNEL_B_REG_BASE;
8154 }
8155 }
8156 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;
8157
8158
8159 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
8160 {
8161 // dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
8162
8163 printf("\n org add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
8164 }
8165
8166 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
8167 {
8168 printf("\n lef add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
8169 }
8170
8171 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
8172 {
8173 printf("\n rig add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
8174 }
8175
8176 printf("\n ddrtest size ==0x%08x, test times==0x%08x,test_loop==0x%08x\n",ddr_test_size,(test_times+1),test_loop);
8177 printf("\n add 0x00000000 reg== org lef rig center win lef_m rig_m min_c min_win \n");
8178 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
8179 {
8180 {
8181
8182 if (temp_count_i == DATX8_DQ_LANE_LANE00)
8183 {
8184 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
8185
8186 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
8187 {
8188 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
8189
8190 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
8191 {
8192 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
8193 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
8194 {
8195 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
8196 }
8197
8198 dq_lcd_bdl_temp_reg_lef=(dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
8199 dq_lcd_bdl_temp_reg_rig=(dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
8200
8201 if (test_times == 0)
8202 {
8203 (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_lef;
8204 (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_rig;
8205
8206 }
8207 dq_lcd_bdl_temp_reg_lef_min_value=(dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
8208 dq_lcd_bdl_temp_reg_rig_min_value=(dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
8209
8210
8211 //dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value&0x0000ff);
8212 dq_lcd_bdl_temp_reg_center=( (((dq_lcd_bdl_temp_reg_lef&0xff)+(dq_lcd_bdl_temp_reg_rig&0xff))/2)
8213 |(((((dq_lcd_bdl_temp_reg_lef>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<8)
8214 |(((((dq_lcd_bdl_temp_reg_lef>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<16) );
8215
8216 dq_lcd_bdl_temp_reg_windows=( (((dq_lcd_bdl_temp_reg_rig&0xff)-(dq_lcd_bdl_temp_reg_lef&0xff)))
8217 |(((((dq_lcd_bdl_temp_reg_rig>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<8)
8218 |(((((dq_lcd_bdl_temp_reg_rig>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<16) );
8219
8220
8221 dq_lcd_bdl_temp_reg_center_min=( (((dq_lcd_bdl_temp_reg_lef_min_value&0xff)+(dq_lcd_bdl_temp_reg_rig_min_value&0xff))/2)
8222 |(((((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<8)
8223 |(((((dq_lcd_bdl_temp_reg_lef_min_value>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<16) );
8224
8225 dq_lcd_bdl_temp_reg_windows_min=( (((dq_lcd_bdl_temp_reg_rig_min_value&0xff)-(dq_lcd_bdl_temp_reg_lef_min_value&0xff)))
8226 |(((((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<8)
8227 |(((((dq_lcd_bdl_temp_reg_rig_min_value>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<16) );
8228
8229 printf("\n add 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8230 (dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8231 (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8232 (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8233 (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8234 dq_lcd_bdl_temp_reg_center,dq_lcd_bdl_temp_reg_windows,
8235 (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8236 (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
8237 dq_lcd_bdl_temp_reg_center_min,dq_lcd_bdl_temp_reg_windows_min
8238 );
8239 }
8240
8241
8242 }
8243
8244 }
8245
8246
8247
8248
8249 return 0;
8250
8251usage:
8252 cmd_usage(cmdtp);
8253 return 1;
8254
8255}
8256
8257U_BOOT_CMD(
8258 ddr_tune_dqs, 6, 1, do_ddr_test_fine_tune_dqs,
8259 "DDR tune dqs function",
8260 "ddr_tune_dqs a 0 0x80000 3 or ddr_tune_dqs b 0 0x80000 5 or ddr_tune_dqs a b 0x80000 l\n dcache off ? \n"
8261);
8262
8263
8264
8265int do_ddr_test_dqs_window_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8266{
8267 printf("\nEnter test ddr dqs window step function\n");
8268 // if(!argc)
8269 // goto DDR_TUNE_DQS_START;
8270 printf("\nargc== 0x%08x\n", argc);
8271
8272 unsigned int temp_test_error= 0;
8273
8274
8275 char *endp;
8276 // unsigned int *p_start_addr;
8277 unsigned int test_lane_step=0;
8278 unsigned int testing_lane=0;
8279 unsigned int test_lane_step_rdqs_flag=0;
8280 unsigned int test_min_max_flag=0;
8281 unsigned int test_times=1;
8282 unsigned int reg_add=0;
8283 unsigned int reg_base_adj=0;
8284 unsigned int channel_a_en = 0;
8285 unsigned int channel_b_en = 0;
8286
8287
8288 unsigned int dq_lcd_bdl_reg_org=0;
8289 unsigned int dq_lcd_bdl_reg_left=0;
8290 unsigned int dq_lcd_bdl_reg_right=0;
8291
8292
8293 unsigned int dq_lcd_bdl_reg_left_min=0;
8294 unsigned int dq_lcd_bdl_reg_right_min=0;
8295
8296 unsigned int dq_lcd_bdl_temp_reg_value=0;
8297
8298
8299 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
8300 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
8301
8302
8303 // unsigned int dq_lcd_bdl_temp_reg_lef;
8304 // unsigned int dq_lcd_bdl_temp_reg_rig;
8305
8306
8307 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
8308
8309
8310
8311 if (argc == 2)
8312 {
8313 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
8314
8315 {channel_a_en = 1;
8316 }
8317 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
8318
8319 {channel_b_en = 1;
8320 }
8321 else
8322 {
8323 goto usage;
8324 }
8325 }
8326 if (argc > 2)
8327 {
8328 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
8329
8330 {channel_a_en = 1;
8331 }
8332 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
8333
8334 {channel_b_en = 1;
8335 }
8336 }
8337 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
8338 if (argc >3) {
8339 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
8340 if (*argv[3] == 0 || *endp != 0)
8341 {
8342 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
8343 }
8344
8345 }
8346 if (argc >4) {
8347 test_lane_step = 0;
8348 test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
8349 if (*argv[4] == 0 || *endp != 0)
8350 {
8351 test_lane_step = 0;
8352 }
8353 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
8354 {
8355 test_lane_step = 0;
8356 }
8357 }
8358 if (test_lane_step >7)
8359 test_lane_step = 0;
8360 unsigned int test_loop=1;
8361 if (argc >5) {
8362
8363 test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
8364 if (*argv[5] == 0 || *endp != 0)
8365 {
8366 test_min_max_flag = 0;
8367 }
8368 else
8369 {
8370 //test_min_max_flag =1;
8371 }
8372 }
8373 unsigned int test_temp_value_use_sticky_register=0;
8374 if (argc >6) {
8375
8376 test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
8377 if (*argv[6] == 0 || *endp != 0)
8378 {
8379 test_temp_value_use_sticky_register = 0;
8380 }
8381 else
8382 {
8383 //test_min_max_flag =1;
8384 }
8385 }
8386 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
8387
8388 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
8389 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
8390 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
8391 printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
8392 printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
8393 printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
8394
8395 const char *temp_s;
8396 char *env_lcdlr_temp_count;
8397 char *buf;
8398 buf="";
8399 unsigned int lcdlr_temp_count=0;
8400 env_lcdlr_temp_count="lcdlr_temp_count";
8401
8402 if (test_temp_value_use_sticky_register)
8403 {lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
8404 }
8405 else
8406 {
8407
8408 temp_s= env_get(env_lcdlr_temp_count);
8409 if (temp_s)
8410 {
8411 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
8412 }
8413 else
8414 {lcdlr_temp_count=0;
8415 }
8416 }
8417
8418 if ( channel_a_en)
8419 {
8420 //writel((0), 0xc8836c00);
8421 OPEN_CHANNEL_A_PHY_CLK();
8422 }
8423 if ( channel_b_en)
8424 {
8425 OPEN_CHANNEL_B_PHY_CLK();
8426 //writel((0), 0xc8836c00);
8427 }
8428
8429
8430
8431 //save and print org training dqs value
8432 if (channel_a_en || channel_b_en)
8433 {
8434 //dcache_disable();
8435 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
8436
8437 }////save and print org training dqs value
8438
8439
8440 for (test_times=0;(test_times<test_loop);(test_times++))
8441 {
8442 ////tune and save training dqs value
8443 if (channel_a_en || channel_b_en)
8444
8445 {
8446
8447 {
8448
8449 if (( channel_a_en) && ( channel_b_en == 0))
8450 {
8451 reg_base_adj=CHANNEL_A_REG_BASE;
8452 }
8453 else if(( channel_b_en)&&( channel_a_en==0))
8454 {
8455 reg_base_adj=CHANNEL_B_REG_BASE;
8456 }
8457 else if ((channel_a_en+channel_b_en)==2)
8458 {
8459 reg_base_adj=CHANNEL_A_REG_BASE;
8460 }
8461
8462
8463
8464 {
8465 printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR0_PUB_REG_BASE+4));
8466 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
8467 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
8468 if ( channel_b_en)
8469 { printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR1_PUB_REG_BASE+4));
8470 writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
8471 printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
8472 }
8473 if (test_lane_step>8)
8474 test_lane_step=0;
8475 printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
8476
8477 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_lane_step>>1);
8478 test_lane_step_rdqs_flag=test_lane_step%2;
8479 testing_lane=(test_lane_step>>1);
8480 if (!test_lane_step_rdqs_flag)
8481 {reg_add=reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0;
8482 }
8483 else
8484 {
8485#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8486 reg_add=reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0;
8487#else
8488 reg_add=reg_add+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0BDLR0;
8489#endif
8490
8491 }
8492
8493 dq_lcd_bdl_temp_reg_value=readl(reg_add);
8494 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8495 printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
8496#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8497 if (test_lane_step_rdqs_flag)
8498 {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0xff00)>>8);
8499 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8500 }
8501 else
8502 {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0x00ff)>>0);
8503 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8504 }
8505#endif
8506
8507 if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
8508 {
8509 while (dq_lcd_bdl_temp_reg_value>0)
8510 {
8511 ddr_test_watchdog_clear();
8512 temp_test_error=0;
8513 dq_lcd_bdl_temp_reg_value--;
8514
8515 {
8516 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
8517 sprintf(buf, "0x%08x", lcdlr_temp_count);
8518 printf( "%s\n", buf);
8519 if (test_temp_value_use_sticky_register)
8520 {
8521 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
8522 }
8523 else
8524 {
8525 env_set(env_lcdlr_temp_count, buf);
8526 run_command("save",0);
8527 }
8528 }
8529
8530
8531
8532 printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
8533 if (!test_lane_step_rdqs_flag)
8534 {
8535#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8536 writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
8537#else
8538 writel(dq_lcd_bdl_temp_reg_value,reg_add);
8539#endif
8540 }
8541 else
8542 {
8543#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8544 writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
8545#else
8546 writel(dq_lcd_bdl_temp_reg_value,reg_add);
8547 writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8548#endif
8549 }
8550 printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
8551 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
8552
8553 if (temp_test_error)
8554 {
8555 //printf("\nwdqd left edge detect \n");
8556 dq_lcd_bdl_temp_reg_value++;
8557 break;
8558 }
8559 }
8560 printf("\n left edge detect \n");
8561 printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
8562
8563
8564 dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
8565 if (test_times == 0)
8566 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
8567 if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
8568 {
8569 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
8570 }
8571 } else
8572 {
8573 printf("\n left edge skip \n");
8574 }
8575
8576 if (!test_lane_step_rdqs_flag)
8577 {
8578#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8579 writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
8580#else
8581 writel(dq_lcd_bdl_reg_org,reg_add);
8582#endif
8583 // writel(dq_lcd_bdl_reg_org,reg_add);
8584 }
8585 else
8586 {
8587#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8588 writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
8589#else
8590 writel(dq_lcd_bdl_reg_org,reg_add);
8591 writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8592#endif
8593 // writel(dq_lcd_bdl_reg_org,reg_add);
8594 // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8595 }
8596
8597 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
8598
8599 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
8600
8601
8602 if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
8603 {
8604 while (dq_lcd_bdl_temp_reg_value<DQLCDLR_MAX)
8605 {
8606 ddr_test_watchdog_clear();
8607 temp_test_error=0;
8608 dq_lcd_bdl_temp_reg_value++;
8609
8610
8611 {
8612 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
8613 sprintf(buf, "0x%08x", lcdlr_temp_count);
8614 printf( "%s\n", buf);
8615 if (test_temp_value_use_sticky_register)
8616 {
8617 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
8618 }
8619 else
8620 {
8621 env_set(env_lcdlr_temp_count, buf);
8622 run_command("save",0);
8623 }
8624 }
8625
8626 printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
8627 if (!test_lane_step_rdqs_flag)
8628 {
8629 //writel(dq_lcd_bdl_temp_reg_value,reg_add);
8630#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8631 writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
8632#else
8633 writel(dq_lcd_bdl_temp_reg_value,reg_add);
8634#endif
8635 }
8636 else
8637 {
8638#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8639 writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
8640#else
8641 writel(dq_lcd_bdl_temp_reg_value,reg_add);
8642 writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8643#endif
8644 // writel(dq_lcd_bdl_temp_reg_value,reg_add);
8645 // writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8646 }
8647 printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
8648 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
8649 if (temp_test_error)
8650 {
8651 //printf("\nwdqd right edge detect \n");
8652 dq_lcd_bdl_temp_reg_value--;
8653 break;
8654 }
8655 }
8656 printf("\n right edge detect \n");
8657 printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
8658
8659 dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
8660 if (test_times == 0)
8661 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
8662 if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
8663 {
8664 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
8665 }
8666 }
8667
8668 if (!test_lane_step_rdqs_flag)
8669 {
8670 // writel(dq_lcd_bdl_reg_org,reg_add);
8671#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8672 writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
8673#else
8674 writel(dq_lcd_bdl_reg_org,reg_add);
8675#endif
8676 }
8677 else
8678 {
8679#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
8680 writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
8681#else
8682 writel(dq_lcd_bdl_reg_org,reg_add);
8683 writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8684#endif
8685 // writel(dq_lcd_bdl_reg_org,reg_add);
8686 // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
8687 }
8688
8689 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
8690 printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
8691 writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
8692 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
8693 }
8694
8695
8696
8697 }
8698 }
8699
8700 }
8701
8702 dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
8703 if (!test_lane_step_rdqs_flag)
8704 {if(channel_a_en){
8705 dq_lcd_bdl_value_wdq_org_a[testing_lane]=dq_lcd_bdl_reg_org;
8706 if (test_min_max_flag != 1)
8707 dq_lcd_bdl_value_wdq_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
8708 if (test_min_max_flag != 2)
8709 dq_lcd_bdl_value_wdq_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
8710 }
8711 if (channel_b_en)
8712 {
8713 dq_lcd_bdl_value_wdq_org_b[testing_lane]=dq_lcd_bdl_reg_org;
8714 if (test_min_max_flag != 1)
8715 dq_lcd_bdl_value_wdq_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
8716 if (test_min_max_flag != 2)
8717 dq_lcd_bdl_value_wdq_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
8718 }
8719 }
8720 else
8721 {
8722 if (channel_a_en) {
8723 dq_lcd_bdl_value_rdqs_org_a[testing_lane]=dq_lcd_bdl_reg_org;
8724 if (test_min_max_flag != 1)
8725 dq_lcd_bdl_value_rdqs_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
8726 if (test_min_max_flag != 2)
8727 dq_lcd_bdl_value_rdqs_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
8728 }
8729 if (channel_b_en) {
8730 dq_lcd_bdl_value_rdqs_org_b[testing_lane]=dq_lcd_bdl_reg_org;
8731 if (test_min_max_flag != 1)
8732 dq_lcd_bdl_value_rdqs_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
8733 if (test_min_max_flag != 2)
8734 dq_lcd_bdl_value_rdqs_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
8735 }
8736 }
8737
8738 return dq_lcd_bdl_temp_reg_value;
8739
8740usage:
8741 cmd_usage(cmdtp);
8742 return 1;
8743
8744}
8745
8746///*
8747U_BOOT_CMD(
8748 ddr_tune_dqs_step, 7, 1, do_ddr_test_dqs_window_step,
8749 "ddr_tune_dqs_step function",
8750 "ddr_tune_dqs_step a 0 0x80000 3 or ddr_tune_dqs_step b 0 0x80000 5 \n dcache off ? \n"
8751);
8752
8753
8754
8755extern int ddr_test_s_add_cross_talk_pattern(int ddr_test_size);
8756
8757
8758int do_ddr_test_lcdlr_clk_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8759{
8760 printf("\nEnter test ddr lcdlr clk step function\n");
8761 // if(!argc)
8762 // goto DDR_TUNE_DQS_START;
8763 printf("\nargc== 0x%08x\n", argc);
8764
8765 unsigned int temp_test_error= 0;
8766
8767
8768 char *endp;
8769 // unsigned int *p_start_addr;
8770 unsigned int test_lane_step=0;
8771 // unsigned int testing_lane=0;
8772 // unsigned int test_lane_step_rdqs_flag=0;
8773 unsigned int test_min_max_flag=0;
8774 unsigned int test_times=1;
8775 unsigned int reg_add=0;
8776 unsigned int reg_base_adj=0;
8777 unsigned int channel_a_en = 0;
8778 unsigned int channel_b_en = 0;
8779
8780
8781 unsigned int dq_lcd_bdl_reg_org=0;
8782 unsigned int dq_lcd_bdl_reg_left=0;
8783 unsigned int dq_lcd_bdl_reg_right=0;
8784
8785
8786 unsigned int dq_lcd_bdl_reg_left_min=0;
8787 unsigned int dq_lcd_bdl_reg_right_min=0;
8788
8789 unsigned int dq_lcd_bdl_temp_reg_value=0;
8790
8791
8792 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
8793 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
8794
8795
8796 // unsigned int dq_lcd_bdl_temp_reg_lef;
8797 // unsigned int dq_lcd_bdl_temp_reg_rig;
8798
8799
8800 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
8801
8802
8803
8804 if (argc == 2)
8805 {
8806 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
8807
8808 {channel_a_en = 1;
8809 }
8810 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
8811
8812 {channel_b_en = 1;
8813 }
8814 else
8815 {
8816 goto usage;
8817 }
8818 }
8819 if (argc > 2)
8820 {
8821 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
8822
8823 {channel_a_en = 1;
8824 }
8825 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
8826
8827 {channel_b_en = 1;
8828 }
8829 }
8830 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
8831 if (argc >3) {
8832 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
8833 if (*argv[3] == 0 || *endp != 0)
8834 {
8835 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
8836 }
8837
8838 }
8839 if (argc >4) {
8840 test_lane_step = 0;
8841 test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
8842 if (*argv[4] == 0 || *endp != 0)
8843 {
8844 test_lane_step = 0;
8845 }
8846 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
8847 {
8848 test_lane_step = 0;
8849 }
8850 }
8851 if (test_lane_step >7)
8852 test_lane_step = 0;
8853 unsigned int test_loop=1;
8854 if (argc >5) {
8855
8856 test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
8857 if (*argv[5] == 0 || *endp != 0)
8858 {
8859 test_min_max_flag = 0;
8860 }
8861 else
8862 {
8863 //test_min_max_flag =1;
8864 }
8865 }
8866 unsigned int test_temp_value_use_sticky_register=0;
8867 if (argc >6) {
8868
8869 test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
8870 if (*argv[6] == 0 || *endp != 0)
8871 {
8872 test_temp_value_use_sticky_register = 0;
8873 }
8874 else
8875 {
8876 //test_min_max_flag =1;
8877 }
8878 }
8879 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
8880 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
8881 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
8882 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
8883 printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
8884 printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
8885 printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
8886 const char *temp_s;
8887 char *env_lcdlr_temp_count;
8888 char *buf;
8889 buf="";
8890 unsigned int lcdlr_temp_count=0;
8891 env_lcdlr_temp_count="lcdlr_temp_count_a";
8892 unsigned int lcdlr_max=0;
8893 if (test_temp_value_use_sticky_register)
8894 {lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
8895 }
8896 else
8897 {
8898
8899 temp_s= env_get(env_lcdlr_temp_count);
8900 if (temp_s)
8901 {
8902 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
8903 }
8904 else
8905 {lcdlr_temp_count=0;
8906 }
8907 }
8908
8909 if ( channel_a_en)
8910 {
8911 //writel((0), 0xc8836c00);
8912 OPEN_CHANNEL_A_PHY_CLK();
8913 }
8914 if ( channel_b_en)
8915 {
8916 OPEN_CHANNEL_B_PHY_CLK();
8917 //writel((0), 0xc8836c00);
8918 }
8919
8920
8921
8922 //save and print org training dqs value
8923 if (channel_a_en || channel_b_en)
8924 {
8925 //dcache_disable();
8926 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
8927
8928 }////save and print org training dqs value
8929
8930
8931 for (test_times=0;(test_times<test_loop);(test_times++))
8932 {
8933 ////tune and save training dqs value
8934 if (channel_a_en || channel_b_en)
8935
8936 {
8937
8938 {
8939
8940 if (( channel_a_en) && ( channel_b_en == 0))
8941 {
8942 reg_base_adj=CHANNEL_A_REG_BASE;
8943 }
8944 else if(( channel_b_en)&&( channel_a_en==0))
8945 {
8946 reg_base_adj=CHANNEL_B_REG_BASE;
8947 }
8948 else if ((channel_a_en+channel_b_en)==2)
8949 {
8950 reg_base_adj=CHANNEL_A_REG_BASE;
8951 }
8952
8953
8954
8955 {
8956 printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR0_PUB_REG_BASE+4));
8957 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
8958 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
8959 if ( channel_b_en)
8960 { printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR1_PUB_REG_BASE+4));
8961 writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
8962 printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
8963 }
8964 if (test_lane_step>2)
8965 test_lane_step=0;
8966 printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
8967 if (test_lane_step == 0)
8968 {reg_add=DDR0_PUB_ACLCDLR+reg_base_adj;
8969 lcdlr_max=ACLCDLR_MAX;
8970 }
8971 if (test_lane_step == 1)
8972 {reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
8973 lcdlr_max=ACBDLR_MAX;
8974 }
8975
8976
8977 dq_lcd_bdl_temp_reg_value=readl(reg_add);
8978 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8979 printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
8980
8981 if (test_lane_step == 0)
8982 {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACLCDLR_MAX));
8983 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8984 }
8985 if (test_lane_step == 1)
8986 {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACBDLR_MAX));
8987 dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
8988 }
8989
8990
8991 if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
8992 {
8993 while (dq_lcd_bdl_temp_reg_value>0)
8994 {
8995 ddr_test_watchdog_clear();
8996 temp_test_error=0;
8997 dq_lcd_bdl_temp_reg_value--;
8998
8999 {
9000 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
9001 sprintf(buf, "0x%08x", lcdlr_temp_count);
9002 printf( "%s\n", buf);
9003 if (test_temp_value_use_sticky_register)
9004 {
9005 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
9006 }
9007 else
9008 {
9009 env_set(env_lcdlr_temp_count, buf);
9010 run_command("save",0);
9011 }
9012
9013 }
9014
9015
9016
9017 printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
9018
9019 {
9020 writel(dq_lcd_bdl_temp_reg_value,reg_add);
9021 }
9022
9023 printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
9024 //temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9025 //#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
9026 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
9027 // #else
9028 // temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
9029 // temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
9030 // #endif
9031
9032
9033 if (temp_test_error)
9034 {
9035 //printf("\nwdqd left edge detect \n");
9036 dq_lcd_bdl_temp_reg_value++;
9037 break;
9038 }
9039 }
9040 printf("\n left edge detect \n");
9041 printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
9042
9043
9044 dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
9045 if (test_times == 0)
9046 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
9047 if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
9048 {
9049 dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
9050 }
9051 }
9052 else
9053 {
9054 printf("\n left edge skip \n");
9055 }
9056
9057
9058 {
9059
9060 writel(dq_lcd_bdl_reg_org,reg_add);
9061
9062 }
9063
9064 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
9065
9066 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
9067
9068
9069 if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
9070 {
9071 //if(test_lane_step==0)
9072 while (dq_lcd_bdl_temp_reg_value<lcdlr_max)
9073 {
9074 ddr_test_watchdog_clear();
9075 temp_test_error=0;
9076 dq_lcd_bdl_temp_reg_value++;
9077 {
9078 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
9079 sprintf(buf, "0x%08x", lcdlr_temp_count);
9080 printf( "%s\n", buf);
9081 if (test_temp_value_use_sticky_register)
9082 {
9083 writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
9084 }
9085 else
9086 {
9087 env_set(env_lcdlr_temp_count, buf);
9088 run_command("save",0);
9089 }
9090 }
9091
9092 printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
9093 {
9094 writel(dq_lcd_bdl_temp_reg_value,reg_add);
9095 }
9096
9097 printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
9098 // temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9099 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
9100 if (temp_test_error)
9101 {
9102 //printf("\nwdqd right edge detect \n");
9103 dq_lcd_bdl_temp_reg_value--;
9104 break;
9105 }
9106 }
9107 printf("\n right edge detect \n");
9108 printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
9109
9110 dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
9111 if (test_times == 0)
9112 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
9113 if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
9114 {
9115 dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
9116 }
9117 }
9118
9119 {
9120 writel(dq_lcd_bdl_reg_org,reg_add);
9121 }
9122
9123 printf("\n read reg==0x%08x\n ",(readl(reg_add)));
9124 printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
9125 writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
9126 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
9127 }
9128
9129
9130
9131 }
9132 }
9133
9134 }
9135
9136 dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
9137
9138 {if(channel_a_en){
9139 if (test_lane_step == 0)
9140 {
9141 dq_lcd_bdl_value_aclcdlr_org_a=dq_lcd_bdl_reg_org;
9142 if (test_min_max_flag != 1)
9143 dq_lcd_bdl_value_aclcdlr_min_a=dq_lcd_bdl_reg_left_min;
9144 if (test_min_max_flag != 2)
9145 dq_lcd_bdl_value_aclcdlr_max_a=dq_lcd_bdl_reg_right_min;
9146 }
9147 if (test_lane_step == 1)
9148 {
9149 dq_lcd_bdl_value_bdlr0_org_a=dq_lcd_bdl_reg_org;
9150 if (test_min_max_flag != 1)
9151 dq_lcd_bdl_value_bdlr0_min_a=dq_lcd_bdl_reg_left_min;
9152 if (test_min_max_flag != 2)
9153 dq_lcd_bdl_value_bdlr0_max_a=dq_lcd_bdl_reg_right_min;
9154 }
9155 }
9156 if (channel_b_en)
9157 {
9158 if (test_lane_step == 0)
9159 {
9160 dq_lcd_bdl_value_aclcdlr_org_b=dq_lcd_bdl_reg_org;
9161 if (test_min_max_flag != 1)
9162 dq_lcd_bdl_value_aclcdlr_min_b=dq_lcd_bdl_reg_left_min;
9163 if (test_min_max_flag != 2)
9164 dq_lcd_bdl_value_aclcdlr_max_b=dq_lcd_bdl_reg_right_min;
9165 }
9166 if (test_lane_step == 1)
9167 {
9168 dq_lcd_bdl_value_bdlr0_org_b=dq_lcd_bdl_reg_org;
9169 if (test_min_max_flag != 1)
9170 dq_lcd_bdl_value_bdlr0_min_b=dq_lcd_bdl_reg_left_min;
9171 if (test_min_max_flag != 2)
9172 dq_lcd_bdl_value_bdlr0_max_b=dq_lcd_bdl_reg_right_min;
9173 }
9174 }
9175 }
9176
9177
9178
9179 return dq_lcd_bdl_temp_reg_value;
9180
9181usage:
9182 cmd_usage(cmdtp);
9183 return 1;
9184
9185}
9186
9187U_BOOT_CMD(
9188 ddr_tune_aclcdlr_step, 7, 1, do_ddr_test_lcdlr_clk_step,
9189 "ddr_tune_aclcdlr_step function",
9190 "ddr_tune_aclcdlr_step a 0 0x80000 3 or ddr_tune_aclcdlr_step b 0 0x80000 5 \n dcache off ? \n"
9191);
9192
9193int do_ddr_test_dqs_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
9194{
9195 printf("\nEnterddr_test_dqs_window function\n");
9196 unsigned int channel_a_en = 0;
9197 unsigned int channel_b_en = 0;
9198 // unsigned int reg_add=0;
9199 // unsigned int reg_base_adj=0;
9200
9201 unsigned int lane_step= 0;
9202 unsigned int reg_value= 0;
9203 //int argc2;
9204 //char * argv2[30];
9205 char *endp;
9206
9207 if (argc == 2)
9208 {
9209 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
9210
9211 {channel_a_en = 1;
9212 }
9213 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
9214
9215 {channel_b_en = 1;
9216 }
9217
9218
9219 }
9220 if (argc > 2)
9221 {
9222 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
9223
9224 {channel_a_en = 1;
9225 }
9226 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
9227
9228 {channel_b_en = 1;
9229 }
9230 }
9231 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
9232 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
9233 if (argc >3) {
9234 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
9235 if (*argv[3] == 0 || *endp != 0)
9236 {
9237 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
9238 }
9239 }
9240 //argc2=5;
9241 //for(i = 1;i<(argc);i++)
9242 {
9243 //argv2[i-1]=argv[i];
9244 }
9245
9246 //argv2[0]=argv[1];
9247 //argv2[1]=argv[2];
9248 //argv2[2]=argv[3];
9249 //#include <stdio.h>
9250 // unsigned int wr_adj_per[24] ;
9251 if (1)
9252 {
9253 printf("\ntest use uboot env\n");
9254 {
9255 //char str[24];
9256 const char *s;
9257 unsigned int str_to_numarry[48];
9258 //str_buf = (char *)malloc(sizeof(char)*1024);
9259
9260 unsigned int *num_arry;
9261 num_arry = (unsigned int *)(&str_to_numarry);
9262 int i;
9263 // char *varname;
9264 // int value=0;
9265
9266 ///varname="env_ddrtest";
9267 s = env_get("env_wr_lcdlr_pr");
9268 if (s)
9269 {//i=0;
9270 //while(s_temp)
9271 {
9272 env_to_num("env_wr_lcdlr_pr",num_arry);//unsigned int *num_arry
9273
9274
9275 for (i = 0; i < 48; i++) {
9276
9277 printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
9278 }
9279 // printf("%s,length=%d",s,(strlen(s)));
9280 //sscanf(s,"d%,",wr_adj_per);
9281 //sprintf(str,"d%",s);
9282 //getc
9283 // if (strlen(s) > 16)
9284 {
9285 // sscanf(s, "%08x, %08x, %08x, \n",
9286 // &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
9287 }
9288 }
9289 }
9290 }
9291 }
9292 // unsigned int = 0, max = 0xff, min = 0x00;
9293 /*
9294 if (0)
9295 {
9296 {printf("\ntest use uboot env\n");
9297 {
9298 //char str[24];
9299 const char *s;
9300
9301 // char *varname;
9302 int value=0;
9303
9304 ///varname="env_ddrtest";
9305 s = env_get("env_wr_lcdlr_pr");
9306 if (s)
9307 {//i=0;
9308 //while(s_temp)
9309 {
9310 printf("%s",s);
9311 //sscanf(s,"d%,",wr_adj_per);
9312 //sprintf(str,"d%",s);
9313 //getc
9314 if (strlen(s) > 16) {
9315 sscanf(s, "%08x, %08x, %08x, %08x, %08x\n",
9316 &wr_adj_per[i-2], &max, &min, &type_h, &type_l);
9317 } else {
9318 sscanf(buf, "%08x, %08x, %08x\n",
9319 &reg, &max, &min);
9320 }
9321
9322 }
9323 value = simple_strtoull_ddr(s, &endp, 16);
9324 printf("%d",value);
9325 }
9326 s = env_get("env_rd_lcdlr_pr");
9327
9328 if (s)
9329 {//i=0;
9330 //while(s_temp)
9331 {
9332 printf("%s",s);
9333 //sscanf(s,"d%,",rd_adj_per);
9334
9335 }
9336 //value = simple_strtoull_ddr(s, &endp, 16);
9337 }
9338
9339 //sprintf(str, "%lx", value);
9340 // env_set("env_ddrtest", str);
9341
9342
9343 //run_command("save",0);
9344 }
9345
9346 if (argc>24+2)
9347 argc=24+2;
9348 for (i = 2;i<argc;i++)
9349 {
9350 if (i<(2+12)) {
9351 wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
9352 }
9353 else
9354 {
9355 rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
9356 }
9357 }
9358
9359
9360 }
9361 printf(" int wr_adj_per[12]={\n");
9362 for (i = 0;i<12;i++)
9363 {
9364 printf("%04d ,\n",wr_adj_per[i]);
9365}
9366printf("};\n");
9367printf(" int rd_adj_per[12]={\n");
9368for (i = 0;i<12;i++)
9369{
9370 printf("%04d ,\n",rd_adj_per[i]);
9371}
9372printf("};\n");
9373
9374}
9375*/
9376
9377char str[100];
9378
9379if (channel_a_en)
9380{
9381
9382 //*(char *)(argv2[0])="a";
9383 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
9384 printf("\ntest dqs window lane a\n");
9385 for ((lane_step=0);(lane_step<8);(lane_step++))
9386 {
9387 //sprintf(argv2[3],"d%",( lane_step));
9388 //itoa_ddr_test(lane_step,(argv2[3]),10);
9389 //printf("\nargv2[%d]=%s\n",0,argv2[0]);
9390 // printf("\nargv2[%d]=%s\n",3,argv2[3]);
9391 // reg_value=do_ddr_test_dqs_window_step((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
9392 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d",ddr_test_size,( lane_step));
9393 printf("\nstr=%s\n",str);
9394 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
9395 //printf("\nstr=%s\n",str);
9396 run_command(str,0);
9397
9398 }
9399}
9400
9401
9402if (channel_b_en)
9403{//*(char *)(argv2[0])="b";
9404 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
9405 printf("\ntest dqs window lane b\n");
9406 for ((lane_step=0);(lane_step<8);(lane_step++))
9407 {
9408 //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
9409 //printf("\nstr=%s\n",str);
9410 sprintf(str,"ddr_tune_dqs_step b 0 0x%08x %d",ddr_test_size,( lane_step));
9411 printf("\nstr=%s\n",str);
9412 run_command(str,0);
9413
9414 }
9415}
9416
9417if (channel_a_en)
9418{
9419 for ((lane_step=0);(lane_step<4);(lane_step++))
9420 {
9421 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
9422 lane_step,
9423 dq_lcd_bdl_value_wdq_org_a[lane_step],
9424 dq_lcd_bdl_value_wdq_min_a[lane_step],dq_lcd_bdl_value_wdq_max_a[lane_step],
9425 dq_lcd_bdl_value_rdqs_org_a[lane_step],
9426 dq_lcd_bdl_value_rdqs_min_a[lane_step],dq_lcd_bdl_value_rdqs_max_a[lane_step]);
9427 }}
9428if (channel_b_en)
9429{
9430 for ((lane_step=0);(lane_step<4);(lane_step++))
9431 {
9432 printf("\n b_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
9433 lane_step,
9434 dq_lcd_bdl_value_wdq_org_b[lane_step],
9435 dq_lcd_bdl_value_wdq_min_b[lane_step],dq_lcd_bdl_value_wdq_max_b[lane_step],
9436 dq_lcd_bdl_value_rdqs_org_b[lane_step],
9437 dq_lcd_bdl_value_rdqs_min_b[lane_step],dq_lcd_bdl_value_rdqs_max_b[lane_step]);
9438 }}
9439
9440return reg_value;
9441}
9442
9443/*
9444U_BOOT_CMD(
9445 ddr_tune_dqs_step, 5, 1, do_ddr_test_fine_tune_dqs_step,
9446 "ddr_tune_dqs_step function",
9447 "ddr_tune_dqs_step a 0 0x800000 3 or ddr_tune_dqs_step b 0 0x800000 5 or ddr_tune_dqs_step a b 0x800000 l\n dcache off ? \n"
9448);
9449*/
9450
9451int do_ddr_test_fine_tune_dqs_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
9452{
9453 printf("\nEnter Tune ddr dqs step function\n");
9454 // if(!argc)
9455 // goto DDR_TUNE_DQS_START;
9456 printf("\nargc== 0x%08x\n", argc);
9457 // unsigned int loop = 1;
9458 unsigned int temp_count_i = 1;
9459 unsigned int temp_count_j= 1;
9460 unsigned int temp_count_k= 1;
9461 unsigned int temp_test_error= 0;
9462
9463
9464 char *endp;
9465 // unsigned int *p_start_addr;
9466 unsigned int test_lane_step=0;
9467 unsigned int test_lane_step_rdqs_flag=0;
9468 unsigned int test_loop=1;
9469 unsigned int test_times=1;
9470 unsigned int reg_add=0;
9471 unsigned int reg_base_adj=0;
9472 unsigned int channel_a_en = 0;
9473 unsigned int channel_b_en = 0;
9474 unsigned int testing_channel = 0;
9475
9476#define DATX8_DQ_LCD_BDL_REG_WIDTH 12
9477
9478#define DATX8_DQ_LANE_WIDTH 4
9479#define CHANNEL_CHANNEL_WIDTH 2
9480
9481#define CHANNEL_A 0
9482#define CHANNEL_B 1
9483
9484
9485
9486#define DATX8_DQ_LANE_LANE00 0
9487#define DATX8_DQ_LANE_LANE01 1
9488#define DATX8_DQ_LANE_LANE02 2
9489#define DATX8_DQ_LANE_LANE03 3
9490
9491#define DATX8_DQ_BDLR0 0
9492#define DATX8_DQ_BDLR1 1
9493#define DATX8_DQ_BDLR2 2
9494#define DATX8_DQ_BDLR3 3
9495#define DATX8_DQ_BDLR4 4
9496#define DATX8_DQ_BDLR5 5
9497#define DATX8_DQ_BDLR6 6
9498#define DATX8_DQ_DXNLCDLR0 7
9499#define DATX8_DQ_DXNLCDLR1 8
9500#define DATX8_DQ_DXNLCDLR2 9
9501#define DATX8_DQ_DXNMDLR 10
9502#define DATX8_DQ_DXNGTR 11
9503
9504
9505#define DDR_CROSS_TALK_TEST_SIZE 0x20000
9506
9507#define DQ_LCD_BDL_REG_NUM_PER_CHANNEL DATX8_DQ_LCD_BDL_REG_WIDTH*DATX8_DQ_LANE_WIDTH
9508#define DQ_LCD_BDL_REG_NUM DQ_LCD_BDL_REG_NUM_PER_CHANNEL*CHANNEL_CHANNEL_WIDTH
9509
9510 unsigned int dq_lcd_bdl_reg_org[DQ_LCD_BDL_REG_NUM];
9511 unsigned int dq_lcd_bdl_reg_left[DQ_LCD_BDL_REG_NUM];
9512 unsigned int dq_lcd_bdl_reg_right[DQ_LCD_BDL_REG_NUM];
9513 unsigned int dq_lcd_bdl_reg_index[DQ_LCD_BDL_REG_NUM];
9514
9515 unsigned int dq_lcd_bdl_reg_left_min[DQ_LCD_BDL_REG_NUM];
9516 unsigned int dq_lcd_bdl_reg_right_min[DQ_LCD_BDL_REG_NUM];
9517
9518 unsigned int dq_lcd_bdl_temp_reg_value;
9519 unsigned int dq_lcd_bdl_temp_reg_value_dqs;
9520 unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
9521 unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
9522 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsnd;
9523 unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
9524 unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
9525 // unsigned int dq_lcd_bdl_temp_reg_value_dqs;
9526 // unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
9527 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
9528
9529 unsigned int dq_lcd_bdl_temp_reg_lef;
9530 unsigned int dq_lcd_bdl_temp_reg_rig;
9531 unsigned int dq_lcd_bdl_temp_reg_center;
9532 unsigned int dq_lcd_bdl_temp_reg_windows;
9533 unsigned int dq_lcd_bdl_temp_reg_center_min;
9534 unsigned int dq_lcd_bdl_temp_reg_windows_min;
9535
9536 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
9537
9538
9539
9540 if (argc == 2)
9541 {
9542 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
9543
9544 {channel_a_en = 1;
9545 }
9546 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
9547
9548 {channel_b_en = 1;
9549 }
9550 else
9551 {
9552 goto usage;
9553 }
9554 }
9555 if (argc > 2)
9556 {
9557 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
9558
9559 {channel_a_en = 1;
9560 }
9561 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
9562
9563 {channel_b_en = 1;
9564 }
9565 }
9566 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
9567 if (argc >3) {
9568 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
9569 if (*argv[3] == 0 || *endp != 0)
9570 {
9571 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
9572 }
9573
9574 }
9575 if (argc >4) {
9576 test_lane_step = 0;
9577 test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
9578 if (*argv[4] == 0 || *endp != 0)
9579 {
9580 test_lane_step = 0;
9581 }
9582 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
9583 {
9584 test_lane_step = 0;
9585 }
9586 }
9587 test_loop=1;
9588
9589 unsigned int test_min_max=0;
9590 if (argc >5) {
9591
9592 test_min_max = simple_strtoull_ddr(argv[5], &endp, 16);
9593 if (*argv[5] == 0 || *endp != 0)
9594 {
9595 test_min_max = 0;
9596 }
9597 else
9598 test_min_max=1;
9599
9600 }
9601
9602 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
9603 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
9604 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
9605 printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
9606 printf("\ntest_loop== 0x%08x\n", test_loop);
9607 printf("\ntest_min_max== 0x%08x\n", test_min_max);
9608 if ( channel_a_en)
9609 {
9610 //writel((0), 0xc8836c00);
9611 OPEN_CHANNEL_A_PHY_CLK();
9612 }
9613 if ( channel_b_en)
9614 {
9615 OPEN_CHANNEL_B_PHY_CLK();
9616 //writel((0), 0xc8836c00);
9617 }
9618
9619
9620
9621 //save and print org training dqs value
9622 if (channel_a_en || channel_b_en)
9623 {
9624
9625
9626 //dcache_disable();
9627 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
9628
9629 {
9630 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
9631 {
9632 if (( channel_a_en) && ( channel_b_en == 0))
9633 {
9634 reg_base_adj=CHANNEL_A_REG_BASE;
9635 }
9636 else if(( channel_b_en)&&( channel_a_en==0))
9637 {
9638 reg_base_adj=CHANNEL_B_REG_BASE;
9639 }
9640 else if ((channel_a_en+channel_b_en)==2)
9641 {
9642 if ( testing_channel == CHANNEL_A)
9643 {
9644 reg_base_adj=CHANNEL_A_REG_BASE;
9645 }
9646 else if( testing_channel==CHANNEL_B)
9647 {
9648 reg_base_adj=CHANNEL_B_REG_BASE;
9649 }
9650 }
9651
9652 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
9653 {
9654
9655 if (temp_count_i == DATX8_DQ_LANE_LANE00)
9656 {
9657 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
9658
9659 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
9660 {
9661 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
9662
9663 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
9664 {
9665 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
9666 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
9667 {
9668 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
9669
9670
9671
9672 for ((temp_count_j=0);(temp_count_j<DATX8_DQ_LCD_BDL_REG_WIDTH);(temp_count_j++))
9673 {
9674 dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=readl(reg_add+4*temp_count_j);
9675 dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
9676 printf("\n org add 0x%08x reg== 0x%08x\n",(reg_add+4*temp_count_j), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]));
9677 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
9678 =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
9679 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
9680 =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
9681
9682 }
9683 }
9684
9685 }
9686
9687 }
9688
9689 }////save and print org training dqs value
9690
9691
9692 for (test_times=0;(test_times<test_loop);(test_times++))
9693 {
9694 ////tune and save training dqs value
9695 if (channel_a_en || channel_b_en)
9696
9697 {
9698 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
9699 {
9700
9701 if (( channel_a_en) && ( channel_b_en == 0))
9702 {
9703 reg_base_adj=CHANNEL_A_REG_BASE;
9704 }
9705 else if(( channel_b_en)&&( channel_a_en==0))
9706 {
9707 reg_base_adj=CHANNEL_B_REG_BASE;
9708 }
9709 else if ((channel_a_en+channel_b_en)==2)
9710 {
9711 if ( testing_channel == CHANNEL_A)
9712 {
9713 reg_base_adj=CHANNEL_A_REG_BASE;
9714 }
9715 else if( testing_channel==CHANNEL_B)
9716 {
9717 reg_base_adj=CHANNEL_B_REG_BASE;
9718 }
9719 }
9720
9721 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
9722 {
9723 if (test_lane_step>8)
9724 test_lane_step=0;
9725 if (test_lane_step)
9726 {
9727 printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
9728 temp_count_i=(test_lane_step>>1);
9729 test_lane_step_rdqs_flag=test_lane_step-(temp_count_i<<1);
9730 test_lane_step=0;
9731 }
9732 {
9733 printf("\ntest lane==0x%08x\n ",temp_count_i);
9734 if (temp_count_i == DATX8_DQ_LANE_LANE00)
9735 {
9736 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
9737
9738 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
9739 {
9740 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
9741
9742 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
9743 {
9744 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
9745 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
9746 {
9747 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
9748 }
9749
9750 for ((temp_count_k=0);(temp_count_k<2);(temp_count_k++))
9751 {
9752 if (test_lane_step_rdqs_flag)
9753 {
9754 temp_count_k=1;
9755 test_lane_step_rdqs_flag=0;
9756 }
9757 if (temp_count_k == 0)
9758 {
9759 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
9760 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
9761 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
9762 // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
9763
9764 while (dq_lcd_bdl_temp_reg_value_wdqd>0)
9765 {
9766 if (test_min_max)
9767 {break;
9768 }
9769 temp_test_error=0;
9770 dq_lcd_bdl_temp_reg_value_wdqd--;
9771 printf("\nwdqd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
9772 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9773 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
9774 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9775
9776 if (temp_test_error)
9777 {
9778 //printf("\nwdqd left edge detect \n");
9779 dq_lcd_bdl_temp_reg_value_wdqd++;
9780 break;
9781 }
9782 }
9783 printf("\nwdqd left edge detect \n");
9784 printf("\nwdqd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
9785 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9786 //only update dq_lcd_bdl_temp_reg_value_wdqd
9787 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9788 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
9789 dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
9790
9791
9792 dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9793 if (dq_lcd_bdl_temp_reg_value_wdqd>(dq_lcd_bdl_temp_reg_lef_min_value&0xff)) //update wdqd min value
9794 {
9795 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
9796 =((dq_lcd_bdl_temp_reg_lef_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
9797 }
9798
9799
9800 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
9801
9802 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
9803 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
9804 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
9805
9806
9807 while (dq_lcd_bdl_temp_reg_value_wdqd<0xff)
9808 {
9809 temp_test_error=0;
9810 dq_lcd_bdl_temp_reg_value_wdqd++;
9811 printf("\nwdqd rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
9812 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9813 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
9814 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9815 if (temp_test_error)
9816 {
9817 //printf("\nwdqd right edge detect \n");
9818 dq_lcd_bdl_temp_reg_value_wdqd--;
9819 break;
9820 }
9821 }
9822 printf("\nwdqd right edge detect \n");
9823 printf("\nwdqd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
9824 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9825 //only update dq_lcd_bdl_temp_reg_value_wdqd
9826 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9827 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
9828
9829 dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
9830
9831 dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9832 if (dq_lcd_bdl_temp_reg_value_wdqd<(dq_lcd_bdl_temp_reg_rig_min_value&0xff)) //update wdqd min value
9833 {
9834 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
9835 =((dq_lcd_bdl_temp_reg_rig_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
9836 }
9837
9838
9839
9840 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
9841
9842
9843 }
9844 else if(temp_count_k==1)
9845 {
9846
9847 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
9848 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
9849 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
9850
9851 while (dq_lcd_bdl_temp_reg_value_rdqsd>0)
9852 {
9853 temp_test_error=0;
9854 dq_lcd_bdl_temp_reg_value_rdqsd--;
9855 printf("\nrdqsd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
9856 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9857 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
9858 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9859 if (temp_test_error)
9860 {
9861 //printf("\nrdqsd left edge detect \n");
9862 dq_lcd_bdl_temp_reg_value_rdqsd++;
9863 break;
9864 }
9865 }
9866 printf("\nrdqsd left edge detect \n");
9867 printf("\nrdqsd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
9868 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9869 //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
9870 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9871 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9872
9873 dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
9874
9875
9876 dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9877 if (dq_lcd_bdl_temp_reg_value_rdqsd>((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)) //update wdqd min value
9878 {
9879 dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
9880 =((dq_lcd_bdl_temp_reg_lef_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
9881 }
9882
9883
9884 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
9885
9886 dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
9887 dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
9888 dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
9889
9890 while (dq_lcd_bdl_temp_reg_value_rdqsd<0xff)
9891 {
9892 temp_test_error=0;
9893 dq_lcd_bdl_temp_reg_value_rdqsd++;
9894 printf("\nrdqsd right temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
9895 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9896 writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
9897 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
9898 if (temp_test_error)
9899 {
9900 //printf("\nrdqsd right edge detect \n");
9901 dq_lcd_bdl_temp_reg_value_rdqsd--;
9902 break;
9903 }
9904 }
9905 printf("\nrdqsd right edge detect \n");
9906 printf("\nrdqsd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
9907 dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9908 //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
9909 dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9910 dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
9911 dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
9912
9913
9914 dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
9915 if (dq_lcd_bdl_temp_reg_value_rdqsd<((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)) //update wdqd min value
9916 {
9917 dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
9918 =((dq_lcd_bdl_temp_reg_rig_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
9919 }
9920
9921
9922
9923 writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
9924
9925
9926
9927
9928 }
9929
9930 }
9931 }
9932
9933 }
9934 }
9935
9936 ////tune and save training dqs value
9937
9938
9939
9940
9941 ////calculate and print dqs value
9942 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
9943 {
9944 if (( channel_a_en) && ( channel_b_en == 0))
9945 {
9946 reg_base_adj=CHANNEL_A_REG_BASE;
9947 }
9948 else if(( channel_b_en)&&( channel_a_en==0))
9949 {
9950 reg_base_adj=CHANNEL_B_REG_BASE;
9951 }
9952 else if ((channel_a_en+channel_b_en)==2)
9953 {
9954 if ( testing_channel == CHANNEL_A)
9955 {
9956 reg_base_adj=CHANNEL_A_REG_BASE;
9957 }
9958 else if( testing_channel==CHANNEL_B)
9959 {
9960 reg_base_adj=CHANNEL_B_REG_BASE;
9961 }
9962 }
9963 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;
9964
9965
9966 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
9967 {
9968 // dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
9969
9970 printf("\n org add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
9971 }
9972
9973 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
9974 {
9975 printf("\n lef add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
9976 }
9977
9978 for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
9979 {
9980 printf("\n rig add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
9981 }
9982
9983 printf("\n ddrtest size ==0x%08x, test times==0x%08x,test_loop==0x%08x\n",ddr_test_size,(test_times+1),test_loop);
9984 printf("\n add 0x00000000 reg== org lef rig center win lef_m rig_m min_c min_win \n");
9985 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
9986 {
9987 {
9988
9989 if (temp_count_i == DATX8_DQ_LANE_LANE00)
9990 {
9991 reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
9992
9993 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
9994 {
9995 reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
9996
9997 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
9998 {
9999 reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
10000 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
10001 {
10002 reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
10003 }
10004
10005 dq_lcd_bdl_temp_reg_lef=(dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
10006 dq_lcd_bdl_temp_reg_rig=(dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
10007
10008 if (test_times == 0)
10009 {
10010 (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_lef;
10011 (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_rig;
10012
10013 }
10014 dq_lcd_bdl_temp_reg_lef_min_value=(dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
10015 dq_lcd_bdl_temp_reg_rig_min_value=(dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
10016
10017
10018 //dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value&0x0000ff);
10019 dq_lcd_bdl_temp_reg_center=( (((dq_lcd_bdl_temp_reg_lef&0xff)+(dq_lcd_bdl_temp_reg_rig&0xff))/2)
10020 |(((((dq_lcd_bdl_temp_reg_lef>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<8)
10021 |(((((dq_lcd_bdl_temp_reg_lef>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<16) );
10022
10023 dq_lcd_bdl_temp_reg_windows=( (((dq_lcd_bdl_temp_reg_rig&0xff)-(dq_lcd_bdl_temp_reg_lef&0xff)))
10024 |(((((dq_lcd_bdl_temp_reg_rig>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<8)
10025 |(((((dq_lcd_bdl_temp_reg_rig>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<16) );
10026
10027
10028 dq_lcd_bdl_temp_reg_center_min=( (((dq_lcd_bdl_temp_reg_lef_min_value&0xff)+(dq_lcd_bdl_temp_reg_rig_min_value&0xff))/2)
10029 |(((((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<8)
10030 |(((((dq_lcd_bdl_temp_reg_lef_min_value>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<16) );
10031
10032 dq_lcd_bdl_temp_reg_windows_min=( (((dq_lcd_bdl_temp_reg_rig_min_value&0xff)-(dq_lcd_bdl_temp_reg_lef_min_value&0xff)))
10033 |(((((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<8)
10034 |(((((dq_lcd_bdl_temp_reg_rig_min_value>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<16) );
10035
10036 printf("\n add 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
10037 (dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10038 (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10039 (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10040 (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10041 dq_lcd_bdl_temp_reg_center,dq_lcd_bdl_temp_reg_windows,
10042 (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10043 (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
10044 dq_lcd_bdl_temp_reg_center_min,dq_lcd_bdl_temp_reg_windows_min
10045 );
10046 }
10047
10048
10049 }
10050
10051 }
10052
10053
10054
10055
10056
10057 return 0;
10058
10059usage:
10060 cmd_usage(cmdtp);
10061 return 1;
10062
10063}
10064
10065
10066
10067int do_ddr_test_dqs_window_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
10068{
10069 printf("\nEnterddr_test_dqs_window function\n");
10070 printf("\nddr_test_cmd 0x22 a 0 0x80000 ns lane_disable add_test_size --- watchdog should >15s\n");
10071 unsigned int channel_a_en = 0;
10072 unsigned int channel_b_en = 0;
10073 // unsigned int reg_add=0;
10074 // unsigned int reg_base_adj=0;
10075
10076 unsigned int lane_step= 0;
10077 unsigned int reg_value= 0;
10078 //int argc2;
10079 //char * argv2[30];
10080 char *endp;
10081 char *buf;
10082 buf="";
10083
10084 if (argc == 2)
10085 {
10086 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
10087
10088 {channel_a_en = 1;
10089 }
10090 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
10091
10092 {channel_b_en = 1;
10093 }
10094
10095
10096 }
10097 if (argc > 2)
10098 {
10099 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
10100
10101 {channel_a_en = 1;
10102 }
10103 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
10104
10105 {channel_b_en = 1;
10106 }
10107 }
10108 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
10109 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
10110 if (argc >3) {
10111 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
10112 if (*argv[3] == 0 || *endp != 0)
10113 {
10114 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
10115 }
10116 }
10117
10118
10119
10120 if (argc >4) {
10121 watchdog_time_s = simple_strtoull_ddr(argv[4], &endp, 0);
10122 if (*argv[4] == 0 || *endp != 0)
10123 {
10124 watchdog_time_s= 20;
10125 }
10126 }
10127 printf("watchdog_time_s==%d\n",watchdog_time_s);
10128
10129 unsigned int lane_disable= 0;
10130
10131 if (argc >5) {
10132 lane_disable = simple_strtoull_ddr(argv[5], &endp, 0);
10133 if (*argv[5] == 0 || *endp != 0)
10134 {
10135 lane_disable= 0;
10136 }
10137 }
10138 printf("lane_disable==0x%08x\n",lane_disable);
10139
10140 unsigned int add_test_size= DDR_CROSS_TALK_TEST_SIZE;
10141
10142 if (argc >6) {
10143 add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
10144 if (*argv[6] == 0 || *endp != 0)
10145 {
10146 add_test_size= ddr_test_size;
10147 }
10148 }
10149 printf("add_test_size==0x%08x\n",add_test_size);
10150 //argc2=5;
10151 //for(i = 1;i<(argc);i++)
10152 {
10153 //argv2[i-1]=argv[i];
10154 }
10155
10156 //argv2[0]=argv[1];
10157 //argv2[1]=argv[2];
10158 //argv2[2]=argv[3];
10159 //#include <stdio.h>
10160 // unsigned int wr_adj_per[24] ;
10161 //if(1)
10162
10163 printf("\ntest use uboot env\n");
10164
10165 char str[1024]="";
10166 char str_temp1[1024]="";
10167 char str_temp2[1024]="";
10168 const char *s;
10169 unsigned int str_to_numarry[48];
10170 //str_buf = (char *)malloc(sizeof(char)*1024);
10171
10172 unsigned int *num_arry;
10173 //unsigned int *num_arry_temp;
10174 unsigned int *num_arry_lane0=NULL;
10175 unsigned int *num_arry_lane1=NULL;
10176 unsigned int *num_arry_lane2=NULL;
10177 unsigned int *num_arry_lane3=NULL;
10178 char *name_lane0;
10179 char *name_lane1;
10180 char *name_lane2;
10181 char *name_lane3;
10182 num_arry = (unsigned int *)(&str_to_numarry);
10183 int i;
10184 char *varname; char *env_lcdlr_temp_count;
10185 unsigned int lcdlr_temp_count=0;
10186 const char *temp_s;const char *temp_s1;
10187 // int value=0;
10188
10189 varname="env_ddrtest_data_lane";
10190 name_lane0="ddr_test_data_lane0";
10191 name_lane1="ddr_test_data_lane1";
10192 name_lane2="ddr_test_data_lane2";
10193 name_lane3="ddr_test_data_lane3";
10194 env_lcdlr_temp_count="lcdlr_temp_count";
10195 s = env_get(varname);
10196 if (s)
10197 {//i=0;
10198 //while(s_temp)
10199 {
10200 env_to_num(varname,num_arry);//unsigned int *num_arry
10201 temp_s= env_get(env_lcdlr_temp_count);
10202 if (temp_s)
10203 {
10204 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10205 }
10206 else
10207 {lcdlr_temp_count=0;
10208 }
10209
10210 if (0) {
10211 env_to_num(name_lane0,num_arry_lane0);//unsigned int *num_arry
10212 env_to_num(name_lane1,num_arry_lane1);//unsigned int *num_arry
10213 env_to_num(name_lane2,num_arry_lane2);//unsigned int *num_arry
10214 env_to_num(name_lane3,num_arry_lane3);//unsigned int *num_arry
10215 }
10216
10217 for (i = 0; i < 48; i++) {
10218
10219 printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
10220 }
10221 //for (lane_step = 0;lane_step< 4;lane_step++)
10222 if (0)
10223 {
10224 for (i = 0; i < 8; i++) {
10225
10226 printf("lane_0 str_to_numarry[%d]==%d\n",i,num_arry_lane0[i]);
10227 }
10228 for (i = 0; i < 8; i++) {
10229
10230 printf("lane_1 str_to_numarry[%d]==%d\n",i,num_arry_lane1[i]);
10231 }
10232 for (i = 0; i < 8; i++) {
10233
10234 printf("lane_2 str_to_numarry[%d]==%d\n",i,num_arry_lane2[i]);
10235 }
10236 for (i = 0; i < 8; i++) {
10237
10238 printf("lane_3 str_to_numarry[%d]==%d\n",i,num_arry_lane3[i]);
10239 }
10240 }
10241 // printf("%s,length=%d",s,(strlen(s)));
10242 //sscanf(s,"d%,",wr_adj_per);
10243 //sprintf(str,"d%",s);
10244 //getc
10245 // if (strlen(s) > 16)
10246 {
10247 // sscanf(s, "%08x, %08x, %08x, \n",
10248 // &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
10249 }
10250 }
10251 }
10252 else
10253 {
10254 printf("no env set,exit\n");
10255 return 0;}
10256 s = env_get(varname);//for debug display env should add
10257
10258
10259 ///*
10260 //if(1)
10261
10262 unsigned int test_arg_0_cmd0 =0; //master cmd
10263 unsigned int test_arg_1_cmd1 =0; //min cmd
10264 unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
10265 unsigned int test_arg_3_freq =0;
10266 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
10267 // unsigned int lane_step= 0;
10268 //char str[24];
10269
10270
10271 test_arg_0_cmd0=num_arry[0];
10272 test_arg_1_cmd1=num_arry[1];
10273 test_arg_2_step=num_arry[2];
10274 test_arg_3_freq=num_arry[3];
10275 test_arg_4_step_status=num_arry[4];
10276 printf("test_arg_0_cmd0==%d\n",test_arg_0_cmd0);
10277 printf("test_arg_0_cmd1==%d\n",test_arg_1_cmd1);
10278 printf("test_arg_2_step==%d\n",test_arg_2_step);
10279 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
10280 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
10281
10282 if (test_arg_2_step)
10283 {
10284 if (test_arg_3_freq != global_ddr_clk)
10285 {
10286 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
10287 sprintf(str,"d2pll %d",test_arg_3_freq);
10288 printf("\nstr=%s\n",str);
10289 run_command(str,0);
10290 while (1) ;
10291 }
10292 }
10293 if (test_arg_2_step == 0)
10294 {
10295 {
10296 test_arg_0_cmd0=0x22;
10297 test_arg_1_cmd1=0;
10298 test_arg_2_step=1;
10299 test_arg_3_freq=global_ddr_clk;
10300 test_arg_4_step_status=0;
10301 num_arry[0]=test_arg_0_cmd0;
10302 num_arry[1]=test_arg_1_cmd1;
10303 num_arry[2]=test_arg_2_step;
10304 num_arry[3]=test_arg_3_freq;
10305 num_arry[4]=test_arg_4_step_status;
10306 num_arry[5]=0;
10307 num_arry[6]=0;
10308 num_arry[7]=0;
10309 for (i = 8; i < 48; i++) {
10310 num_arry[i]=0;
10311 }
10312
10313 for (lane_step = 0; lane_step < 4; lane_step++)
10314 {
10315 //if(lane_step%2)
10316 {
10317#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
10318 dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
10319 DDR0_PUB_DX0LCDLR1)
10320 +DDR0_PUB_DX0LCDLR1))&0xff);
10321 dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
10322 DDR0_PUB_DX0LCDLR1)
10323 +DDR0_PUB_DX0LCDLR1))>>8)&0xff);
10324#else
10325 dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
10326 DDR0_PUB_DX0LCDLR1)
10327 +DDR0_PUB_DX0LCDLR1))&0x1ff);
10328 dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
10329 DDR0_PUB_DX0LCDLR3)
10330 +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff);
10331
10332 printf("lcdlr1 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
10333 DDR0_PUB_DX0LCDLR1)
10334 +DDR0_PUB_DX0LCDLR1),
10335 ((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
10336 DDR0_PUB_DX0LCDLR1)
10337 +DDR0_PUB_DX0LCDLR1))&0x1ff),dq_lcd_bdl_value_wdq_org_a[lane_step]);
10338 printf("lcdlr3 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
10339 DDR0_PUB_DX0LCDLR3)
10340 +DDR0_PUB_DX0LCDLR3),
10341 (((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
10342 DDR0_PUB_DX0LCDLR3)
10343 +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff),dq_lcd_bdl_value_rdqs_org_a[lane_step]);
10344#endif
10345
10346 //printf("lcdlr1 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
10347 //DDR0_PUB_DX0LCDLR1)
10348 //+DDR0_PUB_DX0LCDLR1));
10349 //printf("lcdlr3 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
10350 //DDR0_PUB_DX0LCDLR3)
10351 //+DDR0_PUB_DX0LCDLR3));
10352 //dq_lcd_bdl_value_rdqs_org_a[lane_step]=0;
10353 dq_lcd_bdl_value_rdqs_min_a[lane_step]=0xffff;
10354 dq_lcd_bdl_value_rdqs_max_a[lane_step]=0xffff;
10355 dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
10356 }
10357 //else
10358 {
10359 //dq_lcd_bdl_value_wdq_org_a[lane_step]=0;
10360 dq_lcd_bdl_value_wdq_min_a[lane_step]=0xffff;
10361 dq_lcd_bdl_value_wdq_max_a[lane_step]=0xffff;
10362 dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
10363 }
10364 }
10365
10366 {
10367 dq_lcd_bdl_value_aclcdlr_org_a=((readl(DDR0_PUB_ACLCDLR))&ACLCDLR_MAX);
10368 dq_lcd_bdl_value_aclcdlr_min_a=0xffff;
10369 dq_lcd_bdl_value_aclcdlr_max_a=0xffff;
10370 dq_lcd_bdl_value_aclcdlr_status_a=0;
10371 dq_lcd_bdl_value_bdlr0_org_a=((readl(DDR0_PUB_ACBDLR0))&ACBDLR_MAX);
10372 dq_lcd_bdl_value_bdlr0_min_a=0xffff;
10373 dq_lcd_bdl_value_bdlr0_max_a=0xffff;
10374 dq_lcd_bdl_value_bdlr0_status_a=0;
10375 }
10376
10377
10378
10379#if 1 //( CONFIG_DDR_PHY<P_DDR_PHY_905X)
10380 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
10381 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
10382 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
10383 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
10384 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
10385 lane_disable= lane_disable|1;
10386 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
10387 lane_disable= lane_disable|(1<<1);
10388 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
10389 lane_disable= lane_disable|(1<<2);
10390 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
10391 lane_disable= lane_disable|(1<<3);
10392
10393#endif
10394 if (lane_disable)
10395 {if(lane_disable&0x1){
10396 dq_lcd_bdl_value_wdq_status_a[0]=4;
10397 dq_lcd_bdl_value_rdqs_status_a[0]=4;
10398 }
10399 if (lane_disable&0x2) {
10400 dq_lcd_bdl_value_wdq_status_a[1]=4;
10401 dq_lcd_bdl_value_rdqs_status_a[1]=4;
10402 }
10403 if (lane_disable&0x4) {
10404 dq_lcd_bdl_value_wdq_status_a[2]=4;
10405 dq_lcd_bdl_value_rdqs_status_a[2]=4;
10406 }
10407 if (lane_disable&0x8) {
10408 dq_lcd_bdl_value_wdq_status_a[3]=4;
10409 dq_lcd_bdl_value_rdqs_status_a[3]=4;
10410 }
10411 printf("lane_disable==%x\n",lane_disable);
10412 if (lane_disable&0x10) {
10413 dq_lcd_bdl_value_aclcdlr_status_a=4;
10414 printf("dq_lcd_bdl_value_aclcdlr_status_a==%x\n",dq_lcd_bdl_value_aclcdlr_status_a);
10415 }
10416 if (lane_disable&0x20) {
10417 dq_lcd_bdl_value_bdlr0_status_a=4;
10418 printf("dq_lcd_bdl_value_bdlr0_status_a==%x\n",dq_lcd_bdl_value_bdlr0_status_a);
10419
10420 }
10421 }
10422
10423 {
10424 for (lane_step = 0; lane_step < 4; lane_step++)
10425
10426
10427 {
10428 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
10429 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
10430 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
10431 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
10432 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
10433 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
10434 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
10435 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10436 }
10437
10438
10439
10440
10441 lane_step=4;
10442 {
10443 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
10444 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
10445 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
10446 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
10447 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
10448 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
10449 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
10450 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
10451 }
10452 }
10453
10454 if (0) {
10455 for (i = 0; i < 8; i++) {
10456 num_arry_lane0[i]=num_arry[8+i];
10457 }
10458 for (i = 0; i < 8; i++) {
10459 num_arry_lane1[i]=num_arry[8+8+i];
10460 }
10461 for (i = 0; i < 8; i++) {
10462 num_arry_lane2[i]=num_arry[8+8+8+i];
10463 }
10464 for (i = 0; i < 8; i++) {
10465 num_arry_lane3[i]=num_arry[8+8+8+8+i];
10466 }
10467 num_to_env(name_lane0,num_arry_lane0);
10468 num_to_env(name_lane1,num_arry_lane1);
10469 num_to_env(name_lane2,num_arry_lane2);
10470 num_to_env(name_lane3,num_arry_lane3);
10471 run_command("save",0);
10472 }
10473
10474 }
10475
10476
10477
10478
10479 for (i = 0; i < 48; i++) {
10480 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10481 sprintf(str_temp2,"0x%08x",num_arry[i]);
10482 env_set(str_temp1, str_temp2);
10483 run_command("save",0);
10484 }
10485
10486
10487
10488 }
10489
10490 test_arg_2_step++;
10491 num_arry[2]=test_arg_2_step;
10492 sprintf(str, "0x%08x", num_arry[0]);
10493 printf("%d %d\n", 0,num_arry[0]);
10494 for (i = 1; i < 48; i++) {
10495 //num_arry[i]=0;
10496 sprintf(str, "%s;0x%08x", str,num_arry[i]);
10497 printf("%d %d\n", i,num_arry[i]);
10498
10499 }
10500 //sprintf(str, "%lx", value);
10501 printf("%s", str);
10502 env_set(varname, str);
10503 run_command("save",0);
10504
10505
10506 i=2;
10507 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10508 sprintf(str_temp2,"0x%08x",num_arry[i]);
10509 env_set(str_temp1, str_temp2);
10510 run_command("save",0);
10511
10512 for (i = 8; i < 48; i++) {
10513 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10514 temp_s1= env_get(str_temp1);
10515 if (temp_s1)
10516 {
10517 num_arry[i]= simple_strtoull_ddr(temp_s1, &endp, 0);
10518 }
10519 else
10520 {num_arry[i]=0;
10521 }
10522 printf("ddr_test_data_num_%04d==%d\n",i,num_arry[i]);
10523 }
10524
10525 ///*
10526 {
10527 for (lane_step = 0; lane_step < 4; lane_step++)
10528 {
10529 {
10530 dq_lcd_bdl_value_wdq_org_a[lane_step]=num_arry[8+lane_step*4*2+0];
10531 dq_lcd_bdl_value_wdq_min_a[lane_step]=num_arry[8+lane_step*4*2+1];
10532 dq_lcd_bdl_value_wdq_max_a[lane_step]=num_arry[8+lane_step*4*2+2];
10533 dq_lcd_bdl_value_wdq_status_a[lane_step]=num_arry[8+lane_step*4*2+3];
10534 }
10535 {
10536 dq_lcd_bdl_value_rdqs_org_a[lane_step]=num_arry[8+lane_step*4*2+4];
10537 dq_lcd_bdl_value_rdqs_min_a[lane_step]=num_arry[8+lane_step*4*2+5];
10538 dq_lcd_bdl_value_rdqs_max_a[lane_step]=num_arry[8+lane_step*4*2+6];
10539 dq_lcd_bdl_value_rdqs_status_a[lane_step]=num_arry[8+lane_step*4*2+7];
10540 }
10541
10542
10543 }
10544 lane_step=4;
10545 {
10546 dq_lcd_bdl_value_aclcdlr_org_a=num_arry[8+lane_step*4*2+0];
10547 dq_lcd_bdl_value_aclcdlr_min_a=num_arry[8+lane_step*4*2+1];
10548 dq_lcd_bdl_value_aclcdlr_max_a=num_arry[8+lane_step*4*2+2];
10549 dq_lcd_bdl_value_aclcdlr_status_a=num_arry[8+lane_step*4*2+3];
10550 dq_lcd_bdl_value_bdlr0_org_a=num_arry[8+lane_step*4*2+4];
10551 dq_lcd_bdl_value_bdlr0_min_a=num_arry[8+lane_step*4*2+5];
10552 dq_lcd_bdl_value_bdlr0_max_a=num_arry[8+lane_step*4*2+6];
10553 dq_lcd_bdl_value_bdlr0_status_a=num_arry[8+lane_step*4*2+7];
10554 }
10555 }
10556 //*/
10557
10558
10559
10560
10561 if (channel_a_en)
10562 {
10563
10564 //*(char *)(argv2[0])="a";
10565 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
10566 printf("\ntest dqs window lane a\n");
10567 for ((lane_step=0);(lane_step<4);(lane_step++))
10568 {
10569 ddr_test_watchdog_enable(watchdog_time_s); //s
10570 printf("\nenable %ds watchdog \n",watchdog_time_s);
10571
10572 /*
10573 {
10574 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
10575 sprintf(buf, "0x%08x", lcdlr_temp_count);
10576 printf( "%s", buf);
10577 env_set(env_lcdlr_temp_count, buf);
10578 run_command("save",0);
10579 }
10580 */
10581 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
10582 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0)
10583 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
10584 )
10585 {
10586 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
10587 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0))
10588 { dq_lcd_bdl_value_wdq_status_a[lane_step]=1;
10589 {
10590 {
10591 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
10592 i=8+lane_step*8+3;
10593 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10594 sprintf(str_temp2,"0x%08x",num_arry[i]);
10595 env_set(str_temp1, str_temp2);
10596 run_command("save",0);
10597 }
10598 lcdlr_temp_count=0;
10599 sprintf(buf, "0x%08x", lcdlr_temp_count);
10600 printf( "%s", buf);
10601 env_set(env_lcdlr_temp_count, buf);
10602 run_command("save",0);
10603 }
10604
10605 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+0),2);
10606 printf("\nstr=%s\n",str);
10607 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10608 //printf("\nstr=%s\n",str);
10609 ddr_test_watchdog_clear();
10610 run_command(str,0);
10611 ddr_test_watchdog_clear();
10612 ddr_udelay(2000000);
10613 dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
10614
10615 }
10616 else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
10617 {
10618 temp_s= env_get(env_lcdlr_temp_count);
10619 if (temp_s)
10620 {
10621 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10622 }
10623 dq_lcd_bdl_value_wdq_min_a[lane_step]=lcdlr_temp_count;
10624 dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
10625 }
10626
10627 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
10628 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
10629 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
10630 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
10631
10632 //ddr_udelay(1000000);
10633 //num_to_env(varname,num_arry);
10634 {
10635 i=8+lane_step*8+1;
10636 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10637 sprintf(str_temp2,"0x%08x",num_arry[i]);
10638 env_set(str_temp1, str_temp2);
10639 run_command("save",0);
10640 i=8+lane_step*8+3;
10641 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10642 sprintf(str_temp2,"0x%08x",num_arry[i]);
10643 env_set(str_temp1, str_temp2);
10644 run_command("save",0);
10645 }
10646
10647
10648 run_command("reset",0);
10649 }
10650
10651 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 2) ||
10652 (dq_lcd_bdl_value_wdq_status_a[lane_step]==3))
10653 {
10654 // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
10655 // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
10656 // num_to_env(varname,num_arry);
10657 // run_command("reset",0);
10658 // }
10659
10660 {
10661 if (dq_lcd_bdl_value_wdq_status_a[lane_step] == 2)
10662 { dq_lcd_bdl_value_wdq_status_a[lane_step]=3;
10663 {
10664 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
10665 i=8+lane_step*8+3;
10666 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10667 sprintf(str_temp2,"0x%08x",num_arry[i]);
10668 env_set(str_temp1, str_temp2);
10669 run_command("save",0);
10670 }
10671 {
10672 lcdlr_temp_count=0;
10673 sprintf(buf, "0x%08x", lcdlr_temp_count);
10674 printf( "%s", buf);
10675 env_set(env_lcdlr_temp_count, buf);
10676 run_command("save",0);
10677 }
10678
10679 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+0),1);
10680 printf("\nstr=%s\n",str);
10681 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10682 //printf("\nstr=%s\n",str);
10683 ddr_test_watchdog_clear();
10684 run_command(str,0);
10685 ddr_test_watchdog_clear();
10686 ddr_udelay(2000000);
10687 dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
10688
10689 }
10690 else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==3)
10691 {
10692 temp_s= env_get(env_lcdlr_temp_count);
10693 if (temp_s)
10694 {
10695 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10696 }
10697 dq_lcd_bdl_value_wdq_max_a[lane_step]=lcdlr_temp_count;
10698 dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
10699 }
10700
10701 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
10702 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
10703 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
10704 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
10705 //ddr_udelay(1000000);
10706 //num_to_env(varname,num_arry);
10707 {
10708 i=8+lane_step*8+2;
10709 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10710 sprintf(str_temp2,"0x%08x",num_arry[i]);
10711 env_set(str_temp1, str_temp2);
10712 run_command("save",0);
10713 i=8+lane_step*8+3;
10714 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10715 sprintf(str_temp2,"0x%08x",num_arry[i]);
10716 env_set(str_temp1, str_temp2);
10717 run_command("save",0);
10718 }
10719
10720 run_command("reset",0);
10721 }
10722
10723 }
10724
10725
10726 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
10727 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0)
10728 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
10729 )
10730 {
10731 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
10732 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
10733 { dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
10734 {
10735 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10736 i=8+lane_step*8+7;
10737 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10738 sprintf(str_temp2,"0x%08x",num_arry[i]);
10739 env_set(str_temp1, str_temp2);
10740 run_command("save",0);
10741 }
10742 {
10743 lcdlr_temp_count=0;
10744 sprintf(buf, "0x%08x", lcdlr_temp_count);
10745 printf( "%s", buf);
10746 env_set(env_lcdlr_temp_count, buf);
10747 run_command("save",0);
10748 }
10749
10750 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
10751 printf("\nstr=%s\n",str);
10752 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10753 //printf("\nstr=%s\n",str);
10754 ddr_test_watchdog_clear();
10755 run_command(str,0);
10756 ddr_test_watchdog_clear();
10757 ddr_udelay(2000000);
10758 dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
10759
10760 }
10761 else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
10762 {
10763 temp_s= env_get(env_lcdlr_temp_count);
10764 if (temp_s)
10765 {
10766 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10767 }
10768 dq_lcd_bdl_value_rdqs_min_a[lane_step]=lcdlr_temp_count;
10769 dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
10770 }
10771
10772 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
10773 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
10774 //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
10775 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10776 //ddr_udelay(1000000);
10777 //num_to_env(varname,num_arry);
10778 {
10779 i=8+lane_step*8+5;
10780 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10781 sprintf(str_temp2,"0x%08x",num_arry[i]);
10782 env_set(str_temp1, str_temp2);
10783 run_command("save",0);
10784 i=8+lane_step*8+7;
10785 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10786 sprintf(str_temp2,"0x%08x",num_arry[i]);
10787 env_set(str_temp1, str_temp2);
10788 run_command("save",0);
10789 }
10790
10791 run_command("reset",0);
10792 }
10793
10794 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2) ||
10795 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3))
10796 {
10797
10798 {
10799 if (dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2)
10800 {
10801
10802 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
10803 {
10804 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10805 i=8+lane_step*8+7;
10806 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10807 sprintf(str_temp2,"0x%08x",num_arry[i]);
10808 env_set(str_temp1, str_temp2);
10809 run_command("save",0);
10810 }
10811
10812 {
10813 lcdlr_temp_count=0;
10814 sprintf(buf, "0x%08x", lcdlr_temp_count);
10815 printf( "%s", buf);
10816 env_set(env_lcdlr_temp_count, buf);
10817 run_command("save",0);
10818 }
10819
10820 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
10821 printf("\nstr=%s\n",str);
10822 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10823 //printf("\nstr=%s\n",str);
10824 ddr_test_watchdog_clear();
10825 run_command(str,0);
10826 ddr_test_watchdog_clear();
10827 ddr_udelay(2000000);
10828 dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
10829
10830 }
10831 else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3)
10832 {
10833 temp_s= env_get(env_lcdlr_temp_count);
10834 if (temp_s)
10835 {
10836 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10837 }
10838 dq_lcd_bdl_value_rdqs_max_a[lane_step]=lcdlr_temp_count;
10839 dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
10840 }
10841
10842 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
10843 //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
10844 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
10845 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10846 //ddr_udelay(1000000);
10847 // num_to_env(varname,num_arry);
10848
10849 {
10850 i=8+lane_step*8+6;
10851 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10852 sprintf(str_temp2,"0x%08x",num_arry[i]);
10853 env_set(str_temp1, str_temp2);
10854 run_command("save",0);
10855 i=8+lane_step*8+7;
10856 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10857 sprintf(str_temp2,"0x%08x",num_arry[i]);
10858 env_set(str_temp1, str_temp2);
10859 run_command("save",0);
10860 }
10861 run_command("reset",0);
10862 }
10863
10864 }
10865
10866 /*
10867 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
10868 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
10869 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
10870 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
10871 printf("\nstr=%s\n",str);
10872 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10873 //printf("\nstr=%s\n",str);
10874 ddr_test_watchdog_clear();
10875 run_command(str,0);
10876 ddr_test_watchdog_clear();
10877 dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
10878 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
10879 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
10880 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
10881 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10882 num_to_env(varname,num_arry);
10883 run_command("reset",0);
10884 }
10885
10886 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
10887 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
10888 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
10889 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
10890 printf("\nstr=%s\n",str);
10891 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10892 //printf("\nstr=%s\n",str);
10893 ddr_test_watchdog_clear();
10894 run_command(str,0);
10895 ddr_test_watchdog_clear();
10896 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
10897 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
10898 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
10899 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
10900 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
10901 num_to_env(varname,num_arry);
10902 run_command("reset",0);
10903 }
10904 */
10905
10906
10907 ddr_test_watchdog_disable(); //s
10908 {printf("close watchdog\n");
10909 }
10910
10911
10912 }
10913
10914
10915
10916 }
10917
10918 if (channel_a_en)
10919 {
10920
10921 //*(char *)(argv2[0])="a";
10922 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
10923 printf("\ntest lcdlr ac bdlr window lane a...\n");
10924
10925 {
10926 ddr_test_watchdog_enable(watchdog_time_s); //s
10927 printf("\nenable %ds watchdog \n",watchdog_time_s);
10928 printf("\ndq_lcd_bdl_value_aclcdlr_status_a %d \n",dq_lcd_bdl_value_aclcdlr_status_a);
10929 lane_step=4;
10930 env_lcdlr_temp_count="lcdlr_temp_count_a";
10931 if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
10932 ||(dq_lcd_bdl_value_aclcdlr_status_a==0)
10933 ||(dq_lcd_bdl_value_aclcdlr_status_a==1)
10934 )
10935 {
10936 if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
10937 ||(dq_lcd_bdl_value_aclcdlr_status_a==0))
10938 { dq_lcd_bdl_value_aclcdlr_status_a=1;
10939 {
10940 {
10941 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
10942 i=8+lane_step*8+3;
10943 printf("aclcdlr_status_a==0x%08x\n",num_arry[i]);
10944 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10945 sprintf(str_temp2,"0x%08x",num_arry[i]);
10946 env_set(str_temp1, str_temp2);
10947 run_command("save",0);
10948 }
10949 printf("\n222test lcdlr ac bdlr window lane a...\n");
10950 lcdlr_temp_count=0;
10951 sprintf(buf, "0x%08x", lcdlr_temp_count);
10952 printf( "%s", buf);
10953 env_set(env_lcdlr_temp_count, buf);
10954 run_command("save",0);
10955 }
10956
10957 printf("\n333test lcdlr ac bdlr window lane a...\n");
10958 //ddr_tune_aclcdlr_step
10959 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 0),2);
10960 printf("\nstr=%s\n",str);
10961 printf("aclcdlr_status_a1==0x%08x\n",num_arry[i]);
10962 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
10963 //printf("\nstr=%s\n",str);
10964 ddr_test_watchdog_clear();
10965 run_command(str,0);
10966 ddr_test_watchdog_clear();
10967 ddr_udelay(2000000);
10968 dq_lcd_bdl_value_aclcdlr_status_a=2;
10969
10970 }
10971 else if (dq_lcd_bdl_value_aclcdlr_status_a==1)
10972 {
10973 temp_s= env_get(env_lcdlr_temp_count);
10974 if (temp_s)
10975 {
10976 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
10977 }
10978 dq_lcd_bdl_value_aclcdlr_min_a=lcdlr_temp_count;
10979 dq_lcd_bdl_value_aclcdlr_status_a=2;
10980 }
10981
10982 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
10983 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
10984 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
10985 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
10986
10987 //ddr_udelay(1000000);
10988 //num_to_env(varname,num_arry);
10989 {
10990 i=8+lane_step*8+1;
10991 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10992 sprintf(str_temp2,"0x%08x",num_arry[i]);
10993 env_set(str_temp1, str_temp2);
10994 run_command("save",0);
10995 i=8+lane_step*8+3;
10996 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
10997 sprintf(str_temp2,"0x%08x",num_arry[i]);
10998 env_set(str_temp1, str_temp2);
10999 run_command("save",0);
11000 }
11001
11002
11003 run_command("reset",0);
11004 }
11005
11006 if ((dq_lcd_bdl_value_aclcdlr_status_a == 2) ||
11007 (dq_lcd_bdl_value_aclcdlr_status_a==3))
11008 {
11009 // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
11010 // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
11011 // num_to_env(varname,num_arry);
11012 // run_command("reset",0);
11013 // }
11014
11015 {
11016 if (dq_lcd_bdl_value_aclcdlr_status_a == 2)
11017 { dq_lcd_bdl_value_aclcdlr_status_a=3;
11018 {
11019 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
11020 i=8+lane_step*8+3;
11021 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11022 sprintf(str_temp2,"0x%08x",num_arry[i]);
11023 env_set(str_temp1, str_temp2);
11024 run_command("save",0);
11025 }
11026 {
11027 lcdlr_temp_count=0;
11028 sprintf(buf, "0x%08x", lcdlr_temp_count);
11029 printf( "%s", buf);
11030 env_set(env_lcdlr_temp_count, buf);
11031 run_command("save",0);
11032 }
11033
11034 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 0),1);
11035 printf("\nstr=%s\n",str);
11036 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
11037 //printf("\nstr=%s\n",str);
11038 ddr_test_watchdog_clear();
11039 run_command(str,0);
11040 ddr_test_watchdog_clear();
11041 ddr_udelay(2000000);
11042 dq_lcd_bdl_value_aclcdlr_status_a=4;
11043
11044 }
11045 else if (dq_lcd_bdl_value_aclcdlr_status_a==3)
11046 {
11047 temp_s= env_get(env_lcdlr_temp_count);
11048 if (temp_s)
11049 {
11050 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
11051 }
11052 dq_lcd_bdl_value_aclcdlr_max_a=lcdlr_temp_count;
11053 dq_lcd_bdl_value_aclcdlr_status_a=4;
11054 }
11055
11056 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
11057 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
11058 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
11059 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
11060 //ddr_udelay(1000000);
11061 //num_to_env(varname,num_arry);
11062 {
11063 i=8+lane_step*8+2;
11064 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11065 sprintf(str_temp2,"0x%08x",num_arry[i]);
11066 env_set(str_temp1, str_temp2);
11067 run_command("save",0);
11068 i=8+lane_step*8+3;
11069 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11070 sprintf(str_temp2,"0x%08x",num_arry[i]);
11071 env_set(str_temp1, str_temp2);
11072 run_command("save",0);
11073 }
11074
11075 run_command("reset",0);
11076 }
11077
11078 }
11079
11080
11081 if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
11082 ||(dq_lcd_bdl_value_bdlr0_status_a==0)
11083 ||(dq_lcd_bdl_value_bdlr0_status_a==1)
11084 )
11085 {
11086 if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
11087 ||(dq_lcd_bdl_value_bdlr0_status_a==0))
11088 { dq_lcd_bdl_value_bdlr0_status_a=1;
11089 {
11090 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
11091 i=8+lane_step*8+7;
11092 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11093 sprintf(str_temp2,"0x%08x",num_arry[i]);
11094 env_set(str_temp1, str_temp2);
11095 run_command("save",0);
11096 }
11097 {
11098 lcdlr_temp_count=0;
11099 sprintf(buf, "0x%08x", lcdlr_temp_count);
11100 printf( "%s", buf);
11101 env_set(env_lcdlr_temp_count, buf);
11102 run_command("save",0);
11103 }
11104
11105 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 1),2);
11106 printf("\nstr=%s\n",str);
11107 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
11108 //printf("\nstr=%s\n",str);
11109 ddr_test_watchdog_clear();
11110 run_command(str,0);
11111 ddr_test_watchdog_clear();
11112 ddr_udelay(2000000);
11113 dq_lcd_bdl_value_bdlr0_status_a=2;
11114
11115 }
11116 else if (dq_lcd_bdl_value_bdlr0_status_a==1)
11117 {
11118 temp_s= env_get(env_lcdlr_temp_count);
11119 if (temp_s)
11120 {
11121 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
11122 }
11123 dq_lcd_bdl_value_bdlr0_min_a=lcdlr_temp_count;
11124 dq_lcd_bdl_value_bdlr0_status_a=2;
11125 }
11126
11127 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
11128 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
11129 //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
11130 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
11131 //ddr_udelay(1000000);
11132 //num_to_env(varname,num_arry);
11133 {
11134 i=8+lane_step*8+5;
11135 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11136 sprintf(str_temp2,"0x%08x",num_arry[i]);
11137 env_set(str_temp1, str_temp2);
11138 run_command("save",0);
11139 i=8+lane_step*8+7;
11140 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11141 sprintf(str_temp2,"0x%08x",num_arry[i]);
11142 env_set(str_temp1, str_temp2);
11143 run_command("save",0);
11144 }
11145
11146 run_command("reset",0);
11147 }
11148
11149 if ((dq_lcd_bdl_value_bdlr0_status_a == 2) ||
11150 (dq_lcd_bdl_value_bdlr0_status_a==3))
11151 {
11152
11153 {
11154 if (dq_lcd_bdl_value_bdlr0_status_a == 2)
11155 {
11156
11157 dq_lcd_bdl_value_bdlr0_status_a=3;
11158 {
11159 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
11160 i=8+lane_step*8+7;
11161 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11162 sprintf(str_temp2,"0x%08x",num_arry[i]);
11163 env_set(str_temp1, str_temp2);
11164 run_command("save",0);
11165 }
11166
11167 {
11168 lcdlr_temp_count=0;
11169 sprintf(buf, "0x%08x", lcdlr_temp_count);
11170 printf( "%s", buf);
11171 env_set(env_lcdlr_temp_count, buf);
11172 run_command("save",0);
11173 }
11174
11175 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 1),1);
11176 printf("\nstr=%s\n",str);
11177 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
11178 //printf("\nstr=%s\n",str);
11179 ddr_test_watchdog_clear();
11180 run_command(str,0);
11181 ddr_test_watchdog_clear();
11182 ddr_udelay(2000000);
11183 dq_lcd_bdl_value_bdlr0_status_a=4;
11184
11185 }
11186 else if (dq_lcd_bdl_value_bdlr0_status_a==3)
11187 {
11188 temp_s= env_get(env_lcdlr_temp_count);
11189 if (temp_s)
11190 {
11191 lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
11192 }
11193 dq_lcd_bdl_value_bdlr0_max_a=lcdlr_temp_count;
11194 dq_lcd_bdl_value_bdlr0_status_a=4;
11195 }
11196
11197 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
11198 //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
11199 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
11200 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
11201 //ddr_udelay(1000000);
11202 // num_to_env(varname,num_arry);
11203
11204 {
11205 i=8+lane_step*8+6;
11206 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11207 sprintf(str_temp2,"0x%08x",num_arry[i]);
11208 env_set(str_temp1, str_temp2);
11209 run_command("save",0);
11210 i=8+lane_step*8+7;
11211 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
11212 sprintf(str_temp2,"0x%08x",num_arry[i]);
11213 env_set(str_temp1, str_temp2);
11214 run_command("save",0);
11215 }
11216 run_command("reset",0);
11217 }
11218
11219 }
11220
11221 /*
11222 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
11223 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
11224 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
11225 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
11226 printf("\nstr=%s\n",str);
11227 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
11228 //printf("\nstr=%s\n",str);
11229 ddr_test_watchdog_clear();
11230 run_command(str,0);
11231 ddr_test_watchdog_clear();
11232 dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
11233 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
11234 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
11235 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
11236 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
11237 num_to_env(varname,num_arry);
11238 run_command("reset",0);
11239 }
11240
11241 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
11242 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
11243 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
11244 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
11245 printf("\nstr=%s\n",str);
11246 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
11247 //printf("\nstr=%s\n",str);
11248 ddr_test_watchdog_clear();
11249 run_command(str,0);
11250 ddr_test_watchdog_clear();
11251 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
11252 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
11253 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
11254 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
11255 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
11256 num_to_env(varname,num_arry);
11257 run_command("reset",0);
11258 }
11259 */
11260
11261
11262 ddr_test_watchdog_disable(); //s
11263 {printf("close watchdog\n");
11264 }
11265
11266
11267 }
11268
11269
11270
11271 }
11272
11273 if (channel_b_en)
11274 {//*(char *)(argv2[0])="b";
11275 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
11276 printf("\ntest dqs window lane b\n");
11277 for ((lane_step=0);(lane_step<8);(lane_step++))
11278 {
11279 //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
11280 //printf("\nstr=%s\n",str);
11281 sprintf(str,"ddr_tune_dqs_step b 0 0x%08x %d",ddr_test_size,( lane_step));
11282 printf("\nstr=%s\n",str);
11283 run_command(str,0);
11284
11285 }
11286 }
11287
11288 unsigned int acmdlr= 0;
11289 unsigned int delay_step_x100= 0;
11290 if (channel_a_en)
11291 {
11292 acmdlr=((readl((DDR0_PUB_ACMDLR)))&ACLCDLR_MAX);
11293 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
11294 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
11295 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
11296
11297 for ((lane_step=0);(lane_step<4);(lane_step++))
11298 {
11299 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
11300 lane_step,
11301 dq_lcd_bdl_value_wdq_org_a[lane_step],
11302 dq_lcd_bdl_value_wdq_min_a[lane_step],dq_lcd_bdl_value_wdq_max_a[lane_step],
11303 dq_lcd_bdl_value_rdqs_org_a[lane_step],
11304 dq_lcd_bdl_value_rdqs_min_a[lane_step],dq_lcd_bdl_value_rdqs_max_a[lane_step]);
11305 }
11306 {
11307 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
11308 4,
11309 dq_lcd_bdl_value_aclcdlr_org_a,
11310 dq_lcd_bdl_value_aclcdlr_min_a,dq_lcd_bdl_value_aclcdlr_max_a,
11311 dq_lcd_bdl_value_bdlr0_org_a,
11312 dq_lcd_bdl_value_bdlr0_min_a,dq_lcd_bdl_value_bdlr0_max_a);
11313 }
11314 printf("\n\n-----------------------------------------------------------------------------\n\n");
11315 {
11316 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
11317 clk_setup ps| clk_hold ps|adj_percent[100]\n");
11318
11319 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
11320 4,
11321 dq_lcd_bdl_value_aclcdlr_org_a,
11322 (((dq_lcd_bdl_value_aclcdlr_max_a-dq_lcd_bdl_value_aclcdlr_org_a)*delay_step_x100
11323 )/100),
11324 (((dq_lcd_bdl_value_aclcdlr_org_a-dq_lcd_bdl_value_aclcdlr_min_a)*delay_step_x100
11325 )/100),
11326
11327 0,
11328 0,
11329 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
11330 2*dq_lcd_bdl_value_aclcdlr_org_a));
11331 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
11332 4,
11333 dq_lcd_bdl_value_bdlr0_org_a,
11334 0,
11335 0,
11336 (((dq_lcd_bdl_value_bdlr0_org_a-dq_lcd_bdl_value_bdlr0_min_a)*delay_step_x100
11337 )/100),
11338 (((dq_lcd_bdl_value_bdlr0_max_a-dq_lcd_bdl_value_bdlr0_org_a)*delay_step_x100
11339 )/100),
11340
11341 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
11342 2*dq_lcd_bdl_value_bdlr0_org_a));
11343 }
11344 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
11345 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
11346
11347
11348 for ((lane_step=0);(lane_step<4);(lane_step++))
11349 {
11350 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
11351 lane_step,
11352 dq_lcd_bdl_value_wdq_org_a[lane_step],
11353 (((dq_lcd_bdl_value_wdq_max_a[lane_step]-dq_lcd_bdl_value_wdq_org_a[lane_step])*delay_step_x100
11354 )/100),
11355 (((dq_lcd_bdl_value_wdq_org_a[lane_step]-dq_lcd_bdl_value_wdq_min_a[lane_step])*delay_step_x100
11356 )/100),
11357
11358 0,
11359 0,
11360 100*(dq_lcd_bdl_value_wdq_max_a[lane_step]+dq_lcd_bdl_value_wdq_min_a[lane_step])/(
11361 2*dq_lcd_bdl_value_wdq_org_a[lane_step]));
11362
11363 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
11364 lane_step,
11365 dq_lcd_bdl_value_rdqs_org_a[lane_step],
11366 0,
11367 0,
11368
11369 (((dq_lcd_bdl_value_rdqs_org_a[lane_step]-dq_lcd_bdl_value_rdqs_min_a[lane_step])*delay_step_x100
11370 )/100),
11371 (((dq_lcd_bdl_value_rdqs_max_a[lane_step]-dq_lcd_bdl_value_rdqs_org_a[lane_step])*delay_step_x100
11372 )/100),
11373 100*(dq_lcd_bdl_value_rdqs_max_a[lane_step]+dq_lcd_bdl_value_rdqs_min_a[lane_step])/(
11374 2*dq_lcd_bdl_value_rdqs_org_a[lane_step]));
11375
11376
11377
11378 }
11379 }
11380
11381
11382
11383 if (channel_b_en)
11384 {
11385 for ((lane_step=0);(lane_step<4);(lane_step++))
11386 {;
11387 }
11388 }
11389
11390 return reg_value;
11391}
11392
11393
11394U_BOOT_CMD(
11395 ddr_dqs_window_step, 6, 1, do_ddr_test_dqs_window_step,
11396 "DDR tune dqs function",
11397 "ddr_dqs_window_step a 0 0x800000 1 or ddr_dqs_window_step b 0 0x800000 5\n dcache off ? \n"
11398);
11399
11400///*
11401
11402#endif
11403
11404int do_ddr2pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
11405{
11406
11407#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
11408 extern int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
11409 do_ddr2pll_g12_cmd(cmdtp,flag,argc, argv);
11410 return 1;
11411#endif
11412
11413#define DDR_TEST_CMD_TEST_ZQ 0
11414#define DDR_TEST_CMD_TEST_AC_BIT_SETUP 1
11415#define DDR_TEST_CMD_TEST_AC_BIT_HOLD 2
11416#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_SETUP 3
11417#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_HOLD 4
11418#define DDR_TEST_CMD_TEST_DATA_READ_BIT_SETUP 5
11419#define DDR_TEST_CMD_TEST_DATA_READ_BIT_HOLD 6
11420#define DDR_TEST_CMD_TEST_DATA_VREF 7
11421#define DDR_TEST_CMD_TEST_CLK_INVETER 8
11422
11423#define DDR_TEST_CMD_TEST_FULLTEST 0xffffffff
11424 char *endp;
11425 unsigned int pll, zqcr;
11426 unsigned int zqpr_soc_dram=0;
11427 unsigned int ddr_test_cmd_soc_vref=0;
11428 unsigned int ddr_test_cmd_dram_vref=0;//0x3f;
11429 unsigned int ddr_test_cmd_zq_vref=0;//0x3f;
11430
11431
11432 unsigned int ddr_full_test_enable=0;
11433 /*
11434#define DDR3_DRV_40OHM 0
11435#define DDR3_DRV_34OHM 1
11436#define DDR3_ODT_0OHM 0
11437#define DDR3_ODT_60OHM 1
11438#define DDR3_ODT_120OHM 2
11439#define DDR3_ODT_40OHM 3
11440#define DDR3_ODT_20OHM 4
11441#define DDR3_ODT_30OHM 5
11442
11443 // lpddr2 drv odt
11444#define LPDDR2_DRV_34OHM 1
11445#define LPDDR2_DRV_40OHM 2
11446#define LPDDR2_DRV_48OHM 3
11447#define LPDDR2_DRV_60OHM 4
11448#define LPDDR2_DRV_80OHM 6
11449#define LPDDR2_DRV_120OHM 7
11450#define LPDDR2_ODT_0OHM 0
11451
11452 // lpddr3 drv odt
11453#define LPDDR3_DRV_34OHM 1
11454#define LPDDR3_DRV_40OHM 2
11455#define LPDDR3_DRV_48OHM 3
11456#define LPDDR3_DRV_60OHM 4
11457#define LPDDR3_DRV_80OHM 6
11458#define LPDDR3_DRV_34_40OHM 9
11459#define LPDDR3_DRV_40_48OHM 10
11460#define LPDDR3_DRV_34_48OHM 11
11461#define LPDDR3_ODT_0OHM 0
11462#define LPDDR3_ODT_60OHM 1
11463#define LPDDR3_ODT_12OHM 2
11464#define LPDDR3_ODT_240HM 3
11465
11466#define DDR4_DRV_34OHM 0
11467#define DDR4_DRV_48OHM 1
11468#define DDR4_ODT_0OHM 0
11469#define DDR4_ODT_60OHM 1
11470#define DDR4_ODT_120OHM 2
11471#define DDR4_ODT_40OHM 3
11472#define DDR4_ODT_240OHM 4
11473#define DDR4_ODT_48OHM 5
11474#define DDR4_ODT_80OHM 6
11475#define DDR4_ODT_34OHM 7
11476*/
11477 printf("\nargc== 0x%08x\n", argc);
11478 int i ;
11479 for (i = 0;i<argc;i++)
11480 {
11481 printf("\nargv[%d]=%s\n",i,argv[i]);
11482 }
11483
11484 unsigned int soc_data_drv_odt = 0;
11485 //unsigned int dram_drv = 0;
11486 //unsigned int dram_odt = 0;
11487 /* need at least two arguments */
11488 if (argc < 2)
11489 goto usage;
11490
11491 pll = simple_strtoull_ddr(argv[1], &endp,0);
11492 if (*argv[1] == 0 || *endp != 0) {
11493 printf ("Error: Wrong format parament!\n");
11494 return 1;
11495 }
11496 if (argc >2)
11497 {
11498 zqcr = simple_strtoull_ddr(argv[2], &endp, 0);
11499 if (*argv[2] == 0 || *endp != 0) {
11500 zqcr = 0;
11501 }
11502 }
11503 else
11504 {
11505 zqcr = 0;
11506 }
11507
11508 if (zqcr == 0xffffffff)
11509 {
11510 ddr_full_test_enable=1;
11511 zqcr=0;}
11512
11513 if (argc >3)
11514 {
11515 // soc_data_drv_odt=zqpr_soc_dram&0xfffff;
11516 // dram_drv=(zqpr_soc_dram>>20)&0xf;
11517 // dram_odt=(zqpr_soc_dram>>24)&0xf;
11518 //bit28 enable soc_zqpr ,bit 29 enable dram_drv bit 30 enable dram_odt
11519 zqpr_soc_dram = simple_strtoull_ddr(argv[3], &endp, 0);
11520 if (*argv[3] == 0 || *endp != 0) {
11521 zqpr_soc_dram = 0;
11522 }
11523 }
11524 else
11525 {
11526 zqpr_soc_dram = 0;
11527 }
11528
11529 if (argc >4)
11530 {
11531 ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
11532 if (*argv[4] == 0 || *endp != 0) {
11533 ddr_test_cmd_soc_vref = 0;
11534 }
11535 }
11536 else
11537 {
11538 ddr_test_cmd_soc_vref = 0;
11539 }
11540 if (argc >5)
11541 {
11542 ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
11543 if (*argv[5] == 0 || *endp != 0) {
11544 ddr_test_cmd_dram_vref = 0;
11545 }
11546 }
11547 unsigned int soc_dram_hex_dec=0;
11548 if (argc >6)
11549 {
11550 soc_dram_hex_dec = simple_strtoull_ddr(argv[6], &endp, 0);
11551 if (*argv[6] == 0 || *endp != 0) {
11552 soc_dram_hex_dec = 0;
11553 }
11554 }
11555 if (argc >7)
11556 {
11557 ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
11558 if (*argv[7] == 0 || *endp != 0) {
11559 ddr_test_cmd_zq_vref = 0;
11560 }
11561 }
11562
11563
11564
11565 unsigned int soc_dram_drv_odt_use_vlaue=0;
11566 unsigned int soc_ac_drv=0;
11567 unsigned int soc_ac_odt=0;
11568 unsigned int soc_data_drv=0;
11569 unsigned int soc_data_odt=0;
11570 unsigned int dram_drv=0;
11571 unsigned int dram_odt=0;
11572 unsigned int soc_data_drv_odt_adj_enable=0;
11573 unsigned int dram_data_drv_adj_enable=0;
11574 unsigned int dram_data_odt_adj_enable=0;
11575
11576 unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
11577 unsigned int zq1pr_org = rd_reg(DDR0_PUB_ZQ1PR);
11578 unsigned int pub_dcr= rd_reg(DDR0_PUB_DCR);
11579#define DDR_TYPE_LPDDR2 0
11580#define DDR_TYPE_LPDDR3 1
11581#define DDR_TYPE_DDR3 3
11582#define DDR_TYPE_DDR4 4
11583 unsigned int ddr_type= pub_dcr&0x7; //0 -lpddr2 | 1- lpddr3 | 2- rev | 3 -ddr3 | 4- ddr4
11584 // unsigned int zq2pr_org = rd_reg(DDR0_PUB_ZQ2PR);
11585 if (argc >8)
11586 {
11587 soc_dram_drv_odt_use_vlaue = simple_strtoull_ddr(argv[8], &endp, 0);
11588 if (*argv[8] == 0 || *endp != 0) {
11589 soc_dram_drv_odt_use_vlaue = 0;
11590 }
11591 }
11592 if (soc_dram_drv_odt_use_vlaue)
11593 {if(zqcr)
11594 {printf("zqcr[0x%08x],\n", zqcr);
11595 {
11596 soc_ac_drv=zqcr%100;
11597 if (soc_ac_drv>100)
11598 {soc_ac_drv=0;}
11599 if (soc_ac_drv == 0)
11600 {soc_ac_drv=1;}
11601 soc_ac_drv=(480/soc_ac_drv)-1;
11602
11603 if (ddr_type == DDR_TYPE_DDR3)
11604 {
11605 if (soc_ac_drv>0xf)
11606 {soc_ac_drv=zq0pr_org&0xf;}
11607 }
11608 if (ddr_type == DDR_TYPE_DDR4)
11609 {
11610 if (soc_ac_drv>0xf)
11611 {soc_ac_drv=(zq0pr_org>>8)&0xf;}
11612 }
11613 }
11614
11615
11616 {
11617 soc_ac_odt=zqcr/100;
11618 if (soc_ac_odt>240)
11619 {soc_ac_odt=480;}
11620 if (soc_ac_odt == 0)
11621 {soc_ac_odt=1;}
11622
11623
11624 if (ddr_type == DDR_TYPE_DDR3)
11625 {
11626 soc_ac_odt=(360/soc_ac_odt)-1;
11627 if (soc_ac_odt>0xf)
11628 {soc_ac_odt=(zq0pr_org>>4)&0xf;}
11629 }
11630 if (ddr_type == DDR_TYPE_DDR4)
11631 {
11632 soc_ac_odt=(480/soc_ac_odt)-1;
11633 if (soc_ac_odt>0xf)
11634 {soc_ac_odt=(zq0pr_org>>16)&0xf;}
11635 }
11636 }
11637
11638 zqcr=(soc_ac_odt<<16)|(soc_ac_drv<<12)|(soc_ac_drv<<8)|(soc_ac_odt<<4)|(soc_ac_drv);
11639 printf("zqcr[0x%08x],soc_ac_odt [0x%08x],soc_ac_drv [0x%08x]\n", zqcr,soc_ac_odt,soc_ac_drv);
11640 }
11641 if (zqpr_soc_dram)
11642 {printf("zqpr_soc_dram[0x%08x],\n", zqpr_soc_dram);
11643 {
11644 soc_data_drv=zqpr_soc_dram%100;
11645 printf("soc_data_drv[%d],\n", soc_data_drv);
11646 if (soc_data_drv>100)
11647 {soc_data_drv=0;
11648
11649 }
11650 if (soc_data_drv == 0)
11651 {soc_data_drv=1;
11652 //soc_data_drv_odt_adj_enable=0;
11653 }
11654 else
11655 {//soc_data_drv_odt_adj_enable=1;
11656 }
11657 soc_data_drv=(480/soc_data_drv)-1;
11658
11659 if (ddr_type == DDR_TYPE_DDR3)
11660 {
11661 if (soc_data_drv>0xf)
11662 {soc_data_drv=zq1pr_org&0xf;}
11663 }
11664 if (ddr_type == DDR_TYPE_DDR4)
11665 {
11666 if (soc_data_drv>0xf)
11667 {soc_data_drv=(zq1pr_org>>8)&0xf;}
11668 }
11669 }
11670
11671
11672 {
11673 soc_data_odt=(zqpr_soc_dram/100)%1000;
11674 printf("soc_data_odt[%d],\n", soc_data_odt);
11675 if (soc_data_odt>240)
11676 {soc_data_odt=360;}
11677 if (soc_data_odt == 0)
11678 {soc_data_odt=1;}
11679
11680
11681 if (ddr_type == DDR_TYPE_DDR3)
11682 {
11683 soc_data_odt=(360/soc_data_odt)-1;
11684 if (soc_data_odt>0xf)
11685 {soc_data_odt=(zq1pr_org>>4)&0xf;}
11686 }
11687 if (ddr_type == DDR_TYPE_DDR4)
11688 {
11689 soc_data_odt=(480/soc_data_odt)-1;
11690 if (soc_data_odt>0xf)
11691 {soc_data_odt=(zq1pr_org>>16)&0xf;}
11692 }
11693
11694 }
11695
11696 soc_data_drv_odt_adj_enable=1;
11697
11698 {
11699 dram_drv=(zqpr_soc_dram/100000)%100;
11700 printf("dram_drv[%d],\n", dram_drv);
11701
11702 if (dram_drv>100)
11703 {dram_drv=0;}
11704 if (dram_drv == 0)
11705 {
11706 dram_data_drv_adj_enable=0;}
11707 else
11708 {dram_data_drv_adj_enable=1;
11709 }
11710
11711 if (ddr_type == DDR_TYPE_DDR3)
11712 {
11713 if (dram_drv >= 40)
11714 {dram_drv=0;}
11715
11716 else
11717 {dram_drv=1;
11718 }
11719 }
11720
11721
11722 if (ddr_type == DDR_TYPE_DDR4)
11723 {
11724 if (dram_drv<48)
11725 {dram_drv=0;}
11726
11727 else
11728 {dram_drv=1;
11729 }
11730 }
11731 }
11732
11733
11734 {
11735 dram_odt=(zqpr_soc_dram/100000)/100;
11736 printf("dram_odt[%d],\n", dram_odt);
11737 if (dram_odt>240)
11738 {dram_odt=480;}
11739 if (dram_odt == 0)
11740 {
11741 dram_data_odt_adj_enable=0;
11742 }
11743 else
11744 {dram_data_odt_adj_enable=1;
11745 }
11746
11747
11748 if (ddr_type == DDR_TYPE_DDR3)
11749 {
11750 if (dram_odt>160)
11751 {dram_odt=0;}
11752 else if (dram_odt>90)
11753 {dram_odt=2;}
11754 else if (dram_odt>50)
11755 {dram_odt=1;}
11756 else if (dram_odt>35)
11757 {dram_odt=3;}
11758 else if (dram_odt>25)
11759 {dram_odt=5;}
11760 else if (dram_odt<=25)
11761 {dram_odt=4;}
11762
11763 }
11764 if (ddr_type == DDR_TYPE_DDR4)
11765 {
11766 if (dram_odt>280)
11767 {dram_odt=0;}
11768 else if (dram_odt>180)
11769 {dram_odt=4;}
11770 else if (dram_odt>100)
11771 {dram_odt=2;}
11772 else if (dram_odt>70)
11773 {dram_odt=6;}
11774 else if (dram_odt>54)
11775 {dram_odt=1;}
11776 else if (dram_odt>44)
11777 {dram_odt=5;}
11778 else if (dram_odt>37)
11779 {dram_odt=3;}
11780 else if (dram_odt<=34)
11781 {dram_odt=7;}
11782
11783 }
11784
11785
11786
11787 }
11788
11789 zqpr_soc_dram=(dram_data_odt_adj_enable<<30)|(dram_data_drv_adj_enable<<29)|(soc_data_drv_odt_adj_enable<<28)|
11790 (dram_odt<<24)|(dram_drv<<20)|(soc_data_odt<<16)|(soc_data_drv<<12)|(soc_data_drv<<8)|(soc_data_odt<<4)|(soc_data_drv);
11791 }
11792 }
11793
11794
11795 if (soc_dram_hex_dec)
11796 {
11797 if (argc >4)
11798 {
11799 ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
11800 if (*argv[4] == 0 || *endp != 0) {
11801 ddr_test_cmd_soc_vref = 0;
11802 }
11803 }
11804 else
11805 {
11806 ddr_test_cmd_soc_vref = 0;
11807 }
11808 if (argc >5)
11809 {
11810 ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
11811 if (*argv[5] == 0 || *endp != 0) {
11812 ddr_test_cmd_dram_vref = 0;
11813 }
11814 }
11815 if (argc >7)
11816 {
11817 ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
11818 if (*argv[7] == 0 || *endp != 0) {
11819 ddr_test_cmd_zq_vref = 0;
11820 }
11821 }
11822 if (ddr_test_cmd_soc_vref)
11823 {
11824 if (ddr_test_cmd_soc_vref<45)
11825 ddr_test_cmd_soc_vref=45;
11826 if (ddr_test_cmd_soc_vref>88)
11827 ddr_test_cmd_soc_vref=88;
11828 ddr_test_cmd_soc_vref=(ddr_test_cmd_soc_vref*100-4407)/70;
11829 }
11830
11831 if (ddr_test_cmd_dram_vref)
11832 {
11833 if (ddr_test_cmd_dram_vref<45)
11834 ddr_test_cmd_dram_vref=45;
11835 if (ddr_test_cmd_dram_vref>92)
11836 ddr_test_cmd_dram_vref=92;
11837 if (ddr_test_cmd_dram_vref>60) {
11838 ddr_test_cmd_dram_vref=(ddr_test_cmd_dram_vref*100-6000)/65;
11839 }
11840 else{
11841 ddr_test_cmd_dram_vref=((ddr_test_cmd_dram_vref*100-4500)/65)|(1<<6);
11842 }
11843 }
11844
11845
11846 printf("\nSet ddr_test_cmd_dram_vref [0x%08x]\n",ddr_test_cmd_dram_vref);
11847 if (ddr_test_cmd_zq_vref == 0)
11848 ddr_test_cmd_zq_vref=0;
11849 if (ddr_test_cmd_zq_vref) {
11850 if (ddr_test_cmd_zq_vref<45)
11851 ddr_test_cmd_zq_vref=45;
11852 if (ddr_test_cmd_zq_vref>88)
11853 ddr_test_cmd_zq_vref=88;
11854 ddr_test_cmd_zq_vref=(ddr_test_cmd_zq_vref*100-4407)/70;
11855 }
11856 }
11857
11858 //if(ddr_test_cmd_type==DDR_TEST_CMD_TEST_AC_BIT_HOLD)
11859 //{if (ddr_test_cmd_clk_seed ==0)
11860 //ddr_test_cmd_clk_seed = 0x3f;
11861 //if (ddr_test_cmd_acbdl_x_seed ==0)
11862 //ddr_test_cmd_acbdl_x_seed = 0x3f;
11863 //}
11864
11865#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
11866 writel(zqcr | (0x3c << 24), PREG_STICKY_REG0);
11867#else
11868 writel(zqcr | (0xf13 << 20), PREG_STICKY_REG0);
11869#endif
11870#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
11871 writel((ddr_test_cmd_zq_vref<<24)|(ddr_test_cmd_soc_vref<<8)|ddr_test_cmd_dram_vref , PREG_STICKY_REG9);
11872 writel((zqpr_soc_dram<<0) , PREG_STICKY_REG8);
11873 soc_data_drv_odt=zqpr_soc_dram&0xfffff;
11874 dram_drv=(zqpr_soc_dram>>20)&0xf;
11875 dram_odt=(zqpr_soc_dram>>24)&0xf;
11876 printf("setting zqpr_soc_dram [0x%08x],..bit28 enable soc_zqpr , bit 29 enable dram_drv, bit 30 enable dram_odt\n", zqpr_soc_dram);
11877 printf("soc_data_drv_odt [0x%08x],dram_drv [0x%08x],dram_odt [0x%08x]\n", soc_data_drv_odt,dram_drv,dram_odt);
11878 if (ddr_full_test_enable)
11879 {
11880 pll=(ddr_full_test_enable<<21)|pll;
11881 printf("ddr_full_test_enable %08x,set sticky reg1 bit 21 1\n", ddr_full_test_enable);
11882 }
11883
11884#endif
11885
11886
11887 writel(pll, PREG_STICKY_REG1);
11888
11889 printf("Set pll done [0x%08x]\n", readl(PREG_STICKY_REG1));
11890 printf("Set STICKY_REG0 [0x%08x]\n", readl(PREG_STICKY_REG0));
11891#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
11892 printf("Set STICKY_REG9 [0x%08x]\n", readl(PREG_STICKY_REG9));
11893 printf("Set STICKY_REG8 [0x%08x]\n", readl(PREG_STICKY_REG8));
11894
11895#endif
11896 printf("\nbegin reset 111...........\n");
11897 printf("\nbegin reset 2...........\n");
11898 printf("\nbegin reset 3...........\n");
11899
11900#ifdef CONFIG_M8B
11901 printf(" t1 \n");
11902 writel(0xf080000 | 2000, WATCHDOG_TC);
11903#else
11904 printf(" t2 \n");
11905 // writel(WATCHDOG_TC, 0xf400000 | 2000);
11906 // *P_WATCHDOG_RESET = 0;
11907 ddr_test_watchdog_reset_system();
11908#endif
11909 while (1) ;
11910 return 0;
11911
11912usage:
11913
11914 printf(" ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n");
11915 printf("example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n");
11916 printf("or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
11917 printf("or ddr_test_cmd 0x17 1200 6034 0603406034 0 0 0 0 1 \n");
11918 printf("setting zqpr_soc_dram ,..bit28 enable soc_zqpr , bit 29 enabe dram_drv, bit 30 enable dram_odt\n");
11919 printf("setting zqpr_soc_dram ,bit0-bit19 soc_data_drv_odt,bit20-bit24 dram_drv , bit24-bit28 dram_odt\n");
11920 printf("setting zqpr_soc_dram ,bit0-bit19 bit 0-7 use for ddr3��bit8-19 use for ddr4,odt_down_up\n");
11921 printf("setting zqpr_soc_dram ,soc_drv=(480/((setting)+1));ddr4---soc_odt=(480/(setting)+1));ddr3---soc_odt=(360/(setting)+1));\n");
11922
11923 printf(" DDR3_DRV_40OHM 0\n");
11924 printf(" DDR3_DRV_34OHM 1\n\n");
11925
11926 printf(" DDR3_ODT_0OHM 0\n");
11927 printf(" DDR3_ODT_60OHM 1\n");
11928 printf(" DDR3_ODT_120OHM 2\n");
11929 printf(" DDR3_ODT_40OHM 3\n");
11930 printf(" DDR3_ODT_20OHM 4\n");
11931 printf(" DDR3_ODT_30OHM 5\n\n\n");
11932
11933 printf(" LPDDR2_DRV_34OHM 1\n");
11934 printf(" LPDDR2_DRV_40OHM 2\n");
11935 printf(" LPDDR2_DRV_48OHM 3\n");
11936 printf(" LPDDR2_DRV_60OHM 4\n");
11937 printf(" LPDDR2_DRV_80OHM 6\n");
11938 printf(" LPDDR2_DRV_120OHM 7\n\n");
11939
11940 printf(" LPDDR2_ODT_0OHM 0\n\n\n");
11941
11942
11943 printf(" LPDDR3_DRV_34OHM 1\n");
11944 printf(" LPDDR3_DRV_40OHM 2\n");
11945 printf(" LPDDR3_DRV_48OHM 3\n");
11946 printf(" LPDDR3_DRV_60OHM 4\n");
11947 printf(" LPDDR3_DRV_80OHM 6\n");
11948 printf(" LPDDR3_DRV_34_40OHM 9\n");
11949 printf(" LPDDR3_DRV_40_48OHM 10\n");
11950 printf(" LPDDR3_DRV_34_48OHM 11\n\n");
11951
11952 printf(" LPDDR3_ODT_0OHM 0\n");
11953 printf(" LPDDR3_ODT_60OHM 1\n");
11954 printf(" LPDDR3_ODT_12OHM 2\n");
11955 printf(" LPDDR3_ODT_240HM 3\n\n\n");
11956
11957 printf(" DDR4_DRV_34OHM 0\n");
11958 printf(" DDR4_DRV_48OHM 1\n\n");
11959
11960 printf(" DDR4_ODT_0OHM 0\n");
11961 printf(" DDR4_ODT_60OHM 1\n");
11962 printf(" DDR4_ODT_120OHM 2\n");
11963 printf(" DDR4_ODT_40OHM 3\n");
11964 printf(" DDR4_ODT_240OHM 4\n");
11965 printf(" DDR4_ODT_48OHM 5\n");
11966 printf(" DDR4_ODT_80OHM 6\n");
11967 printf(" DDR4_ODT_34OHM 7\n\n\n\n");
11968
11969
11970 cmd_usage(cmdtp);
11971 return 1;
11972}
11973
11974int do_ddr_uboot_new_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
11975{
11976 //ddr_test_cmd 0x36 0x20180030 0x1 cmd_offset cmd_value value_size reset_enable
11977#if 1
11978 //#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
11979 //#define DDR_STICKY_MAGIC_NUMBER 0x20180000
11980 //#define DDR_CHIP_ID 0x30
11981 //#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
11982 //#define DDR_STICKY_SOURCE_SRAM 0x2
11983 //dmc sticky reg default not 0. need use common sticky reg as identity
11984
11985#if 0
11986 unsigned int ddr_pll = rd_reg(AM_DDR_PLL_CNTL0);
11987 extern int pll_convert_to_ddr_clk_g12a(unsigned int);
11988 global_ddr_clk=pll_convert_to_ddr_clk_g12a(ddr_pll);
11989#endif
11990#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
11991#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
11992
11993#define G12_DMC_STICKY_0 ((0x0000 << 2) + 0xff638800)
11994 uint32_t magic_chipid= 0;//rd_reg(P_PREG_STICKY_REG0);
11995 uint32_t sticky_cmd = 0;//rd_reg(P_PREG_STICKY_REG1);
11996 uint32_t cmd_offset = 0;
11997 uint32_t cmd_value = 0;
11998 uint32_t reset_enable = 0;
11999 uint32_t value_size = 4;
12000 char *endp;
12001 //bit 0 trigger effect reset.
12002 if ((magic_chipid) != ((DDR_STICKY_MAGIC_NUMBER+DDR_CHIP_ID)&0xffff0000)) {
12003 //magic number not match
12004 // magic_chipid=DDR_STICKY_MAGIC_NUMBER+DDR_CHIP_ID;
12005 // sticky_cmd=DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD;
12006 printf("sticky0 magic not match\n");
12007
12008 }
12009
12010
12011 // wr_reg(P_PREG_STICKY_REG0, 0);
12012 // wr_reg(P_PREG_STICKY_REG1, 0);
12013
12014
12015
12016 printf("\nargc== 0x%08x\n", argc);
12017 int i ;
12018 for (i = 0;i<argc;i++)
12019 {
12020 printf("\nargv[%d]=%s\n",i,argv[i]);
12021 }
12022
12023
12024
12025 if (argc < 2)
12026 goto usage;
12027
12028 magic_chipid = simple_strtoull_ddr(argv[1], &endp,0);
12029 if (*argv[1] == 0 || *endp != 0) {
12030 printf ("Error: Wrong format parament!\n");
12031 return 1;
12032 }
12033 if (argc >2)
12034 {
12035 sticky_cmd = simple_strtoull_ddr(argv[2], &endp, 0);
12036 if (*argv[2] == 0 || *endp != 0) {
12037 sticky_cmd = 0;
12038 }
12039 }
12040
12041 if (argc >3)
12042 {
12043 cmd_offset = simple_strtoull_ddr(argv[3], &endp, 0);
12044 if (*argv[3] == 0 || *endp != 0) {
12045 cmd_offset = 0;
12046 }
12047 }
12048 if (argc >4)
12049 {
12050 cmd_value= simple_strtoull_ddr(argv[4], &endp, 0);
12051 if (*argv[4] == 0 || *endp != 0) {
12052 cmd_value = 0;
12053 }
12054 }
12055 if (argc >5)
12056 {
12057 value_size= simple_strtoull_ddr(argv[5], &endp, 0);
12058 if (*argv[5] == 0 || *endp != 0) {
12059 value_size = 4;
12060 }
12061 }
12062 if (argc >6)
12063 {
12064 reset_enable= simple_strtoull_ddr(argv[6], &endp, 0);
12065 if (*argv[6] == 0 || *endp != 0) {
12066 reset_enable = 0;
12067 }
12068 }
12069 printf("cmd_offset[0x%08x}==cmd_value [0x%08x]\n", cmd_offset,cmd_value);
12070 writel((magic_chipid&0xffff0000)|(rd_reg(PREG_STICKY_REG0)), PREG_STICKY_REG0);
12071 writel(sticky_cmd, PREG_STICKY_REG1);
12072
12073 uint32_t read_value = 0;
12074 if (value_size)
12075 {
12076 read_value=rd_reg(G12_DMC_STICKY_0+((cmd_offset/4)<<2));
12077 if (value_size == 1) {
12078 wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xff<<((cmd_offset%4)*8))))));
12079 }
12080 if (value_size == 2) {
12081 wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8))))));
12082 }
12083 if (value_size == 4) {
12084 // wr_reg((G12_DMC_STICKY_0+cmd_offset/4), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8))))));
12085 wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), cmd_value);
12086 }
12087
12088
12089
12090
12091 printf("DMC_STICKY_0_ offset[0x%08x}== [0x%08x]\n", cmd_offset,readl((G12_DMC_STICKY_0+((cmd_offset/4)<<2))));
12092 }
12093
12094
12095 printf("PREG_STICKY_REG0== [0x%08x]\n", readl(PREG_STICKY_REG0));
12096
12097 if (reset_enable)
12098 {
12099 ddr_test_watchdog_reset_system();
12100
12101 while (1) ;
12102 }
12103 return 0;
12104
12105usage:
12106
12107
12108
12109
12110
12111 cmd_usage(cmdtp);
12112
12113#endif
12114 return 1;
12115}
12116
12117
12118#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
12119#else
12120int do_ddr_test_ac_bit_setup_hold_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
12121{
12122 printf("\nEnter test ddr ac bit window function\n");
12123 // if(!argc)
12124 // goto DDR_TUNE_DQS_START;
12125 printf("\nargc== 0x%08x\n", argc);
12126 unsigned int ddl_100step_ps= 0;
12127
12128 unsigned int temp_test_error= 0;
12129 unsigned int temp_count= 0;
12130 unsigned int temp_reg_value[40];
12131
12132 char *endp;
12133 // unsigned int *p_start_addr;
12134 unsigned int test_ac_setup_hold=0;
12135 //unsigned int testing_seed=0;
12136 // unsigned int test_lane_step_rdqs_flag=0;
12137 unsigned int test_acbdl=0;
12138 // unsigned int test_times=1;
12139 unsigned int reg_add=0;
12140 unsigned int reg_base_adj=0;
12141 unsigned int channel_a_en = 0;
12142 unsigned int channel_b_en = 0;
12143
12144
12145 unsigned int acbdlr0_reg_org=0;
12146 unsigned int acbdlr_x_reg_org=0;
12147 unsigned int acbdlr_x_reg_hold_min=0;
12148 // unsigned int acbdlr_x_reg_hold_min=0;
12149 unsigned int acbdlr_x_reg_setup_max=0;
12150 // unsigned int acbdlr_x_reg_setup_max=0;
12151 // unsigned int dq_lcd_bdl_reg_left=0;
12152 // unsigned int dq_lcd_bdl_reg_right=0;
12153
12154
12155 // unsigned int dq_lcd_bdl_reg_left_min=0;
12156 // unsigned int dq_lcd_bdl_reg_right_min=0;
12157
12158 unsigned int dq_lcd_bdl_temp_reg_value=0;
12159
12160
12161 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
12162 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
12163
12164
12165 // unsigned int dq_lcd_bdl_temp_reg_lef;
12166 // unsigned int dq_lcd_bdl_temp_reg_rig;
12167
12168
12169 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
12170
12171
12172 {
12173 if (argc == 2)
12174 {
12175 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
12176
12177 {channel_a_en = 1;
12178 }
12179 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
12180
12181 {channel_b_en = 1;
12182 }
12183 else
12184 {
12185 goto usage;
12186 }
12187 }
12188 if (argc > 2)
12189 {
12190 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
12191
12192 {channel_a_en = 1;
12193 }
12194 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
12195
12196 {channel_b_en = 1;
12197 }
12198 }
12199 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
12200 if (argc >3) {
12201 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
12202 if (*argv[3] == 0 || *endp != 0)
12203 {
12204 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
12205 }
12206
12207 }
12208 if (argc >4) {
12209 test_ac_setup_hold = 0;
12210 test_ac_setup_hold = simple_strtoull_ddr(argv[4], &endp, 16);
12211 if (*argv[4] == 0 || *endp != 0)
12212 {
12213 test_ac_setup_hold = 0;
12214 }
12215 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
12216 {
12217 test_ac_setup_hold = 0;
12218 }
12219 }
12220 if (test_ac_setup_hold >1)
12221 test_ac_setup_hold = 2;
12222 if (argc >5) {
12223
12224 test_acbdl= simple_strtoull_ddr(argv[5], &endp, 16);
12225 if (*argv[5] == 0 || *endp != 0)
12226 {
12227 test_acbdl = 0;
12228 }
12229 if (test_acbdl>39)
12230 test_acbdl =12;//default test cs0 pin
12231 }
12232 }
12233 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
12234 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
12235 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
12236 printf("\ntest_ac_setup_hold== 0x%08x\n", test_ac_setup_hold);
12237 printf("\ntest_acbdl== 0x%08x\n", test_acbdl);
12238 if ( channel_a_en)
12239 {
12240 //writel((0), 0xc8836c00);
12241 OPEN_CHANNEL_A_PHY_CLK();
12242 }
12243 if ( channel_b_en)
12244 {
12245 OPEN_CHANNEL_B_PHY_CLK();
12246 //writel((0), 0xc8836c00);
12247 }
12248
12249
12250
12251 //save and print org training dqs value
12252 if (channel_a_en || channel_b_en)
12253 {
12254 //dcache_disable();
12255 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
12256
12257 }////save and print org training dqs value
12258 {
12259 ////tune and save training dqs value
12260 if (channel_a_en || channel_b_en)
12261 {
12262
12263 {
12264
12265 if (( channel_a_en) && ( channel_b_en == 0))
12266 {
12267 reg_base_adj=CHANNEL_A_REG_BASE;
12268 }
12269 else if(( channel_b_en)&&( channel_a_en==0))
12270 {
12271 reg_base_adj=CHANNEL_B_REG_BASE;
12272 }
12273 else if ((channel_a_en+channel_b_en)==2)
12274 {
12275 reg_base_adj=CHANNEL_A_REG_BASE;
12276 }
12277 printf("\nshould pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12278 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
12279 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12280
12281
12282 for ((temp_count=0);(temp_count<10);(temp_count++))
12283 {
12284 acbdlr0_9_reg_org[temp_count]=(readl(DDR0_PUB_ACBDLR0+(temp_count<<2)+reg_base_adj));
12285
12286 };
12287
12288
12289 {
12290 ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0+reg_base_adj)))>>16)&0xff);
12291 printf("\nddl_100step_ps== %08d,0_5cycle_ps== %08d,0_5cycle==0x%08x\n", ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)),
12292 ((((readl(DDR0_PUB_ACMDLR0+reg_base_adj)))>>16)&0xff));
12293
12294 reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
12295 acbdlr0_reg_org=readl(DDR0_PUB_ACBDLR0+reg_base_adj);
12296 acbdlr_x_reg_org=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12297 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x\n ",test_acbdl,test_ac_setup_hold);
12298 printf("\nacbdlr0_reg_0x%08x_org==0x%08x | acbdlr_x_reg_0x%08x_org==0x%08x\n ",(DDR0_PUB_ACBDLR0+reg_base_adj),
12299 acbdlr0_reg_org,(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj),acbdlr_x_reg_org);
12300 if (test_ac_setup_hold == 0)
12301 {
12302 printf("\ntest_ac_setup\n ");
12303
12304
12305 //writel(0,(DDR0_PUB_ACBDLR0+reg_base_adj));
12306 dq_lcd_bdl_temp_reg_value=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12307
12308
12309 //{writel((dq_lcd_bdl_temp_reg_value&(~(0xff<<(8*(test_acbdl%4))))),((test_acbdl/4)*4+DDR0_PUB_ACBDLR0+reg_base_adj));
12310 //}
12311
12312
12313
12314 reg_add=(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12315 acbdlr_x_reg_org=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12316 dq_lcd_bdl_temp_reg_value=((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff);
12317 while (dq_lcd_bdl_temp_reg_value<ACBDLR_MAX)
12318 {
12319 temp_test_error=0;
12320 dq_lcd_bdl_temp_reg_value++;
12321 printf("\n reg_add==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_add,dq_lcd_bdl_temp_reg_value,
12322 ((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))));
12323
12324 {
12325 writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12326
12327 }
12328 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
12329
12330 if (temp_test_error)
12331 {
12332 //printf("\nwdqd left edge detect \n");
12333 dq_lcd_bdl_temp_reg_value--;
12334 break;
12335 }
12336 }
12337 printf("\n right edge detect ,reg==0x%08x\n",(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12338 printf("\n org==0x%08x,right edge==0x%08x,value==0x%08x\n ",((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff),dq_lcd_bdl_temp_reg_value,
12339 ((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))));
12340
12341 {acbdlr_x_reg_setup_max=dq_lcd_bdl_temp_reg_value;}
12342
12343 dq_lcd_bdl_temp_reg_value=0;
12344 //writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12345 writel(((acbdlr_x_reg_org)),reg_add);
12346 //test_ac_setup_hold=1;
12347 {
12348 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x acmdlr==0x%08x ddl_100step_ps==%08d\n",test_acbdl,test_ac_setup_hold,
12349 readl(DDR0_PUB_ACMDLR0+reg_base_adj),ddl_100step_ps);
12350 printf("\nacbdlr0_reg_org==0x%08x | acbdlr_x_reg_org==0x%08x\n ",acbdlr0_reg_org,acbdlr_x_reg_org);
12351 printf("acbdlr_x_reg_setup_max 0x%08x \
12352 setup time==0x%08x, %08d ps \n ",
12353 acbdlr_x_reg_setup_max,(acbdlr_x_reg_setup_max-
12354 ((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)),((acbdlr_x_reg_setup_max-
12355 ((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)) *ddl_100step_ps)/100
12356 );
12357 acbdlr0_9_reg_setup_max[test_acbdl]=(acbdlr_x_reg_setup_max-
12358 ((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff));
12359 acbdlr0_9_reg_setup_time[test_acbdl]=((acbdlr_x_reg_setup_max-
12360 ((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)) *ddl_100step_ps)/100;
12361 for ((temp_count=0);(temp_count<10);(temp_count++))
12362 {
12363 writel(((acbdlr0_9_reg_org[temp_count])),(DDR0_PUB_ACBDLR0+(temp_count<<2)+reg_base_adj));
12364
12365 };
12366
12367 }
12368
12369 }
12370
12371 if (test_ac_setup_hold == 1)
12372 {
12373 printf("\ntest_ac_hold 1\n ");
12374 acbdlr0_reg_org=readl(DDR0_PUB_ACBDLR0+reg_base_adj);
12375 acbdlr_x_reg_org=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12376 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x\n ",test_acbdl,test_ac_setup_hold);
12377 printf("\nacbdlr0_reg_org==0x%08x | acbdlr_x_reg_org==0x%08x\n ",acbdlr0_reg_org,acbdlr_x_reg_org);
12378
12379
12380 printf("\nacbdlr0_reg==0x%08x | acbdlr_x_reg==0x%08x\n ",
12381 readl(DDR0_PUB_ACBDLR0+reg_base_adj),readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12382
12383 reg_add=(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12384 dq_lcd_bdl_temp_reg_value=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12385 dq_lcd_bdl_temp_reg_value=((dq_lcd_bdl_temp_reg_value>>(8*(test_acbdl%4)))&0xff);
12386 while (dq_lcd_bdl_temp_reg_value>0)
12387 {
12388 temp_test_error=0;
12389 dq_lcd_bdl_temp_reg_value--;
12390 printf("\n reg==0x%08x, left temp==0x%08x\n ,value==0x%08x ",reg_add,dq_lcd_bdl_temp_reg_value,
12391 ((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))));
12392
12393 {
12394 writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12395
12396 }
12397 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
12398
12399 if (temp_test_error)
12400 {
12401 //printf("\nwdqd left edge detect \n");
12402 dq_lcd_bdl_temp_reg_value++;
12403 break;
12404 }
12405 }
12406 printf("\n left edge detect ,reg==0x%08x\n",(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12407 printf("\n org==0x%08x,left edge==0x%08x\n ",((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff),dq_lcd_bdl_temp_reg_value);
12408
12409 {acbdlr_x_reg_hold_min=dq_lcd_bdl_temp_reg_value;}
12410
12411
12412 //test_ac_setup_hold=1;
12413 //writel(acbdlr0_reg_org,(DDR0_PUB_ACBDLR0+reg_base_adj));
12414 writel(acbdlr_x_reg_org,(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12415 //dq_lcd_bdl_temp_reg_value=0;
12416 // writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12417 {
12418
12419
12420 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x acmdlr==0x%08x ddl_100step_ps==%08d\n",test_acbdl,test_ac_setup_hold,
12421 readl(DDR0_PUB_ACMDLR0+reg_base_adj),ddl_100step_ps);
12422 printf("\nacbdlr0_reg_org==0x%08x | acbdlr_x_reg_org==0x%08x\n ",acbdlr0_reg_org,acbdlr_x_reg_org);
12423 printf("acbdlr_x_reg_hold_min==0x%08x \
12424 holdup time==0x%08x, %08d ps\n ",
12425 acbdlr_x_reg_hold_min,
12426 (((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)-acbdlr_x_reg_hold_min),
12427 ((((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)-acbdlr_x_reg_hold_min)*ddl_100step_ps)/100);
12428
12429 }
12430 acbdlr0_9_reg_hold_max[test_acbdl]=(((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)-acbdlr_x_reg_hold_min);
12431 acbdlr0_9_reg_hold_time[test_acbdl]=((((acbdlr_x_reg_org>>(8*(test_acbdl%4)))&0xff)-acbdlr_x_reg_hold_min)*ddl_100step_ps)/100;
12432
12433 for ((temp_count=0);(temp_count<10);(temp_count++))
12434 {
12435 writel(((acbdlr0_9_reg_org[temp_count])),(DDR0_PUB_ACBDLR0+(temp_count<<2)+reg_base_adj));
12436
12437 };
12438
12439 }
12440
12441 if (test_ac_setup_hold == 2)
12442 {
12443 printf("\ntest_ac_hold 2 method\n ");
12444 acbdlr0_reg_org=readl(DDR0_PUB_ACBDLR0+reg_base_adj);
12445 acbdlr_x_reg_org=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12446 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x\n ",test_acbdl,test_ac_setup_hold);
12447 printf("\nacbdlr0_reg_org==0x%08x | acbdlr_x_reg_org==0x%08x\n ",acbdlr0_reg_org,acbdlr_x_reg_org);
12448
12449
12450 printf("\nacbdlr0_reg==0x%08x | acbdlr_x_reg==0x%08x\n ",
12451 readl(DDR0_PUB_ACBDLR0+reg_base_adj),readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12452
12453 reg_add=(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12454 //dq_lcd_bdl_temp_reg_value=readl(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj);
12455 //dq_lcd_bdl_temp_reg_value=((dq_lcd_bdl_temp_reg_value>>(8*(test_acbdl%4)))&0xff);
12456 dq_lcd_bdl_temp_reg_value=(readl(DDR0_PUB_ACBDLR0+reg_base_adj)&0xff);
12457 while (dq_lcd_bdl_temp_reg_value<0x3f)
12458 {
12459 temp_test_error=0;
12460 dq_lcd_bdl_temp_reg_value++;
12461 printf("\n reg==0x%08x, right temp==0x%08x,value==0x%08x\n ",(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj),dq_lcd_bdl_temp_reg_value,
12462 ((dq_lcd_bdl_temp_reg_value|(dq_lcd_bdl_temp_reg_value<<(8))|(dq_lcd_bdl_temp_reg_value<<(16))
12463 |(dq_lcd_bdl_temp_reg_value<<(24)))&(~(0xff<<(8*(test_acbdl%4)))))|(acbdlr_x_reg_org&((0xff<<(8*(test_acbdl%4))))));
12464 /*
12465 {
12466 for ((temp_count=0);(temp_count<10);(temp_count++))
12467 {
12468 writel((dq_lcd_bdl_temp_reg_value|(dq_lcd_bdl_temp_reg_value<<(8))|(dq_lcd_bdl_temp_reg_value<<(16))
12469 |(dq_lcd_bdl_temp_reg_value<<(24))),(DDR0_PUB_ACBDLR0+(temp_count<<2)+reg_base_adj));
12470 };
12471
12472 writel(((dq_lcd_bdl_temp_reg_value|(dq_lcd_bdl_temp_reg_value<<(8))|(dq_lcd_bdl_temp_reg_value<<(16))
12473 |(dq_lcd_bdl_temp_reg_value<<(24)))&(~(0xff<<(8*(test_acbdl%4)))))|(acbdlr_x_reg_org&((0xff<<(8*(test_acbdl%4))))),
12474 (((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12475
12476 }
12477 */
12478
12479 {
12480 for ((temp_count=0);(temp_count<40);(temp_count++))
12481 {if(temp_count==(test_acbdl))
12482 {
12483 temp_reg_value[temp_count]=((readl(DDR0_PUB_ACBDLR0+(((temp_count)>>2)<<2)+
12484 reg_base_adj))>>(8*(temp_count%4)))&0xff;
12485 }else
12486 {
12487 temp_reg_value[temp_count]=(((readl(DDR0_PUB_ACBDLR0+(((temp_count)>>2)<<2)+
12488 reg_base_adj))>>(8*(temp_count%4)))&0xff)+1;
12489 }
12490 temp_reg_value[temp_count]=((temp_reg_value[temp_count]>ACBDLR_MAX)?(ACBDLR_MAX):(temp_reg_value[temp_count]));
12491
12492 };
12493 for ((temp_count=0);(temp_count<40);(temp_count++))
12494 {
12495 writel((((temp_reg_value[(temp_count)])|((temp_reg_value[temp_count+1])<<(8))|(((temp_reg_value[temp_count+2])<<(16)))
12496 |((temp_reg_value[temp_count+3])<<(24)))),
12497 (DDR0_PUB_ACBDLR0+(((temp_count)>>2)<<2)+
12498 reg_base_adj));
12499 temp_count=temp_count+3;
12500 };
12501 printf("\n reg_bdlr_ck==0x%08x,right temp==0x%08x\n,ck_value==0x%08x",(DDR0_PUB_ACBDLR0+
12502 reg_base_adj),(dq_lcd_bdl_temp_reg_value),
12503 (readl(DDR0_PUB_ACBDLR0+
12504 reg_base_adj)));
12505 printf("\n reg_bdlr_x==0x%08x,right temp==0x%08x\n,x_value==0x%08x",(DDR0_PUB_ACBDLR0+(((test_acbdl)>>2)<<2)+
12506 reg_base_adj),(dq_lcd_bdl_temp_reg_value),
12507 (readl(DDR0_PUB_ACBDLR0+(((test_acbdl)>>2)<<2)+
12508 reg_base_adj)));
12509
12510 }
12511
12512
12513
12514 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
12515
12516 if (temp_test_error)
12517 {
12518 //printf("\nwdqd left edge detect \n");
12519 dq_lcd_bdl_temp_reg_value--;
12520 break;
12521 }
12522 }
12523 printf("\n right edge detect ,reg==0x%08x\n",(((test_acbdl>>2)<<2)+DDR0_PUB_ACBDLR0+reg_base_adj));
12524 printf("\norg==0x%08x, right edge==0x%08x\n ",acbdlr0_reg_org&0xff,dq_lcd_bdl_temp_reg_value);
12525
12526 {acbdlr_x_reg_hold_min=dq_lcd_bdl_temp_reg_value;}
12527
12528
12529 //test_ac_setup_hold=1;
12530 dq_lcd_bdl_temp_reg_value=0;
12531
12532 {
12533
12534
12535 printf("\ntest_acbdl %08x | ac_setup_hold==0x%08x acmdlr==0x%08x ddl_100step_ps==%08d\n",test_acbdl,test_ac_setup_hold,
12536 readl(DDR0_PUB_ACMDLR0+reg_base_adj),ddl_100step_ps);
12537 printf("\nacbdlr0_reg_org==0x%08x | acbdlr_x_reg_org==0x%08x\n ",acbdlr0_reg_org,acbdlr_x_reg_org);
12538 printf("acbdlr_x_reg_hold_max==0x%08x \
12539 holdup time==0x%08x, %08d ps\n ",
12540 acbdlr_x_reg_hold_min,
12541 ((acbdlr_x_reg_hold_min-(acbdlr0_reg_org&0xff))),((acbdlr_x_reg_hold_min-(acbdlr0_reg_org&0xff))*ddl_100step_ps)/100);
12542
12543 }
12544 acbdlr0_9_reg_hold_max[test_acbdl]=((acbdlr_x_reg_hold_min-(acbdlr0_reg_org&0xff)));
12545 acbdlr0_9_reg_hold_time[test_acbdl]=((acbdlr_x_reg_hold_min-(acbdlr0_reg_org&0xff))*ddl_100step_ps)/100;
12546 for ((temp_count=0);(temp_count<10);(temp_count++))
12547 {
12548 writel(((acbdlr0_9_reg_org[temp_count])),(DDR0_PUB_ACBDLR0+(temp_count<<2)+reg_base_adj));
12549
12550 };
12551
12552 }
12553 }
12554 }
12555
12556 }
12557
12558 // ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0+reg_base_adj)))>>16)&0xff);
12559
12560
12561
12562 printf("\nddl_100step_ps== %08d,0_5cycle_ps== %08d\n", ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)));
12563
12564 printf("\nresume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12565 writel((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29)),(DDR0_PUB_REG_BASE+4));
12566 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12567
12568 return dq_lcd_bdl_temp_reg_value;
12569
12570usage:
12571 cmd_usage(cmdtp);
12572 return 1;
12573
12574 }
12575}
12576
12577U_BOOT_CMD(
12578 ddr_test_ac_bit_setup_hold_window, 6, 1, do_ddr_test_ac_bit_setup_hold_window,
12579 "DDR test ac bit margin function",
12580 "do_ddr_test_ac_bit_setup_hold_window a 0 0x8000000 0 c or do_ddr_test_ac_bit_setup_hold_window a 0 0x8000000 2 c \n dcache off ? \n"
12581 //do_ddr_test_ac_bit_setup_hold_window a 0 0x8000000 setup/hold pin_id //c --- cs ,,8 --- ba0
12582);
12583
12584int do_ddr_test_data_bit_setup_hold_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
12585{
12586 ///*
12587 printf("\nEnter test ddr data bit window function\n");
12588 // if(!argc)
12589 // goto DDR_TUNE_DQS_START;
12590 printf("\nargc== 0x%08x\n", argc);
12591 unsigned int ddl_100step_ps= 0;
12592
12593 unsigned int temp_test_error= 0;
12594 unsigned int temp_count= 0;
12595
12596
12597 char *endp;
12598 // unsigned int *p_start_addr;
12599 unsigned int test_data_setup_hold=0;
12600 //unsigned int testing_seed=0;
12601 // unsigned int test_lane_step_rdqs_flag=0;
12602 unsigned int open_vt=0;
12603 unsigned int test_bdl=0;
12604 // unsigned int test_times=1;
12605 // unsigned int reg_add=0;
12606 unsigned int reg_base_adj=0;
12607 unsigned int reg_bdlrck=0;
12608 unsigned int reg_bdlr_x=0;
12609 unsigned int channel_a_en = 0;
12610 unsigned int channel_b_en = 0;
12611
12612
12613 unsigned int bdlrck_reg_org=0;
12614 unsigned int bdlr_x_reg_org=0;
12615 // unsigned int bdlr_x_reg_hold_min=0;
12616 // unsigned int acbdlr_x_reg_hold_min=0;
12617 unsigned int bdlr_x_reg_setup_max=0;
12618 unsigned int bdlr_x_reg_hold_max=0;
12619 // unsigned int acbdlr_x_reg_setup_max=0;
12620 // unsigned int dq_lcd_bdl_reg_left=0;
12621 // unsigned int dq_lcd_bdl_reg_right=0;
12622
12623
12624 // unsigned int dq_lcd_bdl_reg_left_min=0;
12625 // unsigned int dq_lcd_bdl_reg_right_min=0;
12626
12627 unsigned int dq_lcd_bdl_temp_reg_value=0;
12628 unsigned int temp_reg_value[24];
12629
12630
12631 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
12632 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
12633
12634
12635 // unsigned int dq_lcd_bdl_temp_reg_lef;
12636 // unsigned int dq_lcd_bdl_temp_reg_rig;
12637
12638
12639 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
12640
12641
12642 {
12643 if (argc == 2)
12644 {
12645 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
12646
12647 {channel_a_en = 1;
12648 }
12649 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
12650
12651 {channel_b_en = 1;
12652 }
12653 else
12654 {
12655 goto usage;
12656 }
12657 }
12658 if (argc > 2)
12659 {
12660 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
12661
12662 {channel_a_en = 1;
12663 }
12664 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
12665
12666 {channel_b_en = 1;
12667 }
12668 }
12669 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
12670 if (argc >3) {
12671 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
12672 if (*argv[3] == 0 || *endp != 0)
12673 {
12674 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
12675 }
12676
12677 }
12678 if (argc >4) {
12679 test_data_setup_hold = 0;
12680 test_data_setup_hold = simple_strtoull_ddr(argv[4], &endp, 16);
12681 if (*argv[4] == 0 || *endp != 0)
12682 {
12683 test_data_setup_hold = 0;
12684 }
12685 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
12686 {
12687 test_data_setup_hold = 0;
12688 }
12689 }
12690 if (test_data_setup_hold >1)
12691 test_data_setup_hold = 1;
12692 if (argc >5) {
12693
12694 test_bdl= simple_strtoull_ddr(argv[5], &endp, 0);
12695 if (*argv[5] == 0 || *endp != 0)
12696 {
12697 test_bdl = 0;
12698 }
12699 if (test_bdl>96)
12700 test_bdl =0;
12701 }
12702 if (argc >6) {
12703
12704 open_vt= simple_strtoull_ddr(argv[6], &endp, 0);
12705 if (*argv[6] == 0 || *endp != 0)
12706 {
12707 open_vt = 0;
12708 }
12709 //if(open_vt)
12710 // open_vt =1;
12711 }
12712 }
12713 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
12714 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
12715 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
12716 printf("\ntest_data_setup_hold== 0x%08x\n", test_data_setup_hold);
12717 printf("\ntest_bdl== 0x%08x\n", test_bdl);
12718 if ( channel_a_en)
12719 {
12720 //writel((0), 0xc8836c00);
12721 OPEN_CHANNEL_A_PHY_CLK();
12722 }
12723 if ( channel_b_en)
12724 {
12725 OPEN_CHANNEL_B_PHY_CLK();
12726 //writel((0), 0xc8836c00);
12727 }
12728
12729
12730
12731 //save and print org training dqs value
12732 if (channel_a_en || channel_b_en)
12733 {
12734 //dcache_disable();
12735 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
12736
12737 }////save and print org training dqs value
12738
12739
12740
12741 {
12742 ////tune and save training dqs value
12743 if (channel_a_en || channel_b_en)
12744
12745 {
12746
12747 {
12748
12749 if (( channel_a_en) && ( channel_b_en == 0))
12750 {
12751 reg_base_adj=CHANNEL_A_REG_BASE;
12752 }
12753 else if(( channel_b_en)&&( channel_a_en==0))
12754 {
12755 reg_base_adj=CHANNEL_B_REG_BASE;
12756 }
12757 else if ((channel_a_en+channel_b_en)==2)
12758 {
12759 reg_base_adj=CHANNEL_A_REG_BASE;
12760 }
12761
12762 printf("\nshould pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12763 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
12764 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
12765 for ((temp_count=0);(temp_count<28);(temp_count++))
12766 {
12767 //data_bdlr0_5_reg_org[temp_count]=(((readl(((temp_count>>2)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/6)+reg_base_adj))
12768 // >>(8*(test_bdl%4)))&0xff);
12769 data_bdlr0_5_reg_org[temp_count]=((readl(((temp_count%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/7)+reg_base_adj))
12770 );
12771 };
12772
12773
12774 {
12775 ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_DX0MDLR0+reg_base_adj)))>>16)&0xff);
12776 printf("\nddl_100step_ps== %08d,0_5cycle_ps== %08d,0_5cycle==0x%08x\n", ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)),
12777 ((((readl(DDR0_PUB_DX0MDLR0+reg_base_adj)))>>16)&0xff));
12778
12779 //reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;
12780 reg_bdlrck=((((test_bdl%24)>11)?(DDR0_PUB_DX0BDLR5):(DDR0_PUB_DX0BDLR2))+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12781 reg_bdlr_x= (DDR0_PUB_DX0BDLR0+((((test_bdl%24)>>2)<<2))+
12782 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12783 if ((test_bdl%24)>11)
12784 {reg_bdlr_x=reg_bdlr_x+4;//dxnbdlr345 register add have a gap with dxnbdlr012
12785 }
12786 bdlrck_reg_org=readl(reg_bdlrck) ;
12787 bdlr_x_reg_org=readl(reg_bdlr_x);
12788 printf("\ntest_bdl %08x | data_setup_hold==0x%08x\n ",test_bdl,test_data_setup_hold);
12789 printf("\nbdlr0_reg_0x%08x_org==0x%08x | bdlr_x_reg_0x%08x_org==0x%08x\n ",reg_bdlrck,
12790 bdlrck_reg_org,reg_bdlr_x,bdlr_x_reg_org);
12791 if (test_data_setup_hold == 0)
12792 {
12793 printf("\ntest_data_setup\n ");
12794
12795
12796
12797 reg_bdlrck=((((test_bdl%24)>11)?(DDR0_PUB_DX0BDLR5):(DDR0_PUB_DX0BDLR2))+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12798 reg_bdlr_x= (DDR0_PUB_DX0BDLR0+((((test_bdl%24)>>2)<<2))+
12799 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12800 if ((test_bdl%24)>11)
12801 {reg_bdlr_x=reg_bdlr_x+4;//dxnbdlr345 register add have a gap with dxnbdlr012
12802 }
12803 bdlrck_reg_org=readl(reg_bdlrck) ;
12804 bdlr_x_reg_org=readl(reg_bdlr_x);
12805
12806 dq_lcd_bdl_temp_reg_value=((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff);
12807 while (dq_lcd_bdl_temp_reg_value<ACBDLR_MAX)
12808 {
12809 temp_test_error=0;
12810 dq_lcd_bdl_temp_reg_value++;
12811 printf("\n reg_bdlr_x==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_bdlr_x,dq_lcd_bdl_temp_reg_value,
12812 ((bdlr_x_reg_org)&(~(0xff<<(8*(test_bdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_bdl%4))));
12813
12814 {
12815 writel(((bdlr_x_reg_org)&(~(0xff<<(8*(test_bdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_bdl%4))),reg_bdlr_x);
12816
12817 }
12818 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
12819
12820 if (temp_test_error)
12821 {
12822 //printf("\nwdqd left edge detect \n");
12823 dq_lcd_bdl_temp_reg_value--;
12824 break;
12825 }
12826 }
12827 printf("\n right edge detect ,reg==0x%08x\n",(reg_bdlr_x));
12828 printf("\n org==0x%08x,right edge==0x%08x,value==0x%08x\n ",((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff),dq_lcd_bdl_temp_reg_value,
12829 ((bdlr_x_reg_org)&(~(0xff<<(8*(test_bdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_bdl%4))));
12830
12831 {bdlr_x_reg_setup_max=dq_lcd_bdl_temp_reg_value;}
12832
12833 dq_lcd_bdl_temp_reg_value=0;
12834 //writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12835 writel(((bdlr_x_reg_org)),reg_bdlr_x);
12836 //test_ac_setup_hold=1;
12837 {
12838 printf("\ntest_bdl %08x | data_setup_hold==0x%08x mdlr==0x%08x ddl_100step_ps==%08d\n",test_bdl,test_data_setup_hold,
12839 readl(DDR0_PUB_DX0MDLR0+reg_base_adj),ddl_100step_ps);
12840 printf("\nbdlr_ck_reg_org==0x%08x | bdlr_x_reg_org==0x%08x\n ",bdlrck_reg_org,bdlr_x_reg_org);
12841 printf("acbdlr_x_reg_setup_max 0x%08x \
12842 setup time==0x%08x, %08d ps \n ",
12843 bdlr_x_reg_setup_max,(bdlr_x_reg_setup_max-
12844 ((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff)),((bdlr_x_reg_setup_max-
12845 ((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff)) *ddl_100step_ps)/100
12846 );
12847 bdlr0_9_reg_setup_max[test_bdl]=(bdlr_x_reg_setup_max-
12848 ((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff));
12849 bdlr0_9_reg_setup_time[test_bdl]=((bdlr_x_reg_setup_max-
12850 ((bdlr_x_reg_org>>(8*(test_bdl%4)))&0xff)) *ddl_100step_ps)/100;
12851 for ((temp_count=0);(temp_count<28);(temp_count++))
12852 {
12853 writel(((data_bdlr0_5_reg_org[temp_count])),
12854 (((temp_count%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/7)+reg_base_adj));
12855
12856 };
12857
12858 }
12859
12860 }
12861
12862
12863
12864
12865 if (test_data_setup_hold)
12866 {
12867 printf("\ntest_data_hold\n ");
12868
12869
12870
12871 reg_bdlrck=((((test_bdl%24)>11)?(DDR0_PUB_DX0BDLR5):(DDR0_PUB_DX0BDLR2))+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12872 reg_bdlr_x= (DDR0_PUB_DX0BDLR0+((((test_bdl%24)>>2)<<2))+
12873 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj);
12874 if ((test_bdl%24)>11)
12875 {reg_bdlr_x=reg_bdlr_x+4;//dxnbdlr345 register add have a gap with dxnbdlr012
12876 }
12877 bdlrck_reg_org=readl(reg_bdlrck) ;
12878 bdlr_x_reg_org=readl(reg_bdlr_x);
12879
12880 dq_lcd_bdl_temp_reg_value=((bdlrck_reg_org>>(8*(1)))&0xff);
12881 while (dq_lcd_bdl_temp_reg_value<ACBDLR_MAX)
12882 {
12883 temp_test_error=0;
12884 dq_lcd_bdl_temp_reg_value++;
12885 printf("\n reg_bdlr_ck==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_bdlrck,dq_lcd_bdl_temp_reg_value,
12886 (((bdlrck_reg_org)&(~(0xffff<<(8*(1)))))|(dq_lcd_bdl_temp_reg_value<<(8*(1)))|(dq_lcd_bdl_temp_reg_value<<(8*(2)))));
12887
12888 {
12889 // writel((((bdlrck_reg_org)&(~(0xffff<<(8*(1)))))|(dq_lcd_bdl_temp_reg_value<<(8*(1)))|(dq_lcd_bdl_temp_reg_value<<(8*(2)))),reg_bdlrck);
12890
12891 }
12892
12893
12894
12895 if (((test_bdl%24)<12))
12896 {
12897 for ((temp_count=0);(temp_count<12);(temp_count++))
12898 {if(temp_count==(test_bdl%24))
12899 {
12900 temp_reg_value[temp_count]=((readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+
12901 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj))>>(8*(temp_count%4)))&0xff;
12902 }else
12903 {
12904 temp_reg_value[temp_count]=(((readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+
12905 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj))>>(8*(temp_count%4)))&0xff)+1;
12906 }
12907 temp_reg_value[temp_count]=((temp_reg_value[temp_count]>ACBDLR_MAX)?(ACBDLR_MAX):(temp_reg_value[temp_count]));
12908
12909 };
12910 for ((temp_count=0);(temp_count<12);(temp_count++))
12911 {
12912 writel((((temp_reg_value[(temp_count)])|((temp_reg_value[temp_count+1])<<(8))|(((temp_reg_value[temp_count+2])<<(16)))
12913 |((temp_reg_value[temp_count+3])<<(24)))),
12914 (DDR0_PUB_DX0BDLR0+(((temp_count%24)>>2)<<2)+
12915 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj));
12916 temp_count=temp_count+3;
12917 };
12918 printf("\n reg_bdlr_x==0x%08x,right temp==0x%08x\n,x_value==0x%08x",reg_bdlr_x,dq_lcd_bdl_temp_reg_value,
12919 (readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+
12920 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj)));
12921
12922 }
12923
12924
12925 if (((test_bdl%24) >= 12))
12926 {
12927 for ((temp_count=12);(temp_count<24);(temp_count++))
12928 {if(temp_count==(test_bdl%24))
12929 {
12930 temp_reg_value[temp_count]=((readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+4+
12931 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj))>>(8*(temp_count%4)))&0xff;
12932 }else
12933 {
12934 temp_reg_value[temp_count]=(((readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+4+
12935 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj))>>(8*(temp_count%4)))&0xff)+1;
12936 }
12937 temp_reg_value[temp_count]=((temp_reg_value[temp_count]>ACBDLR_MAX)?(ACBDLR_MAX):(temp_reg_value[temp_count]));
12938
12939 };
12940 for ((temp_count=12);(temp_count<24);(temp_count++))
12941 {
12942 writel((((temp_reg_value[(temp_count)])|((temp_reg_value[temp_count+1])<<(8))|(((temp_reg_value[temp_count+2])<<(16)))
12943 |((temp_reg_value[temp_count+3])<<(24)))),
12944 (DDR0_PUB_DX0BDLR0+(((temp_count%24)>>2)<<2)+4+
12945 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj));
12946 temp_count=temp_count+3;
12947 };
12948 printf("\n reg_bdlr_x==0x%08x,right temp==0x%08x\n,x_value==0x%08x",reg_bdlr_x,dq_lcd_bdl_temp_reg_value,
12949 (readl(DDR0_PUB_DX0BDLR0+(((test_bdl%24)>>2)<<2)+4+
12950 (DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_bdl/24)+reg_base_adj)));
12951 }
12952
12953 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
12954
12955 if (temp_test_error)
12956 {
12957 //printf("\nwdqd left edge detect \n");
12958 dq_lcd_bdl_temp_reg_value--;
12959 break;
12960 }
12961 }
12962
12963 printf("\n right edge detect ,reg==0x%08x\n",(reg_bdlrck));
12964 printf("\n org==0x%08x,right edge==0x%08x,value==0x%08x\n ",((bdlrck_reg_org>>(8*(1)))&0xff),dq_lcd_bdl_temp_reg_value,
12965 (((bdlrck_reg_org)&(~(0xffff<<(8*(1)))))|(dq_lcd_bdl_temp_reg_value<<(8*(1)))|(dq_lcd_bdl_temp_reg_value<<(8*(2)))));
12966
12967 {bdlr_x_reg_hold_max=dq_lcd_bdl_temp_reg_value;}
12968
12969 dq_lcd_bdl_temp_reg_value=0;
12970 //writel(((acbdlr_x_reg_org)&(~(0xff<<(8*(test_acbdl%4)))))|(dq_lcd_bdl_temp_reg_value<<(8*(test_acbdl%4))),reg_add);
12971 writel(((bdlrck_reg_org)),reg_bdlrck);
12972 //test_ac_setup_hold=1;
12973 {
12974 printf("\ntest_bdl %08x | data_setup_hold==0x%08x mdlr==0x%08x ddl_100step_ps==%08d\n",test_bdl,test_data_setup_hold,
12975 readl(DDR0_PUB_DX0MDLR0+reg_base_adj),ddl_100step_ps);
12976 printf("\nbdlr_ck_reg_org==0x%08x | bdlr_x_reg_org==0x%08x\n ",bdlrck_reg_org,bdlr_x_reg_org);
12977 printf("acbdlr_x_reg_hold_max 0x%08x \
12978 hold time==0x%08x, %08d ps \n ",
12979 bdlr_x_reg_hold_max,(bdlr_x_reg_hold_max-
12980 ((bdlrck_reg_org>>(8*(1)))&0xff)),((bdlr_x_reg_hold_max-
12981 ((bdlrck_reg_org>>(8*(1)))&0xff)) *ddl_100step_ps)/100
12982 );
12983 bdlr0_9_reg_hold_max[test_bdl]=(bdlr_x_reg_hold_max-
12984 ((bdlrck_reg_org>>(8*(1)))&0xff));
12985 bdlr0_9_reg_hold_time[test_bdl]=((bdlr_x_reg_hold_max-
12986 ((bdlrck_reg_org>>(8*(1)))&0xff)) *ddl_100step_ps)/100;
12987 for ((temp_count=0);(temp_count<28);(temp_count++))
12988 {
12989 writel(((data_bdlr0_5_reg_org[temp_count])),
12990 (((temp_count%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/7)+reg_base_adj));
12991
12992 };
12993
12994 }
12995
12996 }
12997
12998
12999
13000
13001
13002 }
13003 }
13004
13005 }
13006
13007 // ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0+reg_base_adj)))>>16)&0xff);
13008
13009
13010
13011 printf("\nddl_100step_ps== %08d,0_5cycle_ps== %08d\n", ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)));
13012
13013 printf("\nresume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
13014 if (open_vt)
13015 {
13016 writel((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29)),(DDR0_PUB_REG_BASE+4));
13017 }
13018 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
13019
13020 return dq_lcd_bdl_temp_reg_value;
13021
13022
13023
13024 }
13025
13026usage:
13027 cmd_usage(cmdtp);
13028 //*/
13029 return 1;
13030}
13031U_BOOT_CMD(
13032 ddr_test_data_bit_setup_hold_window, 6, 1, do_ddr_test_data_bit_setup_hold_window,
13033 "DDR test data bit margin function",
13034 "ddr_test_data_bit_setup_hold_window a 0 0x8000000 0 3 or ddr_test_data_bit_setup_hold_window a 0 0x8000000 1 3 \n dcache off ? \n"
13035);
13036#endif
13037
13038unsigned int
13039do_test_address_bus(volatile unsigned int * baseAddress, unsigned int nBytes)
13040{
13041 unsigned int addressMask = (nBytes/sizeof(unsigned int) - 1);
13042 unsigned int offset;
13043 unsigned int testOffset;
13044
13045 unsigned int pattern = (unsigned int) 0xAAAAAAAA;
13046 unsigned int antipattern = (unsigned int) 0x55555555;
13047
13048 unsigned int data1, data2;
13049
13050 unsigned int ret = 0;
13051
13052 /*
13053 * Write the default pattern at each of the power-of-two offsets.
13054 */
13055 for (offset = 1; (offset & addressMask) != 0; offset <<= 1)
13056 {
13057 baseAddress[offset] = pattern;
13058 }
13059
13060 /*
13061 * Check for address bits stuck high.
13062 */
13063 testOffset = 0;
13064 baseAddress[testOffset] = antipattern;
13065
13066 for (offset = 1; (offset & addressMask) != 0; offset <<= 1)
13067 {
13068 data1 = baseAddress[offset];
13069 data2 = baseAddress[offset];
13070 if (data1 != data2)
13071 {
13072 printf(" memTestAddressBus - read twice different[offset]: 0x%8x-0x%8x\n", data1, data2);
13073 ret = 1;
13074 }
13075 if (data1 != pattern)
13076 {
13077 printf(" memTestAddressBus - write[0x%8x]: 0x%8x, read[0x%8x]: 0x%8x\n", \
13078 offset, pattern, offset, data1);
13079 ret = 1;
13080 //return ((unsigned int) &baseAddress[offset]);
13081 }
13082 }
13083
13084 baseAddress[testOffset] = pattern;
13085
13086 /*
13087 * Check for address bits stuck low or shorted.
13088 */
13089 for (testOffset = 1; (testOffset & addressMask) != 0; testOffset <<= 1)
13090 {
13091 baseAddress[testOffset] = antipattern;
13092
13093 if (baseAddress[0] != pattern)
13094 {
13095 printf(" memTestAddressBus2 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0]: 0x%8x\n", \
13096 testOffset, antipattern, baseAddress[0]);
13097 ret = 1;
13098 //return ((unsigned int) &baseAddress[testOffset]);
13099 }
13100
13101 for (offset = 1; (offset & addressMask) != 0; offset <<= 1)
13102 {
13103 data1 = baseAddress[offset];
13104 if ((data1 != pattern) && (offset != testOffset))
13105 {
13106 printf(" memTestAddressBus3 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
13107 testOffset, antipattern, testOffset, data1);
13108 ret = 1;
13109 //return ((unsigned int) &baseAddress[testOffset]);
13110 }
13111 }
13112
13113 baseAddress[testOffset] = pattern;
13114 }
13115
13116
13117 for (offset = 0x1; (offset <=addressMask) ; offset++)
13118 {
13119 if (((~offset) <= addressMask) )
13120 {
13121 baseAddress[offset] = pattern;
13122 baseAddress[(~offset)] = antipattern;
13123 }
13124 }
13125
13126 for (offset = 0x1; (offset <=addressMask); offset++)
13127 {
13128 if (((~offset) <= addressMask) )
13129 {
13130 if (baseAddress[offset] != pattern)
13131 {
13132 printf(" memTestAddressBus4 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
13133 offset, pattern, offset, baseAddress[offset]);
13134
13135 ret = 1;
13136 break;
13137 }
13138
13139 if (baseAddress[(~offset)] != antipattern)
13140 {
13141 printf(" memTestAddressBus5 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
13142 ((~offset)), antipattern, ((~offset)), baseAddress[((~offset))]);
13143 ret = 1;
13144 break;
13145 }
13146 }
13147 }
13148
13149 if (ret)
13150 {return (ret);
13151 }
13152 //unsigned int suq_value;
13153 for (offset = 0x1; (offset <=addressMask) ; offset++)
13154 {
13155
13156 {
13157 pattern=((offset<<2)-offset);
13158 baseAddress[offset] = pattern;
13159 //baseAddress[(~offset)] = antipattern;
13160 }
13161 }
13162
13163 for (offset = 0x1; (offset <=addressMask); offset++)
13164 {
13165
13166 {
13167 pattern=((offset<<2)-offset);
13168 if (baseAddress[offset] != pattern)
13169 {
13170 printf(" memTestAddressBus6 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
13171 offset,pattern, offset, baseAddress[offset]);
13172 ret = 1;
13173 break;
13174 }
13175
13176
13177 }
13178 }
13179 if (ret)
13180 {return (ret);
13181 }
13182 for (offset = 0x1; (offset <=addressMask) ; offset++)
13183 {
13184
13185 {
13186 pattern=~((offset<<2)-offset);
13187 baseAddress[offset] = pattern;
13188 //baseAddress[(~offset)] = antipattern;
13189 }
13190 }
13191
13192 for (offset = 0x1; (offset <=addressMask); offset++)
13193 {
13194
13195 {
13196 pattern=~((offset<<2)-offset);
13197 if (baseAddress[offset] != pattern)
13198 {
13199 printf(" memTestAddressBus7 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
13200 offset,pattern, offset, baseAddress[offset]);
13201 ret = 1;
13202 break;
13203 }
13204
13205
13206 }
13207 }
13208
13209
13210 return (ret);
13211} /* memTestAddressBus() */
13212
13213int ddr_test_s_add_cross_talk_pattern(int ddr_test_size)
13214{
13215 // unsigned int start_addr = DDR_TEST_START_ADDR;
13216 unsigned int start_addr=test_start_addr;
13217 error_outof_count_flag=1;
13218 error_count=0;
13219 ///*
13220 printf("\rStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13221 ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
13222 printf("\rEnd write. ");
13223 printf("\nStart 1st reading... ");
13224 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
13225 printf("\rEnd 1st read. ");
13226 printf("\rStart 2nd reading... ");
13227 ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
13228 //*/
13229 /*
13230 printf("\rStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13231 ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
13232 printf("\rEnd write. ");
13233 printf("\rStart 1st reading... ");
13234 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
13235 printf("\rEnd 1st read. ");
13236 printf("\rStart 2nd reading... ");
13237 ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
13238 */
13239 ddr_write_full((void *)(int_convter_p(start_addr)), ddr_test_size,0x0,0x3);
13240 printf("\rEnd write. ");
13241 printf("\rStart 1st reading... ");
13242 ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size,0,3);
13243 printf("\rEnd 1st read. ");
13244 printf("\rStart 2nd reading... ");
13245 ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size,0,3);
13246
13247
13248 printf("\rStart writing add pattern ");
13249 if (do_test_address_bus((void *)(int_convter_p(start_addr)), ddr_test_size))
13250 error_count++;
13251
13252
13253 /*
13254 printf("\nStart *4 no cross talk pattern. ");
13255 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13256 ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
13257 printf("\nEnd write. ");
13258 printf("\nStart 1st reading... ");
13259 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
13260 printf("\nEnd 1st read. ");
13261 printf("\nStart 2nd reading... ");
13262 ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
13263
13264 //if(cross_talk_pattern_flag==1)
13265 {
13266 printf("\nStart *4 cross talk pattern p. ");
13267 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13268 ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
13269 printf("\rEnd write. ");
13270 printf("\rStart 1st reading... ");
13271 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
13272 printf("\rEnd 1st read. ");
13273 printf("\rStart 2nd reading... ");
13274 ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
13275 printf("\rEnd 2nd read. ");
13276
13277 // printf("\rStart 3rd reading... ");
13278 // ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
13279 // printf("\rEnd 3rd read. \n");
13280
13281 printf("\nStart *4 cross talk pattern n. ");
13282 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13283 ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
13284 printf("\rEnd write. ");
13285 printf("\rStart 1st reading... ");
13286 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
13287 printf("\rEnd 1st read. ");
13288 printf("\rStart 2nd reading... ");
13289 ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
13290 printf("\rEnd 2nd read. ");
13291 // printf("\rStart 3rd reading... ");
13292 // ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
13293 // printf("\rEnd 3rd read. \n");
13294
13295
13296 }
13297
13298 {
13299 printf("\nStart *4 cross talk pattern p2. ");
13300 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13301 ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
13302 printf("\rEnd write. ");
13303 printf("\rStart 1st reading... ");
13304 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
13305 printf("\rEnd 1st read. ");
13306 printf("\rStart 2nd reading... ");
13307 ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
13308 printf("\rEnd 2nd read. ");
13309
13310 // printf("\rStart 3rd reading... ");
13311 // ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
13312 // printf("\rEnd 3rd read. \n");
13313
13314 printf("\nStart *4 cross talk pattern n. ");
13315 printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
13316 ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
13317 printf("\rEnd write. ");
13318 printf("\rStart 1st reading... ");
13319 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
13320 printf("\rEnd 1st read. ");
13321 printf("\rStart 2nd reading... ");
13322 ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
13323 printf("\rEnd 2nd read. ");
13324 // printf("\rStart 3rd reading... ");
13325 // ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
13326 // printf("\rEnd 3rd read. \n");
13327
13328
13329}
13330 */
13331if (error_count)
13332 return 1;
13333 else
13334 return 0;
13335 }
13336
13337int do_ddr_test_ac_windows_aclcdlr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
13338{
13339 printf("\nEnter Test ddr ac windows function\n");
13340 printf("\nset ddr test test_start_addr==0x%08x \n",test_start_addr);
13341 // if(!argc)
13342 // goto DDR_TUNE_DQS_START;
13343 printf("\nargc== 0x%08x\n", argc);
13344 // unsigned int loop = 1;
13345 //unsigned int temp_count_i = 1;
13346 // unsigned int temp_count_j= 1;
13347 // unsigned int temp_count_k= 1;
13348 unsigned int temp_test_error= 0;
13349
13350
13351 char *endp;
13352 // unsigned int *p_start_addr;
13353 unsigned int test_loop=1;
13354 unsigned int test_times=1;
13355 unsigned int reg_add=0;
13356 unsigned int reg_base_adj=0;
13357 unsigned int channel_a_en = 0;
13358 unsigned int channel_b_en = 0;
13359 unsigned int testing_channel = 0;
13360
13361
13362
13363#define CHANNEL_A 0
13364#define CHANNEL_B 1
13365
13366
13367
13368
13369
13370
13371#define DDR_CROSS_TALK_TEST_SIZE 0x20000
13372
13373 unsigned int ac_mdlr_a_org=0;
13374 unsigned int ac_mdlr_b_org=0;
13375
13376 unsigned int ac_lcdlr_a_org=0;
13377 unsigned int ac_bdlr0_a_org=0;
13378 unsigned int ac_lcdlr_b_org=0;
13379 unsigned int ac_bdlr0_b_org=0;
13380 unsigned int ac_lcdlr_a_rig=0;
13381 unsigned int ac_bdlr0_a_rig=0;
13382 unsigned int ac_lcdlr_b_rig=0;
13383 unsigned int ac_bdlr0_b_rig=0;
13384 unsigned int ac_lcdlr_a_lef=0;
13385 unsigned int ac_bdlr0_a_lef=0;
13386 unsigned int ac_lcdlr_b_lef=0;
13387 unsigned int ac_bdlr0_b_lef=0;
13388
13389 unsigned int ac_lcdlr_a_rig_min=0;
13390 unsigned int ac_bdlr0_a_rig_min=0;
13391 unsigned int ac_lcdlr_b_rig_min=0;
13392 unsigned int ac_bdlr0_b_rig_min=0;
13393 unsigned int ac_lcdlr_a_lef_min=0;
13394 unsigned int ac_bdlr0_a_lef_min=0;
13395 unsigned int ac_lcdlr_b_lef_min=0;
13396 unsigned int ac_bdlr0_b_lef_min=0;
13397 unsigned int ac_lcdlr_temp=0;
13398 unsigned int ac_bdlr0_temp=0;
13399
13400
13401
13402 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
13403
13404 //#define DDR_TEST_ACLCDLR
13405
13406
13407 if (argc == 2)
13408 {
13409 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
13410
13411 {channel_a_en = 1;
13412 }
13413 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
13414
13415 {channel_b_en = 1;
13416 }
13417 else
13418 {
13419 goto usage;
13420 }
13421 }
13422 if (argc > 2)
13423 {
13424 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
13425
13426 {channel_a_en = 1;
13427 }
13428 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
13429
13430 {channel_b_en = 1;
13431 }
13432 }
13433 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
13434 if (argc >3) {
13435 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
13436 if (*argv[3] == 0 || *endp != 0)
13437 {
13438 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
13439 }
13440
13441 }
13442 if (argc >4) {
13443 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
13444 if (*argv[4] == 0 || *endp != 0)
13445 {
13446 test_loop = 1;
13447 }
13448 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
13449 {
13450 test_loop = 100000;
13451 }
13452 }
13453 unsigned int test_min_max=0;
13454 if (argc >5) {
13455
13456 test_min_max = simple_strtoull_ddr(argv[5], &endp, 16);
13457 if (*argv[5] == 0 || *endp != 0)
13458 {
13459 test_min_max = 0;
13460 }
13461 else
13462 test_min_max=1;
13463
13464 }
13465
13466
13467 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
13468 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
13469 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
13470 printf("\ntest_loop== 0x%08x\n", test_loop);
13471 printf("\ntest_min_max== 0x%08x\n", test_min_max);
13472 if ( channel_a_en)
13473 {
13474 //writel((0), 0xc8836c00);
13475 OPEN_CHANNEL_A_PHY_CLK();
13476 }
13477 if ( channel_b_en)
13478 {
13479 OPEN_CHANNEL_B_PHY_CLK();
13480 //writel((0), 0xc8836c00);
13481 }
13482
13483
13484 //save and print org training dqs value
13485 if (channel_a_en || channel_b_en)
13486 {
13487
13488
13489 //dcache_disable();
13490 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
13491
13492 {
13493 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
13494 {
13495 if (( channel_a_en) && ( channel_b_en == 0))
13496 {
13497 reg_base_adj=CHANNEL_A_REG_BASE;
13498 }
13499 else if(( channel_b_en)&&( channel_a_en==0))
13500 {
13501 reg_base_adj=CHANNEL_B_REG_BASE;
13502 }
13503 else if ((channel_a_en+channel_b_en)==2)
13504 {
13505 if ( testing_channel == CHANNEL_A)
13506 {
13507 reg_base_adj=CHANNEL_A_REG_BASE;
13508 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
13509
13510
13511
13512 }
13513 else if( testing_channel==CHANNEL_B)
13514 {
13515 reg_base_adj=CHANNEL_B_REG_BASE;
13516
13517 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
13518
13519
13520
13521 }
13522 }
13523
13524 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
13525
13526 printf("\ntest A channel AC110\n");
13527 if (reg_base_adj == CHANNEL_A_REG_BASE)
13528 {
13529 printf("\ntest A channel 0x%08x\n",reg_add);
13530 ac_mdlr_a_org=(unsigned int )(readl((unsigned int )reg_add));//readl(reg_add);//0xc8836000
13531 ac_lcdlr_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR)));//readl(reg_add+4);
13532 ac_bdlr0_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR)));//readl(reg_add+8);
13533 printf("\ntest A channel AC113\n");
13534 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
13535 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
13536 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
13537 }
13538 if (reg_base_adj == CHANNEL_B_REG_BASE)
13539 {
13540 printf("\ntest A channel AC112\n");
13541 ac_mdlr_b_org=readl(reg_add);
13542 ac_lcdlr_b_org=readl(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR);
13543 ac_bdlr0_b_org=readl(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR);
13544 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
13545 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
13546 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
13547 }
13548
13549
13550 }
13551
13552 }
13553
13554 }////save and print org training value
13555
13556
13557 for (test_times=0;(test_times<test_loop);(test_times++))
13558 {
13559 ////tune and save training dqs value
13560 if (channel_a_en || channel_b_en)
13561
13562 {
13563 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
13564 {
13565
13566 if (( channel_a_en) && ( channel_b_en == 0))
13567 {
13568 reg_base_adj=CHANNEL_A_REG_BASE;
13569 }
13570 else if(( channel_b_en)&&( channel_a_en==0))
13571 {
13572 reg_base_adj=CHANNEL_B_REG_BASE;
13573 }
13574 else if ((channel_a_en+channel_b_en)==2)
13575 {
13576 if ( testing_channel == CHANNEL_A)
13577 {
13578 reg_base_adj=CHANNEL_A_REG_BASE;
13579 }
13580 else if( testing_channel==CHANNEL_B)
13581 {
13582 reg_base_adj=CHANNEL_B_REG_BASE;
13583 }
13584 }
13585
13586 if (reg_base_adj == CHANNEL_A_REG_BASE)
13587 {
13588 printf("\ntest A channel AC\n");
13589 }
13590 else
13591 {
13592 printf("\ntest B channel AC\n");
13593 }
13594
13595 {
13596 {
13597 //#ifdef DDR_TEST_ACLCDLR
13598
13599 reg_add=DDR0_PUB_ACLCDLR+reg_base_adj;
13600
13601 ac_lcdlr_temp=readl(reg_add);
13602
13603 while (ac_lcdlr_temp>0)
13604 {
13605 if (test_min_max)
13606 {break;
13607 }
13608 temp_test_error=0;
13609 ac_lcdlr_temp--;
13610
13611 printf("\nlcdlr test value==0x%08x\n ",ac_lcdlr_temp);
13612 writel(ac_lcdlr_temp,(reg_add));
13613#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
13614 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13615#else
13616 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13617 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
13618#endif
13619 if (temp_test_error)
13620 {
13621 //printf("\nwdqd left edge detect \n");
13622 ac_lcdlr_temp++;
13623 break;
13624 }
13625 }
13626
13627 printf("\nlcdlr left edge detect \n");
13628 printf("\nlcdlr left edge==0x%08x\n ",ac_lcdlr_temp);
13629 if (reg_base_adj == CHANNEL_A_REG_BASE)
13630 {
13631 ac_lcdlr_a_lef=ac_lcdlr_temp;
13632 ac_lcdlr_temp=ac_lcdlr_a_org;
13633 }
13634 else
13635 {
13636 ac_lcdlr_b_lef=ac_lcdlr_temp;
13637 ac_lcdlr_temp=ac_lcdlr_b_org;
13638
13639 }
13640 writel(ac_lcdlr_temp,(reg_add));
13641
13642 while (ac_lcdlr_temp<ACLCDLR_MAX)
13643 {
13644 temp_test_error=0;
13645 ac_lcdlr_temp++;
13646 printf("\nlcdlr test value==0x%08x\n ",ac_lcdlr_temp);
13647 writel(ac_lcdlr_temp,(reg_add));
13648#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
13649 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13650#else
13651 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13652 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
13653#endif
13654 if (temp_test_error)
13655 {
13656 //printf("\nlcdlr right edge detect \n");
13657 ac_lcdlr_temp--;
13658 break;
13659 }
13660 }
13661 printf("\nlcdlr right edge detect \n");
13662 printf("\nlcdlr right edge==0x%08x\n ",ac_lcdlr_temp);
13663
13664
13665
13666 if (reg_base_adj == CHANNEL_A_REG_BASE)
13667 {
13668 ac_lcdlr_a_rig=ac_lcdlr_temp;
13669 ac_lcdlr_temp=ac_lcdlr_a_org;
13670 }
13671 else
13672 {
13673 ac_lcdlr_b_rig=ac_lcdlr_temp;
13674 ac_lcdlr_temp=ac_lcdlr_b_org;
13675
13676 }
13677 writel(ac_lcdlr_temp,(reg_add));
13678
13679
13680
13681 //#endif
13682
13683 {
13684 reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
13685
13686 ac_bdlr0_temp=readl(reg_add);
13687 while (ac_bdlr0_temp>0)
13688 {
13689 if (test_min_max)
13690 {break;
13691 }
13692 temp_test_error=0;
13693 ac_bdlr0_temp--;
13694 printf("\nbdlr0 test value==0x%08x\n ",ac_bdlr0_temp);
13695 writel(ac_bdlr0_temp,(reg_add));
13696#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
13697 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13698#else
13699 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13700 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
13701#endif
13702 if (temp_test_error)
13703 {
13704 //printf("\nwdqd left edge detect \n");
13705 ac_bdlr0_temp++;
13706 break;
13707 }
13708 }
13709 printf("\nacbdlr0 left edge detect \n");
13710 printf("\nacbdlr0 left edge==0x%08x\n ",ac_bdlr0_temp);
13711
13712 if (reg_base_adj == CHANNEL_A_REG_BASE)
13713 {
13714 ac_bdlr0_a_lef=ac_bdlr0_temp;
13715 ac_bdlr0_temp=ac_bdlr0_a_org;
13716 }
13717 else
13718 {
13719 ac_bdlr0_b_lef=ac_bdlr0_temp;
13720 ac_bdlr0_temp=ac_bdlr0_b_org;
13721
13722 }
13723
13724 writel(ac_bdlr0_temp,(reg_add));
13725
13726 while (ac_bdlr0_temp<ACBDLR_MAX)
13727 {
13728 temp_test_error=0;
13729 ac_bdlr0_temp++;
13730 printf("\nbdlr0 test value==0x%08x\n ",ac_bdlr0_temp);
13731 writel(ac_bdlr0_temp,(reg_add));
13732#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
13733 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13734#else
13735 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
13736 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
13737#endif
13738 if (temp_test_error)
13739 {
13740 //printf("\nacbdlr0 right edge detect \n");
13741 ac_bdlr0_temp--;
13742 break;
13743 }
13744 }
13745 printf("\nacbdlr0 right edge detect \n");
13746 printf("\nacbdlr0 right edge==0x%08x\n ",ac_bdlr0_temp);
13747
13748 if (reg_base_adj == CHANNEL_A_REG_BASE)
13749 {
13750 ac_bdlr0_a_rig=ac_bdlr0_temp;
13751 ac_bdlr0_temp=ac_bdlr0_a_org;
13752 }
13753 else
13754 {
13755 ac_bdlr0_b_rig=ac_bdlr0_temp;
13756 ac_bdlr0_temp=ac_bdlr0_b_org;
13757
13758 }
13759
13760 writel(ac_bdlr0_temp,(reg_add));
13761
13762 }
13763 }
13764
13765 }
13766 }
13767
13768 ////tune and save training dqs value
13769
13770
13771
13772
13773 ////calculate and print dqs value
13774 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
13775 {
13776 if (( channel_a_en) && ( channel_b_en == 0))
13777 {
13778 reg_base_adj=CHANNEL_A_REG_BASE;
13779 }
13780 else if(( channel_b_en)&&( channel_a_en==0))
13781 {
13782 reg_base_adj=CHANNEL_B_REG_BASE;
13783 }
13784 else if ((channel_a_en+channel_b_en)==2)
13785 {
13786 if ( testing_channel == CHANNEL_A)
13787 {
13788 reg_base_adj=CHANNEL_A_REG_BASE;
13789 }
13790 else if( testing_channel==CHANNEL_B)
13791 {
13792 reg_base_adj=CHANNEL_B_REG_BASE;
13793 }
13794 }
13795 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
13796
13797 if (reg_base_adj == CHANNEL_A_REG_BASE)
13798 {
13799 if (test_times)
13800 {
13801 if (ac_lcdlr_a_lef>ac_lcdlr_a_lef_min)
13802 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
13803
13804 if (ac_lcdlr_a_rig<ac_lcdlr_a_rig_min)
13805 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
13806
13807 if (ac_bdlr0_a_lef>ac_bdlr0_a_lef_min)
13808 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
13809
13810 if (ac_bdlr0_a_rig<ac_bdlr0_a_rig_min)
13811 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
13812 }
13813 else
13814 {
13815 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
13816 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
13817 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
13818 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
13819 }
13820 printf("\ntest A channel AC result\n");
13821 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
13822 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
13823 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
13824
13825 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_a_org);
13826 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org,ac_lcdlr_a_lef,ac_lcdlr_a_rig,ac_lcdlr_a_lef_min,ac_lcdlr_a_rig_min);
13827 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org,ac_bdlr0_a_lef,ac_bdlr0_a_rig,ac_bdlr0_a_lef_min,ac_bdlr0_a_rig_min);
13828
13829
13830
13831 }
13832
13833 if (reg_base_adj == CHANNEL_B_REG_BASE)
13834 {
13835 if (test_times)
13836 {
13837 if (ac_lcdlr_b_lef>ac_lcdlr_b_lef_min)
13838 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
13839
13840 if (ac_lcdlr_b_rig<ac_lcdlr_b_rig_min)
13841 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
13842
13843 if (ac_bdlr0_b_lef>ac_bdlr0_b_lef_min)
13844 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
13845
13846 if (ac_bdlr0_b_rig<ac_bdlr0_b_rig_min)
13847 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
13848 }
13849 else
13850 {
13851 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
13852 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
13853 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
13854 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
13855 }
13856 printf("\ntest B channel AC result\n");
13857 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
13858 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
13859 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
13860
13861 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_b_org);
13862 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org,ac_lcdlr_b_lef,ac_lcdlr_b_rig,ac_lcdlr_b_lef_min,ac_lcdlr_b_rig_min);
13863 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org,ac_bdlr0_b_lef,ac_bdlr0_b_rig,ac_bdlr0_b_lef_min,ac_bdlr0_b_rig_min);
13864
13865
13866
13867 }
13868
13869
13870
13871 }
13872
13873
13874 }
13875
13876 }
13877
13878
13879
13880
13881 return 0;
13882
13883usage:
13884 cmd_usage(cmdtp);
13885 return 1;
13886
13887}
13888
13889
13890
13891
13892U_BOOT_CMD(
13893 ddr_tune_ddr_ac_aclcdlr, 6, 1, do_ddr_test_ac_windows_aclcdlr,
13894 "DDR tune dqs function",
13895 "ddr_tune_ddr_ac_aclcdlr a 0 0x8000000 3 or ddr_tune_ddr_ac_aclcdlr b 0 0x80000 5 or ddr_tune_ddr_ac_aclcdlr a b 0x80000 l\n dcache off ? \n"
13896);
13897
13898
13899int do_ddr_test_ac_windows_acbdlr_ck(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
13900{
13901 printf("\nEnter Test ddr ac windows function\n");
13902 // if(!argc)
13903 // goto DDR_TUNE_DQS_START;
13904 printf("\nargc== 0x%08x\n", argc);
13905 // unsigned int loop = 1;
13906 // unsigned int temp_count_i = 1;
13907 // unsigned int temp_count_j= 1;
13908 // unsigned int temp_count_k= 1;
13909 unsigned int temp_test_error= 0;
13910
13911
13912 char *endp;
13913 // unsigned int *p_start_addr;
13914 unsigned int test_loop=1;
13915 unsigned int test_times=1;
13916 unsigned int reg_add=0;
13917 unsigned int reg_base_adj=0;
13918 unsigned int channel_a_en = 0;
13919 unsigned int channel_b_en = 0;
13920 unsigned int testing_channel = 0;
13921
13922
13923
13924#define CHANNEL_A 0
13925#define CHANNEL_B 1
13926
13927
13928
13929
13930
13931
13932#define DDR_CROSS_TALK_TEST_SIZE 0x20000
13933
13934 unsigned int ac_mdlr_a_org=0;
13935 unsigned int ac_mdlr_b_org=0;
13936
13937 unsigned int ac_lcdlr_a_org=0;
13938 unsigned int ac_bdlr0_a_org=0;
13939 unsigned int ac_lcdlr_b_org=0;
13940 unsigned int ac_bdlr0_b_org=0;
13941 unsigned int ac_lcdlr_a_rig=0;
13942 unsigned int ac_bdlr0_a_rig=0;
13943 unsigned int ac_lcdlr_b_rig=0;
13944 unsigned int ac_bdlr0_b_rig=0;
13945 unsigned int ac_lcdlr_a_lef=0;
13946 unsigned int ac_bdlr0_a_lef=0;
13947 unsigned int ac_lcdlr_b_lef=0;
13948 unsigned int ac_bdlr0_b_lef=0;
13949
13950 unsigned int ac_lcdlr_a_rig_min=0;
13951 unsigned int ac_bdlr0_a_rig_min=0;
13952 unsigned int ac_lcdlr_b_rig_min=0;
13953 unsigned int ac_bdlr0_b_rig_min=0;
13954 unsigned int ac_lcdlr_a_lef_min=0;
13955 unsigned int ac_bdlr0_a_lef_min=0;
13956 unsigned int ac_lcdlr_b_lef_min=0;
13957 unsigned int ac_bdlr0_b_lef_min=0;
13958 // unsigned int ac_lcdlr_temp;
13959 unsigned int ac_bdlr0_temp=0;
13960
13961
13962
13963 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
13964
13965
13966 //#define DDR_TEST_ACLCDLR
13967
13968
13969 if (argc == 2)
13970 {
13971 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
13972
13973 {channel_a_en = 1;
13974 }
13975 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
13976
13977 {channel_b_en = 1;
13978 }
13979 else
13980 {
13981 goto usage;
13982 }
13983 }
13984 if (argc > 2)
13985 {
13986 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
13987
13988 {channel_a_en = 1;
13989 }
13990 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
13991
13992 {channel_b_en = 1;
13993 }
13994 }
13995 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
13996 if (argc >3) {
13997 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
13998 if (*argv[3] == 0 || *endp != 0)
13999 {
14000 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
14001 }
14002
14003 }
14004 if (argc >4) {
14005 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
14006 if (*argv[4] == 0 || *endp != 0)
14007 {
14008 test_loop = 1;
14009 }
14010 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
14011 {
14012 test_loop = 100000;
14013 }
14014 }
14015
14016 unsigned int test_min_max=0;
14017 if (argc >5) {
14018
14019 test_min_max = simple_strtoull_ddr(argv[5], &endp, 16);
14020 if (*argv[5] == 0 || *endp != 0)
14021 {
14022 test_min_max = 0;
14023 }
14024 else
14025 test_min_max=1;
14026
14027 }
14028
14029 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
14030 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
14031 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
14032 printf("\ntest_loop== 0x%08x\n", test_loop);
14033 printf("\ntest_min_max== 0x%08x\n", test_min_max);
14034 if ( channel_a_en)
14035 {
14036 //writel((0), 0xc8836c00);
14037 OPEN_CHANNEL_A_PHY_CLK();
14038 }
14039 if ( channel_b_en)
14040 {
14041 OPEN_CHANNEL_B_PHY_CLK();
14042 //writel((0), 0xc8836c00);
14043 }
14044
14045
14046 //save and print org training dqs value
14047 if (channel_a_en || channel_b_en)
14048 {
14049
14050
14051 //dcache_disable();
14052 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
14053
14054 {
14055 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
14056 {
14057 if (( channel_a_en) && ( channel_b_en == 0))
14058 {
14059 reg_base_adj=CHANNEL_A_REG_BASE;
14060 }
14061 else if(( channel_b_en)&&( channel_a_en==0))
14062 {
14063 reg_base_adj=CHANNEL_B_REG_BASE;
14064 }
14065 else if ((channel_a_en+channel_b_en)==2)
14066 {
14067 if ( testing_channel == CHANNEL_A)
14068 {
14069 reg_base_adj=CHANNEL_A_REG_BASE;
14070 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
14071
14072
14073
14074 }
14075 else if( testing_channel==CHANNEL_B)
14076 {
14077 reg_base_adj=CHANNEL_B_REG_BASE;
14078
14079 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
14080
14081
14082
14083 }
14084 }
14085
14086 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
14087
14088
14089 if (reg_base_adj == CHANNEL_A_REG_BASE)
14090 {
14091 printf("\ntest A channel 0x%08x\n",reg_add);
14092 ac_mdlr_a_org=(unsigned int )(readl((unsigned int )reg_add));//readl(reg_add);//0xc8836000
14093 ac_lcdlr_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR)));//readl(reg_add+4);
14094 ac_bdlr0_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR)));//readl(reg_add+8);
14095
14096 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
14097 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
14098 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
14099 }
14100 if (reg_base_adj == CHANNEL_B_REG_BASE)
14101 {
14102
14103 ac_mdlr_b_org=readl(reg_add);
14104 ac_lcdlr_b_org=readl(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR);
14105 ac_bdlr0_b_org=readl(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR);
14106 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
14107 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
14108 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
14109 }
14110
14111
14112 }
14113
14114 }
14115
14116 }////save and print org training value
14117
14118
14119 for (test_times=0;(test_times<test_loop);(test_times++))
14120 {
14121 ////tune and save training dqs value
14122 if (channel_a_en || channel_b_en)
14123
14124 {
14125 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
14126 {
14127
14128 if (( channel_a_en) && ( channel_b_en == 0))
14129 {
14130 reg_base_adj=CHANNEL_A_REG_BASE;
14131 }
14132 else if(( channel_b_en)&&( channel_a_en==0))
14133 {
14134 reg_base_adj=CHANNEL_B_REG_BASE;
14135 }
14136 else if ((channel_a_en+channel_b_en)==2)
14137 {
14138 if ( testing_channel == CHANNEL_A)
14139 {
14140 reg_base_adj=CHANNEL_A_REG_BASE;
14141 }
14142 else if( testing_channel==CHANNEL_B)
14143 {
14144 reg_base_adj=CHANNEL_B_REG_BASE;
14145 }
14146 }
14147
14148 if (reg_base_adj == CHANNEL_A_REG_BASE)
14149 {
14150 printf("\ntest A channel AC\n");
14151 }
14152 else
14153 {
14154 printf("\ntest B channel AC\n");
14155 }
14156
14157 {
14158 {
14159#ifdef DDR_TEST_ACLCDLR
14160
14161 reg_add=DDR0_PUB_ACLCDLR+reg_base_adj;
14162
14163 ac_lcdlr_temp=readl(reg_add);
14164
14165 while (ac_lcdlr_temp>0)
14166 {
14167 if (test_min_max)
14168 {break;
14169 }
14170 temp_test_error=0;
14171 ac_lcdlr_temp--;
14172
14173 printf("\nlcdlr test value==0x%08x\n ",ac_lcdlr_temp);
14174 writel(ac_lcdlr_temp,(reg_add));
14175#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
14176 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14177#else
14178 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14179 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
14180#endif
14181 if (temp_test_error)
14182 {
14183 //printf("\nwdqd left edge detect \n");
14184 ac_lcdlr_temp++;
14185 break;
14186 }
14187 }
14188
14189 printf("\nlcdlr left edge detect \n");
14190 printf("\nlcdlr left edge==0x%08x\n ",ac_lcdlr_temp);
14191 if (reg_base_adj == CHANNEL_A_REG_BASE)
14192 {
14193 ac_lcdlr_a_lef=ac_lcdlr_temp;
14194 ac_lcdlr_temp=ac_lcdlr_a_org;
14195 }
14196 else
14197 {
14198 ac_lcdlr_b_lef=ac_lcdlr_temp;
14199 ac_lcdlr_temp=ac_lcdlr_b_org;
14200
14201 }
14202 writel(ac_lcdlr_temp,(reg_add));
14203
14204 while (ac_lcdlr_temp<ACLCDLR_MAX)
14205 {
14206 temp_test_error=0;
14207 ac_lcdlr_temp++;
14208 printf("\nlcdlr test value==0x%08x\n ",ac_lcdlr_temp);
14209 writel(ac_lcdlr_temp,(reg_add));
14210#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
14211 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14212#else
14213 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14214 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
14215#endif
14216 if (temp_test_error)
14217 {
14218 //printf("\nlcdlr right edge detect \n");
14219 ac_lcdlr_temp--;
14220 break;
14221 }
14222 }
14223 printf("\nlcdlrright edge detect \n");
14224 printf("\nlcdlr right edge==0x%08x\n ",ac_lcdlr_temp);
14225
14226
14227
14228 if (reg_base_adj == CHANNEL_A_REG_BASE)
14229 {
14230 ac_lcdlr_a_rig=ac_lcdlr_temp;
14231 ac_lcdlr_temp=ac_lcdlr_a_org;
14232 }
14233 else
14234 {
14235 ac_lcdlr_b_rig=ac_lcdlr_temp;
14236 ac_lcdlr_temp=ac_lcdlr_b_org;
14237
14238 }
14239 writel(ac_lcdlr_temp,(reg_add));
14240
14241
14242
14243#endif
14244
14245 {
14246 reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
14247
14248 ac_bdlr0_temp=readl(reg_add);
14249 while (ac_bdlr0_temp>0)
14250 {
14251 temp_test_error=0;
14252 ac_bdlr0_temp--;
14253 printf("\nbdlr0 test value==0x%08x\n ",ac_bdlr0_temp);
14254 writel(ac_bdlr0_temp,(reg_add));
14255#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
14256 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14257#else
14258 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14259 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
14260#endif
14261 if (temp_test_error)
14262 {
14263 //printf("\nwdqd left edge detect \n");
14264 ac_bdlr0_temp++;
14265 break;
14266 }
14267 }
14268 printf("\nacbdlr0 left edge detect \n");
14269 printf("\nacbdlr0 left edge==0x%08x\n ",ac_bdlr0_temp);
14270
14271 if (reg_base_adj == CHANNEL_A_REG_BASE)
14272 {
14273 ac_bdlr0_a_lef=ac_bdlr0_temp;
14274 ac_bdlr0_temp=ac_bdlr0_a_org;
14275 }
14276 else
14277 {
14278 ac_bdlr0_b_lef=ac_bdlr0_temp;
14279 ac_bdlr0_temp=ac_bdlr0_b_org;
14280
14281 }
14282
14283 writel(ac_bdlr0_temp,(reg_add));
14284
14285 while (ac_bdlr0_temp<ACBDLR_MAX)
14286 {
14287 temp_test_error=0;
14288 ac_bdlr0_temp++;
14289 printf("\nbdlr0 test value==0x%08x\n ",ac_bdlr0_temp);
14290 writel(ac_bdlr0_temp,(reg_add));
14291#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
14292 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14293#else
14294 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
14295 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
14296#endif
14297 if (temp_test_error)
14298 {
14299 //printf("\nacbdlr0 right edge detect \n");
14300 ac_bdlr0_temp--;
14301 break;
14302 }
14303 }
14304 printf("\nacbdlr0 right edge detect \n");
14305 printf("\nacbdlr0 right edge==0x%08x\n ",ac_bdlr0_temp);
14306
14307 if (reg_base_adj == CHANNEL_A_REG_BASE)
14308 {
14309 ac_bdlr0_a_rig=ac_bdlr0_temp;
14310 ac_bdlr0_temp=ac_bdlr0_a_org;
14311 }
14312 else
14313 {
14314 ac_bdlr0_b_rig=ac_bdlr0_temp;
14315 ac_bdlr0_temp=ac_bdlr0_b_org;
14316
14317 }
14318
14319 writel(ac_bdlr0_temp,(reg_add));
14320
14321 }
14322 }
14323
14324 }
14325 }
14326
14327 ////tune and save training dqs value
14328
14329
14330
14331
14332 ////calculate and print dqs value
14333 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
14334 {
14335 if (( channel_a_en) && ( channel_b_en == 0))
14336 {
14337 reg_base_adj=CHANNEL_A_REG_BASE;
14338 }
14339 else if(( channel_b_en)&&( channel_a_en==0))
14340 {
14341 reg_base_adj=CHANNEL_B_REG_BASE;
14342 }
14343 else if ((channel_a_en+channel_b_en)==2)
14344 {
14345 if ( testing_channel == CHANNEL_A)
14346 {
14347 reg_base_adj=CHANNEL_A_REG_BASE;
14348 }
14349 else if( testing_channel==CHANNEL_B)
14350 {
14351 reg_base_adj=CHANNEL_B_REG_BASE;
14352 }
14353 }
14354 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
14355
14356 if (reg_base_adj == CHANNEL_A_REG_BASE)
14357 {
14358 if (test_times)
14359 {
14360 if (ac_lcdlr_a_lef>ac_lcdlr_a_lef_min)
14361 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
14362
14363 if (ac_lcdlr_a_rig<ac_lcdlr_a_rig_min)
14364 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
14365
14366 if (ac_bdlr0_a_lef>ac_bdlr0_a_lef_min)
14367 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
14368
14369 if (ac_bdlr0_a_rig<ac_bdlr0_a_rig_min)
14370 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
14371 }
14372 else
14373 {
14374 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
14375 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
14376 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
14377 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
14378 }
14379 printf("\ntest A channel AC result\n");
14380 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
14381 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
14382 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
14383
14384 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_a_org);
14385 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org,ac_lcdlr_a_lef,ac_lcdlr_a_rig,ac_lcdlr_a_lef_min,ac_lcdlr_a_rig_min);
14386 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org,ac_bdlr0_a_lef,ac_bdlr0_a_rig,ac_bdlr0_a_lef_min,ac_bdlr0_a_rig_min);
14387
14388
14389
14390 }
14391
14392 if (reg_base_adj == CHANNEL_B_REG_BASE)
14393 {
14394 if (test_times)
14395 {
14396 if (ac_lcdlr_b_lef>ac_lcdlr_b_lef_min)
14397 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
14398
14399 if (ac_lcdlr_b_rig<ac_lcdlr_b_rig_min)
14400 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
14401
14402 if (ac_bdlr0_b_lef>ac_bdlr0_b_lef_min)
14403 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
14404
14405 if (ac_bdlr0_b_rig<ac_bdlr0_b_rig_min)
14406 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
14407 }
14408 else
14409 {
14410 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
14411 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
14412 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
14413 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
14414 }
14415 printf("\ntest B channel AC result\n");
14416 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
14417 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
14418 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
14419
14420 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_b_org);
14421 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org,ac_lcdlr_b_lef,ac_lcdlr_b_rig,ac_lcdlr_b_lef_min,ac_lcdlr_b_rig_min);
14422 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org,ac_bdlr0_b_lef,ac_bdlr0_b_rig,ac_bdlr0_b_lef_min,ac_bdlr0_b_rig_min);
14423
14424
14425
14426
14427 }
14428
14429
14430
14431 }
14432
14433
14434 }
14435
14436 }
14437
14438
14439
14440
14441 return 0;
14442
14443usage:
14444 cmd_usage(cmdtp);
14445 return 1;
14446
14447}
14448
14449
14450
14451
14452U_BOOT_CMD(
14453 ddr_tune_ddr_ac_acbdlr_ck, 6, 1, do_ddr_test_ac_windows_acbdlr_ck,
14454 "DDR tune dqs function",
14455 "ddr_tune_ddr_ac_acbdlr_ck a 0 0x8000000 3 or ddr_tune_ddr_ac_acbdlr_ck b 0 0x80000 5 or ddr_tune_ddr_ac_acbdlr_ck a b 0x80000 l\n dcache off ? \n"
14456);
14457
14458
14459int do_ddr_test_ac_bit_margin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
14460{
14461 printf("\nEnterddr_test_ac_window function\n");
14462 unsigned int channel_a_en = 0;
14463 // unsigned int channel_b_en = 0;
14464 // unsigned int reg_add=0;
14465 // unsigned int reg_base_adj=0;
14466
14467 unsigned int lane_step= 0;
14468 unsigned int reg_value= 0;
14469 unsigned int test_ac_setup_hold= 0;
14470 //int argc2;
14471 //char * argv2[30];
14472 // unsigned int acbdlr0_9_reg_org[10];
14473 // unsigned int acbdlr0_9_reg_setup_max[40];
14474 // unsigned int acbdlr0_9_reg_hold_max[40];
14475 // unsigned int acbdlr0_9_reg_setup_time[40];
14476 // unsigned int acbdlr0_9_reg_hold_time[40];
14477
14478 char *endp;
14479
14480 if (argc == 2)
14481 {
14482 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
14483 {
14484 channel_a_en = 1;
14485 }
14486 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
14487 {//channel_b_en = 1;
14488 }
14489 }
14490 if (argc > 2)
14491 {
14492 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
14493 {
14494 channel_a_en = 1;
14495 }
14496 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
14497
14498 {//channel_b_en = 1;
14499 }
14500 }
14501 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
14502 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
14503 if (argc >3) {
14504 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
14505 if (*argv[3] == 0 || *endp != 0)
14506 {
14507 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
14508 }
14509 }
14510 //argc2=5;
14511 //for(i = 1;i<(argc);i++)
14512 {
14513 //argv2[i-1]=argv[i];
14514 }
14515
14516 //argv2[0]=argv[1];
14517 //argv2[1]=argv[2];
14518 //argv2[2]=argv[3];
14519 char str[100];
14520 test_ac_setup_hold=0;
14521 if (channel_a_en)
14522 {
14523
14524 //*(char *)(argv2[0])="a";
14525 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
14526 printf("\ntest ac window a\n");
14527 for ((lane_step=4);(lane_step<40);(lane_step++))
14528 {
14529 if (lane_step == 7)
14530 {lane_step=8;
14531 }
14532 if (lane_step == 12)
14533 {lane_step=16;
14534 }
14535 if (lane_step == 14)
14536 {lane_step=16;
14537 }
14538 if (lane_step == 18)
14539 {lane_step=20;
14540 }
14541 if (lane_step == 22)
14542 {lane_step=24;
14543 }
14544 //sprintf(argv2[3],"d%",( lane_step));
14545 //itoa_ddr_test(lane_step,(argv2[3]),10);
14546 //printf("\nargv2[%d]=%s\n",0,argv2[0]);
14547 // printf("\nargv2[%d]=%s\n",3,argv2[3]);//a 0 0x8000000 0 c
14548 // reg_value=do_ddr_test_dqs_window_step((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
14549 sprintf(str,"ddr_test_ac_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
14550 printf("\nstr=%s\n",str);
14551 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
14552 //printf("\nstr=%s\n",str);
14553 run_command(str,0);
14554
14555 test_ac_setup_hold=2;
14556 sprintf(str,"ddr_test_ac_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
14557 printf("\nstr=%s\n",str);
14558 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
14559 //printf("\nstr=%s\n",str);
14560 run_command(str,0);
14561 test_ac_setup_hold=0;
14562
14563 }
14564 }
14565 if (channel_a_en)
14566 {
14567 for ((lane_step=0);(lane_step<10);(lane_step++))
14568 {
14569 printf("acbdlr0_9_reg_org[%d]0x%08x==0x%08x\n", lane_step,(DDR0_PUB_ACBDLR0+(lane_step<<2)),acbdlr0_9_reg_org[lane_step]);
14570
14571 };
14572
14573 for ((lane_step=0);(lane_step<40);(lane_step++))
14574 {
14575 printf("\n a_ac_lane_0x%08x|setup_max 0x%08x |hold_max 0x%08x |setup_time %08d ps ::|hold_time %08d ps \n",
14576 lane_step,
14577 acbdlr0_9_reg_setup_max[lane_step],
14578 acbdlr0_9_reg_hold_max[lane_step],
14579 acbdlr0_9_reg_setup_time[lane_step],
14580 acbdlr0_9_reg_hold_time[lane_step]);
14581
14582 }
14583 }
14584 return reg_value;
14585}
14586
14587int do_ddr_test_data_bit_margin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
14588{
14589 printf("\nEnterddr_test_data_window function\n");
14590 unsigned int channel_a_en = 0;
14591 // unsigned int channel_b_en = 0;
14592 // unsigned int reg_add=0;
14593 // unsigned int reg_base_adj=0;
14594
14595 unsigned int lane_step= 0;
14596 unsigned int reg_value= 0;
14597 unsigned int test_ac_setup_hold= 0;
14598 //int argc2;
14599 //char * argv2[30];
14600 // unsigned int acbdlr0_9_reg_org[10];
14601 // unsigned int acbdlr0_9_reg_setup_max[40];
14602 // unsigned int acbdlr0_9_reg_hold_max[40];
14603 // unsigned int acbdlr0_9_reg_setup_time[40];
14604 // unsigned int acbdlr0_9_reg_hold_time[40];
14605
14606 char *endp;
14607
14608 if (argc == 2)
14609 {
14610 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
14611
14612 {channel_a_en = 1;
14613 }
14614 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
14615
14616 {//channel_b_en = 1;
14617 }
14618
14619
14620 }
14621 if (argc > 2)
14622 {
14623 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
14624
14625 {channel_a_en = 1;
14626 }
14627 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
14628
14629 {//channel_b_en = 1;
14630 }
14631 }
14632 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
14633 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
14634 if (argc >3) {
14635 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
14636 if (*argv[3] == 0 || *endp != 0)
14637 {
14638 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
14639 }
14640 }
14641 unsigned int ddr_test_type=0;
14642 unsigned int ddr_test_type_para1=0;
14643 unsigned int ddr_test_type_para2=0;
14644 if (argc >4) {
14645 ddr_test_type = simple_strtoull_ddr(argv[4], &endp, 0);
14646 if (*argv[4] == 0 || *endp != 0)
14647 {
14648 ddr_test_type = 0;
14649 }
14650 }
14651 if (ddr_test_type) {
14652 if (argc >5) {
14653 ddr_test_type_para1 = simple_strtoull_ddr(argv[5], &endp, 0);
14654 if (*argv[5] == 0 || *endp != 0)
14655 {
14656 ddr_test_type_para1 = 0;
14657 }
14658 }
14659 if (argc >6) {
14660 ddr_test_type_para2 = simple_strtoull_ddr(argv[6], &endp, 0);
14661 if (*argv[6] == 0 || *endp != 0)
14662 {
14663 ddr_test_type_para2 = 96;
14664 }
14665 }
14666 }else
14667 { ddr_test_type_para1 = 0;
14668 ddr_test_type_para2 = 96;
14669 }
14670 //argc2=5;
14671 //for(i = 1;i<(argc);i++)
14672 {
14673 //argv2[i-1]=argv[i];
14674 }
14675
14676 //argv2[0]=argv[1];
14677 //argv2[1]=argv[2];
14678 //argv2[2]=argv[3];
14679 printf("\ntest data window ddr_test_type==0x%08x, ddr_test_type_para1==0x%08x,ddr_test_type_para2==0x%08x\n",
14680 ddr_test_type,ddr_test_type_para1,ddr_test_type_para2);
14681 char str[100];
14682 unsigned int temp_count=0;
14683 test_ac_setup_hold=0;
14684 if (channel_a_en)
14685 {
14686 for ((temp_count=0);(temp_count<28);(temp_count++))
14687 {
14688 //data_bdlr0_5_reg_org[temp_count]=(((readl(((temp_count>>2)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/6)+reg_base_adj))
14689 // >>(8*(test_bdl%4)))&0xff);
14690 data_bdlr0_5_reg_org[temp_count]=((readl(((temp_count%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/7)))
14691 );
14692 };
14693
14694 //*(char *)(argv2[0])="a";
14695 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
14696 printf("\ntest data window a\n");
14697 for ((lane_step=ddr_test_type_para1);(lane_step<ddr_test_type_para2);(lane_step++))
14698 {
14699 if (lane_step == 9)
14700 {lane_step=12;
14701 }
14702 if (lane_step == 21)
14703 {lane_step=24;
14704 }
14705 if (lane_step == 33)
14706 {lane_step=36;
14707 }
14708 if (lane_step == 45)
14709 {lane_step=48;
14710 }
14711 if (lane_step == 33+24)
14712 {lane_step=36+24;
14713 }
14714 if (lane_step == 45+24)
14715 {lane_step=48+24;
14716 }
14717 if (lane_step == 33+48)
14718 {lane_step=36+48;
14719 }
14720 if (lane_step == 44+48)
14721 {lane_step=48+48;
14722 }
14723
14724 //sprintf(argv2[3],"d%",( lane_step));
14725 //itoa_ddr_test(lane_step,(argv2[3]),10);
14726 //printf("\nargv2[%d]=%s\n",0,argv2[0]);
14727 // printf("\nargv2[%d]=%s\n",3,argv2[3]);//a 0 0x8000000 0 c
14728 // reg_value=do_ddr_test_dqs_window_step((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
14729 sprintf(str,"ddr_test_data_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
14730 printf("\nstr=%s\n",str);
14731 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
14732 //printf("\nstr=%s\n",str);
14733 run_command(str,0);
14734
14735 test_ac_setup_hold=1;
14736 sprintf(str,"ddr_test_data_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
14737 printf("\nstr=%s\n",str);
14738 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
14739 //printf("\nstr=%s\n",str);
14740 run_command(str,0);
14741 test_ac_setup_hold=0;
14742 for ((temp_count=0);(temp_count<28);(temp_count++))
14743 {
14744 writel(((data_bdlr0_5_reg_org[temp_count])),
14745 (((temp_count%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(temp_count/7)));
14746
14747 };
14748
14749
14750 }
14751 }
14752
14753
14754
14755
14756
14757 if (channel_a_en)
14758 {
14759 for ((lane_step=0);(lane_step<28);(lane_step++))
14760 {
14761 printf("data_bdlr0_5_reg_org[%d]0x%08x==0x%08x\n", lane_step,
14762 (((lane_step%7)<<2)+DDR0_PUB_DX0BDLR0+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(lane_step/7)),
14763 data_bdlr0_5_reg_org[lane_step]);
14764
14765 };
14766
14767 for ((lane_step=0);(lane_step<96);(lane_step++))
14768 {
14769 printf("\n a_ac_lane_0x%08x|setup_max 0x%08x |hold_max 0x%08x |setup_time %08d ps ::|hold_time %08d ps \n",
14770 lane_step,
14771 bdlr0_9_reg_setup_max[lane_step],
14772 bdlr0_9_reg_hold_max[lane_step],
14773 bdlr0_9_reg_setup_time[lane_step],
14774 bdlr0_9_reg_hold_time[lane_step]);
14775
14776 }}
14777
14778
14779
14780 return reg_value;
14781}
14782
14783//#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
14784int do_ddr_gx_crosstalk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
14785{
14786 ///*
14787 unsigned int des[8] ;
14788 unsigned int pattern_1[4][8] ;
14789 unsigned int pattern_2[4][8] ;
14790 unsigned int pattern_3[4][8] ;
14791 unsigned int pattern_4[4][8] ;
14792 unsigned int pattern_5[4][8] ;
14793 unsigned int pattern_6[4][8] ;
14794
14795
14796 des[0] = 0xaec83f49;
14797 des[1] = 0xd243a62c;
14798 des[2] = 0xf8774a0b;
14799 des[3] = 0x63d214e5;
14800 des[4] = 0x3f4166d5;
14801 des[5] = 0x239672c0;
14802 des[6] = 0x47ba7533;
14803 des[7] = 0xcae4cd7f;
14804 pattern_1[0][0] = 0xff00ff00;
14805 pattern_1[0][1] = 0xff00ff00;
14806 pattern_1[0][2] = 0xff00ff00;
14807 pattern_1[0][3] = 0xff00ff00;
14808 pattern_1[0][4] = 0xff00ff00;
14809 pattern_1[0][5] = 0xff00ff00;
14810 pattern_1[0][6] = 0xff00ff00;
14811 pattern_1[0][7] = 0xff00ff00;
14812
14813 pattern_1[1][0] = 0x00ffff00;
14814 pattern_1[1][1] = 0x00ffff00;
14815 pattern_1[1][2] = 0x00ffff00;
14816 pattern_1[1][3] = 0x00ffff00;
14817 pattern_1[1][4] = 0x00ffff00;
14818 pattern_1[1][5] = 0x00ffff00;
14819 pattern_1[1][6] = 0x00ffff00;
14820 pattern_1[1][7] = 0x00ffff00;
14821
14822 pattern_1[2][0] = 0xffff0000;
14823 pattern_1[2][1] = 0xffff0000;
14824 pattern_1[2][2] = 0xffff0000;
14825 pattern_1[2][3] = 0xffff0000;
14826 pattern_1[2][4] = 0xffff0000;
14827 pattern_1[2][5] = 0xffff0000;
14828 pattern_1[2][6] = 0xffff0000;
14829 pattern_1[2][7] = 0xffff0000;
14830
14831 pattern_1[3][0] = 0xff00ff00;
14832 pattern_1[3][1] = 0xff00ff00;
14833 pattern_1[3][2] = 0xff00ff00;
14834 pattern_1[3][3] = 0xff00ff00;
14835 pattern_1[3][4] = 0xff00ff00;
14836 pattern_1[3][5] = 0xff00ff00;
14837 pattern_1[3][6] = 0xff00ff00;
14838 pattern_1[3][7] = 0xff00ff00;
14839
14840 pattern_2[0][0] = 0x0001fe00;
14841 pattern_2[0][1] = 0x0000ff00;
14842 pattern_2[0][2] = 0x0000ff00;
14843 pattern_2[0][3] = 0x0000ff00;
14844 pattern_2[0][4] = 0x0002fd00;
14845 pattern_2[0][5] = 0x0000ff00;
14846 pattern_2[0][6] = 0x0000ff00;
14847 pattern_2[0][7] = 0x0000ff00;
14848
14849 pattern_2[1][0] = 0x0004fb00;
14850 pattern_2[1][1] = 0x0000ff00;
14851 pattern_2[1][2] = 0x0000ff00;
14852 pattern_2[1][3] = 0x0000ff00;
14853 pattern_2[1][4] = 0x0008f700;
14854 pattern_2[1][5] = 0x0000ff00;
14855 pattern_2[1][6] = 0x0000ff00;
14856 pattern_2[1][7] = 0x0000ff00;
14857
14858 pattern_2[2][0] = 0x0010ef00;
14859 pattern_2[2][1] = 0x0000ff00;
14860 pattern_2[2][2] = 0x0000ff00;
14861 pattern_2[2][3] = 0x0000ff00;
14862 pattern_2[2][4] = 0x0020df00;
14863 pattern_2[2][5] = 0x0000ff00;
14864 pattern_2[2][6] = 0x0000ff00;
14865 pattern_2[2][7] = 0x0000ff00;
14866
14867 pattern_2[3][0] = 0x0040bf00;
14868 pattern_2[3][1] = 0x0000ff00;
14869 pattern_2[3][2] = 0x0000ff00;
14870 pattern_2[3][3] = 0x0000ff00;
14871 pattern_2[3][4] = 0x00807f00;
14872 pattern_2[3][5] = 0x0000ff00;
14873 pattern_2[3][6] = 0x0000ff00;
14874 pattern_2[3][7] = 0x0000ff00;
14875
14876 pattern_3[0][0] = 0x00010000;
14877 pattern_3[0][1] = 0x00000000;
14878 pattern_3[0][2] = 0x00000000;
14879 pattern_3[0][3] = 0x00000000;
14880 pattern_3[0][4] = 0x00020000;
14881 pattern_3[0][5] = 0x00000000;
14882 pattern_3[0][6] = 0x00000000;
14883 pattern_3[0][7] = 0x00000000;
14884
14885 pattern_3[1][0] = 0x00040000;
14886 pattern_3[1][1] = 0x00000000;
14887 pattern_3[1][2] = 0x00000000;
14888 pattern_3[1][3] = 0x00000000;
14889 pattern_3[1][4] = 0x00080000;
14890 pattern_3[1][5] = 0x00000000;
14891 pattern_3[1][6] = 0x00000000;
14892 pattern_3[1][7] = 0x00000000;
14893
14894 pattern_3[2][0] = 0x00100000;
14895 pattern_3[2][1] = 0x00000000;
14896 pattern_3[2][2] = 0x00000000;
14897 pattern_3[2][3] = 0x00000000;
14898 pattern_3[2][4] = 0x00200000;
14899 pattern_3[2][5] = 0x00000000;
14900 pattern_3[2][6] = 0x00000000;
14901 pattern_3[2][7] = 0x00000000;
14902
14903 pattern_3[3][0] = 0x00400000;
14904 pattern_3[3][1] = 0x00000000;
14905 pattern_3[3][2] = 0x00000000;
14906 pattern_3[3][3] = 0x00000000;
14907 pattern_3[3][4] = 0x00800000;
14908 pattern_3[3][5] = 0x00000000;
14909 pattern_3[3][6] = 0x00000000;
14910 pattern_3[3][7] = 0x00000000;
14911
14912 ///*
14913 pattern_4[0][0] = 0x51c8c049 ;
14914 pattern_4[0][1] = 0x2d43592c ;
14915 pattern_4[0][2] = 0x0777b50b ;
14916 pattern_4[0][3] = 0x9cd2ebe5 ;
14917 pattern_4[0][4] = 0xc04199d5 ;
14918 pattern_4[0][5] = 0xdc968dc0 ;
14919 pattern_4[0][6] = 0xb8ba8a33 ;
14920 pattern_4[0][7] = 0x35e4327f ;
14921
14922 pattern_4[1][0] = 0xae37c049 ;
14923 pattern_4[1][1] = 0xd2bc592c ;
14924 pattern_4[1][2] = 0xf888b50b ;
14925 pattern_4[1][3] = 0x632debe5 ;
14926 pattern_4[1][4] = 0x3fbe99d5 ;
14927 pattern_4[1][5] = 0x23698dc0 ;
14928 pattern_4[1][6] = 0x47458a33 ;
14929 pattern_4[1][7] = 0xca1b327f ;
14930
14931 pattern_4[2][0] = 0x51373f49 ;
14932 pattern_4[2][1] = 0x2dbca62c ;
14933 pattern_4[2][2] = 0x07884a0b ;
14934 pattern_4[2][3] = 0x9c2d14e5 ;
14935 pattern_4[2][4] = 0xc0be66d5 ;
14936 pattern_4[2][5] = 0xdc6972c0 ;
14937 pattern_4[2][6] = 0xb8457533 ;
14938 pattern_4[2][7] = 0x351bcd7f ;
14939
14940
14941 pattern_4[3][0] = 0x51c8c049 ;
14942 pattern_4[3][1] = 0x2d43592c ;
14943 pattern_4[3][2] = 0x0777b50b ;
14944 pattern_4[3][3] = 0x9cd2ebe5 ;
14945 pattern_4[3][4] = 0xc04199d5 ;
14946 pattern_4[3][5] = 0xdc968dc0 ;
14947 pattern_4[3][6] = 0xb8ba8a33 ;
14948 pattern_4[3][7] = 0x35e4327f ;
14949
14950 pattern_5[0][0] = 0xaec9c149 ;
14951 pattern_5[0][1] = 0xd243592c ;
14952 pattern_5[0][2] = 0xf877b50b ;
14953 pattern_5[0][3] = 0x63d2ebe5 ;
14954 pattern_5[0][4] = 0x3f439bd5 ;
14955 pattern_5[0][5] = 0x23968dc0 ;
14956 pattern_5[0][6] = 0x47ba8a33 ;
14957 pattern_5[0][7] = 0xcae4327f ;
14958 pattern_5[1][0] = 0xaeccc449 ;
14959 pattern_5[1][1] = 0xd243592c ;
14960 pattern_5[1][2] = 0xf877b50b ;
14961 pattern_5[1][3] = 0x63d2ebe5 ;
14962 pattern_5[1][4] = 0x3f4991d5 ;
14963 pattern_5[1][5] = 0x23968dc0 ;
14964 pattern_5[1][6] = 0x47ba8a33 ;
14965 pattern_5[1][7] = 0xcae4327f ;
14966 pattern_5[2][0] = 0xaed8d049 ;
14967 pattern_5[2][1] = 0xd243592c ;
14968 pattern_5[2][2] = 0xf877b50b ;
14969 pattern_5[2][3] = 0x63d2ebe5 ;
14970 pattern_5[2][4] = 0x3f61b9d5 ;
14971 pattern_5[2][5] = 0x23968dc0 ;
14972 pattern_5[2][6] = 0x47ba8a33 ;
14973 pattern_5[2][7] = 0xcae4327f ;
14974 pattern_5[3][0] = 0xae888049 ;
14975 pattern_5[3][1] = 0xd243592c ;
14976 pattern_5[3][2] = 0xf877b50b ;
14977 pattern_5[3][3] = 0x63d2ebe5 ;
14978 pattern_5[3][4] = 0x3fc119d5 ;
14979 pattern_5[3][5] = 0x23968dc0 ;
14980 pattern_5[3][6] = 0x47ba8a33 ;
14981 pattern_5[3][7] = 0xcae4327f ;
14982
14983 pattern_6[0][0] = 0xaec93f49 ;
14984 pattern_6[0][1] = 0xd243a62c ;
14985 pattern_6[0][2] = 0xf8774a0b ;
14986 pattern_6[0][3] = 0x63d214e5 ;
14987 pattern_6[0][4] = 0x3f4366d5 ;
14988 pattern_6[0][5] = 0x239672c0 ;
14989 pattern_6[0][6] = 0x47ba7533 ;
14990 pattern_6[0][7] = 0xcae4cd7f ;
14991 pattern_6[1][0] = 0xaecc3f49 ;
14992 pattern_6[1][1] = 0xd243a62c ;
14993 pattern_6[1][2] = 0xf8774a0b ;
14994 pattern_6[1][3] = 0x63d214e5 ;
14995 pattern_6[1][4] = 0x3f4966d5 ;
14996 pattern_6[1][5] = 0x239672c0 ;
14997 pattern_6[1][6] = 0x47ba7533 ;
14998 pattern_6[1][7] = 0xcae4cd7f ;
14999 pattern_6[2][0] = 0xaed83f49 ;
15000 pattern_6[2][1] = 0xd243a62c ;
15001 pattern_6[2][2] = 0xf8774a0b ;
15002 pattern_6[2][3] = 0x63d214e5 ;
15003 pattern_6[2][4] = 0x3f6166d5 ;
15004 pattern_6[2][5] = 0x239672c0 ;
15005 pattern_6[2][6] = 0x47ba7533 ;
15006 pattern_6[2][7] = 0xcae4cd7f ;
15007 pattern_6[3][0] = 0xae883f49 ;
15008 pattern_6[3][1] = 0xd243a62c ;
15009 pattern_6[3][2] = 0xf8774a0b ;
15010 pattern_6[3][3] = 0x63d214e5 ;
15011 pattern_6[3][4] = 0x3fc166d5 ;
15012 pattern_6[3][5] = 0x239672c0 ;
15013 pattern_6[3][6] = 0x47ba7533 ;
15014 pattern_6[3][7] = 0xcae4cd7f ;
15015 //*/
15016 //*/
15017
15018 char *endp;
15019 unsigned int loop = 1;
15020 unsigned int lflag = 0;
15021 unsigned int start_addr = DDR_TEST_START_ADDR;
15022 unsigned int test_size = DDR_TEST_SIZE;
15023 unsigned int test_addr;
15024
15025 error_outof_count_flag =0;
15026 error_count =0;
15027 printf("\nargc== 0x%08x\n", argc);
15028 int i ;
15029 for (i = 0;i<argc;i++)
15030 {
15031 printf("\nargv[%d]=%s\n",i,argv[i]);
15032 }
15033 if (argc == 1)
15034 goto usage;
15035 if (argc>1)
15036 {
15037 if (strcmp(argv[1], "l") == 0) {
15038 lflag = 1;
15039 }
15040
15041 else{
15042 loop = simple_strtoull_ddr(argv[1], &endp, 10);
15043 if (*argv[1] == 0 || *endp != 0)
15044 loop = 1;
15045 }
15046
15047 // printf("\nLINE== 0x%08x\n", __LINE__);
15048 if (argc ==1) {
15049 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
15050 // if (*argv[2] == 0 || *endp != 0)
15051 start_addr = DDR_TEST_START_ADDR;
15052 loop = 1;
15053
15054 }
15055 }
15056
15057
15058
15059 if (argc >= 2) {
15060 loop = simple_strtoull_ddr(argv[1], &endp, 16);
15061 if (*argv[1] == 0 || *endp != 0)
15062 loop = 1;
15063
15064 }
15065 unsigned int pattern_flag1=1;
15066 unsigned int pattern_flag2=1;
15067 unsigned int pattern_flag3=1;
15068 pattern_flag1 = 1;
15069 pattern_flag2=1;
15070 pattern_flag3 = 1;
15071
15072
15073 if (argc >= 3 ) {
15074 if ( (strcmp(argv[2], "s") == 0))
15075 {
15076 pattern_flag1 = 1;
15077 pattern_flag2=0;
15078 pattern_flag3 = 0;
15079 }
15080 else if ((strcmp(argv[2], "c") == 0))
15081 {
15082 pattern_flag1 = 0;
15083 pattern_flag2=1;
15084 pattern_flag3 = 0;
15085 }
15086 else if ( (strcmp(argv[2], "d") == 0))
15087 {
15088 pattern_flag1 = 0;
15089 pattern_flag2=0;
15090 pattern_flag3 = 1;
15091 }
15092 }
15093
15094 // if(test_size<0x20)
15095 start_addr=0x10000000;
15096 test_size = 0x20;
15097 unsigned int temp_i=0;
15098 unsigned int temp_k=0;
15099 unsigned int pattern_o[8];
15100 unsigned int pattern_d[8];
15101
15102
15103 //DDR_TEST_START:
15104
15105 ///*
15106 error_count=0;
15107 do {
15108 if (lflag)
15109 loop = 888;
15110
15111 //if(old_pattern_flag==1)
15112 {
15113
15114 printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
15115
15116 /*
15117 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15118 {
15119
15120 for ((temp_i=0);(temp_i<8);(temp_i++))
15121 {
15122 test_addr=start_addr+(temp_i<<2);
15123 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15124 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15125 //des[temp_i]^pattern_2[temp_k][temp_i]
15126 }
15127 // _clean_dcache_addr(0x10000000);
15128 flush_dcache_range(start_addr,start_addr + test_size);
15129
15130 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15131 test_addr=start_addr+(temp_i<<2);
15132 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15133 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15134 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15135 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15136 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
15137 {error_count++;
15138 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
15139 }
15140 }
15141 }
15142 }
15143 */
15144 if (pattern_flag1 == 1) {
15145 for ((temp_k=0);(temp_k<4);(temp_k++))
15146 {
15147 {
15148 ddr_udelay(10000);
15149 for ((temp_i=0);(temp_i<8);(temp_i++))
15150 {
15151 test_addr=start_addr+(temp_i<<2);
15152 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15153 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15154 //des[temp_i]^pattern_2[temp_k][temp_i]
15155 }
15156 // _clean_dcache_addr(0x10000000);
15157#ifdef DDR_PREFETCH_CACHE
15158 flush_dcache_range(start_addr,start_addr + test_size);
15159#endif
15160 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15161 test_addr=start_addr+(temp_i<<2);
15162 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15163 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
15164 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15165 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
15166 if (pattern_o[temp_i] != pattern_4[temp_k][temp_i])
15167 {error_count++;
15168 printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
15169 }
15170
15171 }
15172 }
15173 }
15174 for ((temp_k=0);(temp_k<4);(temp_k++))
15175 {
15176 {
15177 ddr_udelay(10000);
15178 for ((temp_i=0);(temp_i<8);(temp_i++))
15179 {
15180 test_addr=start_addr+(temp_i<<2);
15181 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15182 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15183 //des[temp_i]^pattern_2[temp_k][temp_i]
15184 }
15185 // _clean_dcache_addr(0x10000000);
15186#ifdef DDR_PREFETCH_CACHE
15187 flush_dcache_range(start_addr,start_addr + test_size);
15188#endif
15189 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15190 test_addr=start_addr+(temp_i<<2);
15191 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15192 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
15193 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15194 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
15195 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15196 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15197 {error_count++;
15198 printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]);
15199 }
15200
15201 }
15202 }
15203 }
15204 }
15205 if (pattern_flag2 == 1) {
15206 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15207 {
15208 ddr_udelay(10000);
15209 for ((temp_i=0);(temp_i<8);(temp_i++))
15210 {
15211 test_addr=start_addr+(temp_i<<2);
15212 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15213 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15214 //des[temp_i]^pattern_2[temp_k][temp_i]
15215 }
15216 // _clean_dcache_addr(0x10000000);
15217#ifdef DDR_PREFETCH_CACHE
15218 flush_dcache_range(start_addr,start_addr + test_size);
15219#endif
15220 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15221 test_addr=start_addr+(temp_i<<2);
15222 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15223 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15224 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15225 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15226 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
15227 {error_count++;
15228 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
15229 }
15230 }
15231 }
15232 }
15233 for ((temp_k=0);(temp_k<4);(temp_k++))
15234 {
15235 {
15236 ddr_udelay(10000);
15237 for ((temp_i=0);(temp_i<8);(temp_i++))
15238 {
15239 test_addr=start_addr+(temp_i<<2);
15240 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15241 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15242 //des[temp_i]^pattern_2[temp_k][temp_i]
15243 }
15244 // _clean_dcache_addr(0x10000000);
15245#ifdef DDR_PREFETCH_CACHE
15246 flush_dcache_range(start_addr,start_addr + test_size);
15247#endif
15248 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15249 test_addr=start_addr+(temp_i<<2);
15250 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15251 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15252 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15253 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15254 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15255 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15256 {error_count++;
15257 printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]);
15258 }
15259 }
15260 }
15261 }
15262
15263 }
15264
15265 if (pattern_flag3 == 1) {
15266 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15267 {
15268 ddr_udelay(10000);
15269 for ((temp_i=0);(temp_i<8);(temp_i++))
15270 {
15271 test_addr=start_addr+(temp_i<<2);
15272 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15273 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15274 //des[temp_i]^pattern_2[temp_k][temp_i]
15275 }
15276 // _clean_dcache_addr(0x10000000);
15277#ifdef DDR_PREFETCH_CACHE
15278 flush_dcache_range(start_addr,start_addr + test_size);
15279#endif
15280 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15281 test_addr=start_addr+(temp_i<<2);
15282 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15283 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
15284 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15285 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
15286 if (pattern_o[temp_i] != pattern_6[temp_k][temp_i])
15287 {error_count++;
15288 printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]);
15289 }
15290 }
15291 }
15292 }
15293 for ((temp_k=0);(temp_k<4);(temp_k++))
15294 {
15295 {
15296 ddr_udelay(10000);
15297 for ((temp_i=0);(temp_i<8);(temp_i++))
15298 {
15299 test_addr=start_addr+(temp_i<<2);
15300 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15301 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15302 //des[temp_i]^pattern_2[temp_k][temp_i]
15303 }
15304 // _clean_dcache_addr(0x10000000);
15305#ifdef DDR_PREFETCH_CACHE
15306 flush_dcache_range(start_addr,start_addr + test_size);
15307#endif
15308 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15309 test_addr=start_addr+(temp_i<<2);
15310 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15311 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
15312 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15313 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
15314 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15315 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15316 {error_count++;
15317 printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]);
15318 }
15319 }
15320 }
15321 }
15322 }
15323
15324
15325
15326 }
15327
15328 printf("\Error count==0x%08x", error_count);
15329 printf("\n \n");
15330 }while(--loop);
15331 //*/
15332
15333 printf("\rEnd ddr test. \n");
15334
15335 return 0;
15336
15337usage:
15338 cmd_usage(cmdtp);
15339 return 1;
15340}
15341
15342
15343U_BOOT_CMD(
15344 ddrtest_gx_crosstalk, 5, 1, do_ddr_gx_crosstalk,
15345 "DDR test function",
15346 "ddrtest [LOOP] [ADDR].Default address is 0x10000000\n"
15347);
15348
15349
15350
15351//#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY)
15352int do_ddr_gxtvbb_crosstalk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
15353{
15354 ///*
15355 unsigned int a_des[8],b_des[8],des[8] ;
15356 unsigned int pattern_1[4][8] ;
15357 unsigned int pattern_2[4][8] ;
15358 unsigned int pattern_3[4][8] ;
15359 // unsigned int pattern_4[4][8] ;
15360 // unsigned int pattern_5[4][8] ;
15361 // unsigned int pattern_6[4][8] ;
15362
15363
15364 a_des[0] = 0x7ea09b52;
15365 a_des[1] = 0xbc57bb23;
15366 a_des[2] = 0x8d2b6e65;
15367 a_des[3] = 0x15fdcdc4;
15368 a_des[4] = 0xbc1df453;
15369 a_des[5] = 0x21bcbcdf;
15370 a_des[6] = 0x267b7ac1;
15371 a_des[7] = 0x6af03d72;
15372
15373
15374 b_des[0] = 0xdfc2ee12;
15375 b_des[1] = 0x4f58da43;
15376 b_des[2] = 0x87809557;
15377 b_des[3] = 0xb87ddbf4;
15378 b_des[4] = 0x667fb021;
15379 b_des[5] = 0x64593586;
15380 b_des[6] = 0xee73d8d5;
15381 b_des[7] = 0xe65f972d;
15382 pattern_1[0][0] = 0xff00ff00;
15383 pattern_1[0][1] = 0xff00ff00;
15384 pattern_1[0][2] = 0xff00ff00;
15385 pattern_1[0][3] = 0xff00ff00;
15386 pattern_1[0][4] = 0xff00ff00;
15387 pattern_1[0][5] = 0xff00ff00;
15388 pattern_1[0][6] = 0xff00ff00;
15389 pattern_1[0][7] = 0xff00ff00;
15390
15391 pattern_1[1][0] = 0x00ffff00;
15392 pattern_1[1][1] = 0x00ffff00;
15393 pattern_1[1][2] = 0x00ffff00;
15394 pattern_1[1][3] = 0x00ffff00;
15395 pattern_1[1][4] = 0x00ffff00;
15396 pattern_1[1][5] = 0x00ffff00;
15397 pattern_1[1][6] = 0x00ffff00;
15398 pattern_1[1][7] = 0x00ffff00;
15399
15400 pattern_1[2][0] = 0xffff0000;
15401 pattern_1[2][1] = 0xffff0000;
15402 pattern_1[2][2] = 0xffff0000;
15403 pattern_1[2][3] = 0xffff0000;
15404 pattern_1[2][4] = 0xffff0000;
15405 pattern_1[2][5] = 0xffff0000;
15406 pattern_1[2][6] = 0xffff0000;
15407 pattern_1[2][7] = 0xffff0000;
15408
15409 pattern_1[3][0] = 0xff00ff00;
15410 pattern_1[3][1] = 0xff00ff00;
15411 pattern_1[3][2] = 0xff00ff00;
15412 pattern_1[3][3] = 0xff00ff00;
15413 pattern_1[3][4] = 0xff00ff00;
15414 pattern_1[3][5] = 0xff00ff00;
15415 pattern_1[3][6] = 0xff00ff00;
15416 pattern_1[3][7] = 0xff00ff00;
15417
15418 pattern_2[0][0] = 0x0001fe00;
15419 pattern_2[0][1] = 0x0000ff00;
15420 pattern_2[0][2] = 0x0000ff00;
15421 pattern_2[0][3] = 0x0000ff00;
15422 pattern_2[0][4] = 0x0002fd00;
15423 pattern_2[0][5] = 0x0000ff00;
15424 pattern_2[0][6] = 0x0000ff00;
15425 pattern_2[0][7] = 0x0000ff00;
15426
15427 pattern_2[1][0] = 0x0004fb00;
15428 pattern_2[1][1] = 0x0000ff00;
15429 pattern_2[1][2] = 0x0000ff00;
15430 pattern_2[1][3] = 0x0000ff00;
15431 pattern_2[1][4] = 0x0008f700;
15432 pattern_2[1][5] = 0x0000ff00;
15433 pattern_2[1][6] = 0x0000ff00;
15434 pattern_2[1][7] = 0x0000ff00;
15435
15436 pattern_2[2][0] = 0x0010ef00;
15437 pattern_2[2][1] = 0x0000ff00;
15438 pattern_2[2][2] = 0x0000ff00;
15439 pattern_2[2][3] = 0x0000ff00;
15440 pattern_2[2][4] = 0x0020df00;
15441 pattern_2[2][5] = 0x0000ff00;
15442 pattern_2[2][6] = 0x0000ff00;
15443 pattern_2[2][7] = 0x0000ff00;
15444
15445 pattern_2[3][0] = 0x0040bf00;
15446 pattern_2[3][1] = 0x0000ff00;
15447 pattern_2[3][2] = 0x0000ff00;
15448 pattern_2[3][3] = 0x0000ff00;
15449 pattern_2[3][4] = 0x00807f00;
15450 pattern_2[3][5] = 0x0000ff00;
15451 pattern_2[3][6] = 0x0000ff00;
15452 pattern_2[3][7] = 0x0000ff00;
15453
15454 pattern_3[0][0] = 0x00010000;
15455 pattern_3[0][1] = 0x00000000;
15456 pattern_3[0][2] = 0x00000000;
15457 pattern_3[0][3] = 0x00000000;
15458 pattern_3[0][4] = 0x00020000;
15459 pattern_3[0][5] = 0x00000000;
15460 pattern_3[0][6] = 0x00000000;
15461 pattern_3[0][7] = 0x00000000;
15462
15463 pattern_3[1][0] = 0x00040000;
15464 pattern_3[1][1] = 0x00000000;
15465 pattern_3[1][2] = 0x00000000;
15466 pattern_3[1][3] = 0x00000000;
15467 pattern_3[1][4] = 0x00080000;
15468 pattern_3[1][5] = 0x00000000;
15469 pattern_3[1][6] = 0x00000000;
15470 pattern_3[1][7] = 0x00000000;
15471
15472 pattern_3[2][0] = 0x00100000;
15473 pattern_3[2][1] = 0x00000000;
15474 pattern_3[2][2] = 0x00000000;
15475 pattern_3[2][3] = 0x00000000;
15476 pattern_3[2][4] = 0x00200000;
15477 pattern_3[2][5] = 0x00000000;
15478 pattern_3[2][6] = 0x00000000;
15479 pattern_3[2][7] = 0x00000000;
15480
15481 pattern_3[3][0] = 0x00400000;
15482 pattern_3[3][1] = 0x00000000;
15483 pattern_3[3][2] = 0x00000000;
15484 pattern_3[3][3] = 0x00000000;
15485 pattern_3[3][4] = 0x00800000;
15486 pattern_3[3][5] = 0x00000000;
15487 pattern_3[3][6] = 0x00000000;
15488 pattern_3[3][7] = 0x00000000;
15489
15490 /*
15491 pattern_4[0][0] = 0x51c8c049 ;
15492 pattern_4[0][1] = 0x2d43592c ;
15493 pattern_4[0][2] = 0x0777b50b ;
15494 pattern_4[0][3] = 0x9cd2ebe5 ;
15495 pattern_4[0][4] = 0xc04199d5 ;
15496 pattern_4[0][5] = 0xdc968dc0 ;
15497 pattern_4[0][6] = 0xb8ba8a33 ;
15498 pattern_4[0][7] = 0x35e4327f ;
15499
15500 pattern_4[1][0] = 0xae37c049 ;
15501 pattern_4[1][1] = 0xd2bc592c ;
15502 pattern_4[1][2] = 0xf888b50b ;
15503 pattern_4[1][3] = 0x632debe5 ;
15504 pattern_4[1][4] = 0x3fbe99d5 ;
15505 pattern_4[1][5] = 0x23698dc0 ;
15506 pattern_4[1][6] = 0x47458a33 ;
15507 pattern_4[1][7] = 0xca1b327f ;
15508
15509 pattern_4[2][0] = 0x51373f49 ;
15510 pattern_4[2][1] = 0x2dbca62c ;
15511 pattern_4[2][2] = 0x07884a0b ;
15512 pattern_4[2][3] = 0x9c2d14e5 ;
15513 pattern_4[2][4] = 0xc0be66d5 ;
15514 pattern_4[2][5] = 0xdc6972c0 ;
15515 pattern_4[2][6] = 0xb8457533 ;
15516 pattern_4[2][7] = 0x351bcd7f ;
15517
15518
15519 pattern_4[3][0] = 0x51c8c049 ;
15520 pattern_4[3][1] = 0x2d43592c ;
15521 pattern_4[3][2] = 0x0777b50b ;
15522 pattern_4[3][3] = 0x9cd2ebe5 ;
15523 pattern_4[3][4] = 0xc04199d5 ;
15524 pattern_4[3][5] = 0xdc968dc0 ;
15525 pattern_4[3][6] = 0xb8ba8a33 ;
15526 pattern_4[3][7] = 0x35e4327f ;
15527
15528 pattern_5[0][0] = 0xaec9c149 ;
15529 pattern_5[0][1] = 0xd243592c ;
15530 pattern_5[0][2] = 0xf877b50b ;
15531 pattern_5[0][3] = 0x63d2ebe5 ;
15532 pattern_5[0][4] = 0x3f439bd5 ;
15533 pattern_5[0][5] = 0x23968dc0 ;
15534 pattern_5[0][6] = 0x47ba8a33 ;
15535 pattern_5[0][7] = 0xcae4327f ;
15536 pattern_5[1][0] = 0xaeccc449 ;
15537 pattern_5[1][1] = 0xd243592c ;
15538 pattern_5[1][2] = 0xf877b50b ;
15539 pattern_5[1][3] = 0x63d2ebe5 ;
15540 pattern_5[1][4] = 0x3f4991d5 ;
15541 pattern_5[1][5] = 0x23968dc0 ;
15542 pattern_5[1][6] = 0x47ba8a33 ;
15543 pattern_5[1][7] = 0xcae4327f ;
15544 pattern_5[2][0] = 0xaed8d049 ;
15545 pattern_5[2][1] = 0xd243592c ;
15546 pattern_5[2][2] = 0xf877b50b ;
15547 pattern_5[2][3] = 0x63d2ebe5 ;
15548 pattern_5[2][4] = 0x3f61b9d5 ;
15549 pattern_5[2][5] = 0x23968dc0 ;
15550 pattern_5[2][6] = 0x47ba8a33 ;
15551 pattern_5[2][7] = 0xcae4327f ;
15552 pattern_5[3][0] = 0xae888049 ;
15553 pattern_5[3][1] = 0xd243592c ;
15554 pattern_5[3][2] = 0xf877b50b ;
15555 pattern_5[3][3] = 0x63d2ebe5 ;
15556 pattern_5[3][4] = 0x3fc119d5 ;
15557 pattern_5[3][5] = 0x23968dc0 ;
15558 pattern_5[3][6] = 0x47ba8a33 ;
15559 pattern_5[3][7] = 0xcae4327f ;
15560
15561 pattern_6[0][0] = 0xaec93f49 ;
15562 pattern_6[0][1] = 0xd243a62c ;
15563 pattern_6[0][2] = 0xf8774a0b ;
15564 pattern_6[0][3] = 0x63d214e5 ;
15565 pattern_6[0][4] = 0x3f4366d5 ;
15566 pattern_6[0][5] = 0x239672c0 ;
15567 pattern_6[0][6] = 0x47ba7533 ;
15568 pattern_6[0][7] = 0xcae4cd7f ;
15569 pattern_6[1][0] = 0xaecc3f49 ;
15570 pattern_6[1][1] = 0xd243a62c ;
15571 pattern_6[1][2] = 0xf8774a0b ;
15572 pattern_6[1][3] = 0x63d214e5 ;
15573 pattern_6[1][4] = 0x3f4966d5 ;
15574 pattern_6[1][5] = 0x239672c0 ;
15575 pattern_6[1][6] = 0x47ba7533 ;
15576 pattern_6[1][7] = 0xcae4cd7f ;
15577 pattern_6[2][0] = 0xaed83f49 ;
15578 pattern_6[2][1] = 0xd243a62c ;
15579 pattern_6[2][2] = 0xf8774a0b ;
15580 pattern_6[2][3] = 0x63d214e5 ;
15581 pattern_6[2][4] = 0x3f6166d5 ;
15582 pattern_6[2][5] = 0x239672c0 ;
15583 pattern_6[2][6] = 0x47ba7533 ;
15584 pattern_6[2][7] = 0xcae4cd7f ;
15585 pattern_6[3][0] = 0xae883f49 ;
15586 pattern_6[3][1] = 0xd243a62c ;
15587 pattern_6[3][2] = 0xf8774a0b ;
15588 pattern_6[3][3] = 0x63d214e5 ;
15589 pattern_6[3][4] = 0x3fc166d5 ;
15590 pattern_6[3][5] = 0x239672c0 ;
15591 pattern_6[3][6] = 0x47ba7533 ;
15592 pattern_6[3][7] = 0xcae4cd7f ;
15593 */
15594 //*/
15595
15596 char *endp;
15597 unsigned int loop = 1;
15598 unsigned int lflag = 0;
15599 unsigned int start_addr = DDR_TEST_START_ADDR;
15600 unsigned int test_size = DDR_TEST_SIZE;
15601 unsigned int test_addr;
15602
15603 error_outof_count_flag =0;
15604 error_count =0;
15605
15606 printf("\nargc== 0x%08x\n", argc);
15607 int i ;
15608 for (i = 0;i<argc;i++)
15609 {
15610 printf("\nargv[%d]=%s\n",i,argv[i]);
15611 }
15612 if (argc == 1)
15613 goto usage;
15614 if (argc>1)
15615 {
15616 if (strcmp(argv[1], "l") == 0) {
15617 lflag = 1;
15618 }
15619
15620 else{
15621 loop = simple_strtoull_ddr(argv[1], &endp, 10);
15622 if (*argv[1] == 0 || *endp != 0)
15623 loop = 1;
15624 }
15625
15626 // printf("\nLINE== 0x%08x\n", __LINE__);
15627 if (argc ==1) {
15628 // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
15629 // if (*argv[2] == 0 || *endp != 0)
15630 start_addr = DDR_TEST_START_ADDR;
15631 loop = 1;
15632 }
15633 }
15634
15635 if (argc >= 2) {
15636 loop = simple_strtoull_ddr(argv[1], &endp, 16);
15637 if (*argv[1] == 0 || *endp != 0)
15638 loop = 1;
15639
15640 }
15641 unsigned int pattern_flag1=1;
15642 unsigned int pattern_flag2=1;
15643 unsigned int pattern_flag3=1;
15644 pattern_flag1 = 1;
15645 pattern_flag2=1;
15646 pattern_flag3 = 1;
15647
15648
15649 if (argc >= 3 ) {
15650 if ( (strcmp(argv[2], "s") == 0))
15651 {
15652 pattern_flag1 = 1;
15653 pattern_flag2=0;
15654 pattern_flag3 = 0;
15655 }
15656 else if ((strcmp(argv[2], "c") == 0))
15657 {
15658 pattern_flag1 = 0;
15659 pattern_flag2=1;
15660 pattern_flag3 = 0;
15661 }
15662 else if ( (strcmp(argv[2], "d") == 0))
15663 {
15664 pattern_flag1 = 0;
15665 pattern_flag2=0;
15666 pattern_flag3 = 1;
15667 }
15668 }
15669
15670 // if(test_size<0x20)
15671 start_addr=0x10000000;
15672 test_size = 0x20;
15673 unsigned int temp_i=0;
15674 unsigned int temp_k=0;
15675 unsigned int pattern_o[8];
15676 unsigned int pattern_d[8];
15677 //unsigned int i=0;
15678
15679 printf("\nloop should >2 and now loop== 0x%08x\n", loop);
15680 //DDR_TEST_START:
15681
15682 ///*
15683
15684 error_count=0;
15685 do {
15686 if (lflag)
15687 loop = 888;
15688 if (loop%2)
15689 {
15690 start_addr=0x10000000;
15691 test_size = 0x20;
15692 for ((i=0);(i<8);(i++))
15693 {
15694 des[i]= a_des[i];
15695 }
15696 }
15697 else
15698 {
15699 start_addr=0x10000400;
15700 test_size = 0x20;
15701 for ((i=0);(i<8);(i++))
15702 {
15703 des[i]= b_des[i];
15704 }
15705 }
15706 //if(old_pattern_flag==1)
15707 {
15708
15709 printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
15710
15711 /*
15712 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15713 {
15714
15715 for ((temp_i=0);(temp_i<8);(temp_i++))
15716 {
15717 test_addr=start_addr+(temp_i<<2);
15718 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15719 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15720 //des[temp_i]^pattern_2[temp_k][temp_i]
15721 }
15722 // _clean_dcache_addr(0x10000000);
15723 flush_dcache_range(start_addr,start_addr + test_size);
15724
15725 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15726 test_addr=start_addr+(temp_i<<2);
15727 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15728 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15729 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15730 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15731 if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
15732 {error_count++;
15733 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
15734 }
15735 }
15736 }
15737 }
15738 */
15739 if (pattern_flag1 == 1) {
15740 for ((temp_k=0);(temp_k<4);(temp_k++))
15741 {
15742 {
15743 ddr_udelay(10000);
15744 for ((temp_i=0);(temp_i<8);(temp_i++))
15745 {
15746 test_addr=start_addr+(temp_i<<2);
15747 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15748 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15749 //des[temp_i]^pattern_2[temp_k][temp_i]
15750 }
15751 // _clean_dcache_addr(0x10000000);
15752#ifdef DDR_PREFETCH_CACHE
15753 flush_dcache_range(start_addr,start_addr + test_size);
15754#endif
15755 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15756 test_addr=start_addr+(temp_i<<2);
15757 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15758 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
15759 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15760 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
15761 // if(pattern_o[temp_i]!=pattern_4[temp_k][temp_i])
15762 if ((pattern_o[temp_i]) != (des_pattern(temp_i,1,temp_k,temp_i)))
15763 {error_count++;
15764 // printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
15765 printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,1,temp_k,temp_i),pattern_1[temp_k][temp_i]);
15766 }
15767
15768 }
15769 }
15770 }
15771 for ((temp_k=0);(temp_k<4);(temp_k++))
15772 {
15773 {
15774 ddr_udelay(10000);
15775 for ((temp_i=0);(temp_i<8);(temp_i++))
15776 {
15777 test_addr=start_addr+(temp_i<<2);
15778 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15779 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15780 //des[temp_i]^pattern_2[temp_k][temp_i]
15781 }
15782 // _clean_dcache_addr(0x10000000);
15783#ifdef DDR_PREFETCH_CACHE
15784 flush_dcache_range(start_addr,start_addr + test_size);
15785#endif
15786 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15787 test_addr=start_addr+(temp_i<<2);
15788 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15789 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
15790 // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15791 // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
15792 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15793 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15794 {error_count++;
15795 // printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]);
15796 printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(des_pattern(temp_i,1,temp_k,temp_i)),pattern_d[temp_i]);
15797 }
15798
15799 }
15800 }
15801 }
15802 }
15803 if (pattern_flag2 == 1) {
15804 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15805 {
15806 ddr_udelay(10000);
15807 for ((temp_i=0);(temp_i<8);(temp_i++))
15808 {
15809 test_addr=start_addr+(temp_i<<2);
15810 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15811 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15812 //des[temp_i]^pattern_2[temp_k][temp_i]
15813 }
15814 // _clean_dcache_addr(0x10000000);
15815#ifdef DDR_PREFETCH_CACHE
15816 flush_dcache_range(start_addr,start_addr + test_size);
15817#endif
15818 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15819 test_addr=start_addr+(temp_i<<2);
15820 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15821 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15822 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15823 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15824 // if(pattern_o[temp_i]!=pattern_5[temp_k][temp_i])
15825 if ((pattern_o[temp_i]) != (des_pattern(temp_i,2,temp_k,temp_i)))
15826 {error_count++;
15827 // printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
15828 printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,2,temp_k,temp_i),pattern_2[temp_k][temp_i]);
15829 }
15830 }
15831 }
15832 }
15833 for ((temp_k=0);(temp_k<4);(temp_k++))
15834 {
15835 {
15836 ddr_udelay(10000);
15837 for ((temp_i=0);(temp_i<8);(temp_i++))
15838 {
15839 test_addr=start_addr+(temp_i<<2);
15840 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15841 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15842 //des[temp_i]^pattern_2[temp_k][temp_i]
15843 }
15844 // _clean_dcache_addr(0x10000000);
15845#ifdef DDR_PREFETCH_CACHE
15846 flush_dcache_range(start_addr,start_addr + test_size);
15847#endif
15848 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15849 test_addr=start_addr+(temp_i<<2);
15850 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15851 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
15852 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15853 //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
15854 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15855 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15856 {error_count++;
15857 // printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]);
15858 printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(des_inv_pattern(temp_i,2,temp_k,temp_i)),pattern_d[temp_i]);
15859 }
15860 }
15861 }
15862 }
15863
15864 }
15865
15866 if (pattern_flag3 == 1) {
15867 for ((temp_k=0);(temp_k<4);(temp_k++)) {
15868 {
15869 ddr_udelay(10000);
15870 for ((temp_i=0);(temp_i<8);(temp_i++))
15871 {
15872 test_addr=start_addr+(temp_i<<2);
15873 *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15874 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15875 //des[temp_i]^pattern_2[temp_k][temp_i]
15876 }
15877 // _clean_dcache_addr(0x10000000);
15878#ifdef DDR_PREFETCH_CACHE
15879 flush_dcache_range(start_addr,start_addr + test_size);
15880#endif
15881 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15882 test_addr=start_addr+(temp_i<<2);
15883 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15884 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
15885 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15886 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
15887 //if(pattern_o[temp_i]!=pattern_6[temp_k][temp_i])
15888 if ((pattern_o[temp_i]) != (des_pattern(temp_i,3,temp_k,temp_i)))
15889 {error_count++;
15890 // printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]);
15891 printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,3,temp_k,temp_i),pattern_3[temp_k][temp_i]);
15892 }
15893 }
15894 }
15895 }
15896 for ((temp_k=0);(temp_k<4);(temp_k++))
15897 {
15898 {
15899 ddr_udelay(10000);
15900 for ((temp_i=0);(temp_i<8);(temp_i++))
15901 {
15902 test_addr=start_addr+(temp_i<<2);
15903 *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
15904 // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
15905 //des[temp_i]^pattern_2[temp_k][temp_i]
15906 }
15907 // _clean_dcache_addr(0x10000000);
15908#ifdef DDR_PREFETCH_CACHE
15909 flush_dcache_range(start_addr,start_addr + test_size);
15910#endif
15911 for ((temp_i=0);(temp_i<8);(temp_i++)) {
15912 test_addr=start_addr+(temp_i<<2);
15913 pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
15914 // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
15915 //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
15916 // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
15917 pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
15918 if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
15919 {error_count++;
15920 // printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]);
15921 printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(des_inv_pattern(temp_i,3,temp_k,temp_i)),pattern_d[temp_i]);
15922 }
15923 }
15924 }
15925 }
15926 }
15927
15928
15929
15930 }
15931
15932 printf("\Error count==0x%08x", error_count);
15933 printf("\n \n");
15934 }while(--loop);
15935 //*/
15936
15937 printf("\rEnd ddr test. \n");
15938
15939 return 0;
15940
15941usage:
15942 cmd_usage(cmdtp);
15943 return 1;
15944}
15945
15946
15947U_BOOT_CMD(
15948 ddrtest_gxtvbb_crosstalk, 5, 1, do_ddr_gxtvbb_crosstalk,
15949 "DDR test function",
15950 "ddrtest [LOOP] [ADDR].Default address is 0x10000000\n"
15951);
15952
15953#if 1
15954int do_ddrtest_find_gate_wind(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
15955{
15956 printf("\nEnter Tune ddr dqs function\n");
15957 // if(!argc)
15958 // goto DDR_TUNE_DQS_START;
15959 printf("\nargc== 0x%08x\n", argc);
15960 // unsigned int loop = 1;
15961 unsigned int temp_count_i = 1;
15962 // unsigned int temp_count_j= 1;
15963 // unsigned int temp_count_k= 1;
15964 unsigned int temp_test_error= 0;
15965
15966 char *endp;
15967 // unsigned int *p_start_addr;
15968 unsigned int test_loop=1;
15969 unsigned int test_times=1;
15970 unsigned int reg_add=0;
15971 unsigned int reg_base_adj=0;
15972 unsigned int channel_a_en = 0;
15973 unsigned int channel_b_en = 0;
15974 unsigned int testing_channel = 0;
15975
15976 // /*
15977 // #define DATX8_DQ_LCD_BDL_REG_WIDTH 12
15978
15979#define DATX8_DQ_LANE_WIDTH 4
15980#define CHANNEL_CHANNEL_WIDTH 2
15981
15982#define CHANNEL_A 0
15983#define CHANNEL_B 1
15984
15985
15986
15987#define DATX8_DQ_LANE_LANE00 0
15988#define DATX8_DQ_LANE_LANE01 1
15989#define DATX8_DQ_LANE_LANE02 2
15990#define DATX8_DQ_LANE_LANE03 3
15991
15992#define DATX8_DQ_BDLR0 0
15993#define DATX8_DQ_BDLR1 1
15994#define DATX8_DQ_BDLR2 2
15995#define DATX8_DQ_BDLR3 3
15996#define DATX8_DQ_BDLR4 4
15997#define DATX8_DQ_BDLR5 5
15998#define DATX8_DQ_BDLR6 6
15999#define DATX8_DQ_DXNLCDLR0 7
16000#define DATX8_DQ_DXNLCDLR1 8
16001#define DATX8_DQ_DXNLCDLR2 9
16002#define DATX8_DQ_DXNMDLR 10
16003#define DATX8_DQ_DXNGTR 11
16004
16005
16006#define DDR_CROSS_TALK_TEST_SIZE 0x20000
16007
16008 // #define DQ_LCD_BDL_REG_NUM_PER_CHANNEL 5//DATX8_DQ_LCD_BDL_REG_WIDTH*DATX8_DQ_LANE_WIDTH
16009 // #define DQ_LCD_BDL_REG_NUM DQ_LCD_BDL_REG_NUM_PER_CHANNEL*CHANNEL_CHANNEL_WIDTH
16010 //*/
16011
16012
16013 // unsigned int dq_lcd_bdl_reg_org[DQ_LCD_BDL_REG_NUM];
16014 // unsigned int dq_lcd_bdl_reg_left[DQ_LCD_BDL_REG_NUM];
16015 // unsigned int dq_lcd_bdl_reg_right[DQ_LCD_BDL_REG_NUM];
16016 // unsigned int dq_lcd_bdl_reg_index[DQ_LCD_BDL_REG_NUM];
16017
16018 // unsigned int dq_lcd_bdl_reg_left_min[DQ_LCD_BDL_REG_NUM];
16019 // unsigned int dq_lcd_bdl_reg_right_min[DQ_LCD_BDL_REG_NUM];
16020
16021 unsigned int dq_lcd_bdl_temp_reg_value;
16022 // unsigned int dq_lcd_bdl_temp_reg_value_min;
16023 // unsigned int dq_lcd_bdl_temp_reg_value_max;
16024 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
16025 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsnd;
16026 // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
16027 // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
16028 // unsigned int dq_lcd_bdl_temp_reg_value_dqs;
16029 // unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
16030 // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
16031
16032 // unsigned int dq_lcd_bdl_temp_reg_lef;
16033 // unsigned int dq_lcd_bdl_temp_reg_rig;
16034 // unsigned int dq_lcd_bdl_temp_reg_center;
16035 // unsigned int dq_lcd_bdl_temp_reg_windows;
16036 // unsigned int dq_lcd_bdl_temp_reg_center_min;
16037 // unsigned int dq_lcd_bdl_temp_reg_windows_min;
16038
16039 unsigned int dqgtr_org[4],dqlcdlr2_org[4],dqgtr_l[4],dqlcdlr2_l[4],dqgtr_r[4],dqlcdlr2_r[4],dqmdlr[4];
16040 unsigned int dqgtr_temp;
16041 unsigned int dqlcdlr2_temp;
16042 unsigned int dqqsgate_org[4],dqqsgate_l[4], dqqsgate_r[4];
16043 unsigned int ddr_gate_up_down=0;
16044 unsigned int ddr_gate_init_lane=0;
16045
16046 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
16047
16048
16049
16050 if (argc == 2)
16051 {
16052 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
16053 {
16054 channel_a_en = 1;
16055 }
16056 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
16057 {
16058 channel_b_en = 1;
16059 }
16060 else
16061 {
16062 goto usage;
16063 }
16064 }
16065 if (argc > 2)
16066 {
16067 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
16068 {
16069 channel_a_en = 1;
16070 }
16071 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
16072 {
16073 channel_b_en = 1;
16074 }
16075 }
16076 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
16077 if (argc >3) {
16078 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
16079 if (*argv[3] == 0 || *endp != 0)
16080 {
16081 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
16082 }
16083
16084 }
16085 if (argc >4) {
16086 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
16087 if (*argv[4] == 0 || *endp != 0)
16088 {
16089 test_loop = 1;
16090 }
16091 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
16092 {
16093 test_loop = 100000;
16094 }
16095 }
16096
16097
16098 if (argc >5) {
16099 ddr_gate_up_down = simple_strtoull_ddr(argv[5], &endp, 16);
16100 if (*argv[5] == 0 || *endp != 0)
16101 {
16102 ddr_gate_up_down = 0;
16103 }
16104 if ((strcmp(argv[5], "l") == 0) || (strcmp(argv[5], "L") == 0))
16105 {
16106 ddr_gate_up_down = 00000;
16107 }
16108 }
16109 if (argc >6) {
16110 ddr_gate_init_lane = simple_strtoull_ddr(argv[6], &endp, 16);
16111 if (*argv[6] == 0 || *endp != 0)
16112 {
16113 ddr_gate_init_lane = 0;
16114 }
16115 if ((strcmp(argv[6], "l") == 0) || (strcmp(argv[6], "L") == 0))
16116 {
16117 ddr_gate_init_lane = 00000;
16118 }
16119 }
16120
16121
16122 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
16123 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
16124 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
16125 printf("\ntest_loop== 0x%08x\n", test_loop);
16126 printf("\nddr_gate_up_down== 0x%08x\n", ddr_gate_up_down);
16127 printf("\nddr_gate_init_lane== 0x%08x\n", ddr_gate_init_lane);
16128 if ( channel_a_en)
16129 {
16130 //writel((0), 0xc8836c00);
16131 OPEN_CHANNEL_A_PHY_CLK();
16132 }
16133 if ( channel_b_en)
16134 {
16135 OPEN_CHANNEL_B_PHY_CLK();
16136 //writel((0), 0xc8836c00);
16137 }
16138
16139
16140 //save and print org training dqs value
16141 if (channel_a_en || channel_b_en)
16142 {
16143
16144
16145 //dcache_disable();
16146 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
16147
16148 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16149 {
16150 if (( channel_a_en) && ( channel_b_en == 0))
16151 {
16152 reg_base_adj=CHANNEL_A_REG_BASE;
16153 }
16154 else if(( channel_b_en)&&( channel_a_en==0))
16155 {
16156 reg_base_adj=CHANNEL_B_REG_BASE;
16157 }
16158 else if ((channel_a_en+channel_b_en)==2)
16159 {
16160 if ( testing_channel == CHANNEL_A)
16161 {
16162 reg_base_adj=CHANNEL_A_REG_BASE;
16163 }
16164 else if( testing_channel==CHANNEL_B)
16165 {
16166 reg_base_adj=CHANNEL_B_REG_BASE;
16167 }
16168 }
16169
16170 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
16171 {
16172
16173 if (temp_count_i == DATX8_DQ_LANE_LANE00)
16174 {
16175 reg_add=DDR0_PUB_DX0LCDLR0+reg_base_adj;
16176 }
16177 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
16178 {
16179 reg_add=DDR0_PUB_DX1LCDLR0+reg_base_adj;
16180 }
16181 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
16182 {
16183 reg_add=DDR0_PUB_DX2LCDLR0+reg_base_adj;
16184 } else if(temp_count_i==DATX8_DQ_LANE_LANE03)
16185 {
16186 reg_add=DDR0_PUB_DX3LCDLR0+reg_base_adj;
16187 }
16188 }
16189 }
16190 }////save and print org training dqs value
16191
16192
16193 for (test_times=0;(test_times<test_loop);(test_times++))
16194 {
16195 ////tune and save training dqs value
16196 if (channel_a_en || channel_b_en)
16197 {
16198 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16199 {
16200 if (( channel_a_en) && ( channel_b_en == 0))
16201 {
16202 reg_base_adj=CHANNEL_A_REG_BASE;
16203 }
16204 else if(( channel_b_en)&&( channel_a_en==0))
16205 {
16206 reg_base_adj=CHANNEL_B_REG_BASE;
16207 }
16208 else if ((channel_a_en+channel_b_en)==2)
16209 {
16210 if ( testing_channel == CHANNEL_A)
16211 {
16212 reg_base_adj=CHANNEL_A_REG_BASE;
16213 }
16214 else if( testing_channel==CHANNEL_B)
16215 {
16216 reg_base_adj=CHANNEL_B_REG_BASE;
16217 }
16218 }
16219
16220 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
16221 {
16222 printf("\ntest lane==0x%08x\n ",temp_count_i);
16223 if (ddr_gate_init_lane)
16224 {
16225 temp_count_i=ddr_gate_init_lane;
16226 printf("\ntest lane change==0x%08x\n ",temp_count_i);
16227 }
16228
16229
16230 if (temp_count_i == DATX8_DQ_LANE_LANE00)
16231 {
16232 reg_add=DDR0_PUB_DX0LCDLR0+reg_base_adj;
16233 }
16234 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
16235 {
16236 reg_add=DDR0_PUB_DX1LCDLR0+reg_base_adj;
16237 }
16238 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
16239 {
16240 reg_add=DDR0_PUB_DX2LCDLR0+reg_base_adj;
16241 }
16242 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
16243 {
16244 reg_add=DDR0_PUB_DX3LCDLR0+reg_base_adj;
16245 }
16246
16247 // for((temp_count_k=0);(temp_count_k<2);(temp_count_k++))
16248 {
16249 //if(temp_count_k==0)
16250 {
16251 dqlcdlr2_org[temp_count_i]=readl(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0);
16252 dqgtr_org[temp_count_i]=readl(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0);
16253 dqmdlr[temp_count_i]=readl(reg_add+DDR0_PUB_ACMDLR-DDR0_PUB_DX0LCDLR0);
16254 dq_lcd_bdl_temp_reg_value=(((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2*((dqgtr_org[temp_count_i])&(DXNGTR_MAX))+(((dqlcdlr2_org[temp_count_i]))&ACLCDLR_MAX);
16255 dqqsgate_org[temp_count_i]=dq_lcd_bdl_temp_reg_value;
16256
16257 printf("\ngate org==0x%08x 0x%08x 0x%08x 0x%08x\n ",dqqsgate_org[temp_count_i],dqgtr_org[temp_count_i],dqlcdlr2_org[temp_count_i], dqmdlr[temp_count_i]);
16258
16259 if (ddr_gate_up_down == 0)
16260 {
16261 while (dq_lcd_bdl_temp_reg_value>0)
16262 {
16263 temp_test_error=0;
16264 dq_lcd_bdl_temp_reg_value--;
16265 printf("\ngate left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
16266 dqgtr_temp=dq_lcd_bdl_temp_reg_value/((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16267 dqlcdlr2_temp=dq_lcd_bdl_temp_reg_value-dqgtr_temp*((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16268
16269 writel((dqlcdlr2_temp),(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16270 writel((((readl((reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0)))&0xfffff000)|(dqgtr_temp)),(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0));
16271 printf("\n (reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0) 0x%08x gtr==0x%08x\n ",(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0),(readl((reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0))));
16272 printf("\nlcdlr2==0x%08x\n ",readl(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16273 printf("\ndqgtr_temp==0x%08x\n ",dqgtr_temp);
16274 printf("\ngatedqlcdlr2_temp==0x%08x\n ",dqlcdlr2_temp);
16275 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
16276 if (temp_test_error)
16277 {
16278 printf("\ngateleft edge detect \n");
16279 dq_lcd_bdl_temp_reg_value++;
16280 break;
16281 }
16282 }
16283 printf("\ngate left edge detect \n");
16284 printf("\ngate left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
16285 //dq_lcd_bdl_temp_reg_value_min=dq_lcd_bdl_temp_reg_value;
16286 dqqsgate_l[temp_count_i]=dq_lcd_bdl_temp_reg_value;
16287 writel(dqlcdlr2_org[temp_count_i],(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16288 writel( dqgtr_org[temp_count_i],(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0));
16289
16290 dq_lcd_bdl_temp_reg_value=(((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2*((dqgtr_org[temp_count_i])&DXNGTR_MAX)+(((dqlcdlr2_org[temp_count_i]))&ACLCDLR_MAX);
16291 }
16292 while (dq_lcd_bdl_temp_reg_value>0)
16293 {
16294 temp_test_error=0;
16295 dq_lcd_bdl_temp_reg_value++;
16296 printf("\ngate rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
16297 dqgtr_temp=dq_lcd_bdl_temp_reg_value/((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16298 dqlcdlr2_temp=dq_lcd_bdl_temp_reg_value-dqgtr_temp*((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16299
16300 writel((dqlcdlr2_temp),(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16301 writel(((readl((reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0)))&0xfffff000)|(dqgtr_temp),(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0));
16302 printf("\n (reg_addDDR0_PUB_DX0GTR) 0x%08x gtr==0x%08x\n ",(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0),(readl((reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0))));
16303 printf("\nlcdlr2==0x%08x\n ",readl(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16304 printf("\ndqgtr_temp==0x%08x\n ",dqgtr_temp);
16305 printf("\ngatedqlcdlr2_temp==0x%08x\n ",dqlcdlr2_temp);
16306 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
16307 if (temp_test_error)
16308 {
16309 printf("\ngaterig edge detect \n");
16310 dq_lcd_bdl_temp_reg_value++;
16311 break;
16312 }
16313 }
16314 printf("\ngate rig edge detect \n");
16315 printf("\ngate rig edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
16316 //dq_lcd_bdl_temp_reg_value_max=dq_lcd_bdl_temp_reg_value;
16317 dqqsgate_r[temp_count_i]=dq_lcd_bdl_temp_reg_value;
16318 writel(dqlcdlr2_org[temp_count_i],(reg_add+DDR0_PUB_DX0LCDLR2-DDR0_PUB_DX0LCDLR0));
16319 writel( dqgtr_org[temp_count_i],(reg_add+DDR0_PUB_DX0GTR-DDR0_PUB_DX0LCDLR0));
16320
16321
16322
16323
16324
16325
16326 }
16327
16328
16329
16330 }
16331 }
16332
16333 }
16334 }
16335
16336 ////tune and save training dqs value
16337
16338
16339
16340
16341 ////calculate and print dqs value
16342 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16343 {
16344 if (( channel_a_en) && ( channel_b_en == 0))
16345 {
16346 reg_base_adj=CHANNEL_A_REG_BASE;
16347 }
16348 else if(( channel_b_en)&&( channel_a_en==0))
16349 {
16350 reg_base_adj=CHANNEL_B_REG_BASE;
16351 }
16352 else if ((channel_a_en+channel_b_en)==2)
16353 {
16354 if ( testing_channel == CHANNEL_A)
16355 {
16356 reg_base_adj=CHANNEL_A_REG_BASE;
16357 }
16358 else if( testing_channel==CHANNEL_B)
16359 {
16360 reg_base_adj=CHANNEL_B_REG_BASE;
16361 }
16362 }
16363 reg_add=DDR0_PUB_DX0LCDLR0+reg_base_adj;
16364
16365
16366
16367
16368 printf("\n ddrtest size ==0x%08x, test times==0x%08x,test_loop==0x%08x\n",ddr_test_size,(test_times+1),test_loop);
16369 printf("\n add 0x00000000 reg== org lef rig center win lef_m rig_m min_c min_win \n");
16370
16371 for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
16372 {
16373 {
16374
16375 if (temp_count_i == DATX8_DQ_LANE_LANE00)
16376 {
16377 reg_add=DDR0_PUB_DX0LCDLR0+reg_base_adj+0*4;}
16378
16379 else if(temp_count_i==DATX8_DQ_LANE_LANE01)
16380 {
16381 reg_add=DDR0_PUB_DX1LCDLR0+reg_base_adj+0*4;}
16382
16383 else if(temp_count_i==DATX8_DQ_LANE_LANE02)
16384 {
16385 reg_add=DDR0_PUB_DX2LCDLR0+reg_base_adj+0*4;}
16386 else if(temp_count_i==DATX8_DQ_LANE_LANE03)
16387 {
16388 reg_add=DDR0_PUB_DX3LCDLR0+reg_base_adj+0*4;}
16389 }
16390
16391 //unsigned int dqgtr_org[4],dqlcdlr2_org[4],dqgtr_l[4],dqlcdlr2_l[4],dqgtr_r[4],dqlcdlr2_r[4],dqmdlr[4];
16392 // unsigned int dqgtr_temp;
16393 // unsigned int dqlcdlr2_temp;
16394 // unsigned int dqqsgate_l[4], dqqsgate_r[4];
16395 (dqgtr_l[temp_count_i])=(dqqsgate_l[temp_count_i])/((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16396 (dqlcdlr2_l[temp_count_i])=(dqqsgate_l[temp_count_i])-(dqgtr_l[temp_count_i])*((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16397 (dqgtr_r[temp_count_i])=(dqqsgate_r[temp_count_i])/((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16398 (dqlcdlr2_r[temp_count_i])=(dqqsgate_r[temp_count_i])-(dqgtr_r[temp_count_i])*((((dqmdlr[temp_count_i]))&ACLCDLR_MAX)*2);
16399 printf("\n add reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
16400 (dqqsgate_org[temp_count_i]),
16401 (dqqsgate_l[temp_count_i]),
16402 (dqqsgate_r[temp_count_i]),
16403 (dqgtr_org[temp_count_i]),
16404 (dqlcdlr2_org[temp_count_i]),
16405 (dqgtr_l[temp_count_i]),
16406 (dqgtr_r[temp_count_i]),
16407 (dqlcdlr2_l[temp_count_i]),
16408 (dqlcdlr2_r[temp_count_i])
16409 );
16410
16411
16412 }
16413
16414
16415
16416
16417
16418 }
16419
16420 }
16421
16422
16423
16424
16425 return 0;
16426
16427usage:
16428 cmd_usage(cmdtp);
16429 return 1;
16430
16431}
16432
16433
16434U_BOOT_CMD(
16435 ddrtest_gate, 7, 1, do_ddrtest_find_gate_wind,
16436 "DDR test function should dcache off ddrtest_gate a 0 0x80000 1 0 3",
16437 "ddrtest_gate [LOOP] [ADDR].Default address is 0x10000000\n"
16438);
16439
16440
16441#endif
16442
16443///*
16444int do_ddr_test_ac_windows_bdlr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
16445{
16446 printf("\nEnter Test ddr ac bdlr windows function\n");
16447 // if(!argc)
16448 // goto DDR_TUNE_DQS_START;
16449 printf("\nargc== 0x%08x\n", argc);
16450 // unsigned int loop = 1;
16451 // unsigned int temp_count_i = 1;
16452 // unsigned int temp_count_j= 1;
16453 // unsigned int temp_count_k= 1;
16454 unsigned int temp_test_error= 0;
16455 static unsigned int soft_ca_training_seed=0;
16456 static unsigned int soft_ca_training_step=0;
16457
16458 char *endp;
16459 // unsigned int *p_start_addr;
16460 unsigned int test_loop=1;
16461 unsigned int test_times=1;
16462 unsigned int reg_add=0;
16463 unsigned int reg_base_adj=0;
16464 unsigned int channel_a_en = 0;
16465 unsigned int channel_b_en = 0;
16466 unsigned int testing_channel = 0;
16467
16468#define CHANNEL_A 0
16469#define CHANNEL_B 1
16470#define DDR_CROSS_TALK_TEST_SIZE 0x20000
16471
16472 unsigned int ac_mdlr_a_org=0;
16473 unsigned int ac_mdlr_b_org=0;
16474
16475 unsigned int ac_lcdlr_a_org=0;
16476 unsigned int ac_bdlr0_a_org=0;
16477 unsigned int ac_lcdlr_b_org=0;
16478 unsigned int ac_bdlr0_b_org=0;
16479 unsigned int ac_lcdlr_a_rig=0;
16480 unsigned int ac_bdlr0_a_rig=0;
16481 unsigned int ac_lcdlr_b_rig=0;
16482 unsigned int ac_bdlr0_b_rig=0;
16483 unsigned int ac_lcdlr_a_lef=0;
16484 unsigned int ac_bdlr0_a_lef=0;
16485 unsigned int ac_lcdlr_b_lef=0;
16486 unsigned int ac_bdlr0_b_lef=0;
16487
16488 unsigned int ac_lcdlr_a_rig_min=0;
16489 unsigned int ac_bdlr0_a_rig_min=0;
16490 unsigned int ac_lcdlr_b_rig_min=0;
16491 unsigned int ac_bdlr0_b_rig_min=0;
16492 unsigned int ac_lcdlr_a_lef_min=0;
16493 unsigned int ac_bdlr0_a_lef_min=0;
16494 unsigned int ac_lcdlr_b_lef_min=0;
16495 unsigned int ac_bdlr0_b_lef_min=0;
16496 // unsigned int ac_lcdlr_temp;
16497 // unsigned int ac_bdlr0_temp=0;
16498
16499
16500
16501 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
16502
16503 unsigned int ac_bdlr_lef[10];
16504 unsigned int ac_bdlr_rig[10];
16505 unsigned int ac_bdlr_temp_value;
16506 unsigned int ac_bdlr_reg_seed_value;
16507 unsigned int ac_bdlr_temp_reg_value;
16508 // unsigned int temp_test_error;
16509 unsigned int temp_i=0;
16510 unsigned int temp_j=0;
16511 //unsigned int reg_add=0;
16512 // static unsigned int soft_ca_training_enabled=1;
16513
16514 //#define DDR_TEST_ACLCDLR
16515
16516
16517 if (argc == 2)
16518 {
16519 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
16520
16521 {channel_a_en = 1;
16522 }
16523 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
16524
16525 {channel_b_en = 1;
16526 }
16527 else
16528 {
16529 goto usage;
16530 }
16531 }
16532 if (argc > 2)
16533 {
16534 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
16535
16536 {channel_a_en = 1;
16537 }
16538 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
16539
16540 {channel_b_en = 1;
16541 }
16542 }
16543 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
16544 if (argc >3) {
16545 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
16546 if (*argv[3] == 0 || *endp != 0)
16547 {
16548 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
16549 }
16550
16551 }
16552 if (argc >4) {
16553 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
16554 if (*argv[4] == 0 || *endp != 0)
16555 {
16556 test_loop = 1;
16557 }
16558 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
16559 {
16560 test_loop = 100000;
16561 }
16562 }
16563
16564 if (argc >5) {
16565 soft_ca_training_seed = simple_strtoull_ddr(argv[5], &endp, 16);
16566 if (*argv[5] == 0 || *endp != 0)
16567 {
16568 soft_ca_training_seed = 0x1f;
16569 }
16570
16571
16572 }
16573 if (argc >6) {
16574 soft_ca_training_step = simple_strtoull_ddr(argv[6], &endp, 16);
16575 if (*argv[6] == 0 || *endp != 0)
16576 {
16577 soft_ca_training_step = 0;
16578 }
16579
16580
16581 }
16582 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
16583 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
16584 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
16585 printf("\ntest_loop== 0x%08x\n", test_loop);
16586 printf("\nsoft_ca_training_seed== 0x%08x\n", soft_ca_training_seed);
16587 printf("\nsoft_ca_training_step== 0x%08x\n", soft_ca_training_step);
16588 if ( channel_a_en)
16589 {
16590 //writel((0), 0xc8836c00);
16591 OPEN_CHANNEL_A_PHY_CLK();
16592 }
16593 if ( channel_b_en)
16594 {
16595 OPEN_CHANNEL_B_PHY_CLK();
16596 //writel((0), 0xc8836c00);
16597 }
16598
16599 //save and print org training dqs value
16600 if (channel_a_en || channel_b_en)
16601 {
16602
16603
16604 //dcache_disable();
16605 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
16606
16607 {
16608 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16609 {
16610 if (( channel_a_en) && ( channel_b_en == 0))
16611 {
16612 reg_base_adj=CHANNEL_A_REG_BASE;
16613 }
16614 else if(( channel_b_en)&&( channel_a_en==0))
16615 {
16616 reg_base_adj=CHANNEL_B_REG_BASE;
16617 }
16618 else if ((channel_a_en+channel_b_en)==2)
16619 {
16620 if ( testing_channel == CHANNEL_A)
16621 {
16622 reg_base_adj=CHANNEL_A_REG_BASE;
16623 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
16624
16625
16626
16627 }
16628 else if( testing_channel==CHANNEL_B)
16629 {
16630 reg_base_adj=CHANNEL_B_REG_BASE;
16631
16632 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
16633
16634
16635
16636 }
16637 }
16638
16639 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
16640
16641
16642 if (reg_base_adj == CHANNEL_A_REG_BASE)
16643 {
16644 printf("\ntest A channel 0x%08x\n",reg_add);
16645 ac_mdlr_a_org=(unsigned int )(readl((unsigned int )reg_add));//readl(reg_add);//0xc8836000
16646 ac_lcdlr_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR)));//readl(reg_add+4);
16647 ac_bdlr0_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR)));//readl(reg_add+8);
16648
16649 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
16650 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
16651 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
16652 }
16653 if (reg_base_adj == CHANNEL_B_REG_BASE)
16654 {
16655
16656 ac_mdlr_b_org=readl(reg_add);
16657 ac_lcdlr_b_org=readl(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR);
16658 ac_bdlr0_b_org=readl(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR);
16659 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
16660 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
16661 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
16662 }
16663
16664
16665 }
16666
16667 }
16668
16669 }////save and print org training value
16670
16671
16672 for (test_times=0;(test_times<test_loop);(test_times++))
16673 {
16674 ////tune and save training dqs value
16675 if (channel_a_en || channel_b_en)
16676 {
16677 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16678 {
16679 if (( channel_a_en) && ( channel_b_en == 0))
16680 {
16681 reg_base_adj=CHANNEL_A_REG_BASE;
16682 }
16683 else if(( channel_b_en)&&( channel_a_en==0))
16684 {
16685 reg_base_adj=CHANNEL_B_REG_BASE;
16686 }
16687 else if ((channel_a_en+channel_b_en)==2)
16688 {
16689 if ( testing_channel == CHANNEL_A)
16690 {
16691 reg_base_adj=CHANNEL_A_REG_BASE;
16692 }
16693 else if( testing_channel==CHANNEL_B)
16694 {
16695 reg_base_adj=CHANNEL_B_REG_BASE;
16696 }
16697 }
16698
16699 if (reg_base_adj == CHANNEL_A_REG_BASE)
16700 {
16701 printf("\ntest A channel AC\n");
16702 }
16703 else
16704 {
16705 printf("\ntest B channel AC\n");
16706 }
16707
16708
16709#define wrr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
16710#define rdr_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
16711 //wr_reg(DDR0_PUB_ACBDLR3, 0x0808); //cs0 cs1
16712 //wr_reg(DDR0_PUB_ACBDLR0, 0x1f); //ck0
16713 // wr_reg(DDR0_PUB_ACBDLR4, 0x0808); //odt0 odt1
16714 //wr_reg(DDR0_PUB_ACBDLR5, 0x0808); //cke0 cke1
16715
16716
16717 //wr_reg(DDR0_PUB_ACBDLR1, 0x181818); //ras cas we
16718 //wr_reg(DDR0_PUB_ACBDLR2, 0x181818); //ba0 ba1 ba2
16719 //wr_reg(DDR0_PUB_ACBDLR6, 0x12121212); //a0 a1 a2 a3
16720 //wr_reg(DDR0_PUB_ACBDLR7, 0x0d0d0d0d); //a4 a5 a6 a7
16721 //wr_reg(DDR0_PUB_ACBDLR8, 0x10101010); //a8 a9 a10 a11
16722 //wr_reg(DDR0_PUB_ACBDLR9, 0x18181818); //a12 a13 a14 a15
16723 reg_add=DDR0_PUB_ACBDLR0;
16724 ac_bdlr_reg_seed_value=(soft_ca_training_seed|(soft_ca_training_seed<<8)|(soft_ca_training_seed<<16)|(soft_ca_training_seed<<24));
16725 for (( temp_i=0);(temp_i<10);( temp_i++))
16726 {
16727 //wr_reg((DDR0_PUB_ACBDLR0+temp_i*4),
16728 //ac_bdlr_reg_seed_value); //cs0 cs1
16729 //reg_add=reg_add+temp_i*4;
16730
16731 //reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
16732 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16733 reg_add=reg_add+reg_base_adj;
16734 wrr_reg((reg_add),
16735 ac_bdlr_reg_seed_value); //cs0 cs1
16736 ac_bdlr_lef[temp_i]=ac_bdlr_reg_seed_value;
16737 ac_bdlr_rig[temp_i]=ac_bdlr_reg_seed_value;
16738 }
16739
16740 printf("\nbdl soft_ca_training_step==0x%08x\n ",soft_ca_training_step);
16741 for (( temp_i=0);(temp_i<10);( temp_i++))
16742 {
16743 //ac_bdlr_temp_value=rdr_reg((unsigned int )reg_add);
16744 if (temp_i == 1)
16745 {
16746 //temp_i=3;
16747 }
16748
16749 for (( temp_j=0);(temp_j<4);( temp_j++))
16750 {
16751 if (soft_ca_training_step)
16752 {
16753 temp_i=(soft_ca_training_step>>2);
16754 temp_j=soft_ca_training_step-((soft_ca_training_step>>2)<<2);
16755 soft_ca_training_step=0;
16756 }
16757 if ((temp_i*4+temp_j) == 1)
16758 {
16759 temp_i=1;
16760 temp_j=0;
16761 }
16762 if ((temp_i*4+temp_j) == 7)
16763 {
16764 temp_i=2;
16765 temp_j=0;
16766 }
16767 if ((temp_i*4+temp_j) == 14)
16768 {
16769 temp_i=4;
16770 temp_j=0;
16771 }
16772 if ((temp_i*4+temp_j) == 18)
16773 {
16774 temp_i=5;
16775 temp_j=0;
16776 }
16777 if ((temp_i*4+temp_j) == 22)
16778 {
16779 temp_i=6;
16780 temp_j=0;
16781 }
16782 //printf("\nbdl temp_i==0x%08x\n ",temp_i);
16783 printf("\nbdl temp_ij==0x%08x\n ",(temp_i*4+temp_j));
16784 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16785 reg_add=reg_add+reg_base_adj;
16786 ac_bdlr_temp_reg_value=rdr_reg((unsigned int )reg_add);
16787 ac_bdlr_temp_value=((ac_bdlr_temp_reg_value>>(temp_j<<3))&ACBDLR_MAX);
16788 while (ac_bdlr_temp_value>0)
16789 {
16790 temp_test_error=0;
16791 ac_bdlr_temp_value--;
16792
16793 printf("\nbdl temp_ij==0x%08x lef temp==0x%08x\n ",(temp_i*4+temp_j),ac_bdlr_temp_value);
16794
16795 ac_bdlr_temp_reg_value=(((~(0xff<<(temp_j<<3)))&ac_bdlr_reg_seed_value)|((ac_bdlr_temp_value)<<(temp_j<<3)));
16796 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16797 reg_add=reg_add+reg_base_adj;
16798 wrr_reg((unsigned int )reg_add,
16799 ac_bdlr_temp_reg_value);
16800 printf("\nbdl reg_add 0x%08x== 0x%08x\n ",reg_add,ac_bdlr_temp_reg_value);
16801
16802#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
16803 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
16804#else
16805 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
16806 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
16807#endif
16808 if (temp_test_error)
16809 {
16810 printf("\nbdl left edge detect \n");
16811 ac_bdlr_temp_value++;
16812 break;
16813 }
16814 }
16815
16816 printf("\nbdl left edge detect \n");
16817 printf("\n\nbdl temp_ij==0x%08x bdl left edge==0x%08x\n ",(temp_i*4+temp_j),ac_bdlr_temp_value);
16818 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16819 reg_add=reg_add+reg_base_adj;
16820 wrr_reg((unsigned int )reg_add,
16821 ac_bdlr_reg_seed_value);
16822
16823 ac_bdlr_temp_reg_value=(((~(0xff<<(temp_j<<3)))&ac_bdlr_lef[temp_i])|((ac_bdlr_temp_value)<<(temp_j<<3)));
16824 ac_bdlr_lef[temp_i]=ac_bdlr_temp_reg_value;
16825
16826 ac_bdlr_temp_value=((ac_bdlr_reg_seed_value>>(temp_j<<3))&ACBDLR_MAX);
16827 while (ac_bdlr_temp_value<ACBDLR_MAX)
16828 {
16829 temp_test_error=0;
16830 ac_bdlr_temp_value++;
16831 printf("\ntemp_ij==0x%08x rig temp==0x%08x\n ",(temp_i*4+temp_j),ac_bdlr_temp_value);
16832
16833 ac_bdlr_temp_reg_value=(((~(0xff<<(temp_j<<3)))&ac_bdlr_reg_seed_value)|((ac_bdlr_temp_value)<<(temp_j<<3)));
16834 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16835 reg_add=reg_add+reg_base_adj;
16836 wrr_reg((unsigned int )reg_add,
16837 ac_bdlr_temp_reg_value);
16838 printf("\nbdl reg_add 0x%08x== 0x%08x\n ",reg_add,ac_bdlr_temp_reg_value);
16839#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
16840 temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
16841#else
16842 temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
16843 temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
16844#endif
16845 if (temp_test_error)
16846 {
16847 printf("\nbdl rig edge detect \n");
16848 ac_bdlr_temp_value--;
16849 break;
16850 }
16851 }
16852
16853
16854
16855 printf("\nbdl rig edge detect \n");
16856 //printf("\n\nbdl rig edge==0x%08x\n ",ac_bdlr_temp_value);
16857 printf("\n\nbdl temp_ij==0x%08x bdl righ edge==0x%08x\n ",(temp_i*4+temp_j),ac_bdlr_temp_value);
16858 reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
16859 reg_add=reg_add+reg_base_adj;
16860 wrr_reg((unsigned int )reg_add,
16861 ac_bdlr_reg_seed_value);
16862
16863 ac_bdlr_temp_reg_value=(((~(0xff<<(temp_j<<3)))&ac_bdlr_rig[temp_i])|((ac_bdlr_temp_value)<<(temp_j<<3)));
16864 ac_bdlr_rig[temp_i]=ac_bdlr_temp_reg_value;
16865 }
16866 }
16867
16868 printf("\nbdl lef edge==bdlr0 bdlr1 bdlr2 bdlr3 bdlr4 bdlr5 bdlr6 bdlr7 bdlr8 bdlr9 \n ");
16869 printf("\nbdl lef edge==\n");
16870 for (( temp_i=0);(temp_i<10);( temp_i++))
16871 {
16872
16873 printf("0x%08x\n ",ac_bdlr_lef[temp_i]);
16874
16875 }
16876
16877 printf("\n ");
16878 for (( temp_i=0);(temp_i<10);( temp_i++))
16879 {
16880 printf("0x%08x\n ",ac_bdlr_rig[temp_i]);
16881 }
16882 printf("\nbdl rig edge===========\n");
16883 printf("\n===================\n");
16884
16885 printf("\nbdl lef edge==\n");
16886 for (( temp_i=0);(temp_i<10);( temp_i++))
16887 {
16888 for (( temp_j=0);(temp_j<4);( temp_j++))
16889 {
16890 if ((temp_i*4+temp_j) == 1)
16891 {
16892 temp_i=1;
16893 temp_j=0;
16894 }
16895 if ((temp_i*4+temp_j) == 7)
16896 {
16897 temp_i=2;
16898 temp_j=0;
16899 }
16900 if ((temp_i*4+temp_j) == 14)
16901 {
16902 temp_i=4;
16903 temp_j=0;
16904 }
16905 if ((temp_i*4+temp_j) == 18)
16906 {
16907 temp_i=5;
16908 temp_j=0;
16909 }
16910 if ((temp_i*4+temp_j) == 22)
16911 {
16912 temp_i=6;
16913 temp_j=0;
16914 }
16915 ac_bdlr_temp_reg_value=((((0xff<<(temp_j<<3)))&ac_bdlr_lef[temp_i])>>(temp_j<<3));
16916 printf("\ntempi_j0x%08x==0x%08x",((temp_i<<2)+temp_j),ac_bdlr_temp_reg_value);
16917 }
16918 }
16919
16920 printf("\n ");
16921 printf("\nbdl rig edge==\n");
16922 for (( temp_i=0);(temp_i<10);( temp_i++))
16923 {
16924 for (( temp_j=0);(temp_j<4);( temp_j++))
16925 {
16926 if ((temp_i*4+temp_j) == 1)
16927 {
16928 temp_i=1;
16929 temp_j=0;
16930 }
16931 if ((temp_i*4+temp_j) == 7)
16932 {
16933 temp_i=2;
16934 temp_j=0;
16935 }
16936 if ((temp_i*4+temp_j) == 14)
16937 {
16938 temp_i=4;
16939 temp_j=0;
16940 }
16941 if ((temp_i*4+temp_j) == 18)
16942 {
16943 temp_i=5;
16944 temp_j=0;
16945 }
16946 if ((temp_i*4+temp_j) == 22)
16947 {
16948 temp_i=6;
16949 temp_j=0;
16950 }
16951 ac_bdlr_temp_reg_value=((((0xff<<(temp_j<<3)))&ac_bdlr_rig[temp_i])>>(temp_j<<3));
16952 printf("\ntempi_j0x%08x==0x%08x",((temp_i<<2)+temp_j),ac_bdlr_temp_reg_value);
16953 }
16954 }
16955 }
16956
16957 ////tune and save training dqs value
16958 ////calculate and print dqs value
16959 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
16960 {
16961 if (( channel_a_en) && ( channel_b_en == 0))
16962 {
16963 reg_base_adj=CHANNEL_A_REG_BASE;
16964 }
16965 else if(( channel_b_en)&&( channel_a_en==0))
16966 {
16967 reg_base_adj=CHANNEL_B_REG_BASE;
16968 }
16969 else if ((channel_a_en+channel_b_en)==2)
16970 {
16971 if ( testing_channel == CHANNEL_A)
16972 {
16973 reg_base_adj=CHANNEL_A_REG_BASE;
16974 }
16975 else if( testing_channel==CHANNEL_B)
16976 {
16977 reg_base_adj=CHANNEL_B_REG_BASE;
16978 }
16979 }
16980 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
16981
16982 if (reg_base_adj == CHANNEL_A_REG_BASE)
16983 {
16984 if (test_times)
16985 {
16986 if (ac_lcdlr_a_lef>ac_lcdlr_a_lef_min)
16987 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
16988
16989 if (ac_lcdlr_a_rig<ac_lcdlr_a_rig_min)
16990 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
16991
16992 if (ac_bdlr0_a_lef>ac_bdlr0_a_lef_min)
16993 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
16994
16995 if (ac_bdlr0_a_rig<ac_bdlr0_a_rig_min)
16996 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
16997 }
16998 else
16999 {
17000 ac_lcdlr_a_lef_min=ac_lcdlr_a_lef;
17001 ac_lcdlr_a_rig_min=ac_lcdlr_a_rig;
17002 ac_bdlr0_a_lef_min=ac_bdlr0_a_lef;
17003 ac_bdlr0_a_rig_min=ac_bdlr0_a_rig;
17004 }
17005 printf("\ntest A channel AC result\n");
17006 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
17007 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
17008 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
17009
17010 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_a_org);
17011 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org,ac_lcdlr_a_lef,ac_lcdlr_a_rig,ac_lcdlr_a_lef_min,ac_lcdlr_a_rig_min);
17012 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org,ac_bdlr0_a_lef,ac_bdlr0_a_rig,ac_bdlr0_a_lef_min,ac_bdlr0_a_rig_min);
17013 }
17014
17015 if (reg_base_adj == CHANNEL_B_REG_BASE)
17016 {
17017 if (test_times)
17018 {
17019 if (ac_lcdlr_b_lef>ac_lcdlr_b_lef_min)
17020 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
17021
17022 if (ac_lcdlr_b_rig<ac_lcdlr_b_rig_min)
17023 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
17024
17025 if (ac_bdlr0_b_lef>ac_bdlr0_b_lef_min)
17026 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
17027
17028 if (ac_bdlr0_b_rig<ac_bdlr0_b_rig_min)
17029 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
17030 }
17031 else
17032 {
17033 ac_lcdlr_b_lef_min=ac_lcdlr_b_lef;
17034 ac_lcdlr_b_rig_min=ac_lcdlr_b_rig;
17035 ac_bdlr0_b_lef_min=ac_bdlr0_b_lef;
17036 ac_bdlr0_b_rig_min=ac_bdlr0_b_rig;
17037 }
17038 printf("\ntest B channel AC result\n");
17039 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
17040 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
17041 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
17042
17043 printf("\n ac_acmdlr_org 0x%08x reg== 0x%08x lcdlr_lef lcdlr_rig lcdlr_lmin lcdlr_rmin\n",(reg_add),ac_mdlr_b_org);
17044 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org,ac_lcdlr_b_lef,ac_lcdlr_b_rig,ac_lcdlr_b_lef_min,ac_lcdlr_b_rig_min);
17045 printf("\n ac_bdlr0_a_org 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org,ac_bdlr0_b_lef,ac_bdlr0_b_rig,ac_bdlr0_b_lef_min,ac_bdlr0_b_rig_min);
17046 }
17047 }
17048 }
17049
17050 }
17051
17052
17053
17054
17055 return 0;
17056
17057usage:
17058 cmd_usage(cmdtp);
17059 return 1;
17060
17061}
17062
17063
17064U_BOOT_CMD(
17065 ddr_tune_ddr_ac_bdlr, 7, 1, do_ddr_test_ac_windows_bdlr,
17066 "DDR tune ac bdl function",
17067 "ddr_tune_ddr_ac_bdlr a 0 0x8000000 1 seed step or ddr_tune_ddr_ac_bdlr b 0 0x800000 1 seed step or ddr_tune_ddr_ac_acbdlr_ck a b 0x80000 l\n dcache off ? \n"
17068);
17069
17070
17071#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
17072#else
17073int do_ddr_test_vref(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
17074{
17075 printf("\nEnter Test ddr vref function\n");
17076 // if(!argc)
17077 // goto DDR_TUNE_DQS_START;
17078 printf("\nargc== 0x%08x\n", argc);
17079
17080
17081 // unsigned int loop = 1;
17082 // unsigned int temp_count_i = 1;
17083 // unsigned int temp_count_j= 1;
17084 // unsigned int temp_count_k= 1;
17085 unsigned int temp_test_error= 0;
17086 static unsigned int training_seed=0;
17087 static unsigned int training_step=0;
17088
17089 char *endp;
17090 // unsigned int *p_start_addr;
17091 unsigned int test_loop=1;
17092 unsigned int test_times=1;
17093 unsigned int reg_add=0;
17094 unsigned int reg_base_adj=0;
17095 unsigned int channel_a_en = 0;
17096 unsigned int channel_b_en = 0;
17097 unsigned int testing_channel = 0;
17098
17099
17100
17101#define CHANNEL_A 0
17102#define CHANNEL_B 1
17103#define DDR_CROSS_TALK_TEST_SIZE 0x20000
17104
17105 unsigned int ac_mdlr_a_org=0;
17106 unsigned int ac_mdlr_b_org=0;
17107
17108 unsigned int ac_lcdlr_a_org=0;
17109 unsigned int ac_bdlr0_a_org=0;
17110 unsigned int ac_lcdlr_b_org=0;
17111 unsigned int ac_bdlr0_b_org=0;
17112 // unsigned int ac_lcdlr_a_rig=0;
17113 // unsigned int ac_bdlr0_a_rig=0;
17114 // unsigned int ac_lcdlr_b_rig=0;
17115 // unsigned int ac_bdlr0_b_rig=0;
17116 // unsigned int ac_lcdlr_a_lef=0;
17117 // unsigned int ac_bdlr0_a_lef=0;
17118 // unsigned int ac_lcdlr_b_lef=0;
17119 // unsigned int ac_bdlr0_b_lef=0;
17120
17121 // unsigned int ac_lcdlr_a_rig_min=0;
17122 // unsigned int ac_bdlr0_a_rig_min=0;
17123 // unsigned int ac_lcdlr_b_rig_min=0;
17124 // unsigned int ac_bdlr0_b_rig_min=0;
17125 // unsigned int ac_lcdlr_a_lef_min=0;
17126 // unsigned int ac_bdlr0_a_lef_min=0;
17127 // unsigned int ac_lcdlr_b_lef_min=0;
17128 // unsigned int ac_bdlr0_b_lef_min=0;
17129 // unsigned int ac_lcdlr_temp;
17130 // unsigned int ac_bdlr0_temp=0;
17131
17132
17133
17134 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
17135
17136 // unsigned int ac_bdlr_lef[10];
17137 // unsigned int ac_bdlr_rig[10];
17138 unsigned int iovref_temp_value;
17139 unsigned int iovref_temp_reg_value;
17140 unsigned int reg_seed_value;
17141 // unsigned int temp_reg_value;
17142 unsigned int iovref_lef;
17143 unsigned int iovref_rig;
17144 // unsigned int temp_test_error;
17145 // unsigned int temp_i=0;
17146 // unsigned int temp_j=0;
17147 //unsigned int reg_add=0;
17148 // static unsigned int training_enabled=1;
17149
17150 // iovref_lef=0x49;
17151 // printf("\n\n iovref org ==0x%08x %08dmV\n",iovref_lef,(((((iovref_lef&0X3F)*7)+440)*3)/2)+1);
17152 //#define DDR_TEST_ACLCDLR
17153
17154
17155 if (argc == 2)
17156 {
17157 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
17158 {
17159 channel_a_en = 1;
17160 }
17161 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
17162 {
17163 channel_b_en = 1;
17164 }
17165 else
17166 {
17167 goto usage;
17168 }
17169 }
17170 if (argc > 2)
17171 {
17172 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
17173 {
17174 channel_a_en = 1;
17175 }
17176 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
17177
17178 {
17179 channel_b_en = 1;
17180 }
17181 }
17182 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
17183 if (argc >3) {
17184 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
17185 if (*argv[3] == 0 || *endp != 0)
17186 {
17187 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
17188 }
17189
17190 }
17191 if (argc >4) {
17192 test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
17193 if (*argv[4] == 0 || *endp != 0)
17194 {
17195 test_loop = 1;
17196 }
17197 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
17198 {
17199 test_loop = 100000;
17200 }
17201 }
17202 training_seed = 0x49;
17203 if (argc >5) {
17204 training_seed = simple_strtoull_ddr(argv[5], &endp, 16);
17205 if (*argv[5] == 0 || *endp != 0)
17206 {
17207 training_seed = 0x49;
17208 }
17209
17210
17211 }
17212
17213 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*7)+440)*3)/2)+1);
17214
17215 training_step = 0;
17216 if (argc >6) {
17217 training_step = simple_strtoull_ddr(argv[6], &endp, 16);
17218 if (*argv[6] == 0 || *endp != 0)
17219 {
17220 training_step = 0;
17221 }
17222 }
17223 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
17224 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
17225 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
17226 printf("\ntest_loop== 0x%08x\n", test_loop);
17227 if ( channel_a_en)
17228 {
17229 //writel((0), 0xc8836c00);
17230 OPEN_CHANNEL_A_PHY_CLK();
17231 }
17232 if ( channel_b_en)
17233 {
17234 OPEN_CHANNEL_B_PHY_CLK();
17235 //writel((0), 0xc8836c00);
17236 }
17237
17238 //save and print org training dqs value
17239 if (channel_a_en || channel_b_en)
17240 {
17241 //dcache_disable();
17242 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
17243
17244 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
17245 {
17246 if (( channel_a_en) && ( channel_b_en == 0))
17247 {
17248 reg_base_adj=CHANNEL_A_REG_BASE;
17249 }
17250 else if(( channel_b_en)&&( channel_a_en==0))
17251 {
17252 reg_base_adj=CHANNEL_B_REG_BASE;
17253 }
17254 else if ((channel_a_en+channel_b_en)==2)
17255 {
17256 if ( testing_channel == CHANNEL_A)
17257 {
17258 reg_base_adj=CHANNEL_A_REG_BASE;
17259 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
17260 }
17261 else if( testing_channel==CHANNEL_B)
17262 {
17263 reg_base_adj=CHANNEL_B_REG_BASE;
17264
17265 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
17266 }
17267 }
17268
17269 reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
17270
17271 if (reg_base_adj == CHANNEL_A_REG_BASE)
17272 {
17273 printf("\ntest A channel 0x%08x\n",reg_add);
17274 ac_mdlr_a_org=(unsigned int )(readl((unsigned int )reg_add));//readl(reg_add);//0xc8836000
17275 ac_lcdlr_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR)));//readl(reg_add+4);
17276 ac_bdlr0_a_org=(unsigned int )(readl((unsigned int )(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR)));//readl(reg_add+8);
17277
17278 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_a_org);
17279 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_a_org);
17280 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_a_org);
17281 }
17282 if (reg_base_adj == CHANNEL_B_REG_BASE)
17283 {
17284
17285 ac_mdlr_b_org=readl(reg_add);
17286 ac_lcdlr_b_org=readl(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR);
17287 ac_bdlr0_b_org=readl(reg_add+8);
17288 printf("\n ac_mdlr_org 0x%08x reg== 0x%08x\n",(reg_add), ac_mdlr_b_org);
17289 printf("\n ac_lcdlr_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACLCDLR-DDR0_PUB_ACMDLR), ac_lcdlr_b_org);
17290 printf("\n ac_bdlr0_org 0x%08x reg== 0x%08x\n",(reg_add+DDR0_PUB_ACBDLR0-DDR0_PUB_ACMDLR), ac_bdlr0_b_org);
17291 }
17292
17293
17294 }
17295
17296
17297 }////save and print org training value
17298
17299
17300 for (test_times=0;(test_times<test_loop);(test_times++))
17301 {
17302 ////tune and save training dqs value
17303 if (channel_a_en || channel_b_en)
17304 {
17305 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
17306 {
17307 if (( channel_a_en) && ( channel_b_en == 0))
17308 {
17309 reg_base_adj=CHANNEL_A_REG_BASE;
17310 }
17311 else if(( channel_b_en)&&( channel_a_en==0))
17312 {
17313 reg_base_adj=CHANNEL_B_REG_BASE;
17314 }
17315 else if ((channel_a_en+channel_b_en)==2)
17316 {
17317 if ( testing_channel == CHANNEL_A)
17318 {
17319 reg_base_adj=CHANNEL_A_REG_BASE;
17320 }
17321 else if( testing_channel==CHANNEL_B)
17322 {
17323 reg_base_adj=CHANNEL_B_REG_BASE;
17324 }
17325 }
17326
17327 if (reg_base_adj == CHANNEL_A_REG_BASE)
17328 {
17329 printf("\ntest A channel AC\n");
17330 }
17331 else
17332 {
17333 printf("\ntest B channel AC\n");
17334 }
17335
17336
17337#define wrr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
17338#define rdr_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
17339 //wr_reg(DDR0_PUB_ACBDLR3, 0x0808); //cs0 cs1
17340 //wr_reg(DDR0_PUB_ACBDLR0, 0x1f); //ck0
17341 // wr_reg(DDR0_PUB_ACBDLR4, 0x0808); //odt0 odt1
17342 //wr_reg(DDR0_PUB_ACBDLR5, 0x0808); //cke0 cke1
17343
17344
17345 //wr_reg(DDR0_PUB_ACBDLR1, 0x181818); //ras cas we
17346 //wr_reg(DDR0_PUB_ACBDLR2, 0x181818); //ba0 ba1 ba2
17347 //wr_reg(DDR0_PUB_ACBDLR6, 0x12121212); //a0 a1 a2 a3
17348 //wr_reg(DDR0_PUB_ACBDLR7, 0x0d0d0d0d); //a4 a5 a6 a7
17349 //wr_reg(DDR0_PUB_ACBDLR8, 0x10101010); //a8 a9 a10 a11
17350 //wr_reg(DDR0_PUB_ACBDLR9, 0x18181818); //a12 a13 a14 a15
17351 reg_add=DDR0_PUB_IOVCR0;
17352 reg_seed_value=(training_seed|(training_seed<<8)|(training_seed<<16)|(training_seed<<24));
17353 //for(( temp_i=0);(temp_i<10);( temp_i++))
17354 //wr_reg((DDR0_PUB_ACBDLR0+temp_i*4),
17355 //ac_bdlr_reg_seed_value); //cs0 cs1
17356 //reg_add=reg_add+temp_i*4;
17357
17358 //reg_add=DDR0_PUB_ACMDLR+reg_base_adj;
17359 //reg_add=(DDR0_PUB_ACBDLR0+temp_i*4);
17360 reg_add=reg_add+reg_base_adj;
17361 iovref_temp_value=rdr_reg((unsigned int )reg_add);
17362 iovref_temp_value=((iovref_temp_value)&0xff);
17363 // iovref_lef=0x49;
17364 if (iovref_temp_value)
17365 {
17366 printf("\n\n iovref org ==0x%08x %08dmV\n",iovref_temp_value,(((((iovref_temp_value&0X3F)*7)+440)*3)/2)+1);
17367 }
17368 else
17369 {
17370 printf("\nio vref power down ,use external resister \n ");
17371 }
17372
17373 wrr_reg((reg_add),
17374 reg_seed_value); //
17375
17376 wrr_reg((reg_add+4),
17377 reg_seed_value); //
17378 iovref_lef=training_seed;
17379 iovref_rig=training_seed;
17380
17381 printf("\ntraining_step==0x%08x\n ",training_step);
17382
17383 iovref_temp_value=rdr_reg((unsigned int )reg_add);
17384 iovref_temp_value=((iovref_temp_value)&0xff);
17385 while (iovref_temp_value>0x40)
17386 {
17387 temp_test_error=0;
17388 iovref_temp_value--;
17389
17390 printf("\niovref lef temp==0x%08x\n ",iovref_temp_value);
17391
17392 iovref_temp_reg_value=(iovref_temp_value|(iovref_temp_value<<8)|(iovref_temp_value<<16)|(iovref_temp_value<<24));;
17393 wrr_reg((reg_add),
17394 iovref_temp_reg_value); //
17395
17396 wrr_reg((reg_add+DDR0_PUB_IOVCR1-DDR0_PUB_IOVCR0),
17397 iovref_temp_reg_value); //
17398 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,iovref_temp_reg_value);
17399 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
17400 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
17401 if (temp_test_error)
17402 {
17403 printf("\nvref down edge detect \n");
17404 iovref_temp_value++;
17405 break;
17406 }
17407 }
17408
17409 printf("\n down edge detect \n");
17410 printf("\n\n iovref down edge==0x%08x\n ",iovref_temp_value);
17411 iovref_lef=iovref_temp_value;
17412
17413 wrr_reg((reg_add),
17414 reg_seed_value); //
17415
17416 wrr_reg((reg_add+DDR0_PUB_IOVCR1-DDR0_PUB_IOVCR0),
17417 reg_seed_value); //
17418
17419 iovref_temp_value=rdr_reg((unsigned int )reg_add);
17420 iovref_temp_value=((iovref_temp_value)&0xff);
17421
17422
17423 while (iovref_temp_value<0x7f)
17424 {
17425 temp_test_error=0;
17426 iovref_temp_value++;
17427
17428 printf("\niovref lef temp==0x%08x\n ",iovref_temp_value);
17429
17430 iovref_temp_reg_value=(iovref_temp_value|(iovref_temp_value<<8)|(iovref_temp_value<<16)|(iovref_temp_value<<24));;
17431 wrr_reg((reg_add),
17432 iovref_temp_reg_value); //
17433
17434 wrr_reg((reg_add+DDR0_PUB_IOVCR1-DDR0_PUB_IOVCR0),
17435 iovref_temp_reg_value); //
17436 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,iovref_temp_reg_value);
17437
17438 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
17439 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
17440 if (temp_test_error)
17441 {
17442 printf("\nvref up edge detect \n");
17443 iovref_temp_value--;
17444 break;
17445 }
17446 }
17447
17448 printf("\n up edge detect \n");
17449 printf("\n\n iovref up edge==0x%08x\n ",iovref_temp_value);
17450 iovref_rig=iovref_temp_value;
17451
17452 //reg_seed_value=0x49494949
17453 wrr_reg((reg_add),
17454 0x49494949); //
17455
17456 wrr_reg((reg_add+DDR0_PUB_IOVCR1-DDR0_PUB_IOVCR0),
17457 0x49494949); //
17458
17459 printf("\n\n iovref down edge==0x%08x %08dmV\n",iovref_lef,(((((iovref_lef&0X3F)*7)+440)*3)/2)+1);
17460 printf("\n\n iovref up edge==0x%08x %08dmV\n",iovref_rig,(((((iovref_rig&0X3F)*7)+440)*3)/2)+1);
17461 printf("\n\n iovref mid ==0x%08x %08dmV\n",
17462 (iovref_lef+iovref_rig)/2,(((((((iovref_lef+iovref_rig)/2)&0X3F)*7)+440)*3)/2)+1);
17463 if (iovref_lef == 0x40)
17464 printf("\n\n iovref down edge reach reg limited\n");
17465 }
17466 }
17467 }
17468
17469 return 0;
17470
17471usage:
17472 cmd_usage(cmdtp);
17473 return 1;
17474
17475}
17476U_BOOT_CMD(
17477 ddr_tune_ddr_vref, 7, 1, do_ddr_test_vref,
17478 "DDR tune vref function ddr_tune_ddr_vref a 0 0x8000000 1 48 1",
17479 "ddr_tune_ddr_vref a 0 0x8000000 1 seed step \n dcache off ? \n"
17480);
17481
17482
17483int do_ddr4_test_phy_vref(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
17484{
17485 printf("watchdog_time_s==%d\n",watchdog_time_s);
17486 if (watchdog_time_s == 0)
17487 {
17488 watchdog_time_s=50;
17489 printf("test soc_vref re set watchdog_time_s==%d\n",watchdog_time_s);
17490 }
17491
17492#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
17493 // unsigned int start_addr=test_start_addr;
17494 printf("\nEnter Test ddr4 phy vref function\n");
17495 // if(!argc)
17496 // goto DDR_TUNE_DQS_START;
17497 printf("\nargc== 0x%08x\n", argc);
17498
17499 // unsigned int loop = 1;
17500 // unsigned int temp_count_i = 1;
17501 // unsigned int temp_count_j= 1;
17502 // unsigned int temp_count_k= 1;
17503 unsigned int temp_test_error= 0;
17504 int training_seed=0;
17505 int training_step=0;
17506
17507 char *endp;
17508 // unsigned int *p_start_addr;
17509 unsigned int test_soc_dram=0;
17510 // unsigned int test_times=1;
17511 unsigned int reg_add=0;
17512 unsigned int reg_base_adj=0;
17513 unsigned int channel_a_en = 0;
17514 unsigned int channel_b_en = 0;
17515 unsigned int testing_channel = 0;
17516 unsigned int dxnlcdlr3[4];
17517 unsigned int dxnlcdlr4[4];
17518
17519
17520#define CHANNEL_A 0
17521#define CHANNEL_B 1
17522#define DDR_CROSS_TALK_TEST_SIZE 0x20000
17523 // #define DDR0_PUB_REG_BASE 0xc8836000
17524#define DDR0_PUB_DX0GCR4 ( DDR0_PUB_REG_BASE + ( 0x1c4 << 2 ) )
17525#define DDR0_PUB_DX1GCR4 ( DDR0_PUB_REG_BASE + ( 0x204 << 2 ) )
17526#define DDR0_PUB_DX2GCR4 ( DDR0_PUB_REG_BASE + ( 0x244 << 2 ) )
17527#define DDR0_PUB_DX3GCR4 ( DDR0_PUB_REG_BASE + ( 0x284 << 2 ) )
17528#define DDR0_PUB_DX0GCR5 ( DDR0_PUB_REG_BASE + ( 0x1c5 << 2 ) )
17529#define DDR0_PUB_DX1GCR5 ( DDR0_PUB_REG_BASE + ( 0x205 << 2 ) )
17530#define DDR0_PUB_DX2GCR5 ( DDR0_PUB_REG_BASE + ( 0x245 << 2 ) )
17531#define DDR0_PUB_DX3GCR5 ( DDR0_PUB_REG_BASE + ( 0x285 << 2 ) )
17532
17533 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
17534
17535 // unsigned int ac_bdlr_lef[10];
17536 // unsigned int ac_bdlr_rig[10];
17537 int iovref_temp_value;
17538 int ddr_soc_iovref_org=0;
17539 int iovref_temp_reg_value;
17540 // unsigned int reg_seed_value;
17541 // unsigned int temp_reg_value;
17542 int iovref_org[4];
17543 int iovref_lef[4];
17544 int iovref_rig[4];
17545 // unsigned int temp_test_error;
17546 // unsigned int temp_i=0;
17547 // unsigned int temp_j=0;
17548 //unsigned int reg_add=0;
17549 // static unsigned int training_enabled=1;
17550
17551 // iovref_lef=0x49;
17552 // printf("\n\n iovref org ==0x%08x %08dmV\n",iovref_lef,(((((iovref_lef&0X3F)*7)+440)*3)/2)+1);
17553 //#define DDR_TEST_ACLCDLR
17554
17555 char str_temp1[1024]="";
17556 char str_temp2[1024]="";
17557 char str[512]="";
17558 unsigned int soc_iovref_test_ddr_clk=0;
17559 sprintf(str_temp1,"ddr_soc_iovref_test_ddr_clk");
17560 soc_iovref_test_ddr_clk=env_to_a_num(str_temp1);
17561 if (soc_iovref_test_ddr_clk == 0)
17562 {
17563 soc_iovref_test_ddr_clk=global_ddr_clk;
17564 {
17565 sprintf(str_temp1,"ddr_soc_iovref_test_ddr_clk");
17566 sprintf(str_temp2,"0x%08x",soc_iovref_test_ddr_clk);
17567 env_set(str_temp1, str_temp2);
17568 run_command("save",0);
17569 }
17570 }
17571 if (soc_iovref_test_ddr_clk != global_ddr_clk)
17572 {
17573 printf("running ddr freq==%d,but test freq is %d,will reboot use d2pll \n",global_ddr_clk,soc_iovref_test_ddr_clk);
17574 sprintf(str,"d2pll %d",soc_iovref_test_ddr_clk);
17575 printf("\nstr=%s\n",str);
17576 run_command(str,0);
17577 while (1) ;
17578 }
17579 unsigned int soc_iovref_test_step=0;
17580 sprintf(str_temp1,"soc_iovref_test_step");
17581 soc_iovref_test_step=env_to_a_num(str_temp1);
17582 if (soc_iovref_test_step == 0)
17583 iovref_temp_value=0;
17584 {
17585 sprintf(str_temp1,"soc_iovref_test_step");
17586 sprintf(str_temp2,"0x%08x",iovref_temp_value);
17587 env_set(str_temp1, str_temp2);
17588 run_command("save",0);
17589 }
17590
17591 unsigned int soc_iovref_lef=0;
17592 unsigned int soc_iovref_rig=0;
17593 //char *p_str=NULL;
17594 if (argc == 2)
17595 {
17596 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
17597
17598 {channel_a_en = 1;
17599 }
17600 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
17601 {
17602 channel_b_en = 1;
17603 }
17604 else
17605 {
17606 goto usage;
17607 }
17608 }
17609 if (argc > 2)
17610 {
17611 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
17612 {
17613 channel_a_en = 1;
17614 }
17615 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
17616 {
17617 channel_b_en = 1;
17618 }
17619 }
17620 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
17621 if (argc >3) {
17622 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
17623 if (*argv[3] == 0 || *endp != 0)
17624 {
17625 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
17626 }
17627
17628 }
17629 if (argc >4) {
17630 test_soc_dram = simple_strtoull_ddr(argv[4], &endp, 16);
17631 if (*argv[4] == 0 || *endp != 0)
17632 {
17633 test_soc_dram = 0;
17634 }
17635 if (test_soc_dram)
17636 test_soc_dram = 1;
17637
17638 }
17639 training_seed = 0;
17640 if (argc >5) {
17641 training_seed = simple_strtoull_ddr(argv[5], &endp, 16);
17642 if (*argv[5] == 0 || *endp != 0)
17643 {
17644 training_seed =0;// 0x2e;
17645 }
17646 }
17647
17648 if (training_seed>0x3f)
17649 training_seed=0x3f;
17650
17651 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,((((((training_seed&0X3F)*7)+440)*3)/2)+1)*12/15);
17652
17653 training_step = 0;
17654 if (argc >6) {
17655 training_step = simple_strtoull_ddr(argv[6], &endp, 16);
17656 if (*argv[6] == 0 || *endp != 0)
17657 {
17658 training_step = 0;
17659 }
17660 }
17661 int vref_all=1;
17662 if (argc >7) {
17663 vref_all = simple_strtoull_ddr(argv[7], &endp, 16);
17664 if (*argv[7] == 0 || *endp != 0)
17665 {
17666 vref_all =0;//
17667 }
17668 }
17669 vref_all =1;//
17670 int vref_lcdlr_offset=0;
17671 if (argc >8) {
17672 vref_lcdlr_offset = simple_strtoull_ddr(argv[8], &endp, 16);
17673 if (*argv[8] == 0 || *endp != 0)
17674 {
17675 vref_lcdlr_offset =0;
17676 }
17677 }
17678 int vref_set_test_step=0;
17679 if (argc >9) {
17680 vref_set_test_step = simple_strtoull_ddr(argv[9], &endp, 16);
17681 if (*argv[9] == 0 || *endp != 0)
17682 {
17683 vref_set_test_step =0;
17684 }
17685 }
17686
17687 unsigned int soc_dram_hex_dec=0;
17688 if (argc >10)
17689 {
17690 soc_dram_hex_dec = simple_strtoull_ddr(argv[10], &endp, 0);
17691 if (*argv[10] == 0 || *endp != 0) {
17692 soc_dram_hex_dec = 0;
17693 }
17694 }
17695 if (soc_dram_hex_dec)
17696 {
17697 if (argc >5) {
17698 training_seed = simple_strtoull_ddr(argv[5], &endp, 0);
17699 if (*argv[5] == 0 || *endp != 0)
17700 {
17701 training_seed =0;// 0x2e;
17702 }
17703 printf("\ntraining_seed== 0x%08x\n", training_seed);
17704
17705 }
17706 if (training_seed<45)
17707 training_seed=45;
17708 if (training_seed>88)
17709 training_seed=88;
17710 training_seed =(((training_seed*1000-44070)/698));
17711
17712
17713 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,((((((training_seed&0X3F)*7)+440)*3)/2)+1)*12/15);
17714 }
17715 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
17716 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
17717 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
17718 printf("\ntest_soc_dram== 0x%08x\n", test_soc_dram);
17719 printf("\nvref_all== 0x%08x\n", vref_all);
17720 printf("\nvref_lcdlr_offset== 0x%08x\n", vref_lcdlr_offset);
17721 printf("\nsoc_dram_hex_dec== 0x%08x\n", soc_dram_hex_dec);
17722 if ( channel_a_en)
17723 {
17724 //writel((0), 0xc8836c00);
17725 OPEN_CHANNEL_A_PHY_CLK();
17726 }
17727 if ( channel_b_en)
17728 {
17729 OPEN_CHANNEL_B_PHY_CLK();
17730 //writel((0), 0xc8836c00);
17731 }
17732
17733 //save and print org training dqs value
17734 if (channel_a_en || channel_b_en)
17735 {
17736 //dcache_disable();
17737 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
17738 }////save and print org training value
17739
17740
17741
17742 ////tune and save training dqs value
17743 if (channel_a_en || channel_b_en)
17744 {
17745 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
17746 {
17747 if (( channel_a_en) && ( channel_b_en == 0))
17748 {
17749 reg_base_adj=CHANNEL_A_REG_BASE;
17750 }
17751 else if(( channel_b_en)&&( channel_a_en==0))
17752 {
17753 reg_base_adj=CHANNEL_B_REG_BASE;
17754 }
17755 else if ((channel_a_en+channel_b_en)==2)
17756 {
17757 if ( testing_channel == CHANNEL_A)
17758 {
17759 reg_base_adj=CHANNEL_A_REG_BASE;
17760 }
17761 else if( testing_channel==CHANNEL_B)
17762 {
17763 reg_base_adj=CHANNEL_B_REG_BASE;
17764 }
17765 }
17766
17767 if (reg_base_adj == CHANNEL_A_REG_BASE)
17768 {
17769 printf("\ntest A channel data lane\n");
17770 }
17771 else
17772 {
17773 printf("\ntest B channel data lane\n");
17774 }
17775
17776
17777
17778
17779#define wrr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
17780#define rdr_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
17781 unsigned int dxnmdlr=0;
17782 reg_add=DDR0_PUB_DX0MDLR0+reg_base_adj;
17783 dxnmdlr=((rdr_reg((unsigned int )reg_add))>>16)&0x1ff;
17784 // reg_seed_value=(training_seed|(0x0<<8)|(0x0<<16)|(0x0<<24));
17785 wrr_reg((((DDR0_PUB_DX0GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
17786 wrr_reg((((DDR0_PUB_DX1GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
17787 wrr_reg((((DDR0_PUB_DX2GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
17788 wrr_reg((((DDR0_PUB_DX3GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
17789 printf("\nDDR0_PUB_DX0GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4))));
17790 printf("\nDDR0_PUB_DX1GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4))));
17791 printf("\nDDR0_PUB_DX2GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4))));
17792 printf("\nDDR0_PUB_DX3GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4))));
17793
17794 printf("\ndxnmdlr==0x%08x\n ",dxnmdlr);
17795 unsigned int temp_i=0;
17796 unsigned int temp_i_max=4;
17797 for (( temp_i=0);(temp_i<4);( temp_i++))
17798 {
17799 dxnlcdlr3[temp_i]=(rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+temp_i*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))));
17800 dxnlcdlr4[temp_i]=(rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+temp_i*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))));
17801 reg_add=DDR0_PUB_DX0GCR5+reg_base_adj+temp_i*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5);
17802 iovref_temp_value=rdr_reg((unsigned int )reg_add);
17803 iovref_org[temp_i]=iovref_temp_value;
17804 iovref_temp_value=((iovref_temp_value)&0xff);
17805 printf("\ndxnlcdlr3[%08x]==0x%08x,dxnlcdlr4[%08x]==0x%08x\n ",temp_i,dxnlcdlr3[temp_i],temp_i,dxnlcdlr4[temp_i]);
17806 // iovref_lef=0x49;
17807 if (iovref_temp_value)
17808 {
17809 printf("reg_add==0x%08x,value==0x%08x, iovref org ==0x%08x %08dmV\n",reg_add,
17810 iovref_org[temp_i],iovref_temp_value,((((((iovref_temp_value&0X3F)*7)+440)*3)/2)+1)*12/15);
17811 }
17812 else
17813 {
17814 printf("\nio vref power down ,use external resister \n ");
17815 }
17816
17817 wrr_reg((reg_add),
17818 iovref_org[temp_i]); //
17819 iovref_lef[temp_i]=(iovref_org[temp_i])&0xff;
17820 iovref_rig[temp_i]=(iovref_org[temp_i])&0xff;
17821 if (training_seed)
17822 {iovref_lef[temp_i]=training_seed;
17823 iovref_rig[temp_i]=training_seed;
17824
17825 }
17826 }
17827
17828 printf("\ntraining_step==0x%08x\n ",training_step);
17829 if (vref_all)
17830 {temp_i_max=1;
17831 }
17832 for (( temp_i=0);(temp_i<temp_i_max);( temp_i++))
17833 {
17834 reg_add=DDR0_PUB_DX0GCR5+reg_base_adj+temp_i*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5);
17835
17836
17837 if (training_seed)
17838 {
17839 wrr_reg((reg_add),
17840 (training_seed|((iovref_org[temp_i])&0xffffff00)));
17841 if (vref_all) {
17842 wrr_reg(((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
17843 (training_seed|((iovref_org[temp_i+1])&0xffffff00))); //
17844 wrr_reg(((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
17845 (training_seed|((iovref_org[temp_i+2])&0xffffff00))); //
17846 wrr_reg(((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
17847 (training_seed|((iovref_org[temp_i+3])&0xffffff00))); //
17848 }
17849 }
17850
17851 {
17852
17853 iovref_temp_value=rdr_reg((unsigned int )reg_add);
17854 iovref_temp_value=((iovref_temp_value)&0xff);
17855
17856 sprintf(str_temp1,"ddr_soc_iovref_org");
17857 ddr_soc_iovref_org=env_to_a_num(str_temp1);
17858 if (ddr_soc_iovref_org == 0)
17859 {
17860 sprintf(str_temp1,"ddr_soc_iovref_org");
17861 sprintf(str_temp2,"0x%08x",iovref_temp_value);
17862 env_set(str_temp1, str_temp2);
17863 run_command("save",0);
17864
17865 sprintf(str_temp1,"ddr_soc_iovref_lef");
17866 sprintf(str_temp2,"0x%08x",iovref_temp_value);
17867 env_set(str_temp1, str_temp2);
17868 run_command("save",0);
17869
17870 sprintf(str_temp1,"ddr_soc_iovref_rig");
17871 sprintf(str_temp2,"0x%08x",iovref_temp_value);
17872 env_set(str_temp1, str_temp2);
17873 run_command("save",0);
17874 }
17875 sprintf(str_temp1,"ddr_soc_iovref_lef");
17876 soc_iovref_lef=env_to_a_num(str_temp1);
17877 sprintf(str_temp1,"ddr_soc_iovref_rig");
17878 soc_iovref_rig=env_to_a_num(str_temp1);
17879
17880
17881 if (soc_iovref_lef)
17882 {;
17883 }
17884
17885 ddr_test_watchdog_enable(watchdog_time_s);
17886
17887 if (vref_set_test_step)
17888 {
17889 printf("\nvref_set_test_step==0x%08x,skip test left edge\n ",vref_set_test_step);
17890 soc_iovref_test_step=1;
17891 {
17892 sprintf(str_temp1,"soc_iovref_test_step");
17893 sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
17894 env_set(str_temp1, str_temp2);
17895 run_command("save",0);
17896 }
17897 //break;
17898 }
17899
17900 if (soc_iovref_test_step == 0)
17901 {//int temp=0;
17902 if (soc_iovref_lef)
17903 {iovref_temp_value=soc_iovref_lef;
17904 }
17905 while (iovref_temp_value>0x0)
17906 {
17907
17908 temp_test_error=0;
17909 iovref_temp_value=iovref_temp_value-training_step;
17910 if (iovref_temp_value<training_step)
17911 iovref_temp_value=0;
17912 printf("\niovref lef temp==0x%08x\n ",iovref_temp_value);
17913
17914 {
17915 sprintf(str_temp1,"ddr_soc_iovref_lef");
17916 sprintf(str_temp2,"0x%08x",iovref_temp_value);
17917 env_set(str_temp1, str_temp2);
17918 run_command("save",0);
17919 }
17920
17921 iovref_temp_reg_value=(iovref_temp_value|((iovref_org[temp_i])&0xffffff00));
17922 wrr_reg((reg_add),
17923 iovref_temp_reg_value); //
17924 if (vref_all) {
17925 wrr_reg((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
17926 iovref_temp_reg_value); //
17927 wrr_reg((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
17928 iovref_temp_reg_value); //
17929 wrr_reg((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
17930 iovref_temp_reg_value); //
17931 }
17932 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,iovref_temp_reg_value);
17933 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
17934 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
17935 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
17936 ddr_test_watchdog_clear();
17937 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
17938 ddr_test_watchdog_clear();
17939 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
17940 ddr_test_watchdog_clear();
17941 if (vref_lcdlr_offset)
17942 {
17943 {
17944 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR3+reg_base_adj)))+vref_lcdlr_offset)); //
17945 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR4+reg_base_adj)))+vref_lcdlr_offset)); //
17946 if (vref_all) {
17947 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17948 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
17949 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17950 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
17951 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17952 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
17953 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17954 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
17955 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17956 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
17957 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17958 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
17959 }
17960 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17961 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
17962 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17963 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
17964 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17965 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
17966 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17967 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
17968 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17969 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
17970 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17971 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
17972 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17973 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
17974 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17975 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
17976 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
17977 ddr_test_watchdog_clear();
17978
17979 {
17980 {
17981 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
17982 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
17983 if (vref_all) {
17984 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17985 dxnlcdlr3[1]); //
17986 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17987 dxnlcdlr3[2]); //
17988 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
17989 dxnlcdlr3[3]); //
17990 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17991 dxnlcdlr4[1]); //
17992 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17993 dxnlcdlr4[2]); //
17994 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
17995 dxnlcdlr4[3]); //
17996 }
17997
17998 }
17999 }
18000
18001 }
18002
18003 }
18004
18005 if (vref_lcdlr_offset)
18006 {
18007 {
18008 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),(dxnlcdlr3[0]-vref_lcdlr_offset)); //
18009 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),(dxnlcdlr4[0]-vref_lcdlr_offset)); //
18010 if (vref_all) {
18011 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18012 (dxnlcdlr3[1]-vref_lcdlr_offset)); //
18013 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18014 (dxnlcdlr3[2]-vref_lcdlr_offset)); //
18015 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18016 (dxnlcdlr3[3]-vref_lcdlr_offset)); //
18017 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18018 (dxnlcdlr4[1]-vref_lcdlr_offset)); //
18019 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18020 (dxnlcdlr4[2]-vref_lcdlr_offset)); //
18021 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18022 (dxnlcdlr4[3]-vref_lcdlr_offset)); //
18023 }
18024 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18025 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18026 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18027 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18028 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18029 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18030 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18031 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18032 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18033 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18034 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18035 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18036 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18037 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18038 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18039 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18040 ddr_test_watchdog_clear();
18041 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
18042
18043
18044 {
18045 {
18046 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
18047 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
18048 if (vref_all) {
18049 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18050 dxnlcdlr3[1]); //
18051 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18052 dxnlcdlr3[2]); //
18053 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18054 dxnlcdlr3[3]); //
18055 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18056 dxnlcdlr4[1]); //
18057 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18058 dxnlcdlr4[2]); //
18059 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18060 dxnlcdlr4[3]); //
18061 }
18062
18063 }
18064 }
18065
18066 }
18067
18068 }
18069 if (temp_test_error)
18070 {
18071 printf("\nvref down edge detect \n");
18072 iovref_temp_value=iovref_temp_value+training_step;
18073 break;
18074 }
18075 }
18076 printf("\niovref lef temp==0x%08x\n ",iovref_temp_value);
18077
18078 {
18079 sprintf(str_temp1,"ddr_soc_iovref_lef");
18080 sprintf(str_temp2,"0x%08x",iovref_temp_value);
18081 env_set(str_temp1, str_temp2);
18082 run_command("save",0);
18083 }
18084
18085 {
18086 soc_iovref_test_step=1;
18087 sprintf(str_temp1,"soc_iovref_test_step");
18088 sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
18089 env_set(str_temp1, str_temp2);
18090 run_command("save",0);
18091 run_command("reset",0);
18092 }
18093
18094 }
18095
18096 sprintf(str_temp1,"ddr_soc_iovref_lef");
18097 soc_iovref_lef=env_to_a_num(str_temp1);
18098 iovref_temp_value=soc_iovref_lef;
18099 printf("\n down edge detect \n");
18100 printf("\n\n iovref down edge==0x%08x\n ",soc_iovref_lef);
18101 iovref_lef[temp_i]=iovref_temp_value;
18102 //if(soc_iovref_lef)
18103 //{iovref_temp_value=soc_iovref_lef;
18104 //iovref_lef[temp_i]=iovref_temp_value;
18105 //}
18106 wrr_reg((reg_add),
18107 iovref_org[temp_i]); //
18108 if (vref_all) {
18109 wrr_reg(((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18110 iovref_org[temp_i+1]); //
18111 wrr_reg(((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18112 iovref_org[temp_i+2]); //
18113 wrr_reg(((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18114 iovref_org[temp_i+3]); //
18115 }
18116
18117 if (vref_lcdlr_offset)
18118 {
18119 {
18120 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
18121 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
18122 if (vref_all) {
18123 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18124 dxnlcdlr3[1]); //
18125 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18126 dxnlcdlr3[2]); //
18127 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18128 dxnlcdlr3[3]); //
18129 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18130 dxnlcdlr4[1]); //
18131 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18132 dxnlcdlr4[2]); //
18133 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18134 dxnlcdlr4[3]); //
18135 }
18136
18137 }
18138 }
18139 }
18140
18141
18142 {
18143 if (training_seed)
18144 {
18145 wrr_reg((reg_add),
18146 (training_seed|((iovref_org[temp_i])&0xffffff00)));
18147 if (vref_all) {
18148 wrr_reg(((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18149 (training_seed|((iovref_org[temp_i+1])&0xffffff00))); //
18150 wrr_reg(((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18151 (training_seed|((iovref_org[temp_i+2])&0xffffff00))); //
18152 wrr_reg(((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18153 (training_seed|((iovref_org[temp_i+3])&0xffffff00))); //
18154 }
18155 }
18156
18157 iovref_temp_value=rdr_reg((unsigned int )reg_add);
18158 iovref_temp_value=((iovref_temp_value)&0xff);
18159
18160 //if(soc_iovref_rig==0)
18161 if (soc_iovref_test_step == 1)
18162 {
18163 if (soc_iovref_rig)
18164 {iovref_temp_value=soc_iovref_rig;
18165 }
18166 while (iovref_temp_value<0x3f)
18167 {
18168 temp_test_error=0;
18169 iovref_temp_value=iovref_temp_value+training_step;
18170 if (iovref_temp_value>0x3f)
18171 iovref_temp_value=0x3f;
18172 printf("\niovref rig temp==0x%08x\n ",iovref_temp_value);
18173
18174 {
18175 sprintf(str_temp1,"ddr_soc_iovref_rig");
18176 sprintf(str_temp2,"0x%08x",iovref_temp_value);
18177 env_set(str_temp1, str_temp2);
18178 run_command("save",0);
18179 }
18180
18181 iovref_temp_reg_value=(iovref_temp_value|((iovref_org[temp_i])&0xffffff00));
18182 wrr_reg((reg_add),
18183 iovref_temp_reg_value); //
18184 if (vref_all) {
18185 wrr_reg((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
18186 iovref_temp_reg_value); //
18187 wrr_reg((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
18188 iovref_temp_reg_value); //
18189 wrr_reg((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),
18190 iovref_temp_reg_value); //
18191 }
18192
18193 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,iovref_temp_reg_value);
18194 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
18195 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
18196 printf("\n reg_add 0x%08x== 0x%08x\n ",(reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5)),iovref_temp_reg_value);
18197 ddr_test_watchdog_clear();
18198 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
18199 ddr_test_watchdog_clear();
18200 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
18201 if (vref_lcdlr_offset)
18202 {
18203 {
18204 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR3+reg_base_adj)))+vref_lcdlr_offset)); //
18205 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR4+reg_base_adj)))+vref_lcdlr_offset)); //
18206 if (vref_all) {
18207 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18208 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
18209 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18210 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
18211 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18212 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3))))+vref_lcdlr_offset)); //
18213 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18214 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
18215 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18216 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
18217 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18218 ((rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4))))+vref_lcdlr_offset)); //
18219 }
18220 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18221 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18222 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18223 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18224 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18225 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18226 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18227 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18228 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18229 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18230 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18231 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18232 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18233 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18234 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18235 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18236 ddr_test_watchdog_clear();
18237 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
18238 {
18239 {
18240 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
18241 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
18242 if (vref_all) {
18243 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18244 dxnlcdlr3[1]); //
18245 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18246 dxnlcdlr3[2]); //
18247 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18248 dxnlcdlr3[3]); //
18249 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18250 dxnlcdlr4[1]); //
18251 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18252 dxnlcdlr4[2]); //
18253 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18254 dxnlcdlr4[3]); //
18255 }
18256
18257 }
18258 }
18259
18260 }
18261
18262 }
18263
18264 if (vref_lcdlr_offset)
18265 {
18266 {
18267 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),(dxnlcdlr3[0]-vref_lcdlr_offset)); //
18268 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),(dxnlcdlr4[0]-vref_lcdlr_offset)); //
18269 if (vref_all) {
18270 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18271 (dxnlcdlr3[1]-vref_lcdlr_offset)); //
18272 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18273 (dxnlcdlr3[2]-vref_lcdlr_offset)); //
18274 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18275 (dxnlcdlr3[3]-vref_lcdlr_offset)); //
18276 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18277 (dxnlcdlr4[1]-vref_lcdlr_offset)); //
18278 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18279 (dxnlcdlr4[2]-vref_lcdlr_offset)); //
18280 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18281 (dxnlcdlr4[3]-vref_lcdlr_offset)); //
18282 }
18283 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18284 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18285 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18286 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18287 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18288 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18289 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18290 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
18291 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18292 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+0*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18293 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18294 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18295 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18296 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18297 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18298 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)))));
18299 ddr_test_watchdog_clear();
18300 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
18301 ddr_test_watchdog_clear();
18302
18303 {
18304 {
18305 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
18306 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
18307 if (vref_all) {
18308 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18309 dxnlcdlr3[1]); //
18310 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18311 dxnlcdlr3[2]); //
18312 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18313 dxnlcdlr3[3]); //
18314 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18315 dxnlcdlr4[1]); //
18316 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18317 dxnlcdlr4[2]); //
18318 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18319 dxnlcdlr4[3]); //
18320 }
18321
18322 }
18323 }
18324
18325 }
18326
18327 }
18328
18329 if (temp_test_error)
18330 {
18331 printf("\nvref up edge detect \n");
18332 iovref_temp_value=iovref_temp_value-training_step;
18333 break;
18334 }
18335 }
18336 }
18337
18338 printf("\niovref rig temp==0x%08x\n ",iovref_temp_value);
18339
18340 {
18341 sprintf(str_temp1,"ddr_soc_iovref_rig");
18342 sprintf(str_temp2,"0x%08x",iovref_temp_value);
18343 env_set(str_temp1, str_temp2);
18344 run_command("save",0);
18345 }
18346
18347 {
18348 soc_iovref_test_step=2;
18349 sprintf(str_temp1,"soc_iovref_test_step");
18350 sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
18351 env_set(str_temp1, str_temp2);
18352 run_command("save",0);
18353 //run_command("reset",0);
18354 }
18355
18356 }
18357
18358 sprintf(str_temp1,"ddr_soc_iovref_rig");
18359 soc_iovref_rig=env_to_a_num(str_temp1);
18360 iovref_temp_value=soc_iovref_rig;
18361
18362 printf("\n up edge detect \n");
18363 printf("\n\n iovref up edge==0x%08x\n ",iovref_temp_value);
18364 iovref_rig[temp_i]=iovref_temp_value;
18365 //if(soc_iovref_rig)
18366 //{iovref_temp_value=soc_iovref_rig;
18367 //iovref_rig[temp_i]=iovref_temp_value;
18368 //}
18369 wrr_reg((reg_add),
18370 iovref_org[temp_i]); //
18371 if (vref_all) {
18372 wrr_reg(((reg_add+1*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18373 iovref_org[temp_i+1]); //
18374 wrr_reg(((reg_add+2*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18375 iovref_org[temp_i+2]); //
18376 wrr_reg(((reg_add+3*(DDR0_PUB_DX1GCR5-DDR0_PUB_DX0GCR5))),
18377 iovref_org[temp_i+3]); //
18378 }
18379
18380 if (vref_lcdlr_offset)
18381 {
18382 {
18383 wrr_reg((DDR0_PUB_DX0LCDLR3+reg_base_adj),dxnlcdlr3[0]); //
18384 wrr_reg((DDR0_PUB_DX0LCDLR4+reg_base_adj),dxnlcdlr4[0]); //
18385 if (vref_all) {
18386 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18387 dxnlcdlr3[1]); //
18388 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18389 dxnlcdlr3[2]); //
18390 wrr_reg(((DDR0_PUB_DX0LCDLR3+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)),
18391 dxnlcdlr3[3]); //
18392 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+1*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18393 dxnlcdlr4[1]); //
18394 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+2*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18395 dxnlcdlr4[2]); //
18396 wrr_reg(((DDR0_PUB_DX0LCDLR4+reg_base_adj)+3*(DDR0_PUB_DX1LCDLR4-DDR0_PUB_DX0LCDLR4)),
18397 dxnlcdlr4[3]); //
18398 }
18399
18400 }
18401 }
18402
18403
18404 }
18405 // vddq=1.5v
18406 ddr_test_watchdog_disable();
18407 printf("\n\nsoc iovref test clk==%d\n",soc_iovref_test_ddr_clk);
18408 printf("\n\n iovref vddq=1.2v,if use other vddq ,please recount\n");
18409 for (( temp_i=0);(temp_i<4);( temp_i++))
18410 {
18411 printf("\n\n iovref lane_x=0x%08x, org==0x%08x %08dmV\n",temp_i,iovref_org[temp_i],((((((iovref_org[temp_i]&0X3F)*7)+440)*3)/2)+1)*12/15);
18412 printf("\n\n iovref lane_x=0x%08x, down edge==0x%08x %08dmV\n",temp_i,iovref_lef[temp_i],((((((iovref_lef[temp_i]&0X3F)*7)+440)*3)/2)+1)*12/15);
18413 printf("\n\n iovref lane_x=0x%08x, up edge==0x%08x %08dmV\n",temp_i,iovref_rig[temp_i],((((((iovref_rig[temp_i]&0X3F)*7)+440)*3)/2)+1)*12/15);
18414 printf("\n\n iovref lane_x=0x%08x, mid ==0x%08x %08dmV\n",temp_i,
18415 (iovref_lef[temp_i]+iovref_rig[temp_i])/2,((((((((iovref_lef[temp_i]+iovref_rig[temp_i])/2)&0X3F)*7)+440)*3)/2)+1)*12/15);
18416 if (iovref_lef[temp_i] == 0x0)
18417 {
18418 printf("\n\n iovref down edge reach reg limited\n");
18419 }
18420 if (iovref_rig[temp_i] == 0x3f)
18421 {
18422 printf("\n\n iovref up edge reach reg limited\n");
18423 }
18424 }
18425 {
18426 sprintf(str_temp1,"ddr_soc_iovref_org");
18427 sprintf(str_temp2,"0x%08x",iovref_org[0]);
18428 env_set(str_temp1, str_temp2);
18429 run_command("save",0);
18430 }
18431
18432 {
18433 sprintf(str_temp1,"ddr_soc_iovref_lef");
18434 sprintf(str_temp2,"0x%08x",iovref_lef[0]);
18435 env_set(str_temp1, str_temp2);
18436 run_command("save",0);
18437 }
18438 {
18439 sprintf(str_temp1,"ddr_soc_iovref_rig");
18440 sprintf(str_temp2,"0x%08x",iovref_rig[0]);
18441 env_set(str_temp1, str_temp2);
18442 run_command("save",0);
18443 }
18444
18445 printf("\n\n printf soc vref from env ,if remeasure should clear ddr_soc_iovref_org env ddr_soc_iovref_lef \
18446 ddr_soc_iovref_rig ddr_soc_vref_range,ddr_soc_iovref_test_ddr_clk \n");
18447 }
18448 }
18449 return 0;
18450
18451usage:
18452 cmd_usage(cmdtp);
18453#endif
18454 return 1;
18455
18456}
18457//*/
18458
18459int do_ddr4_test_dram_vref(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
18460{
18461
18462
18463 printf("watchdog_time_s==%d\n",watchdog_time_s);
18464 if (watchdog_time_s == 0)
18465 {
18466 watchdog_time_s=50;
18467 printf("test dram_vref re set watchdog_time_s==%d\n",watchdog_time_s);
18468 }
18469
18470#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
18471 // unsigned int start_addr=test_start_addr;
18472 printf("\nEnter Test ddr4 dram vref function\n");
18473 // if(!argc)
18474 // goto DDR_TUNE_DQS_START;
18475 printf("\nargc== 0x%08x\n", argc);
18476
18477
18478 // unsigned int loop = 1;
18479 // unsigned int temp_count_i = 1;
18480 // unsigned int temp_count_j= 1;
18481 // unsigned int temp_count_k= 1;
18482 unsigned int temp_test_error= 0;
18483 int training_seed=0;
18484 int training_step=0;
18485
18486 char *endp;
18487 // unsigned int *p_start_addr;
18488 unsigned int test_clear=0;
18489 // unsigned int test_times=1;
18490 unsigned int reg_add=0;
18491 unsigned int reg_base_adj=0;
18492 unsigned int channel_a_en = 0;
18493 unsigned int channel_b_en = 0;
18494 unsigned int testing_channel = 0;
18495 unsigned int dxnlcdlr1[4];
18496 // unsigned int dxnlcdlr4[4];
18497
18498
18499#define CHANNEL_A 0
18500#define CHANNEL_B 1
18501
18502
18503#define DDR_CROSS_TALK_TEST_SIZE 0x20000
18504 // #define DDR0_PUB_REG_BASE 0xc8836000
18505#define DDR0_PUB_DX0GCR4 ( DDR0_PUB_REG_BASE + ( 0x1c4 << 2 ) )
18506#define DDR0_PUB_DX1GCR4 ( DDR0_PUB_REG_BASE + ( 0x204 << 2 ) )
18507#define DDR0_PUB_DX2GCR4 ( DDR0_PUB_REG_BASE + ( 0x244 << 2 ) )
18508#define DDR0_PUB_DX3GCR4 ( DDR0_PUB_REG_BASE + ( 0x284 << 2 ) )
18509#define DDR0_PUB_DX0GCR5 ( DDR0_PUB_REG_BASE + ( 0x1c5 << 2 ) )
18510#define DDR0_PUB_DX1GCR5 ( DDR0_PUB_REG_BASE + ( 0x205 << 2 ) )
18511#define DDR0_PUB_DX2GCR5 ( DDR0_PUB_REG_BASE + ( 0x245 << 2 ) )
18512#define DDR0_PUB_DX3GCR5 ( DDR0_PUB_REG_BASE + ( 0x285 << 2 ) )
18513
18514
18515
18516 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
18517
18518 // unsigned int ac_bdlr_lef[10];
18519 // unsigned int ac_bdlr_rig[10];
18520 int iovref_temp_value;
18521 // int iovref_temp_reg_value;
18522 // unsigned int reg_seed_value;
18523 // unsigned int temp_reg_value;
18524 int iovref_org=0;
18525 int iovref_lef=0;
18526 int iovref_rig=0;
18527 int iovref_mid;
18528 int iovref_test_read;
18529 int iovref_test_step;
18530 // unsigned int temp_test_error;
18531 // unsigned int temp_i=0;
18532 // unsigned int temp_j=0;
18533 //unsigned int reg_add=0;
18534 // static unsigned int training_enabled=1;
18535
18536 // iovref_lef=0x49;
18537 // printf("\n\n iovref org ==0x%08x %08dmV\n",iovref_lef,(((((iovref_lef&0X3F)*7)+440)*3)/2)+1);
18538 //#define DDR_TEST_ACLCDLR
18539
18540
18541 if (argc == 2)
18542 {
18543 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
18544 {
18545 channel_a_en = 1;
18546 }
18547 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
18548 {
18549 channel_b_en = 1;
18550 }
18551 else
18552 {
18553 goto usage;
18554 }
18555 }
18556 if (argc > 2)
18557 {
18558 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
18559 {
18560 channel_a_en = 1;
18561 }
18562 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
18563 {
18564 channel_b_en = 1;
18565 }
18566 }
18567 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
18568 if (argc >3) {
18569 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
18570 if (*argv[3] == 0 || *endp != 0)
18571 {
18572 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
18573 }
18574
18575 }
18576 if (argc >4) {
18577 test_clear = simple_strtoull_ddr(argv[4], &endp, 16);
18578 if (*argv[4] == 0 || *endp != 0)
18579 {
18580 test_clear = 0;
18581 }
18582 if ( test_clear )
18583 test_clear = 1;
18584
18585 }
18586 training_seed = 0;
18587 if (argc >5) {
18588 training_seed = simple_strtoull_ddr(argv[5], &endp, 16);
18589 if (*argv[5] == 0 || *endp != 0)
18590 {
18591 training_seed =0;// 0x2e;
18592 }
18593
18594
18595 }
18596
18597
18598
18599
18600
18601 training_step = 0;
18602 if (argc >6) {
18603 training_step = simple_strtoull_ddr(argv[6], &endp, 16);
18604 if (*argv[6] == 0 || *endp != 0)
18605 {
18606 training_step = 0;
18607 }
18608
18609 }
18610 if (!training_step)
18611 training_step=1;
18612 int vref_all=0;
18613 if (argc >7) {
18614 vref_all = simple_strtoull_ddr(argv[7], &endp, 16);
18615 if (*argv[7] == 0 || *endp != 0)
18616 {
18617 vref_all =0;// 0x2e;
18618 }}
18619 int vref_lcdlr_offset=0;
18620 if (argc >8) {
18621 vref_lcdlr_offset = simple_strtoull_ddr(argv[8], &endp, 16);
18622 if (*argv[8] == 0 || *endp != 0)
18623 {
18624 vref_lcdlr_offset =0;
18625 }}
18626 int vref_set_test_step=0;
18627 if (argc >9) {
18628 vref_set_test_step = simple_strtoull_ddr(argv[9], &endp, 16);
18629 if (*argv[9] == 0 || *endp != 0)
18630 {
18631 vref_set_test_step =0;
18632 }}
18633 int vref_dram_range=0;
18634 if (argc >10) {
18635 vref_dram_range = simple_strtoull_ddr(argv[10], &endp, 16);
18636 if (*argv[10] == 0 || *endp != 0)
18637 {
18638 vref_dram_range =0;
18639 }}
18640
18641
18642 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
18643 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
18644 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
18645 printf("\ntest_clear== 0x%08x\n", test_clear);
18646 printf("\nvref_all== 0x%08x\n", vref_all);
18647 printf("\nvref_lcdlr_offset== 0x%08x\n", vref_lcdlr_offset);
18648 printf("\nvref_dram_range== 0x%08x\n", vref_dram_range);
18649
18650 unsigned int soc_dram_hex_dec=0;
18651 if (argc >11)
18652 {
18653 soc_dram_hex_dec = simple_strtoull_ddr(argv[11], &endp, 16);
18654 if (*argv[11] == 0 || *endp != 0) {
18655 soc_dram_hex_dec = 0;
18656 }
18657 }
18658 if (soc_dram_hex_dec)
18659 {
18660 if (argc >5) {
18661 training_seed = simple_strtoull_ddr(argv[5], &endp, 0);
18662 if (*argv[5] == 0 || *endp != 0)
18663 {
18664 training_seed =0;// 0x2e;
18665 }
18666
18667
18668 }
18669
18670 }
18671 if (training_seed)
18672 {
18673 if (soc_dram_hex_dec)
18674 {
18675 if (vref_dram_range)
18676 {
18677 if (training_seed<45)
18678 training_seed=45;
18679 if (training_seed>77)
18680 training_seed=77;
18681 training_seed =(((((training_seed*1000-45000)/650)>0X32)?(0X32):(((training_seed*1000-45000)/650))));
18682 }
18683 if (vref_dram_range == 0)
18684 {
18685 if (training_seed<60)
18686 training_seed=60;
18687 if (training_seed>92)
18688 training_seed=92;
18689 training_seed =(((((training_seed*1000-60000)/650)>0X32)?(0X32):(((training_seed*1000-60000)/650))));
18690 }
18691 }
18692 if (vref_dram_range == 0)
18693 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*65)+6000)*1200)/10000));
18694 else
18695 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*65)+4500)*1200)/10000));
18696 }
18697 if ( channel_a_en)
18698 {
18699 //writel((0), 0xc8836c00);
18700 OPEN_CHANNEL_A_PHY_CLK();
18701 }
18702 if ( channel_b_en)
18703 {
18704 OPEN_CHANNEL_B_PHY_CLK();
18705 //writel((0), 0xc8836c00);
18706 }
18707
18708 char str_temp1[1024]="";
18709 char str_temp2[1024]="";
18710 char *p_str=NULL;
18711
18712
18713 char str[512]="";
18714 unsigned int dram_iovref_test_ddr_clk=0;
18715 sprintf(str_temp1,"ddr_dram_iovref_test_ddr_clk");
18716 dram_iovref_test_ddr_clk=env_to_a_num(str_temp1);
18717 if (dram_iovref_test_ddr_clk == 0)
18718 {dram_iovref_test_ddr_clk=global_ddr_clk;
18719 {
18720 sprintf(str_temp1,"ddr_dram_iovref_test_ddr_clk");
18721 sprintf(str_temp2,"0x%08x",dram_iovref_test_ddr_clk);
18722 env_set(str_temp1, str_temp2);
18723 run_command("save",0);
18724 }
18725 }
18726 if (dram_iovref_test_ddr_clk != global_ddr_clk)
18727 {
18728 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,dram_iovref_test_ddr_clk);
18729 sprintf(str,"d2pll %d",dram_iovref_test_ddr_clk);
18730 printf("\nstr=%s\n",str);
18731 run_command(str,0);
18732 while (1) ;
18733 }
18734
18735
18736 {
18737 {
18738 sprintf(str_temp1,"ddr_dram_iovref_org");
18739 // sprintf(str_temp2,"0x%08x",iovref_org);
18740 p_str=env_get(str_temp1);
18741
18742 if (p_str)
18743 {
18744 iovref_org= simple_strtoull_ddr(p_str, &endp, 0);
18745 }
18746
18747
18748 sprintf(str_temp1,"ddr_dram_iovref_lef");
18749 //sprintf(str_temp2,"0x%08x",iovref_lef);
18750 p_str=env_get(str_temp1);
18751
18752 if (p_str)
18753 {
18754 iovref_lef= simple_strtoull_ddr(p_str, &endp, 0);
18755 }
18756
18757
18758 sprintf(str_temp1,"ddr_dram_iovref_rig");
18759 //sprintf(str_temp2,"0x%08x",iovref_rig);
18760 p_str=env_get(str_temp1);
18761
18762 if (p_str)
18763 {
18764 iovref_rig= simple_strtoull_ddr(p_str, &endp, 0);
18765 }
18766
18767 sprintf(str_temp1,"ddr_dram_vref_range");
18768 //sprintf(str_temp2,"0x%08x",vref_dram_range);
18769 p_str=env_get(str_temp1);
18770
18771
18772 if (p_str)
18773 {
18774 vref_dram_range= simple_strtoull_ddr(p_str, &endp, 0);
18775 }
18776
18777 }
18778
18779 if (vref_dram_range|iovref_rig|iovref_org|iovref_lef)
18780 {
18781 printf("\n\ndram iovref test clk==%d\n",dram_iovref_test_ddr_clk);
18782 iovref_mid=(iovref_lef+iovref_rig)/2;
18783 if (vref_dram_range == 0)
18784 {
18785 printf("iovref_org==0x%08x,%08dmV||iovref_lef==0x%08x,%08dmV||iovref_rig==0x%08x,%08dmV||iovref_mid0x%08x,%08dmV\n",
18786 iovref_org,((((((iovref_org&0X3F)*65)+6000)*1200)/10000)),iovref_lef,((((((iovref_lef&0X3F)*65)+6000)*1200)/10000)),
18787 iovref_rig,((((((iovref_rig&0X3F)*65)+6000)*1200)/10000)),iovref_mid,((((((iovref_mid&0X3F)*65)+6000)*1200)/10000)));
18788 }
18789 if (vref_dram_range)
18790 {
18791 printf("iovref_org==0x%08x,%08dmV||iovref_lef==0x%08x,%08dmV||iovref_rig==0x%08x,%08dmV||iovref_mid0x%08x,%08dmV\n",
18792 iovref_org,((((((iovref_org&0X3F)*65)+4500)*1200)/10000)),iovref_lef,((((((iovref_lef&0X3F)*65)+4500)*1200)/10000)),
18793 iovref_rig,((((((iovref_rig&0X3F)*65)+4500)*1200)/10000)),iovref_mid,((((((iovref_mid&0X3F)*65)+4500)*1200)/10000)));
18794 }
18795 if (iovref_rig == 0x32)
18796 {
18797 printf("\n\n iovref rig reach reg max\n");
18798 }
18799 if (iovref_rig == 0x0)
18800 {
18801 printf("\n\n iovref lef reach reg min\n");
18802 }
18803 printf("\n\n printf dram vref from env ,if remeasure should clear ddr_dram_iovref_org env ddr_dram_iovref_lef \
18804 ddr_dram_iovref_rig ddr_dram_vref_range,ddr_dram_iovref_test_ddr_clk \n");
18805 return 1;
18806 }
18807
18808 }
18809
18810
18811 //save and print org training dqs value
18812 if (channel_a_en || channel_b_en)
18813 {
18814 //dcache_disable();
18815 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
18816 }////save and print org training value
18817
18818
18819
18820 {
18821 ////tune and save training dqs value
18822 if (channel_a_en || channel_b_en)
18823
18824 {
18825 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
18826 {
18827
18828 if (( channel_a_en) && ( channel_b_en == 0))
18829 {
18830 reg_base_adj=CHANNEL_A_REG_BASE;
18831 }
18832 else if(( channel_b_en)&&( channel_a_en==0))
18833 {
18834 reg_base_adj=CHANNEL_B_REG_BASE;
18835 }
18836 else if ((channel_a_en+channel_b_en)==2)
18837 {
18838 if ( testing_channel == CHANNEL_A)
18839 {
18840 reg_base_adj=CHANNEL_A_REG_BASE;
18841 }
18842 else if( testing_channel==CHANNEL_B)
18843 {
18844 reg_base_adj=CHANNEL_B_REG_BASE;
18845 }
18846 }
18847
18848 if (reg_base_adj == CHANNEL_A_REG_BASE)
18849 {
18850 printf("\ntest A channel data lane\n");
18851 }
18852 else
18853 {
18854 printf("\ntest B channel data lane\n");
18855 }
18856
18857
18858
18859
18860 }
18861
18862 {
18863
18864
18865#define wrr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
18866#define rdr_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
18867 unsigned int dxnmdlr=0;
18868 reg_add=DDR0_PUB_DX0MDLR0+reg_base_adj;
18869 dxnmdlr=((rdr_reg((unsigned int )reg_add))>>16)&0x1ff;
18870 // reg_seed_value=(training_seed|(0x0<<8)|(0x0<<16)|(0x0<<24));
18871 printf("\ndxnmdlr==0x%08x\n ",dxnmdlr);
18872 //turn off ddr4 phy read vref gate,only output ac lane vref
18873 wrr_reg((((DDR0_PUB_DX0GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
18874 wrr_reg((((DDR0_PUB_DX1GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
18875 wrr_reg((((DDR0_PUB_DX2GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
18876 wrr_reg((((DDR0_PUB_DX3GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
18877 wrr_reg((((DDR0_PUB_IOVCR0))),0x00090909|(0x0f<<24));
18878 wrr_reg((((DDR0_PUB_IOVCR1))),0x109);
18879 printf("\nDDR0_PUB_DX0GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4))));
18880 printf("\nDDR0_PUB_DX1GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4))));
18881 printf("\nDDR0_PUB_DX2GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4))));
18882 printf("\nDDR0_PUB_DX3GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4))));
18883 printf("\nDDR0_PUB_IOVCR0==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR0))));
18884 printf("\nDDR0_PUB_IOVCR1==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR1))));
18885 unsigned int temp_i=0;
18886 //unsigned int temp_i_max=4;//DDR0_PUB_MR6
18887 for (( temp_i=0);(temp_i<4);( temp_i++))
18888 {
18889 dxnlcdlr1[temp_i]=(rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)+temp_i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1))));
18890
18891 printf("\nreg==0x%08x,dxnlcdlr1[%08x]==0x%08x\n ",
18892 ((DDR0_PUB_DX0LCDLR1+reg_base_adj)+temp_i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)),
18893 temp_i,dxnlcdlr1[temp_i]);
18894
18895 }
18896
18897 iovref_test_read=(rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6))))&0x3f;
18898 iovref_temp_value=rdr_reg((unsigned int )(DDR0_PUB_DX0GCR6));
18899 if ((iovref_temp_value&0x3f) == 0x09)
18900 {
18901 iovref_temp_value=(rdr_reg((unsigned int )(DDR0_PUB_MR6)))&0x3f;;
18902 iovref_test_read=iovref_temp_value;
18903 }
18904 iovref_org=(rdr_reg((unsigned int )((PREG_STICKY_REG7))))&0xff;
18905
18906
18907 printf("PREG_STICKY_REG7==0x%08x\n ",(rdr_reg((unsigned int )((PREG_STICKY_REG7)))));
18908 printf("DDR0_PUB_MR6==0x%08x\n ",(rdr_reg((unsigned int )((DDR0_PUB_MR6)))));
18909 printf("DDR0_PUB_DX0GCR6==0x%08x\n ",(rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6)))));
18910 if (((iovref_org) == 0) || (test_clear))
18911 {
18912
18913
18914
18915 iovref_org=iovref_temp_value&0x3f;
18916 iovref_lef=iovref_org;
18917 iovref_rig=iovref_org;
18918 iovref_test_step=0;
18919
18920 if (training_seed)
18921 {
18922 iovref_org=training_seed&0x3f;
18923 iovref_lef=iovref_org;
18924 iovref_rig=iovref_org;
18925 iovref_test_step=0;
18926
18927 }
18928 if (vref_dram_range == 0)
18929 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*65)+6000)*1200)/10000));
18930 else
18931 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*65)+4500)*1200)/10000));
18932 wrr_reg((PREG_STICKY_REG7),iovref_org|(iovref_lef<<8)|((iovref_rig<<16))|(iovref_test_step<<24));
18933 }
18934
18935 printf("PREG_STICKY_REG7==0x%08x\n ",(rdr_reg((unsigned int )((PREG_STICKY_REG7)))));
18936 {
18937 if ((((rdr_reg((unsigned int )((DDR0_PUB_MR6))))>>6)&1) == 0)
18938 {
18939 printf("reg_add==0x%08x,value==0x%08x, iovref org ==0x%08x %08dmV\n",DDR0_PUB_MR6,
18940 iovref_temp_value,iovref_org,((((((iovref_org&0X3F)*65)+6000)*1200)/10000)));
18941 printf("reg_add==0x%08x,value==0x%08x, iovref_dx0gcr6 ==0x%08x %08dmV\n",DDR0_PUB_DX0GCR6,
18942 (rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6)))),(rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6)))),
18943 (((((((rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6))))&0X3F)*65)+6000)*1200)/10000)));
18944
18945 }
18946 if (((rdr_reg((unsigned int )((DDR0_PUB_MR6))))>>6)&1)
18947 {
18948 printf("reg_add==0x%08x,value==0x%08x, iovref org ==0x%08x %08dmV\n",DDR0_PUB_MR6,
18949 iovref_temp_value,iovref_org,((((((iovref_org&0X3F)*65)+4500)*1200)/10000)));
18950 printf("reg_add==0x%08x,value==0x%08x, iovref_dx0gcr6 ==0x%08x %08dmV\n",DDR0_PUB_DX0GCR6,
18951 (rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6)))),(rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6)))),
18952 (((((((rdr_reg((unsigned int )((DDR0_PUB_DX0GCR6))))&0X3F)*65)+4500)*1200)/10000)));
18953
18954 }
18955
18956 }
18957
18958 iovref_org=(rdr_reg((unsigned int )((PREG_STICKY_REG7))))&0x3f; //
18959 iovref_lef=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>8)&0x3f;
18960 iovref_rig=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>16)&0x3f;
18961 iovref_test_step=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>24)&0x3f;
18962
18963
18964
18965 printf("\ntraining_step==0x%08x\n ",training_step);
18966 printf("\niovref_test_step==0x%08x\n ",iovref_test_step);
18967 printf("\niovref_lef==0x%08x\n ",iovref_lef);
18968 printf("\niovref_rig==0x%08x\n ",iovref_rig);
18969 if (vref_set_test_step)
18970 {if(iovref_test_step==0)
18971 iovref_test_step=vref_set_test_step;
18972 }
18973 if (iovref_test_step<2)
18974 {
18975 if (iovref_test_step == 0)
18976 {
18977 iovref_temp_value=iovref_lef;
18978
18979 }
18980 if (iovref_test_step == 1)
18981 {
18982 iovref_temp_value=iovref_rig;
18983 }
18984 //iovref_temp_value=iovref_lef-training_step;
18985 printf("\niovref temp==0x%08x\n ",iovref_temp_value);
18986 printf("\niovref_test_read==0x%08x\n ",iovref_test_read);
18987 temp_test_error=0;
18988 if ((iovref_org == iovref_lef) && (iovref_org == iovref_rig)) {
18989 printf("\nfirst test");
18990 }
18991 else if(iovref_test_read!=iovref_temp_value)
18992 {temp_test_error=1;
18993 }
18994
18995 ddr_test_watchdog_enable(watchdog_time_s);
18996 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
18997 ddr_test_watchdog_clear();
18998 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
18999 if (vref_lcdlr_offset)
19000 {
19001 {
19002 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19003 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19004 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19005 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19006
19007
19008 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19009 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19010 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19011 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19012 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19013 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19014 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19015 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19016
19017 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19018
19019 {
19020 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19021 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19022 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19023 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19024
19025 }
19026 }
19027
19028 // /*
19029 {
19030 {
19031 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19032 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19033 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19034 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19035
19036
19037 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19038 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19039 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19040 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19041 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19042 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19043 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19044 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19045
19046 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19047 ddr_test_watchdog_clear();
19048 {
19049 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19050 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19051 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19052 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19053
19054 }
19055 }
19056
19057
19058 }
19059 //*/
19060 }
19061
19062
19063 if (temp_test_error)
19064 {
19065 printf("\nvref edge detect \n");
19066 if (iovref_test_step == 0)
19067 {
19068
19069 iovref_lef=((iovref_temp_value+training_step)<0x32)?((iovref_temp_value+training_step)):(0x32);
19070 iovref_temp_value=iovref_org;
19071 }
19072 if (iovref_test_step == 1)
19073 {
19074
19075 iovref_rig=(iovref_temp_value>training_step)?((iovref_temp_value-training_step)):(0);
19076 iovref_temp_value=iovref_org;
19077 }
19078 iovref_test_step++;
19079 // break;
19080 }
19081 else
19082 {
19083 printf("\niovref_lef1=%x\n",iovref_lef);
19084 printf("\niovref_test_step=%x\n",iovref_test_step);
19085 if (iovref_test_step == 0)
19086 {
19087 printf("\niovref_lef1_2=%x\n",(iovref_temp_value-training_step));
19088 iovref_lef=(iovref_temp_value>training_step)?((iovref_temp_value-training_step)):(0);
19089 iovref_temp_value=iovref_lef;
19090 if (iovref_lef == 0)
19091 {
19092 iovref_test_step++;
19093 iovref_temp_value=iovref_org;
19094 }
19095 }
19096 if (iovref_test_step == 1)
19097 {
19098 iovref_rig=((iovref_temp_value+training_step)<0x32)?(iovref_temp_value+training_step):(0x32);
19099 iovref_temp_value=iovref_rig;
19100 if (iovref_rig == 0x32)
19101 iovref_test_step++;
19102 }
19103 printf("\niovref_lef2=%x\n",iovref_lef);
19104 }
19105 {
19106
19107
19108 wrr_reg((PREG_STICKY_REG7),iovref_org|(iovref_lef<<8)|((iovref_rig<<16))|(iovref_test_step<<24));
19109 printf("\nddr4ram vref test will reboot use new dram vref setting==0x%08x\n ",(rdr_reg((unsigned int )(PREG_STICKY_REG7))));
19110 char str[100];
19111 sprintf(str,"ddr_test_cmd 0x17 %d 0 0 0 0x%x",dram_iovref_test_ddr_clk,iovref_temp_value|((vref_dram_range&1)<<6));
19112 printf("\nstr=%s\n",str);
19113 run_command(str,0);
19114 //run_command("ddr_test_cmd 0x17 1100 0 0 0xsoc 0xdram ",0);//
19115 }
19116 }
19117
19118 ddr_test_watchdog_disable();
19119 if (iovref_test_step >= 2)
19120 {
19121 printf("\n\ndram iovref test clk==%d\n",dram_iovref_test_ddr_clk);
19122 printf("\n\n iovref vddq=1.2v,if use other vddq ,please recount\n");
19123 printf("\nddr4ram vref test finish iovref_test_step==0x%08x\n ",iovref_test_step);
19124 iovref_org=(rdr_reg((unsigned int )((PREG_STICKY_REG7))))&0x3f; //
19125 iovref_lef=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>8)&0x3f;
19126 iovref_rig=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>16)&0x3f;
19127 iovref_test_step=((rdr_reg((unsigned int )((PREG_STICKY_REG7))))>>24)&0x3f;
19128 iovref_mid=(iovref_lef+iovref_rig)/2;
19129 if (vref_dram_range == 0)
19130 {
19131 printf("iovref_org==0x%08x,%08dmV||iovref_lef==0x%08x,%08dmV||iovref_rig==0x%08x,%08dmV||iovref_mid0x%08x,%08dmV\n",
19132 iovref_org,((((((iovref_org&0X3F)*65)+6000)*1200)/10000)),iovref_lef,((((((iovref_lef&0X3F)*65)+6000)*1200)/10000)),
19133 iovref_rig,((((((iovref_rig&0X3F)*65)+6000)*1200)/10000)),iovref_mid,((((((iovref_mid&0X3F)*65)+6000)*1200)/10000)));
19134 }
19135 if (vref_dram_range)
19136 {
19137 printf("iovref_org==0x%08x,%08dmV||iovref_lef==0x%08x,%08dmV||iovref_rig==0x%08x,%08dmV||iovref_mid0x%08x,%08dmV\n",
19138 iovref_org,((((((iovref_org&0X3F)*65)+4500)*1200)/10000)),iovref_lef,((((((iovref_lef&0X3F)*65)+4500)*1200)/10000)),
19139 iovref_rig,((((((iovref_rig&0X3F)*65)+4500)*1200)/10000)),iovref_mid,((((((iovref_mid&0X3F)*65)+4500)*1200)/10000)));
19140 }
19141 if (iovref_rig == 0x32)
19142 {
19143 printf("\n\n iovref rig reach reg max\n");
19144 }
19145 if (iovref_rig == 0x0)
19146 {
19147 printf("\n\n iovref lef reach reg min\n");
19148 }
19149 //char str2[100];
19150 //sprintf(str2,"ddr_test_cmd 0x17 %d 0 0 0 0x%x",global_ddr_clk,iovref_org);
19151 //printf("\nstr2=%s\n",str2);
19152 //run_command(str2,0);
19153 {
19154 {
19155 sprintf(str_temp1,"ddr_dram_iovref_org");
19156 sprintf(str_temp2,"0x%08x",iovref_org);
19157 env_set(str_temp1, str_temp2);
19158 run_command("save",0);
19159 }
19160 {
19161 sprintf(str_temp1,"ddr_dram_iovref_lef");
19162 sprintf(str_temp2,"0x%08x",iovref_lef);
19163 env_set(str_temp1, str_temp2);
19164 run_command("save",0);
19165 }
19166 {
19167 sprintf(str_temp1,"ddr_dram_iovref_rig");
19168 sprintf(str_temp2,"0x%08x",iovref_rig);
19169 env_set(str_temp1, str_temp2);
19170 run_command("save",0);
19171 }
19172 {
19173 sprintf(str_temp1,"ddr_dram_vref_range");
19174 sprintf(str_temp2,"0x%08x",vref_dram_range);
19175 env_set(str_temp1, str_temp2);
19176 run_command("save",0);
19177 }
19178 }
19179
19180
19181
19182
19183
19184
19185
19186
19187
19188
19189
19190
19191
19192
19193
19194
19195
19196
19197
19198 }
19199
19200
19201
19202 }
19203
19204
19205
19206
19207
19208
19209 }
19210
19211 }
19212
19213
19214
19215
19216 return 0;
19217
19218usage:
19219 cmd_usage(cmdtp);
19220#endif
19221 return 1;
19222
19223}
19224
19225#endif
19226int do_ddr4_test_dram_ac_vref(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
19227{
19228#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
19229 ///*
19230 // unsigned int start_addr=test_start_addr;
19231 printf("\nEnter Test ddr4 phy_ac or ddr3 dram data vref function\n");
19232 // if(!argc)
19233 // goto DDR_TUNE_DQS_START;
19234 printf("\nargc== 0x%08x\n", argc);
19235
19236 // unsigned int loop = 1;
19237 // unsigned int temp_count_i = 1;
19238 // unsigned int temp_count_j= 1;
19239 // unsigned int temp_count_k= 1;
19240 unsigned int temp_test_error= 0;
19241 int training_seed=0;
19242 int training_step=0;
19243
19244 char *endp;
19245 // unsigned int *p_start_addr;
19246 unsigned int test_dram_ac_data=0;
19247 // unsigned int test_times=1;
19248 unsigned int reg_add=0;
19249 unsigned int reg_base_adj=0;
19250 unsigned int channel_a_en = 0;
19251 unsigned int channel_b_en = 0;
19252 unsigned int testing_channel = 0;
19253 unsigned int dxnlcdlr1[4];
19254 // unsigned int dxnlcdlr4[4];
19255
19256
19257#define CHANNEL_A 0
19258#define CHANNEL_B 1
19259
19260#define DDR_CROSS_TALK_TEST_SIZE 0x20000
19261 // #define DDR0_PUB_REG_BASE 0xc8836000
19262#define DDR0_PUB_DX0GCR4 ( DDR0_PUB_REG_BASE + ( 0x1c4 << 2 ) )
19263#define DDR0_PUB_DX1GCR4 ( DDR0_PUB_REG_BASE + ( 0x204 << 2 ) )
19264#define DDR0_PUB_DX2GCR4 ( DDR0_PUB_REG_BASE + ( 0x244 << 2 ) )
19265#define DDR0_PUB_DX3GCR4 ( DDR0_PUB_REG_BASE + ( 0x284 << 2 ) )
19266#define DDR0_PUB_DX0GCR5 ( DDR0_PUB_REG_BASE + ( 0x1c5 << 2 ) )
19267#define DDR0_PUB_DX1GCR5 ( DDR0_PUB_REG_BASE + ( 0x205 << 2 ) )
19268#define DDR0_PUB_DX2GCR5 ( DDR0_PUB_REG_BASE + ( 0x245 << 2 ) )
19269#define DDR0_PUB_DX3GCR5 ( DDR0_PUB_REG_BASE + ( 0x285 << 2 ) )
19270
19271 //#define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 ) ) // R/W - IO VREF Control Register 0
19272 //#define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 ) ) // R/W - IO VREF Control Register 1
19273
19274
19275 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
19276
19277 // unsigned int ac_bdlr_lef[10];
19278 // unsigned int ac_bdlr_rig[10];
19279 int iovref_temp_value;
19280 // int iovref_temp_reg_value;
19281 // unsigned int reg_seed_value;
19282 // unsigned int temp_reg_value;
19283 int iovref_org;
19284 int iovref_lef;
19285 int iovref_rig;
19286 // unsigned int temp_test_error;
19287 // unsigned int temp_i=0;
19288 // unsigned int temp_j=0;
19289 //unsigned int reg_add=0;
19290 // static unsigned int training_enabled=1;
19291
19292 // iovref_lef=0x49;
19293 // printf("\n\n iovref org ==0x%08x %08dmV\n",iovref_lef,(((((iovref_lef&0X3F)*7)+440)*3)/2)+1);
19294 //#define DDR_TEST_ACLCDLR
19295
19296
19297 if (argc == 2)
19298 {
19299 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
19300 channel_a_en = 1;
19301 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
19302 channel_b_en = 1;
19303 else
19304 goto usage;
19305 }
19306 if (argc > 2)
19307 {
19308 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
19309 channel_a_en = 1;
19310 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
19311 channel_b_en = 1;
19312 }
19313 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
19314 if (argc >3) {
19315 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
19316 if (*argv[3] == 0 || *endp != 0)
19317 {
19318 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
19319 }
19320
19321 }
19322 if (argc >4) {
19323 test_dram_ac_data = simple_strtoull_ddr(argv[4], &endp, 16);
19324 if (*argv[4] == 0 || *endp != 0)
19325 {
19326 test_dram_ac_data = 0;
19327 }
19328 if ( test_dram_ac_data )
19329 test_dram_ac_data = 1;
19330
19331 }
19332 training_seed = 0;
19333 if (argc >5) {
19334 training_seed = simple_strtoull_ddr(argv[5], &endp, 16);
19335 if (*argv[5] == 0 || *endp != 0)
19336 {
19337 training_seed =0;// 0x2e;
19338 }
19339
19340
19341 }
19342
19343
19344 training_step = 0;
19345 if (argc >6) {
19346 training_step = simple_strtoull_ddr(argv[6], &endp, 16);
19347 if (*argv[6] == 0 || *endp != 0)
19348 {
19349 training_step = 0;
19350 }
19351
19352
19353
19354 }
19355 int vref_all=0;
19356 if (argc >7) {
19357 vref_all = simple_strtoull_ddr(argv[7], &endp, 16);
19358 if (*argv[7] == 0 || *endp != 0)
19359 {
19360 vref_all =0;// 0x2e;
19361 }}
19362 int vref_lcdlr_offset=0;
19363 if (argc >8) {
19364 vref_lcdlr_offset = simple_strtoull_ddr(argv[8], &endp, 16);
19365 if (*argv[8] == 0 || *endp != 0)
19366 {
19367 vref_lcdlr_offset =0;
19368 }}
19369 int soc_dram_hex_dec=0;
19370 if (argc >9)
19371 {
19372 soc_dram_hex_dec = simple_strtoull_ddr(argv[9], &endp, 16);
19373 if (*argv[9] == 0 || *endp != 0) {
19374 soc_dram_hex_dec = 0;
19375 }
19376 }
19377 if (training_seed ==0) // 0x2e;
19378 {training_seed=0x9;
19379 }
19380 if (soc_dram_hex_dec)
19381 {
19382 if (argc >5) {
19383 training_seed = simple_strtoull_ddr(argv[5], &endp, 0);
19384 if (*argv[5] == 0 || *endp != 0)
19385 {
19386 training_seed =0;// 0x2e;
19387 }
19388
19389
19390 }
19391 if (training_seed ==0) // 0x2e;
19392 {training_seed=50;
19393 }
19394 if (training_seed<45)
19395 training_seed=45;
19396 if (training_seed>88)
19397 training_seed=88;
19398 training_seed =(((training_seed*1000-44070)/698));
19399
19400 }
19401
19402
19403
19404 printf("\n\n iovref training_seed ==0x%08x %08dmV\n",training_seed,(((((training_seed&0X3F)*7)+440)*3)/2)+1);
19405 printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
19406 printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
19407 printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
19408 printf("\ntest_dram_ac_data== 0x%08x\n", test_dram_ac_data);
19409 printf("\nvref_all== 0x%08x\n", vref_all);
19410 printf("\nvref_lcdlr_offset== 0x%08x\n", vref_lcdlr_offset);
19411 if ( channel_a_en)
19412 {
19413 //writel((0), 0xc8836c00);
19414 OPEN_CHANNEL_A_PHY_CLK();
19415 }
19416 if ( channel_b_en)
19417 {
19418 OPEN_CHANNEL_B_PHY_CLK();
19419 //writel((0), 0xc8836c00);
19420 }
19421
19422 //save and print org training dqs value
19423 if (channel_a_en || channel_b_en)
19424 {
19425 //dcache_disable();
19426 //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
19427 }////save and print org training value
19428
19429
19430
19431 {
19432 ////tune and save training dqs value
19433 if (channel_a_en || channel_b_en)
19434
19435 {
19436 for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
19437 {
19438
19439 if (( channel_a_en) && ( channel_b_en == 0))
19440 {
19441 reg_base_adj=CHANNEL_A_REG_BASE;
19442 }
19443 else if(( channel_b_en)&&( channel_a_en==0))
19444 {
19445 reg_base_adj=CHANNEL_B_REG_BASE;
19446 }
19447 else if ((channel_a_en+channel_b_en)==2)
19448 {
19449 if ( testing_channel == CHANNEL_A)
19450 {
19451 reg_base_adj=CHANNEL_A_REG_BASE;
19452 }
19453 else if( testing_channel==CHANNEL_B)
19454 {
19455 reg_base_adj=CHANNEL_B_REG_BASE;
19456 }
19457 }
19458
19459 if (reg_base_adj == CHANNEL_A_REG_BASE)
19460 {
19461 printf("\ntest A channel data lane\n");
19462 }
19463 else
19464 {
19465 printf("\ntest B channel data lane\n");
19466 }
19467
19468
19469 {
19470
19471
19472#define wrr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
19473#define rdr_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
19474 unsigned int dxnmdlr=0;
19475 reg_add=DDR0_PUB_DX0MDLR0+reg_base_adj;
19476 dxnmdlr=((rdr_reg((unsigned int )reg_add))>>16)&0x1ff;
19477 // reg_seed_value=(training_seed|(0x0<<8)|(0x0<<16)|(0x0<<24));
19478 printf("\ndxnmdlr==0x%08x\n ",dxnmdlr);
19479 //turn off ddr4 phy read vref gate,only output ac lane vref
19480 wrr_reg((((DDR0_PUB_DX0GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
19481 wrr_reg((((DDR0_PUB_DX1GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
19482 wrr_reg((((DDR0_PUB_DX2GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
19483 wrr_reg((((DDR0_PUB_DX3GCR4))),((rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4)))&(~(1<<28)))|(7<<25)|(0xf<<2));
19484 printf("\norg DDR0_PUB_IOVCR0==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR0))));
19485 printf("\norg DDR0_PUB_IOVCR1==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR1))));
19486 wrr_reg((((DDR0_PUB_IOVCR0))),training_seed|(training_seed<<8)|(training_seed<<16)|(0x1f<<24));
19487 wrr_reg((((DDR0_PUB_IOVCR1))),0x109);
19488 printf("\nDDR0_PUB_DX0GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX0GCR4))));
19489 printf("\nDDR0_PUB_DX1GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX1GCR4))));
19490 printf("\nDDR0_PUB_DX2GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX2GCR4))));
19491 printf("\nDDR0_PUB_DX3GCR4==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_DX3GCR4))));
19492 printf("\nDDR0_PUB_IOVCR0==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR0))));
19493 printf("\nDDR0_PUB_IOVCR1==0x%08x\n ",(rdr_reg((unsigned int )(DDR0_PUB_IOVCR1))));
19494 unsigned int temp_i=0;
19495
19496 for (( temp_i=0);(temp_i<4);( temp_i++))
19497 {
19498 {
19499 dxnlcdlr1[temp_i]=(rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)+temp_i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1))));
19500
19501 printf("\ndxnlcdlr1[%08x]==0x%08x,dxnlcdlr1[%08x]==0x%08x\n ",temp_i,dxnlcdlr1[temp_i],temp_i,dxnlcdlr1[temp_i]);
19502
19503 }
19504 }
19505 reg_add=DDR0_PUB_IOVCR0+reg_base_adj;
19506 iovref_temp_value=rdr_reg((unsigned int )reg_add);
19507 iovref_org=((iovref_temp_value)&0xff);
19508 // iovref_lef=0x49;
19509
19510 {
19511 printf("reg_add==0x%08x,value==0x%08x, iovref org ==0x%08x %08dmV\n",reg_add,
19512 iovref_temp_value,iovref_org,((((((iovref_temp_value&0X3F)*7)+440)*3)/2)+1)*15/15);
19513 }
19514
19515
19516 wrr_reg((reg_add),iovref_temp_value); //
19517 iovref_lef=(iovref_org)&0xff;
19518 iovref_rig=(iovref_org)&0xff;
19519
19520 }
19521
19522 printf("\ntraining_step==0x%08x\n ",training_step);
19523
19524
19525 {
19526
19527
19528
19529
19530
19531
19532 {
19533
19534 iovref_temp_value=rdr_reg((unsigned int )reg_add);
19535 iovref_temp_value=((iovref_temp_value)&0xff);
19536
19537 while (iovref_temp_value>0x0)
19538 {
19539 temp_test_error=0;
19540 iovref_temp_value=iovref_temp_value-training_step;
19541 if (iovref_temp_value<training_step)
19542 iovref_temp_value=0;
19543 printf("\niovref lef temp==0x%08x\n ",iovref_temp_value);
19544
19545
19546 wrr_reg((reg_add),(0x1f000000|iovref_temp_value|(iovref_temp_value<<8)|(iovref_temp_value<<16)));
19547
19548 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,rdr_reg((unsigned int )reg_add));
19549
19550 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
19551 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
19552 if (vref_lcdlr_offset)
19553 {
19554 {
19555 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19556 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19557 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19558 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19559
19560
19561 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19562 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19563 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19564 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19565 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19566 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19567 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19568 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19569
19570 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19571
19572
19573 {
19574 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19575 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19576 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19577 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19578
19579 }
19580
19581 }
19582
19583 }
19584
19585 if (vref_lcdlr_offset)
19586 {
19587 {
19588 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19589 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19590 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19591 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19592
19593
19594 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19595 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19596 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19597 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19598 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19599 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19600 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19601 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19602
19603 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19604
19605
19606 {
19607 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19608 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19609 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19610 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19611
19612 }
19613
19614 }
19615
19616 }
19617 if (temp_test_error)
19618 {
19619 printf("\nvref down edge detect \n");
19620 iovref_temp_value=iovref_temp_value+training_step;
19621 break;
19622 }
19623 }
19624
19625 printf("\n down edge detect \n");
19626 printf("\n\n iovref down edge==0x%08x\n ",iovref_temp_value);
19627 iovref_lef=iovref_temp_value;
19628
19629 wrr_reg((reg_add),iovref_org); //
19630 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19631 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19632 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19633 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19634
19635
19636
19637 }
19638
19639 {
19640
19641 iovref_temp_value=rdr_reg((unsigned int )reg_add);
19642 iovref_temp_value=((iovref_temp_value)&0xff);
19643
19644 while (iovref_temp_value<0x3f)
19645 {
19646 temp_test_error=0;
19647 iovref_temp_value=iovref_temp_value+training_step;
19648 if (iovref_temp_value>0x3f)
19649 iovref_temp_value=0x3f;
19650 printf("\niovref rig temp==0x%08x\n ",iovref_temp_value);
19651
19652 wrr_reg((reg_add),(0x1f000000|iovref_temp_value|(iovref_temp_value<<8)|(iovref_temp_value<<16)));
19653
19654 printf("\n reg_add 0x%08x== 0x%08x\n ",reg_add,rdr_reg((unsigned int )reg_add));
19655
19656 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
19657 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
19658 if (vref_lcdlr_offset)
19659 {
19660 {
19661 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19662 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19663 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19664 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))+vref_lcdlr_offset)); //
19665
19666
19667 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19668 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19669 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19670 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19671 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19672 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19673 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19674 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19675
19676 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19677
19678
19679 {
19680 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19681 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19682 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19683 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19684
19685 }
19686
19687 }
19688
19689 }
19690
19691 if (vref_lcdlr_offset)
19692 {
19693 {
19694 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX0LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19695 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX1LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19696 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX2LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19697 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),((rdr_reg((unsigned int )(DDR0_PUB_DX3LCDLR1+reg_base_adj)))-vref_lcdlr_offset)); //
19698
19699
19700 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX0LCDLR1+reg_base_adj)),
19701 (rdr_reg((unsigned int )((DDR0_PUB_DX0LCDLR1+reg_base_adj)))));
19702 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX1LCDLR1+reg_base_adj)),
19703 (rdr_reg((unsigned int )((DDR0_PUB_DX1LCDLR1+reg_base_adj)))));
19704 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX2LCDLR1+reg_base_adj)),
19705 (rdr_reg((unsigned int )((DDR0_PUB_DX2LCDLR1+reg_base_adj)))));
19706 printf("\n reg_add 0x%08x== 0x%08x\n ",((DDR0_PUB_DX3LCDLR1+reg_base_adj)),
19707 (rdr_reg((unsigned int )((DDR0_PUB_DX3LCDLR1+reg_base_adj)))));
19708
19709 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
19710
19711
19712 {
19713 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19714 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19715 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19716 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19717
19718 }
19719
19720 }
19721
19722 }
19723 if (temp_test_error)
19724 {
19725 printf("\nvref up edge detect \n");
19726 iovref_temp_value=iovref_temp_value-training_step;
19727 break;
19728 }
19729 }
19730
19731 printf("\n up edge detect \n");
19732 printf("\n\n iovref up edge==0x%08x\n ",iovref_temp_value);
19733 iovref_rig=iovref_temp_value;
19734
19735 wrr_reg((reg_add),iovref_org); //
19736 wrr_reg((DDR0_PUB_DX0LCDLR1+reg_base_adj),dxnlcdlr1[0]); //
19737 wrr_reg((DDR0_PUB_DX1LCDLR1+reg_base_adj),dxnlcdlr1[1]); //
19738 wrr_reg((DDR0_PUB_DX2LCDLR1+reg_base_adj),dxnlcdlr1[2]); //
19739 wrr_reg((DDR0_PUB_DX3LCDLR1+reg_base_adj),dxnlcdlr1[3]); //
19740
19741
19742
19743 }
19744
19745
19746
19747 {
19748 printf("\n\n iovref vddq=1.5v,if use other vddq ,please recount\n");
19749 printf("\n vddq=1.5v iovref ac+dram_data org==0x%08x %08dmV||down edge==0x%08x %08dmV||up edge==0x%08x %08dmV||mid==0x%08x %08dmV\n",
19750 iovref_org,(((((((iovref_org&0X3F)*7)+440)*3)/2)+1)*15/15),iovref_lef,(((((((iovref_lef&0X3F)*7)+440)*3)/2)+1)*15/15),
19751 iovref_rig,(((((((iovref_rig&0X3F)*7)+440)*3)/2)+1)*15/15),((iovref_lef+iovref_rig)/2),
19752 (((((((((iovref_lef+iovref_rig)/2)&0X3F)*7)+440)*3)/2)+1)*15/15)
19753 );
19754
19755 if (iovref_lef == 0x0)
19756 {
19757 printf("\n\n iovref down edge reach reg limited\n");
19758 }
19759 if (iovref_rig == 0x3f)
19760 {
19761 printf("\n\n iovref up edge reach reg limited\n");
19762 }
19763 }
19764
19765
19766
19767
19768
19769
19770
19771
19772
19773
19774
19775
19776
19777
19778 }
19779
19780
19781
19782 }
19783
19784
19785
19786
19787
19788
19789 }
19790
19791 }
19792
19793
19794
19795
19796 return 0;
19797
19798usage:
19799 cmd_usage(cmdtp);
19800 //*/
19801#endif
19802 return 1;
19803
19804}
19805//
19806
19807int pll_convert_to_ddr_clk_g12a(unsigned int ddr_pll)
19808{
19809 unsigned int ddr_clk=0;
19810 unsigned int od_div=0xfff;
19811 ddr_pll=ddr_pll&0xfffff;
19812#if 1// (CONFIG_DDR_PHY == P_DDR_PHY_905X)
19813 //unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1)); //od1 od
19814 if (((ddr_pll>>16)&7) == 0)
19815 od_div=2;
19816 if (((ddr_pll>>16)&7) == 1)
19817 od_div=3;
19818
19819 if (((ddr_pll>>16)&7) == 2)
19820 od_div=4;
19821
19822 if (((ddr_pll>>16)&7) == 3)
19823 od_div=6;
19824
19825 if (((ddr_pll>>16)&7) == 4)
19826 od_div=8;
19827
19828 if (((ddr_pll>>10)&0x1f))
19829 ddr_clk = 2*((((24 * ((ddr_pll>>0)&0x1ff))/((ddr_pll>>10)&0x1f))>>((((ddr_pll>>19)&0x1)==1)?(2):(1))))/od_div;
19830
19831#else
19832 ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
19833
19834#endif
19835
19836
19837 return ddr_clk;
19838}
19839
19840
19841int ddr_clk_convert_to_pll_g12a(unsigned int ddr_clk, unsigned char pll_bypass_en)
19842{
19843 uint32_t ddr_pll_vco_ctrl=0;
19844 uint32_t ddr_pll_vco_m=0;
19845 uint32_t ddr_pll_vco_n=0;
19846 uint32_t ddr_pll_vco_ctrl_od=0;
19847 uint32_t ddr_pll_vco_ctrl_od1=0;
19848 ddr_pll_vco_n=1;
19849 if (pll_bypass_en == 0) {
19850 if ((ddr_clk >=4800/4)) {
19851 //datarate==vco should 3-4.8g
19852 ddr_pll_vco_ctrl_od=1;
19853 ddr_pll_vco_ctrl_od1=0x2; //0
19854 ddr_pll_vco_m=(ddr_clk*3)/24; //6
19855 }
19856 else if ((ddr_clk >4800/6)) {
19857 ddr_pll_vco_ctrl_od=2;
19858 ddr_pll_vco_ctrl_od1=0x2; //0
19859 ddr_pll_vco_m=(ddr_clk*4)/24; //8
19860 }
19861 else if ((ddr_clk > 4800/8)) {
19862 ddr_pll_vco_ctrl_od=3;
19863 ddr_pll_vco_ctrl_od1=0x2; //0
19864 ddr_pll_vco_m=(ddr_clk*6)/24; //12
19865 }
19866 else if ((ddr_clk > 4800/12)) {
19867 ddr_pll_vco_ctrl_od=4;
19868 ddr_pll_vco_ctrl_od1=0x2; //0
19869 ddr_pll_vco_m=(ddr_clk*8)/24; //16
19870 }
19871 else if ((ddr_clk > 360)) {
19872 ddr_pll_vco_ctrl_od=3;
19873 ddr_pll_vco_ctrl_od1=0x3; //0
19874 ddr_pll_vco_m=(ddr_clk*12)/24;
19875 }
19876 else {
19877 //32 should >200M
19878 ddr_pll_vco_ctrl_od=4;
19879 ddr_pll_vco_ctrl_od1=0x3;//0
19880 ddr_pll_vco_m=(ddr_clk*16)/24;
19881 }
19882 }
19883 if (pll_bypass_en == 1) {
19884 ddr_pll_vco_ctrl_od1=0x3;//0
19885 if ((ddr_clk >=800)) {
19886 //datarate==vco should 2.4-4.8g
19887 ddr_pll_vco_ctrl_od=0;
19888 ddr_pll_vco_m=(ddr_clk*4)/24;
19889 }
19890 else if ((ddr_clk < 4800/6)) {
19891 ddr_pll_vco_ctrl_od=1;
19892 ddr_pll_vco_m=(ddr_clk*2*3)/24;
19893 }
19894 else if ((ddr_clk < 4800/8)) {
19895 ddr_pll_vco_ctrl_od=2;
19896 ddr_pll_vco_m=(ddr_clk*2*4)/24;
19897 }
19898 else if ((ddr_clk < 4800/12)) {
19899 ddr_pll_vco_ctrl_od=3;
19900 ddr_pll_vco_m=(ddr_clk*2*6)/24;
19901 }
19902 else if ((ddr_clk < 4800/16)) {
19903 ddr_pll_vco_ctrl_od=4;
19904 ddr_pll_vco_m=(ddr_clk*2*8)/24;
19905 }
19906 }
19907 ddr_pll_vco_ctrl=ddr_pll_vco_m|(ddr_pll_vco_n<<10)|(ddr_pll_vco_ctrl_od<<16)|(ddr_pll_vco_ctrl_od1<<19);
19908 return ddr_pll_vco_ctrl;
19909
19910 //return ddr_pll_vco_ctrl;
19911}
19912int pll_convert_to_ddr_clk(unsigned int ddr_pll)
19913{
19914 unsigned int ddr_clk=0;
19915 ddr_pll=ddr_pll&0xfffff;
19916
19917#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
19918 // printf("\ng12 ddr_pll== %08x \n", ddr_pll);
19919 ddr_clk=pll_convert_to_ddr_clk_g12a( ddr_pll);
19920 return ddr_clk;
19921#endif
19922#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
19923 //unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1));
19924 if (((ddr_pll>>16)&0x1f))
19925
19926 ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))>>((((ddr_pll>>2)&0x3)==3)?(2):(((ddr_pll>>2)&0x3))));
19927
19928#else
19929 if ((ddr_pll>>9)&0x1f)
19930 ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
19931
19932#endif
19933
19934#if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
19935 if ((ddr_pll>>9)&0x1f)
19936 ddr_clk = 2*((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3);
19937#endif
19938
19939 return ddr_clk;
19940}
19941
19942int ddr_clk_convert_to_pll(unsigned int ddr_clk)
19943{
19944 unsigned int ddr_pll=0x10221;
19945
19946#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
19947 ddr_pll=ddr_clk_convert_to_pll_g12a( ddr_clk,0);
19948 return ddr_pll;
19949#endif
19950
19951 /* set ddr pll reg */
19952 if ((ddr_clk >= 40) && (ddr_clk < 750)) {
19953 // OD N M
19954 ddr_pll= (2 << 16) | (1 << 9) | ((((ddr_clk/6)*6)/12) << 0);
19955 }
19956 else if((ddr_clk >= 750) && (ddr_clk < 2000)) {
19957 // OD N M
19958 ddr_pll= (1 << 16) | (1 << 9) | ((((ddr_clk/12)*12)/24) << 0);
19959 }
19960
19961#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
19962 ddr_pll=0x00104c5;
19963 /* set ddr pll reg */
19964 /*
19965 if ((ddr_clk >= 40) && (ddr_clk < 750)) {
19966 // OD N M
19967 ddr_pll= (2 << 2) | (1 << 16) | ((((ddr_clk/6)*6)/12) << 4);
19968 }
19969 else if((ddr_clk >= 750) && (ddr_clk < 2000)) {
19970 // OD N M
19971 ddr_pll= (1 << 2) | (1 << 16) | ((((ddr_clk/12)*12)/24) << 4);
19972 }
19973 */
19974 if ((ddr_clk < 200)) {
19975 // OD1 OD N M
19976 ddr_pll= (2 << 0) | (3 << 2) | (1 << 16) | ((((ddr_clk*6)/6)/3) << 4);
19977 }
19978 else if ((ddr_clk>= 200) && (ddr_clk< 400)) {
19979 // OD1 OD N M
19980 ddr_pll= (2 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*6)/6)/6) << 4);
19981 }
19982 else if ((ddr_clk>= 400) && (ddr_clk < 800)) {
19983 // OD1 OD N M
19984 ddr_pll= (1 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*12)/12)/12) << 4);
19985 }
19986 else if ((ddr_clk >= 800) && (ddr_clk < 2000)) {
19987 // OD1 OD N M
19988 ddr_pll= (0 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*12)/12)/24) << 4);
19989 }
19990#endif
19991
19992#if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
19993 {
19994
19995
19996 if ((ddr_clk < 750)) {
19997 // OD N M
19998 ddr_pll= (2 << 16) | (1 << 9) | (((ddr_clk/24)*2)<< 0) ;
19999 }
20000 else if ((ddr_clk >= 750)) {
20001 // OD N M
20002 ddr_pll= (1 << 16) | (1 << 9) | ((ddr_clk/24)<< 0) ;
20003 }
20004
20005 }
20006#endif
20007
20008 return ddr_pll;
20009}
20010
20011
20012int do_ddr4_test_dram_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
20013{
20014 ///*
20015 int i=0;
20016 printf("\nargc== 0x%08x\n", argc);
20017 for (i = 0;i<argc;i++)
20018 {
20019 printf("\nargv[%d]=%s\n",i,argv[i]);
20020 }
20021 char *endp;
20022
20023#define TEST_DRAM_CLK_USE_ENV 1
20024 printf("\ntune ddr CLK use uboot env\n");
20025
20026#define DDR_CROSS_TALK_TEST_SIZE 0x20000
20027#define DDR_TEST_MIN_FREQ_LIMITED 50
20028#define DDR_TEST_MIN_FREQ 300
20029#define DDR_TEST_MAX_FREQ 3000
20030
20031 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
20032 unsigned int start_freq=DDR_TEST_MIN_FREQ;
20033 unsigned int end_freq=DDR_TEST_MAX_FREQ;
20034 unsigned int test_loops=1;
20035 //printf("\n111tune ddr CLK use uboot env\n");
20036 if (argc == 1)
20037 {
20038 printf("\nplease read help\n");
20039 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
20040 start_freq=DDR_TEST_MIN_FREQ;
20041 end_freq=DDR_TEST_MAX_FREQ;
20042
20043 }
20044
20045 if (argc == 2)
20046 {
20047 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
20048 start_freq=DDR_TEST_MIN_FREQ;
20049 end_freq=DDR_TEST_MAX_FREQ;
20050 }
20051 if (argc== 3)
20052 {
20053 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
20054 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
20055 end_freq=DDR_TEST_MAX_FREQ;
20056
20057 }
20058 if (argc== 4)
20059 {
20060 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
20061 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
20062 end_freq=simple_strtoull_ddr(argv[3], &endp, 0);
20063
20064 }
20065 if (argc> 4)
20066 {
20067 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
20068 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
20069 end_freq=simple_strtoull_ddr(argv[3], &endp, 0);
20070 test_loops=simple_strtoull_ddr(argv[4], &endp, 0);
20071 }
20072 unsigned int temp_test_error=0x0;
20073 unsigned int ddr_pll=0;
20074 unsigned int ddr_clk_org=0;
20075 unsigned int ddr_clk_hope_test=0;
20076#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
20077
20078 //#define AM_DDR_PLL_CNTL0 ( MMC_REG_BASE + ( 0x0 << 2 ) )
20079 ddr_pll = rd_reg(G12_AM_DDR_PLL_CNTL0);
20080#else
20081 ddr_pll = rd_reg(AM_DDR_PLL_CNTL);
20082#endif
20083 //ddr_pll=ddr_pll_org;
20084 printf("\nddr_pll== %08x\n", ddr_pll);
20085#if 0
20086#else
20087 unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
20088 ddr_clk_org=ddr_clk;
20089 printf("\nddr_clk== %dMHz\n", ddr_clk);
20090 printf("\nstart_freq== %dMHz\n", start_freq);
20091 printf("\nend_freq== %dMHz\n", end_freq);
20092 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20093#endif
20094
20095 // {
20096 // wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20097 // ddr_udelay(2000);
20098 //}
20099
20100
20101 unsigned int freq_table_test_value[(DDR_TEST_MAX_FREQ)/12]; // step =0 init ,1 test fail, ,2 test pass,3 test skip;
20102 // char char_freq_name_table[30];
20103 // const char *p_char_freq_table;
20104
20105 const char *p_char_ddr_test_step;
20106 const char * p_char_freq_org;
20107 char char_freq_org[30];
20108 int ddr_feq_test_step=0; // step =0 init ,1 going ,2 done;
20109
20110 const char * p_char_freq_name_table;
20111 char char_freq_name_table[30];
20112 char char_cmd_table[100];
20113 char * p_char_store_boot;
20114 // char char_freq_store_boot[200];
20115
20116 //const char *p_freq_table_int;
20117 //char char_ddr_feq_test_step[]="ddr_feq_test_step";
20118 // const char *varname;
20119 // const char *varvalue;
20120 unsigned int temp_count=0;
20121 unsigned int temp_count_sub=0;
20122
20123
20124 //
20125 p_char_ddr_test_step= env_get("ddr_feq_test_step");
20126 if (p_char_ddr_test_step)
20127 {
20128 printf("%s",p_char_ddr_test_step);
20129
20130 ddr_feq_test_step = simple_strtoull_ddr(p_char_ddr_test_step, &endp, 0);
20131 printf("ddr_feq_test_step=%d\n",ddr_feq_test_step);
20132 }
20133 if (ddr_feq_test_step) {
20134 p_char_freq_org= env_get("ddr_feq_org");
20135 if (p_char_freq_org)
20136 {
20137 printf("%s",p_char_freq_org);
20138
20139 ddr_clk_org = simple_strtoull_ddr(p_char_freq_org, &endp, 10); //must use 10 ,freq 0792 maybe not read successful use 0 auto read
20140 printf("ddr_clk_org=%d\n",ddr_clk_org);
20141 }
20142 }
20143 if (ddr_feq_test_step == 0)
20144 {
20145 ddr_feq_test_step=1;
20146 ddr_clk_org=ddr_clk;
20147 sprintf(char_freq_org,"%04d",ddr_clk);
20148 printf("\nddr_org_freq=%s\n",char_freq_org);
20149 env_set("ddr_feq_org", char_freq_org);
20150
20151 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20152 while (temp_count<(DDR_TEST_MAX_FREQ/12)) {
20153
20154 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
20155 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20156 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20157 env_set(char_freq_name_table, "0");
20158 env_set("ddr_feq_test_step", "1");
20159 temp_count++;
20160 }
20161 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20162 while (temp_count<((start_freq)/12)) {
20163
20164 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
20165 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20166 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20167 env_set(char_freq_name_table, "3");
20168 env_set("ddr_feq_test_step", "1");
20169 temp_count++;
20170 }
20171 while (temp_count>((end_freq)/12)) {
20172
20173 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
20174 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20175 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20176 env_set(char_freq_name_table, "3");
20177 env_set("ddr_feq_test_step", "1");
20178 temp_count++;
20179 }
20180
20181 p_char_store_boot= env_get("storeboot");
20182 if (p_char_store_boot)
20183 printf("storeboot %s\n",p_char_store_boot);
20184 sprintf(char_cmd_table,"ddr_test_cmd 0x1c 0x%08x %d %d %d;%s;",ddr_test_size,start_freq,end_freq,test_loops,p_char_store_boot);
20185 env_set("storeboot", char_cmd_table);
20186
20187 run_command("save",0);
20188
20189 }
20190
20191 if (ddr_feq_test_step == 1)
20192 {
20193
20194 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20195 while (temp_count<((DDR_TEST_MAX_FREQ)/12)) {
20196
20197 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20198 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20199
20200 p_char_freq_name_table= env_get(char_freq_name_table);
20201 if (p_char_freq_name_table)
20202 {
20203 printf("%s\n",p_char_freq_name_table);
20204
20205 freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
20206 printf("%s | %d\n",char_freq_name_table,freq_table_test_value[temp_count]);
20207 }
20208 temp_count++;
20209 }
20210
20211 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20212 while (temp_count<((DDR_TEST_MAX_FREQ)/12)) {
20213 ddr_clk_hope_test=(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12)));
20214 if (freq_table_test_value[temp_count] ==1)
20215 {
20216 temp_count_sub=temp_count+1;
20217 while ((pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*12))) ==
20218 (pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))))
20219 {temp_count_sub=temp_count_sub+1;
20220 }
20221 while (temp_count_sub<((DDR_TEST_MAX_FREQ)/12)) {
20222 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*12))));
20223 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20224 // freq_table_test_value[temp_count_sub] =1;
20225 env_set(char_freq_name_table, "3");
20226 temp_count_sub++;
20227 }
20228 {
20229 ddr_feq_test_step++;
20230 env_set("ddr_feq_test_step", "2");
20231 run_command("save",0);
20232
20233 }
20234 {ddr_clk_hope_test=ddr_clk_org;
20235 }
20236 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
20237 printf("\nchar_cmd_table=%s\n",char_cmd_table);
20238 run_command(char_cmd_table,0);
20239
20240 }
20241 if (freq_table_test_value[temp_count] ==0)
20242 {
20243 if ((ddr_clk_hope_test) != (ddr_clk))
20244 {
20245 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
20246 printf("\nchar_cmd_table=%s\n",char_cmd_table);
20247 run_command(char_cmd_table,0);
20248 }
20249 if ((ddr_clk_hope_test) == (ddr_clk))
20250 {
20251
20252 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20253 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20254 freq_table_test_value[temp_count] =1;
20255 env_set(char_freq_name_table, "1");
20256 run_command("save",0);
20257
20258 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20259 while (test_loops--) {
20260 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
20261 }
20262 //temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20263
20264 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20265 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20266 if (temp_test_error)
20267 {
20268 freq_table_test_value[temp_count] =1;
20269 env_set(char_freq_name_table, "1");
20270 }
20271 else
20272 {
20273 freq_table_test_value[temp_count] =2;
20274 env_set(char_freq_name_table, "2");
20275 }
20276 run_command("save",0);
20277
20278 ddr_clk_hope_test=(temp_count*12)+12;
20279 while ((pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(ddr_clk_hope_test))) ==
20280 (pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))))
20281 {ddr_clk_hope_test=ddr_clk_hope_test+12;
20282 }
20283 if (temp_test_error)
20284 {ddr_clk_hope_test=ddr_clk_org;
20285 }
20286 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
20287 printf("\nchar_cmd_table=%s\n",char_cmd_table);
20288 run_command(char_cmd_table,0);
20289 }
20290
20291 }
20292 temp_count++;
20293 }
20294 ddr_feq_test_step++;
20295 env_set("ddr_feq_test_step", "2");
20296 run_command("save",0);
20297
20298 }
20299
20300 if (ddr_feq_test_step >= 2)
20301 {
20302 printf("\nfinish test ddr_feq_test_step=%d\n",ddr_feq_test_step);
20303 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20304 while (temp_count<((DDR_TEST_MAX_FREQ)/12)) {
20305
20306 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20307 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
20308
20309 p_char_freq_name_table= env_get(char_freq_name_table);
20310 if (p_char_freq_name_table)
20311 {
20312 printf("%s\n",p_char_freq_name_table);
20313
20314 freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
20315 printf("%s | %d\n",char_freq_name_table,freq_table_test_value[temp_count]);
20316 }
20317 temp_count++;
20318 }
20319
20320 printf("\nprint test ddr_feq_test_result!!!\n");
20321 temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
20322 while (temp_count<((DDR_TEST_MAX_FREQ)/12)) {
20323
20324 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
20325 p_char_freq_name_table= env_get(char_freq_name_table);
20326 if (p_char_freq_name_table)
20327 {
20328 // printf("%s\n",p_char_freq_name_table);
20329
20330 freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
20331 //printf("%d\n",freq_table_test_value[temp_count]);
20332 if ( (freq_table_test_value[temp_count]) == 0) {
20333 printf("%04d no init %d \n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))),freq_table_test_value[temp_count]);
20334 }
20335 if ( (freq_table_test_value[temp_count]) == 1) {
20336 printf("%04d fail %d\n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))),freq_table_test_value[temp_count]);
20337 }
20338 if ( (freq_table_test_value[temp_count]) == 2) {
20339 printf("%04d pass %d\n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))),freq_table_test_value[temp_count]);
20340 }
20341 if ( (freq_table_test_value[temp_count]) >= 3) {
20342 printf("%04d skip test %d \n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))),freq_table_test_value[temp_count]);
20343 }
20344 temp_count++;
20345 }
20346 }
20347
20348 }
20349 //sprintf(str,"ddr_test_ac_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
20350 // printf("\nstr=%s\n",str);
20351
20352
20353
20354
20355 //sprintf(str, "%lx", value);
20356 // env_set("env_ddrtest", str);
20357
20358
20359 //run_command("save",0);
20360
20361 //*/
20362 return 1;
20363
20364}
20365int update_ddr_zq(unsigned int zq0pr)
20366{
20367 wr_reg( DDR0_PUB_ZQ0PR,zq0pr);
20368 wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)|(1<<27));
20369 wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))&(~((1<<2)|(1<<27))));
20370 printf("\nupdate zq zq0pr=0x%08x,zq0dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ0PR),rd_reg(DDR0_PUB_ZQ0DR));
20371 return rd_reg(DDR0_PUB_ZQ0PR);
20372}
20373
20374int do_ddr_test_ddr_max_freq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
20375{
20376 printf("\nEnter Test ddr max frequency function\n");
20377 // if(!argc)
20378 // goto DDR_TUNE_DQS_START;
20379 printf("\nargc== 0x%08x\n", argc);
20380
20381 //writel((0), 0xc8836c00);
20382 OPEN_CHANNEL_A_PHY_CLK();
20383 OPEN_CHANNEL_B_PHY_CLK();
20384 //writel((0), 0xc8836c00);
20385
20386 char *endp;
20387 // unsigned int *p_start_addr;
20388 unsigned int test_loop=1;
20389 unsigned int test_times=1;
20390 unsigned int add_freq=1;
20391 unsigned int sub_freq=1;
20392 unsigned int max_freq=792;
20393 unsigned int min_freq=792;
20394 unsigned int loop_max_freq=792;
20395 unsigned int loop_min_freq=792;
20396
20397 unsigned int ddr_pll=0x10221;
20398 unsigned int ddr_clk_org=792;
20399 unsigned int ddr_pll_org = rd_reg(AM_DDR_PLL_CNTL);
20400 ddr_pll=ddr_pll_org;
20401 unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
20402 ddr_clk_org=ddr_clk;
20403 printf("\nddr_clk_org== %dMHz\n", ddr_clk_org);
20404
20405 unsigned int zq0pr = rd_reg(DDR0_PUB_ZQ0PR);
20406 printf("\nddr_zq0pr== 0x%08x\n", zq0pr);
20407
20408 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20409
20410 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20411 ddr_udelay(2000);
20412
20413 max_freq=ddr_clk_org;
20414 min_freq=ddr_clk_org;
20415
20416#define DDR_CROSS_TALK_TEST_SIZE 0x20000
20417
20418 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
20419 if (argc == 1)
20420 {
20421 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
20422 test_loop=1;
20423 add_freq=1;
20424 sub_freq=1;
20425 }
20426
20427 if (argc == 2)
20428 {
20429 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20430 test_loop=1;
20431 add_freq=1;
20432 sub_freq=1;
20433 }
20434 if (argc== 3)
20435 {
20436 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20437 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
20438 add_freq=1;
20439 sub_freq=1;
20440 }
20441 if (argc >= 4)
20442 {
20443 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20444 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
20445 add_freq=1;
20446 sub_freq=1;
20447 if ((simple_strtoull_ddr(argv[3], &endp, 16)) == 1)
20448 {
20449 add_freq=1;
20450 sub_freq=0;
20451 }
20452 else if((simple_strtoull_ddr(argv[3], &endp, 16))==0)
20453 {
20454 add_freq=0;
20455 sub_freq=1;
20456 }
20457 }
20458
20459 unsigned int temp_test_error=0;
20460 while (test_times<(test_loop+1))
20461 {
20462 printf("\ntest_times== %d times\n", test_times);
20463
20464 if (add_freq)
20465 {
20466
20467 while (ddr_clk<1500)
20468 {
20469 temp_test_error=0;
20470 ddr_clk=ddr_clk+12;
20471 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20472 {
20473
20474 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20475 ddr_udelay(2000);
20476 printf("\ntesting_ddr_clk== %dMHz\n", ddr_clk);
20477 }
20478
20479 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20480 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20481 if (temp_test_error)
20482 {
20483 max_freq=ddr_clk-12;
20484 printf("\nmax_ddr_clk== %dMHz\n", max_freq);
20485 temp_test_error=0;
20486 break;
20487 }
20488
20489 }
20490
20491 while (ddr_clk>ddr_clk_org)
20492 {
20493 ddr_clk=ddr_clk-12;
20494 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20495 {
20496
20497 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20498 ddr_udelay(2000);
20499 }
20500 }
20501 printf("\nback to org_ddr_clk== %dMHz\n", ddr_clk);
20502
20503
20504 }
20505
20506 if (sub_freq)
20507 {
20508
20509 while (ddr_clk>24)
20510 {
20511 temp_test_error=0;
20512 ddr_clk=ddr_clk-12;
20513 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20514 {
20515
20516 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20517 ddr_udelay(2000);
20518 printf("\ntesting_ddr_clk== %dMHz\n", ddr_clk);
20519 }
20520
20521 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20522 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20523 if (temp_test_error)
20524 {
20525 min_freq=ddr_clk+12;
20526 printf("\nmin_ddr_clk== %dMHz\n", min_freq);
20527 temp_test_error=0;
20528 break;
20529 }
20530
20531 }
20532
20533 while (ddr_clk<ddr_clk_org)
20534 {
20535 ddr_clk=ddr_clk+12;
20536 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20537 {
20538
20539 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20540 ddr_udelay(2000);
20541 }
20542 }
20543 printf("\nback to org_ddr_clk== %dMHz\n", ddr_clk);
20544
20545
20546 }
20547
20548 if (test_times == 1)
20549 {
20550
20551 loop_max_freq=max_freq;
20552 loop_min_freq=min_freq;
20553 }
20554 else
20555 {
20556 if (loop_max_freq>max_freq)
20557 {
20558 loop_max_freq=max_freq;
20559 }
20560 if (min_freq>loop_min_freq)
20561 {
20562 loop_min_freq=min_freq;
20563 }
20564 }
20565 test_times++;
20566
20567 }
20568
20569 printf("\nloop_min_freq== %dMHz,pll==0x%08x\n", loop_min_freq,ddr_clk_convert_to_pll(loop_min_freq));
20570 printf("\nloop_max_freq== %dMHz,pll==0x%08x\n", loop_max_freq,ddr_clk_convert_to_pll(loop_max_freq));
20571
20572 return loop_max_freq;
20573}
20574
20575
20576int do_ddr_test_ddr_zq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
20577{
20578 printf("\nEnter Test ddr zq function\n");
20579 // if(!argc)
20580 // goto DDR_TUNE_DQS_START;
20581 printf("\nargc== 0x%08x\n", argc);
20582 //writel((0), 0xc8836c00);
20583 OPEN_CHANNEL_A_PHY_CLK();
20584 OPEN_CHANNEL_B_PHY_CLK();
20585 //writel((0), 0xc8836c00);
20586
20587 char *endp;
20588 // unsigned int *p_start_addr;
20589 unsigned int test_loop=1;
20590 unsigned int test_times=1;
20591 unsigned int add_freq=1;
20592 unsigned int sub_freq=1;
20593 unsigned int max_freq=792;
20594 unsigned int min_freq=792;
20595 unsigned int loop_max_freq=792;
20596 unsigned int loop_min_freq=792;
20597
20598 unsigned int ddr_pll=0x10221;
20599 unsigned int ddr_clk_org=792;
20600 unsigned int ddr_pll_org = rd_reg(AM_DDR_PLL_CNTL);
20601 ddr_pll=ddr_pll_org;
20602 unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
20603 ddr_clk_org=ddr_clk;
20604 printf("\nddr_clk_org== %dMHz\n", ddr_clk_org);
20605
20606 unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
20607 // unsigned int zq0pr_best;
20608 unsigned int zq0pr= rd_reg(DDR0_PUB_ZQ0PR);
20609 // zq0pr_best=zq0pr_org;
20610 unsigned int zq0pr_drv_max;
20611 unsigned int zq0pr_drv_min;
20612 unsigned int zq0pr_odt_max;
20613 unsigned int zq0pr_odt_min;
20614 unsigned int zq0pr_drv_flag=1;
20615 unsigned int zq0pr_odt_flag=1;
20616
20617
20618 printf("\nzq0pr_org== 0x%08x\n", zq0pr_org);
20619
20620 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20621
20622
20623 {
20624
20625 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20626 ddr_udelay(2000);
20627 }
20628
20629
20630
20631
20632
20633
20634 max_freq=ddr_clk_org;
20635 min_freq=ddr_clk_org;
20636
20637
20638
20639
20640
20641#define DDR_CROSS_TALK_TEST_SIZE 0x20000
20642 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
20643
20644
20645
20646
20647 if (argc == 1)
20648 {
20649 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
20650 test_loop=1;
20651 add_freq=1;
20652 sub_freq=1;
20653 }
20654
20655 if (argc == 2)
20656 {
20657 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20658 test_loop=1;
20659 add_freq=1;
20660 sub_freq=1;
20661 }
20662 if (argc== 3)
20663 {
20664 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20665 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
20666 add_freq=1;
20667 sub_freq=1;
20668 }
20669 if (argc >= 4)
20670 {
20671 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
20672 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
20673 add_freq=1;
20674 sub_freq=1;
20675 if ((simple_strtoull_ddr(argv[3], &endp, 16)) == 1)
20676 {
20677 add_freq=1;
20678 sub_freq=0;
20679 }
20680 else if((simple_strtoull_ddr(argv[3], &endp, 16))==0)
20681 {
20682 add_freq=0;
20683 sub_freq=1;
20684 }
20685 }
20686
20687 if (argc>4)
20688 {
20689 if ((simple_strtoull_ddr(argv[4], &endp, 16)) == 1)
20690 {
20691 zq0pr_drv_flag=0;
20692 zq0pr_odt_flag=1;
20693 }
20694 else if((simple_strtoull_ddr(argv[4], &endp, 16))==0)
20695 {
20696 zq0pr_drv_flag=1;
20697 zq0pr_odt_flag=0;
20698 }
20699
20700 }
20701
20702
20703 unsigned int temp_test_error=0;
20704
20705
20706 test_times=1;
20707 temp_test_error=0;
20708 while (test_times<(test_loop+1))
20709 {
20710 printf("\ntest_times== %d times\n", test_times);
20711
20712 if (add_freq)
20713 {
20714
20715 while (ddr_clk<1500)
20716 {
20717 temp_test_error=0;
20718 ddr_clk=ddr_clk+12;
20719 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20720 {
20721
20722 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20723 ddr_udelay(2000);
20724 printf("\ntesting_ddr_clk== %dMHz\n", ddr_clk);
20725 }
20726
20727 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20728 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20729 if (temp_test_error)
20730 {
20731 max_freq=ddr_clk-12;
20732 printf("\nmax_ddr_clk== %dMHz\n", max_freq);
20733 temp_test_error=0;
20734 break;
20735 }
20736
20737 }
20738
20739 while (ddr_clk>ddr_clk_org)
20740 {
20741 ddr_clk=ddr_clk-12;
20742 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20743 {
20744
20745 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20746 ddr_udelay(2000);
20747 }
20748 }
20749 printf("\nback to org_ddr_clk== %dMHz\n", ddr_clk);
20750
20751
20752 }
20753
20754 if (sub_freq)
20755 {
20756
20757 while (ddr_clk>24)
20758 {
20759 temp_test_error=0;
20760 ddr_clk=ddr_clk-12;
20761 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20762 {
20763
20764 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20765 ddr_udelay(2000);
20766 printf("\ntesting_ddr_clk== %dMHz\n", ddr_clk);
20767 }
20768
20769 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20770 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20771 if (temp_test_error)
20772 {
20773 min_freq=ddr_clk+12;
20774 printf("\nmin_ddr_clk== %dMHz\n", min_freq);
20775 temp_test_error=0;
20776 break;
20777 }
20778
20779 }
20780
20781 while (ddr_clk<ddr_clk_org)
20782 {
20783 ddr_clk=ddr_clk+12;
20784 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20785 {
20786
20787 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20788 ddr_udelay(2000);
20789 }
20790 }
20791 printf("\nback to org_ddr_clk== %dMHz\n", ddr_clk);
20792
20793
20794 }
20795
20796 if (test_times == 1)
20797 {
20798
20799 loop_max_freq=max_freq;
20800 loop_min_freq=min_freq;
20801 }
20802 else
20803 {
20804 if (loop_max_freq>max_freq)
20805 {
20806 loop_max_freq=max_freq;
20807 }
20808 if (min_freq>loop_min_freq)
20809 {
20810 loop_min_freq=min_freq;
20811 }
20812 }
20813 test_times++;
20814
20815 }
20816
20817 printf("\nloop_min_freq== %dMHz,pll==0x%08x\n", loop_min_freq,ddr_clk_convert_to_pll(loop_min_freq));
20818 printf("\nloop_max_freq== %dMHz,pll==0x%08x\n", loop_max_freq,ddr_clk_convert_to_pll(loop_max_freq));
20819
20820
20821 while (ddr_clk
20822 <loop_max_freq)
20823 {
20824 ddr_clk=ddr_clk+12;
20825 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
20826 {
20827
20828 wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
20829 ddr_udelay(2000);
20830 }
20831 }
20832 printf("\nset to loop_max_freq== %dMHz\n", loop_max_freq);
20833
20834 update_ddr_zq(zq0pr);
20835
20836 zq0pr_drv_max=(zq0pr&0xf);
20837 zq0pr_drv_min=(zq0pr&0xf);
20838 zq0pr_odt_max=(zq0pr&0xf0);
20839 zq0pr_odt_min=(zq0pr&0xf0);
20840
20841 if (zq0pr_drv_flag)
20842 {
20843 while ((zq0pr&0xf)<0xf)
20844 {
20845 zq0pr++;
20846 update_ddr_zq(zq0pr);
20847 temp_test_error=0;
20848 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20849 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20850 if (temp_test_error)
20851 {
20852 zq0pr--;
20853 update_ddr_zq(zq0pr);
20854 break;
20855
20856
20857 }
20858 }
20859 zq0pr_drv_max=(zq0pr&0xf);
20860 printf("\nzq0pr_drv_max== 0x%08x\n", zq0pr_drv_max);
20861
20862 update_ddr_zq(zq0pr_org);
20863
20864 while ((zq0pr&0xf)>0x0)
20865 {
20866 zq0pr--;
20867 update_ddr_zq(zq0pr);
20868 temp_test_error=0;
20869 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20870 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20871 if (temp_test_error)
20872 {
20873 zq0pr++;
20874 update_ddr_zq(zq0pr);
20875 break;
20876
20877
20878 }
20879 }
20880
20881
20882 zq0pr_drv_min=(zq0pr&0xf);
20883 printf("\nzq0pr_drv_max== 0x%08x\n", zq0pr_drv_min);
20884 }
20885
20886 if (zq0pr_odt_flag)
20887 {
20888 while ((zq0pr&0xf0)<0xf0)
20889 {
20890 zq0pr=zq0pr+0x10;
20891 update_ddr_zq(zq0pr);
20892 temp_test_error=0;
20893 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20894 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20895 if (temp_test_error)
20896 {
20897 zq0pr=zq0pr-0x10;
20898 update_ddr_zq(zq0pr);
20899 break;
20900
20901
20902 }
20903 }
20904 zq0pr_odt_max=(zq0pr&0xf0);
20905 printf("\nzq0pr_odt_max== 0x%08x\n", zq0pr_odt_max);
20906
20907 update_ddr_zq(zq0pr_org);
20908
20909
20910 while ((zq0pr&0xf0)>0x0)
20911 {
20912 zq0pr=zq0pr-0x10;
20913 update_ddr_zq(zq0pr);
20914 temp_test_error=0;
20915 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
20916 temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
20917 if (temp_test_error)
20918 {
20919 zq0pr=zq0pr+0x10;
20920 update_ddr_zq(zq0pr);
20921 break;
20922
20923
20924 }
20925 }
20926 zq0pr_odt_min=(zq0pr&0xf0);
20927 printf("\nzq0pr_odt_min== 0x%08x\n", zq0pr_odt_min);
20928 }
20929 update_ddr_zq(zq0pr_org);
20930
20931 printf("\nzq0pr_drv_max== 0x%08x\n", zq0pr_drv_max);
20932 printf("\nzq0pr_drv_min== 0x%08x\n", zq0pr_drv_min);
20933 printf("\nzq0pr_odt_max== 0x%08x\n", zq0pr_odt_max);
20934 printf("\nzq0pr_odt_min== 0x%08x\n", zq0pr_odt_min);
20935
20936 return loop_max_freq;
20937
20938
20939
20940}
20941
20942int clear_ddr_band_monitor(unsigned int port,unsigned int port_id,unsigned int timer_counter)
20943{
20944 wr_reg(DMC_MON_CTRL3, timer_counter);
20945 wr_reg(DMC_MON_CTRL2, (port_id<<0)|(port<<16)|(0<<20)|(1<<30));
20946 ddr_udelay(1);
20947 if (((rd_reg(DMC_MON_CTRL2))>>30) == 1)
20948 return 1;
20949 else
20950 return 0;
20951
20952
20953}
20954int open_ddr_band_monitor(unsigned int port,unsigned int port_id,unsigned int timer_counter)
20955{
20956 wr_reg(DMC_MON_CTRL3, timer_counter);
20957 wr_reg(DMC_MON_CTRL2, ((rd_reg(DMC_MON_CTRL2))&(1<<30))|(port_id<<0)|(port<<16)|(0<<20)|(1<<31));
20958
20959 return 1;
20960}
20961
20962int finish_ddr_band_monitor(unsigned int port,unsigned int port_id,unsigned int timer_counter)
20963{
20964 //wr_reg(DMC_MON_CTRL3, timer_time);
20965 if (((rd_reg(DMC_MON_CTRL2))>>31) == 0)
20966 {
20967 printf("\nddr bandwidth timer finish count and print result\n");
20968 printf("\nDMC_MON_port == 0x%08x port_id==0x%08x timer_time==0x%08x",port,port_id,timer_counter);
20969 printf("\nDMC_MON_ALL_REQ_CNT == 0x%08x",(rd_reg(DMC_MON_ALL_REQ_CNT)));
20970
20971 printf("\nDMC_MON_ALL_GRANT_CNT == 0x%08x",(rd_reg(DMC_MON_ALL_GRANT_CNT)));
20972 printf("\nDMC_MON_ALL_GRANT_CNT_band == 0x%08x kbyte,dec== %d Mbyte",((rd_reg(DMC_MON_ALL_GRANT_CNT))*(8))/1024,((rd_reg(DMC_MON_ALL_GRANT_CNT))*(8))/(1024*1024));
20973 printf("\nDMC_MON_ONE _GRANT_CNT for selected port and subids == 0x%08x",(rd_reg(DMC_MON_ONE_GRANT_CNT)));
20974 printf("\nDMC_MON_ONE _GRANT_CNT_band for selected port and subids == 0x%08x,dec== %dMbyte",((rd_reg(DMC_MON_ONE_GRANT_CNT))*(8))/1024,((rd_reg(DMC_MON_ONE_GRANT_CNT))*(8))/(1024*1024));
20975 }
20976 //wr_reg(DMC_MON_CTRL2, ((rd_reg(DMC_MON_CTRL2))&(1<<30))|(port_id<<0)|(port<<16)|(0<<20)|(1<<31));
20977
20978 return 1;
20979}
20980
20981
20982
20983int do_ddr_test_bandwidth(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
20984{
20985 printf("\nEnter Test ddr bandwidth function\n");
20986 // if(!argc)
20987 // goto DDR_TUNE_DQS_START;
20988 printf("\nargc== 0x%08x\n", argc);
20989 //writel((0), 0xc8836c00);
20990 OPEN_CHANNEL_A_PHY_CLK();
20991 OPEN_CHANNEL_B_PHY_CLK();
20992 //writel((0), 0xc8836c00);
20993
20994 char *endp;
20995 // unsigned int *p_start_addr;
20996 unsigned int test_loop=1;
20997 unsigned int test_times=1;
20998 unsigned int timer_time_ms=1000;
20999
21000
21001 unsigned int ddr_pll=0x10221;
21002 unsigned int ddr_clk_org=792;
21003 unsigned int ddr_pll_org = rd_reg(AM_DDR_PLL_CNTL)&(~(1<<29));
21004 ddr_pll=ddr_pll_org;
21005 unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
21006 ddr_clk_org=ddr_clk;
21007 printf("\nddr_clk_org== %dMHz\n", ddr_clk_org);
21008
21009 unsigned int zq0pr = rd_reg(DDR0_PUB_ZQ0PR);
21010 printf("\nddr_zq0pr== 0x%08x\n", zq0pr);
21011
21012 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
21013
21014#define DDR_CROSS_TALK_TEST_SIZE 0x20000
21015
21016 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
21017
21018 unsigned int test_port=0;
21019 unsigned int test_port_sub_id=1;
21020
21021
21022 if (argc == 1)
21023 {
21024 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
21025 test_loop=1;
21026
21027 }
21028
21029 if (argc == 2)
21030 {
21031 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
21032 test_loop=1;
21033
21034 }
21035 if (argc== 3)
21036 {
21037 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
21038 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
21039
21040 }
21041 if (argc >= 4)
21042 {
21043 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
21044 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
21045 test_port= simple_strtoull_ddr(argv[3], &endp, 16);
21046
21047
21048 }
21049 if (argc >= 5)
21050 {
21051 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 16);
21052 test_loop= simple_strtoull_ddr(argv[2], &endp, 16);
21053 test_port= simple_strtoull_ddr(argv[3], &endp, 16);
21054 test_port_sub_id= simple_strtoull_ddr(argv[4], &endp, 16);
21055
21056 }
21057 if (argc >5)
21058 {
21059
21060 timer_time_ms= simple_strtoull_ddr(argv[5], &endp, 16);
21061
21062 }
21063
21064 //unsigned int temp_test_error=0;
21065 unsigned int timer_counter=0;
21066 timer_counter=(timer_time_ms*1000*ddr_clk/2);
21067 //while(test_times<(test_loop+1))
21068 {
21069 {
21070 clear_ddr_band_monitor( test_port, test_port_sub_id, timer_counter);
21071 open_ddr_band_monitor( test_port, test_port_sub_id, timer_counter);
21072 while (test_times<(test_loop+1))
21073 {
21074 printf("\ntest_times== %d times\n", test_times);
21075 ddr_test_s_cross_talk_pattern(ddr_test_size);
21076 test_times++;
21077 }
21078 finish_ddr_band_monitor( test_port, test_port_sub_id, timer_counter);
21079 printf("\ntimer_time_ms== %d ms\n", timer_time_ms);
21080
21081 printf("\nddr_clk== %dMHz\n", ddr_clk);
21082
21083 }
21084 }
21085
21086 return 1;
21087}
21088
21089int do_ddr_fine_tune_lcdlr_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21090{
21091 printf("\nEnter ddr_fine_tune_lcdlr_env function\n");
21092 // if(!argc)
21093 // goto DDR_TUNE_DQS_START;
21094 int i=0;
21095 printf("\nargc== 0x%08x\n", argc);
21096 for (i = 0;i<argc;i++)
21097 {
21098 printf("\nargv[%d]=%s\n",i,argv[i]);
21099 }
21100
21101 //writel((0), 0xc8836c00);
21102 OPEN_CHANNEL_A_PHY_CLK();
21103
21104 OPEN_CHANNEL_B_PHY_CLK();
21105 //writel((0), 0xc8836c00);
21106
21107 char *endp;
21108 // unsigned int *p_start_addr;
21109
21110#define WR_RD_ADJ_USE_ENV 1
21111#define WR_RD_ADJ_USE_UART_INPUT 2
21112 unsigned int wr_rd_adj_input_src=1;
21113
21114 int wr_adj_per[12]={
21115 100 ,
21116 1000 ,
21117 100 ,
21118 100 ,
21119 100 ,
21120 100 ,
21121 100 ,
21122 100 ,
21123 100 ,
21124 100 ,
21125 100 ,
21126 100 ,
21127
21128 };
21129 int rd_adj_per[12]={
21130 100 ,
21131 100 ,
21132 80 ,
21133 80 ,
21134 80 ,
21135 80 ,
21136 100 ,
21137 100 ,
21138 100 ,
21139 100 ,
21140 100 ,
21141 100 ,
21142 };
21143 if (argc == 1)
21144 printf("\nplease read help\n");
21145
21146 if (argc >= 2)
21147 {
21148 wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
21149
21150 unsigned int i=0;
21151 if (wr_rd_adj_input_src == WR_RD_ADJ_USE_UART_INPUT)
21152 {
21153 printf("\ntune ddr lcdlr use uart input\n");
21154 if (argc>24+2)
21155 {argc=24+2;}
21156 {
21157
21158 for (i = 2;i<argc;i++)
21159 {
21160 if (i<(2+12)) {
21161 wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
21162 }
21163 else
21164 {
21165 rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
21166 }
21167 }
21168 }
21169
21170 }
21171 if (wr_rd_adj_input_src == WR_RD_ADJ_USE_ENV)
21172 {printf("\ntune ddr lcdlr use uboot env\n");
21173 {
21174 //char str[24];
21175 const char *s;
21176
21177 // char *varname;
21178 int value=0;
21179
21180 //*varname="env_ddrtest";
21181 s = env_get("env_wr_lcdlr_pr");
21182 if (s)
21183 {//i=0;
21184 //while(s_temp)
21185 {
21186 printf("%s",s);
21187 //sscanf(s,"d%,",wr_adj_per);
21188 //sprintf(str,"d%",s);
21189 //getc
21190
21191 }
21192 value = simple_strtoull_ddr(s, &endp, 16);
21193 printf("%d",value);
21194 }
21195 s = env_get("env_rd_lcdlr_pr");
21196
21197 if (s)
21198 {//i=0;
21199 //while(s_temp)
21200 {
21201 printf("%s",s);
21202 //sscanf(s,"d%,",rd_adj_per);
21203
21204 }
21205 //value = simple_strtoull_ddr(s, &endp, 16);
21206 }
21207
21208 //sprintf(str, "%lx", value);
21209 // env_set("env_ddrtest", str);
21210
21211
21212 //run_command("save",0);
21213 }
21214
21215 if (argc>24+2)
21216 argc=24+2;
21217 for (i = 2;i<argc;i++)
21218 {
21219 if (i<(2+12)) {
21220 wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
21221 }
21222 else
21223 {
21224 rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
21225 }
21226 }
21227
21228
21229 }
21230 printf(" int wr_adj_per[12]={\n");
21231 for (i = 0;i<12;i++)
21232 {
21233 printf("%04d ,\n",wr_adj_per[i]);
21234 }
21235 printf("};\n");
21236 printf(" int rd_adj_per[12]={\n");
21237 for (i = 0;i<12;i++)
21238 {
21239 printf("%04d ,\n",rd_adj_per[i]);
21240 }
21241 printf("};\n");
21242
21243
21244#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
21245 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
21246 wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))|(1<<0));
21247 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
21248 wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))|(1<<0));
21249#else
21250 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
21251 wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))|(1<<26));
21252 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
21253 wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))|(1<<26));
21254#endif
21255
21256 int lcdlr_w=0,lcdlr_r=0;
21257 unsigned temp_reg=0;
21258 int temp_count=0;
21259 for ( temp_count=0;temp_count<2;temp_count++)
21260 { temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
21261 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
21262 lcdlr_w=lcdlr_w?lcdlr_w:1;
21263 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21264 if (temp_count == 1)
21265 lcdlr_w=lcdlr_w&ACBDLR_MAX;
21266 wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
21267 }
21268#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
21269 for ( temp_count=2;temp_count<6;temp_count++)
21270 { temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
21271 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
21272 lcdlr_w=lcdlr_w?lcdlr_w:1;
21273 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
21274 lcdlr_r=lcdlr_r?lcdlr_r:1;
21275 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21276 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
21277 wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
21278 wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
21279 wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
21280 }
21281#else
21282 for ( temp_count=2;temp_count<6;temp_count++)
21283 { temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
21284 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
21285 lcdlr_w=lcdlr_w?lcdlr_w:1;
21286 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&DQLCDLR_MAX);
21287 lcdlr_r=lcdlr_r?lcdlr_r:1;
21288 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21289 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
21290 wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
21291 }
21292#endif
21293 for ( temp_count=6;temp_count<8;temp_count++)
21294 { temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
21295
21296 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
21297 lcdlr_w=lcdlr_w?lcdlr_w:1;
21298 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21299 if (temp_count == 7)
21300 lcdlr_w=lcdlr_w&ACBDLR_MAX;
21301 wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
21302 }
21303#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
21304 for ( temp_count=8;temp_count<12;temp_count++)
21305 { temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
21306 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
21307 lcdlr_w=lcdlr_w?lcdlr_w:1;
21308 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
21309 lcdlr_r=lcdlr_r?lcdlr_r:1;
21310 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21311 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
21312 wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
21313 wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
21314 wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
21315 }
21316#else
21317 for ( temp_count=8;temp_count<12;temp_count++)
21318 { temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
21319 lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
21320 lcdlr_w=lcdlr_w?lcdlr_w:1;
21321 lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&0xff);
21322 lcdlr_r=lcdlr_r?lcdlr_r:1;
21323 lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
21324 lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
21325 wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
21326 }
21327#endif
21328
21329#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
21330
21331
21332 wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
21333 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
21334
21335 wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))&(~(1<<0)));
21336 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
21337
21338
21339#else
21340 wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))&(~(1<<26)));
21341 wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
21342
21343 wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))&(~(1<<26)));
21344 wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
21345#endif
21346 printf("\nend adjust lcdlr\n");
21347
21348 CLOSE_CHANNEL_A_PHY_CLK();
21349 CLOSE_CHANNEL_B_PHY_CLK();
21350 }
21351
21352
21353
21354 return 1;
21355
21356}
21357//*/
21358int do_ddr_modify_reg_use_mask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21359{
21360 printf("\nEnter ddr_modify_reg_use_mask function\n");
21361 // if(!argc)
21362 // goto DDR_TUNE_DQS_START;
21363 int i=0;
21364 printf("\nargc== 0x%08x\n", argc);
21365 for (i = 0;i<argc;i++)
21366 printf("\nargv[%d]=%s\n",i,argv[i]);
21367
21368
21369 //writel((0), 0xc8836c00);
21370 OPEN_CHANNEL_A_PHY_CLK();
21371
21372 OPEN_CHANNEL_B_PHY_CLK();
21373 //writel((0), 0xc8836c00);
21374
21375 char *endp;
21376 // unsigned int *p_start_addr;
21377
21378 unsigned int reg_add=0;
21379 unsigned int wr_reg_value=0;
21380 unsigned int rd_reg_value=0;
21381 unsigned int wr_reg_and_mask_1=0xffffffff;
21382 // unsigned int wr_reg_or_mask_2=0x0;
21383
21384
21385
21386 if (argc == 1)
21387 { printf("\nplease read help\n");
21388 printf("\nexample only change 0xc8836800 0x8c010226 0x000fffff bit20-bit31,no change pll od oc \n");
21389 printf("\nddr_test_cmd 9 0xc8836800 0x8c010226 0x000fffff\n");
21390 }
21391 else {
21392 if (argc >= 2)
21393 {
21394 reg_add = simple_strtoull_ddr(argv[1], &endp, 10);
21395 }
21396 if (argc >= 3)
21397 {
21398 wr_reg_value = simple_strtoull_ddr(argv[2], &endp, 10);
21399 }
21400 if (argc >= 4)
21401 {
21402 wr_reg_and_mask_1 = simple_strtoull_ddr(argv[3], &endp, 10);
21403
21404 }
21405 rd_reg_value= (rd_reg(reg_add));
21406 wr_reg(reg_add,(rd_reg_value&wr_reg_and_mask_1)|(wr_reg_value&(~wr_reg_and_mask_1)) );
21407 //rd_reg_value= (rd_reg(reg_add));
21408 //wr_reg(reg_add,(rd_reg_value&(~wr_reg_or_mask_2))|(wr_reg_value&(wr_reg_or_mask_2)) );
21409
21410 printf("\nmodify ok read==0x%08x\n",(rd_reg(reg_add)));
21411
21412
21413 CLOSE_CHANNEL_A_PHY_CLK();
21414 CLOSE_CHANNEL_B_PHY_CLK();
21415 }
21416
21417 return 1;
21418
21419}
21420int do_ddr_set_zq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21421{
21422 printf("\nEnter set ddr zq function\n");
21423 // if(!argc)
21424 // goto DDR_TUNE_DQS_START;
21425 int i=0;
21426 printf("\nargc== 0x%08x\n", argc);
21427 for (i = 0;i<argc;i++)
21428 {
21429 printf("\nargv[%d]=%s\n",i,argv[i]);
21430 }
21431
21432
21433 //writel((0), 0xc8836c00);
21434 OPEN_CHANNEL_A_PHY_CLK();
21435 OPEN_CHANNEL_B_PHY_CLK();
21436 //writel((0), 0xc8836c00);
21437
21438 char *endp;
21439
21440 unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
21441 unsigned int zq1pr_org = rd_reg(DDR0_PUB_ZQ1PR);
21442 unsigned int zq2pr_org = rd_reg(DDR0_PUB_ZQ2PR);
21443 // unsigned int zq0pr_best;
21444 unsigned int zq0pr0= rd_reg(DDR0_PUB_ZQ0PR);
21445 unsigned int zq1pr0= rd_reg(DDR0_PUB_ZQ1PR);
21446 unsigned int zq2pr0= rd_reg(DDR0_PUB_ZQ2PR);
21447
21448 if (argc == 1)
21449 { printf("\nplease read help\n");
21450 printf("\nexample only change zq \n");
21451 printf("\nddr_test_cmd 10 0x19\n");
21452 }
21453 else{
21454 if (argc >= 2)
21455 {
21456 // zq0pr0 = argv[1];
21457 zq0pr0= simple_strtoull_ddr(argv[1], &endp, 0);
21458 }
21459
21460 if (argc >= 3)
21461 {
21462 // zq1pr0 = argv[2];
21463 zq1pr0= simple_strtoull_ddr(argv[2], &endp, 0);
21464 }
21465
21466 if (argc >= 4)
21467 {
21468 // zq2pr0 =argv[3];
21469 zq2pr0= simple_strtoull_ddr(argv[3], &endp, 0);
21470
21471 }}
21472
21473 printf("\nzq0pr_org== 0x%08x\n", zq0pr_org);
21474 printf("\nzq1pr_org== 0x%08x\n", zq1pr_org);
21475 printf("\nzq2pr_org== 0x%08x\n", zq2pr_org);
21476 wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)|(1<<27));
21477 printf("\norg channel 0 zq zq0pr=0x%08x,zq0dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ0PR),rd_reg(DDR0_PUB_ZQ0DR));
21478 printf("\norg channel 0 zq zq1pr=0x%08x,zq1dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ1PR),rd_reg(DDR0_PUB_ZQ1DR));
21479 printf("\norg channel 0 zq zq2pr=0x%08x,zq2dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ2PR),rd_reg(DDR0_PUB_ZQ2DR));
21480
21481 wr_reg( DDR0_PUB_ZQ0PR,zq0pr0);
21482 wr_reg( DDR0_PUB_ZQ1PR,zq1pr0);
21483 wr_reg( DDR0_PUB_ZQ2PR,zq2pr0);
21484 wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)|(1<<27));
21485 wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))&(~((1<<2)|(1<<27))));
21486 printf("\nupdate channel 0 zq zq0pr=0x%08x,zq0dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ0PR),rd_reg(DDR0_PUB_ZQ0DR));
21487 printf("\nupdate channel 0 zq zq1pr=0x%08x,zq1dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ1PR),rd_reg(DDR0_PUB_ZQ1DR));
21488 printf("\nupdate channel 0 zq zq2pr=0x%08x,zq2dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ2PR),rd_reg(DDR0_PUB_ZQ2DR));
21489
21490 wr_reg( DDR0_PUB_ZQ0PR,zq0pr0);
21491 wr_reg( DDR0_PUB_ZQ1PR,zq1pr0);
21492 wr_reg( DDR0_PUB_ZQ2PR,zq2pr0);
21493 printf("\nupdate channel 0 zq zq0pr=0x%08x,zq0dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ0PR),rd_reg(DDR0_PUB_ZQ0DR));
21494 printf("\nupdate channel 0 zq zq1pr=0x%08x,zq1dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ1PR),rd_reg(DDR0_PUB_ZQ1DR));
21495 printf("\nupdate channel 0 zq zq2pr=0x%08x,zq2dr=0x%08x,\n",rd_reg(DDR0_PUB_ZQ2PR),rd_reg(DDR0_PUB_ZQ2DR));
21496
21497 //wr_reg( DDR1_PUB_ZQCR,(rd_reg(DDR1_PUB_ZQCR))|(1<<2)|(1<<27));
21498 //wr_reg( DDR1_PUB_ZQCR,(rd_reg(DDR1_PUB_ZQCR))&(~((1<<2)|(1<<27))));
21499 CLOSE_CHANNEL_A_PHY_CLK();
21500 CLOSE_CHANNEL_B_PHY_CLK();
21501 return 1;
21502
21503}
21504
21505
21506int ddr_ee_pwm_voltage_table[31][2] = {
21507 { 0x1c0000, 860},
21508 { 0x1b0001, 870},
21509 { 0x1a0002, 880},
21510 { 0x190003, 890},
21511 { 0x180004, 900},
21512 { 0x170005, 910},
21513 { 0x160006, 920},
21514 { 0x150007, 930},
21515 { 0x140008, 940},
21516 { 0x130009, 950},
21517 { 0x12000a, 960},
21518 { 0x11000b, 970},
21519 { 0x10000c, 980},
21520 { 0x0f000d, 990},
21521 { 0x0e000e, 1000},
21522 { 0x0d000f, 1010},
21523 { 0x0c0010, 1020},
21524 { 0x0b0011, 1030},
21525 { 0x0a0012, 1040},
21526 { 0x090013, 1050},
21527 { 0x080014, 1060},
21528 { 0x070015, 1070},
21529 { 0x060016, 1080},
21530 { 0x050017, 1090},
21531 { 0x040018, 1100},
21532 { 0x030019, 1110},
21533 { 0x02001a, 1120},
21534 { 0x01001b, 1130},
21535 { 0x00001c, 1140}
21536};
21537
21538
21539void ddr_test_pwm_set_voltage(unsigned int id, unsigned int voltage)
21540{
21541 int to;
21542
21543#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
21544
21545 enum pwm_id {
21546 pwm_a = 0,
21547 pwm_b,
21548 pwm_c,
21549 pwm_d,
21550 pwm_e,
21551 pwm_f,
21552 };
21553
21554 //printf("test ddr init pwm id %08d \n",id);
21555
21556 unsigned reg;
21557 /*
21558 * TODO: support more pwm controllers, right now only support
21559 * PWM_B, PWM_D
21560 */
21561 switch (id) {
21562 case pwm_b:
21563 reg =* (P_PWM_MISC_REG_AB);
21564 reg &= ~(0x7f << 16);
21565 reg |= ((1 << 23) | (1 << 1));
21566 *(P_PWM_MISC_REG_AB) = reg;
21567 /*
21568 * default set to max voltage
21569 */
21570 *(P_PWM_PWM_B) = ddr_ee_pwm_voltage_table[ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1][0];
21571 reg = *(P_PIN_MUX_REG1);
21572 reg &= ~(1 << 10);
21573 *(P_PIN_MUX_REG1) = reg;
21574
21575 reg = *(P_PIN_MUX_REG2);
21576 reg &= ~(1 << 5);
21577 reg |= (1 << 11); // enable PWM_B
21578 *(P_PIN_MUX_REG2) = reg;
21579 break;
21580
21581 case pwm_d:
21582 reg =*( P_PWM_MISC_REG_CD);
21583 reg &= ~(0x7f << 16);
21584 reg |= ((1 << 23) | (1 << 1));
21585 *(P_PWM_MISC_REG_CD) = reg;
21586 /*
21587 * default set to max voltage
21588 */
21589 *(P_PWM_PWM_D )= ddr_ee_pwm_voltage_table[ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1][0];
21590 reg =*( P_PIN_MUX_REG1);
21591 reg &= ~(1 << 9);
21592 reg &= ~(1 << 11);
21593 *(P_PIN_MUX_REG1) = reg;
21594
21595 reg = *(P_PIN_MUX_REG2);
21596 reg |= (1 << 12); // enable PWM_D
21597 *(P_PIN_MUX_REG2 )= reg;
21598 break;
21599 default:
21600 break;
21601 }
21602
21603 ddr_udelay(200);
21604
21605 //printf("test ddr set vddee to %08d mv\n",voltage);
21606
21607 for (to = 0; to < ARRAY_SIZE(ddr_ee_pwm_voltage_table); to++) {
21608 if (ddr_ee_pwm_voltage_table[to][1] >= voltage) {
21609 break;
21610 }
21611 }
21612 if (to >= ARRAY_SIZE(ddr_ee_pwm_voltage_table)) {
21613 to = ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1;
21614 }
21615 switch (id) {
21616 case pwm_b:
21617 *(P_PWM_PWM_B) = ddr_ee_pwm_voltage_table[to][0];
21618 break;
21619
21620 case pwm_d:
21621 *(P_PWM_PWM_D) = ddr_ee_pwm_voltage_table[to][0];
21622 break;
21623 default:
21624 break;
21625 }
21626 ddr_udelay(200);
21627}
21628
21629int do_ddr_test_pwm_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21630{
21631 printf("\nEnter do_ddr_test_pwm_cmd function\n");
21632 // if(!argc)
21633 // goto DDR_TUNE_DQS_START;
21634 int i=0;
21635 printf("\nargc== 0x%08x\n", argc);
21636 for (i = 0;i<argc;i++)
21637 {
21638 printf("\nargv[%d]=%s\n",i,argv[i]);
21639 }
21640
21641 //writel((0), 0xc8836c00);
21642 OPEN_CHANNEL_A_PHY_CLK();
21643 OPEN_CHANNEL_B_PHY_CLK();
21644 //writel((0), 0xc8836c00);
21645
21646 char *endp;
21647
21648
21649 unsigned int id=0;
21650 // unsigned int voltage=1000;
21651 unsigned int pwm_low=0x1f;
21652 unsigned int pwm_high=0;
21653
21654
21655 {
21656
21657
21658
21659 if (argc == 1)
21660 { printf("\nplease read help\n");
21661
21662 }
21663 else{
21664 if (argc >= 2)
21665 {
21666 // zq0pr0 = argv[1];
21667 // zq1pr0 = argv[2];
21668 id= simple_strtoull_ddr(argv[1], &endp, 0);
21669 //voltage= simple_strtoull_ddr(argv[1], &endp, 0);
21670 }
21671
21672 if (argc >= 3)
21673 {
21674
21675 pwm_low= simple_strtoull_ddr(argv[2], &endp, 0);
21676 }
21677 if (argc >= 4)
21678 {
21679
21680 pwm_high= simple_strtoull_ddr(argv[3], &endp, 0);
21681 }
21682 pwm_low=(pwm_low>0x1f)?(0x1f):(pwm_low);
21683 pwm_high=(pwm_high>0x1f)?(0x1f):(pwm_high);
21684
21685 printf("\npwm_low== 0x%08d 0-1f\n", pwm_low);
21686 printf("\npwm_high== 0x%08d 0-1f\n", pwm_high);
21687 printf("\npwm_id== 0x%08d\n", id);
21688 printf("\npwm_id 0== pwm_a\n");
21689 printf("\npwm_id 1== pwm_b\n");
21690 printf("\npwm_id 2== pwm_c\n");
21691 printf("\npwm_id 3== pwm_d\n");
21692 printf("\npwm_id 4== pwm_e\n");
21693 printf("\npwm_id 5== pwm_f\n");
21694 //ddr_test_pwm_set_voltage(id,voltage);
21695
21696 {
21697
21698
21699
21700
21701#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
21702
21703
21704
21705
21706
21707
21708 enum pwm_id {
21709 pwm_a = 0,
21710 pwm_b,
21711 pwm_c,
21712 pwm_d,
21713 pwm_e,
21714 pwm_f,
21715 };
21716
21717
21718 //printf("test ddr init pwm id %08d \n",id);
21719
21720 unsigned int reg;
21721
21722 /*
21723 * TODO: support more pwm controllers, right now only support
21724 * PWM_B, PWM_D
21725 */
21726
21727 switch (id) {
21728 case pwm_b:
21729 reg = *(P_PWM_MISC_REG_AB);
21730 reg &= ~(0x7f << 16);
21731 reg |= ((1 << 23) | (1 << 1));
21732 *(P_PWM_MISC_REG_AB) = reg;
21733 /*
21734 * default set to max voltage
21735 */
21736 *(P_PWM_PWM_B) =0x00001f;//pwm_low|(pwm_high<<16);// ddr_ee_pwm_voltage_table[ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1][0];
21737 reg = *(P_PIN_MUX_REG1);
21738 reg &= ~(1 << 10);
21739 *(P_PIN_MUX_REG1) = reg;
21740
21741 reg = *(P_PIN_MUX_REG2);
21742 reg &= ~(1 << 5);
21743 reg |= (1 << 11); // enable PWM_B
21744 *(P_PIN_MUX_REG2 )= reg;
21745 break;
21746
21747 case pwm_d:
21748 reg = *(P_PWM_MISC_REG_CD);
21749 reg &= ~(0x7f << 16);
21750 reg |= ((1 << 23) | (1 << 1));
21751 *(P_PWM_MISC_REG_CD) = reg;
21752 /*
21753 * default set to max voltage
21754 */
21755 *(P_PWM_PWM_D )= 0x00001f;//pwm_low|(pwm_high<<16);//ddr_ee_pwm_voltage_table[ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1][0];
21756 reg =*( P_PIN_MUX_REG1);
21757 reg &= ~(1 << 9);
21758 reg &= ~(1 << 11);
21759 *(P_PIN_MUX_REG1) = reg;
21760
21761 reg = *(P_PIN_MUX_REG2);
21762 reg |= (1 << 12); // enable PWM_D
21763 *(P_PIN_MUX_REG2) = reg;
21764 break;
21765 default:
21766 break;
21767 }
21768
21769 ddr_udelay(200);
21770
21771 //printf("test ddr set vddee to %08d mv\n",voltage);
21772
21773 //for (to = 0; to < ARRAY_SIZE(ddr_ee_pwm_voltage_table); to++) {
21774 // if (ddr_ee_pwm_voltage_table[to][1] >= voltage) {
21775 // break;
21776 // }
21777 //}
21778 //if (to >= ARRAY_SIZE(ddr_ee_pwm_voltage_table)) {
21779 // to = ARRAY_SIZE(ddr_ee_pwm_voltage_table) - 1;
21780 //}
21781
21782 switch (id) {
21783 case pwm_b:
21784 *(P_PWM_PWM_B) = pwm_low|(pwm_high<<16);//ddr_ee_pwm_voltage_table[to][0];
21785 break;
21786
21787 case pwm_d:
21788 *(P_PWM_PWM_D) = pwm_low|(pwm_high<<16);//ddr_ee_pwm_voltage_table[to][0];
21789 break;
21790 default:
21791 break;
21792 }
21793 ddr_udelay(200);
21794 }
21795
21796 unsigned int ddl_100step_ps= 0;
21797 ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff);
21798 printf("\nddl_100step_ps== %08d,0_5cycle_ps== %08d,0_5cycle==0x%08x\n", ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)),
21799 ((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff));
21800
21801 CLOSE_CHANNEL_A_PHY_CLK();
21802 CLOSE_CHANNEL_B_PHY_CLK();
21803
21804
21805 }
21806
21807 }
21808 return 1;
21809
21810}
21811int do_ddr_test_pwm_ddl (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21812{
21813 printf("\nEnter do_ddr_test_pwm_ddl function\n");
21814 // if(!argc)
21815 // goto DDR_TUNE_DQS_START;
21816 int i=0;
21817 printf("\nargc== 0x%08x\n", argc);
21818 for (i = 0;i<argc;i++)
21819 {
21820 printf("\nargv[%d]=%s\n",i,argv[i]);
21821 }
21822
21823
21824 //writel((0), 0xc8836c00);
21825 OPEN_CHANNEL_A_PHY_CLK();
21826
21827 OPEN_CHANNEL_B_PHY_CLK();
21828 //writel((0), 0xc8836c00);
21829
21830 char *endp;
21831
21832 unsigned int id=0;
21833 unsigned int voltage=1000;
21834 unsigned int loop=0;
21835 int to;
21836
21837 if (argc == 1)
21838 { printf("\nplease read help\n");
21839
21840 }
21841 else{
21842 if (argc >= 2)
21843 {
21844 // zq0pr0 = argv[1];
21845 voltage= simple_strtoull_ddr(argv[1], &endp, 0);
21846 }
21847
21848 if (argc >= 3)
21849 {
21850 // zq1pr0 = argv[2];
21851 id= simple_strtoull_ddr(argv[2], &endp, 0);
21852 }
21853 if (argc >= 4)
21854 {
21855 // zq1pr0 = argv[2];
21856 loop= simple_strtoull_ddr(argv[3], &endp, 0);
21857 }
21858
21859 printf("\nvoltage== %08d\n", voltage);
21860 printf("\npwm_id== %08d\n", id);
21861 printf("\npwm_id 0== pwm_a\n");
21862 printf("\npwm_id 1== pwm_b\n");
21863 printf("\npwm_id 2== pwm_c\n");
21864 printf("\npwm_id 3== pwm_d\n");
21865 printf("\npwm_id 4== pwm_e\n");
21866 printf("\npwm_id 5== pwm_f\n");
21867 ddr_test_pwm_set_voltage(id,voltage);
21868 unsigned int ddl_100step_ps= 0;
21869 ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff);
21870 printf("\nvoltage ==%08d,ddl_100step_ps== %08d,0_5cycle_ps== %08d,0_5cycle==0x%08x\n",voltage, ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)),
21871 ((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff));
21872
21873 if (loop)
21874 {
21875
21876 for (to = 0; to < ARRAY_SIZE(ddr_ee_pwm_voltage_table); to++) {
21877
21878 ddr_test_pwm_set_voltage(id,(ddr_ee_pwm_voltage_table[to][1]));
21879 ddl_100step_ps=((100*1000*1000)/(2*global_ddr_clk))/((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff);
21880 printf("\nvoltage ==%08d,ddl_100step_ps== %08d,0_5cycle_ps== %08d,0_5cycle==0x%08x\n",
21881 (ddr_ee_pwm_voltage_table[to][1]),ddl_100step_ps,((1000*1000)/(2*global_ddr_clk)),
21882 ((((readl(DDR0_PUB_ACMDLR0)))>>16)&0xff));
21883 }
21884 }
21885
21886
21887 CLOSE_CHANNEL_A_PHY_CLK();
21888 CLOSE_CHANNEL_B_PHY_CLK();
21889
21890
21891 }
21892
21893 return 1;
21894
21895}
21896
21897int do_ddr_test_shift_ddr_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
21898{
21899 printf("\nEnter test shift ddr clk function\n");
21900 // if(!argc)
21901 // goto DDR_TUNE_DQS_START;
21902 int i=0;
21903 printf("\nargc== 0x%08x\n", argc);
21904 for (i = 0;i<argc;i++)
21905 {
21906 printf("\nargv[%d]=%s\n",i,argv[i]);
21907 }
21908
21909 int test_app_pra[4] = {0,0,0,0};
21910
21911 char *endp;
21912
21913
21914 if (argc == 1)
21915 { printf("\nplease read help\n");
21916
21917 }
21918 else{
21919 if (argc >= 2)
21920 {
21921 // zq0pr0 = argv[1];
21922 test_app_pra[0]= simple_strtoull_ddr(argv[1], &endp, 0);
21923 }
21924
21925 if (argc >= 3)
21926 {
21927 // zq1pr0 = argv[2];
21928 test_app_pra[1]= simple_strtoull_ddr(argv[2], &endp, 0);
21929 }
21930
21931 if (argc >= 4)
21932 {
21933 // zq2pr0 =argv[3];
21934 test_app_pra[2]= simple_strtoull_ddr(argv[3], &endp, 0);
21935
21936 }
21937 }
21938
21939
21940 //shift ddr frequency test
21941 printf("test_app_pra[0]==0x%08x\n",test_app_pra[0] );
21942 printf("test_app_pra[1]==0x%08x\n",test_app_pra[1] );
21943 printf("test_app_pra[2]==0x%08x\n",test_app_pra[2] );
21944 unsigned int reg_value[4] = {0};
21945 unsigned int delay_ms_time=30;
21946 unsigned int test_times=0xffff;
21947 unsigned int test_count=0;
21948 unsigned int test_loop_flag=0;
21949 reg_value[0]=0xc4aae860 ;
21950 wr_reg( 0xc883601c,(reg_value[0]));
21951 //update_reg_debug_value(&(reg_value[0]),0xc883601c );
21952 reg_value[1]=0x000ea203 ;
21953 wr_reg( 0xc8837004,(reg_value[1]));
21954 //update_reg_debug_value(&(reg_value[1]),0xc8837004 );
21955
21956 reg_value[3]=0x03e3b740 ;
21957 if ((test_app_pra[1]))
21958 {delay_ms_time=(test_app_pra[1]);
21959 }
21960 if ((test_app_pra[2]))
21961 {test_times=(test_app_pra[2]);
21962 if (test_times == 0xffffffff)
21963 test_loop_flag=1;
21964 }
21965 printf("delay_ms_time==%d\n",delay_ms_time );
21966 printf("test_times==%d\n",test_times );
21967 if (test_app_pra[0] ==0)
21968 reg_value[2]=0x03e3b750 ;
21969 if (test_app_pra[0] ==1)
21970 reg_value[2]=0x03e3b754 ;
21971 if (test_app_pra[0] ==2)
21972 reg_value[2]=0x03e3b758 ;
21973 if (test_app_pra[0] ==3)
21974 reg_value[2]=0x03e3b75c ;
21975
21976 if (test_app_pra[0] ==4)
21977 {
21978 reg_value[2]=0x03e3b750 ;
21979 reg_value[3]=0x03e3b754 ;
21980 }
21981 if (test_app_pra[0] ==5)
21982 {
21983 reg_value[2]=0x03e3b750 ;
21984 reg_value[3]=0x03e3b758 ;
21985 }
21986 if (test_app_pra[0] ==6)
21987 {
21988 reg_value[2]=0x03e3b750 ;
21989 reg_value[3]=0x03e3b75c ;
21990 }
21991 if (test_app_pra[0] ==7)
21992 {
21993 reg_value[2]=0x03e3b754 ;
21994 reg_value[3]=0x03e3b758 ;
21995 }
21996 if (test_app_pra[0] ==8)
21997 {
21998 reg_value[2]=0x03e3b754 ;
21999 reg_value[3]=0x03e3b75c ;
22000 }
22001 if (test_app_pra[0] ==9)
22002 {
22003 reg_value[2]=0x03e3b758 ;
22004 reg_value[3]=0x03e3b75c ;
22005 }
22006 while (1) {test_count++;
22007 // reg_value[2]=0x03e3b750 ;
22008 //update_reg_debug_value(&(reg_value[2]),0xc883700c );
22009
22010 wr_reg( 0xc8837010,(0x001c0101));
22011 ddr_udelay(delay_ms_time * 1000);
22012 wr_reg( 0xc883700c,(reg_value[2]));
22013 printf("\nupdate reg 0xc883700c=0x%08x\n",rd_reg(0xc883700c));
22014 ddr_udelay(delay_ms_time * 1000);
22015 wr_reg( 0xc8837010,(0x000c0101));
22016 ddr_udelay(delay_ms_time * 1000);
22017 wr_reg( 0xc8837010,(0x001c0101));
22018 ddr_udelay(delay_ms_time * 1000);
22019 //usleep(1000 * 1000);
22020 //reg_value[3]=0x03e3b740 ;
22021 //update_reg_debug_value(&(reg_value[3]),0xc883700c );
22022 wr_reg( 0xc883700c,(reg_value[3]));
22023 printf("\nupdate reg 0xc883700c=0x%08x\n",rd_reg(0xc883700c));
22024 ddr_udelay(delay_ms_time * 1000);
22025 wr_reg( 0xc8837010,(0x000c0101));
22026 ddr_udelay(delay_ms_time * 1000);
22027 printf("\ntesting %d times\n",(test_count));
22028 if (!test_loop_flag)
22029 {
22030 if (test_count == test_times)
22031 break;
22032 }
22033 }
22034
22035 return 1;
22036
22037}
22038
22039#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
22040#else
22041int do_ddr_test_shift_ddr_clk_txl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22042{
22043 printf("\nEnter test shift ddr clk function\n");
22044 // if(!argc)
22045 // goto DDR_TUNE_DQS_START;
22046 int i=0;
22047 printf("\nargc== 0x%08x\n", argc);
22048 for (i = 0;i<argc;i++)
22049 printf("\nargv[%d]=%s\n",i,argv[i]);
22050
22051 int test_app_pra[4] = {0,0,0,0};
22052
22053 char *endp;
22054 if (argc == 1)
22055 { printf("\nplease read help\n");
22056
22057 }
22058 else{
22059 if (argc >= 2)
22060 {
22061 // zq0pr0 = argv[1];
22062 test_app_pra[0]= simple_strtoull_ddr(argv[1], &endp, 0);
22063 }
22064
22065 if (argc >= 3)
22066 {
22067 // zq1pr0 = argv[2];
22068 test_app_pra[1]= simple_strtoull_ddr(argv[2], &endp, 0);
22069 }
22070
22071 if (argc >= 4)
22072 {
22073 // zq2pr0 =argv[3];
22074 test_app_pra[2]= simple_strtoull_ddr(argv[3], &endp, 0);
22075
22076 }}
22077 if (argc >= 5)
22078 {
22079 // zq2pr0 =argv[3];
22080 test_app_pra[3]= simple_strtoull_ddr(argv[4], &endp, 0);
22081
22082 }
22083
22084
22085
22086
22087
22088 //shift ddr frequency test
22089 printf("test_app_pra[0]==0x%08x\n",test_app_pra[0] );
22090 printf("test_app_pra[1]==0x%08x\n",test_app_pra[1] );
22091 printf("test_app_pra[2]==0x%08x\n",test_app_pra[2] );
22092 printf("test_app_pra[3]==0x%08x\n",test_app_pra[3] );
22093 // unsigned int reg_value[4] = {0};
22094 unsigned int delay_ms_time=30;
22095 unsigned int test_times=0xffff;
22096 unsigned int test_count=0;
22097 unsigned int test_loop_flag=0;
22098 //reg_value[0]=0 ;
22099 // reg_value[1]=0x000ea202 ;
22100 //wr_reg( 0xc8837004,(reg_value[1]));
22101 //update_reg_debug_value(&(reg_value[1]),0xc8837004 );
22102
22103
22104 if ((test_app_pra[1]))
22105 {delay_ms_time=(test_app_pra[1]);
22106 }
22107 if ((test_app_pra[2]))
22108 {test_times=(test_app_pra[2]);
22109 if (test_times == 0xffffffff)
22110 test_loop_flag=1;
22111 }
22112 delay_ms_time=0;
22113 printf("delay_ms_time==%d\n",delay_ms_time );
22114 printf("test_times==%d\n",test_times );
22115
22116
22117 // printf("\ntesting reg_value[2] ==%08x; \n",(reg_value[2));
22118
22119
22120 while (1) {test_count++;
22121 // reg_value[2]=0x03e3b750 ;
22122 //update_reg_debug_value(&(reg_value[2]),0xc883700c );
22123
22124 wr_reg( 0xff63700c,0x3e3b774);
22125 // wr_reg( 0xff63700c,((rd_reg(0xff63700c))&(~(0x7<2)))|(reg_value[2]<<2)|(1<<4));
22126 printf("\nupdate reg 0xff63700c=0x%08x\n",rd_reg(0xff63700c));
22127 ddr_udelay(delay_ms_time * 1000);
22128 wr_reg( 0xff63700c,0x3e3b764);
22129 //wr_reg( 0xff63700c,((rd_reg(0xff63700c))&(~(0x7<2)))|(reg_value[2]<<2)|(1<<4));
22130 printf("\n...update reg 0xff63700c=0x%08x\n",rd_reg(0xff63700c));
22131 ddr_udelay(delay_ms_time * 1000);
22132
22133
22134
22135 printf("\ntesting %d times\n",(test_count));
22136 if (!test_loop_flag)
22137 {
22138 if (test_count == test_times)
22139 break;
22140 }
22141 }
22142
22143 return 1;
22144}
22145#endif
22146int do_ddr_test_write_read (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22147{
22148 ///*
22149 {
22150 printf("\nEnter do_ddr_test_ddr_write_read_current\n");
22151 // if(!argc)
22152 // goto DDR_TUNE_DQS_START;
22153 int i=0;
22154 printf("\nargc== 0x%08x\n", argc);
22155 for (i = 0;i<argc;i++)
22156 {
22157 printf("\nargv[%d]=%s\n",i,argv[i]);
22158 }
22159
22160 //writel((0), 0xc8836c00);
22161 OPEN_CHANNEL_A_PHY_CLK();
22162 OPEN_CHANNEL_B_PHY_CLK();
22163 //writel((0), 0xc8836c00);
22164
22165 char *endp;
22166
22167 unsigned int pattern_id=1;
22168 unsigned int pattern[4] ={0};
22169 unsigned int write_read=0;
22170 unsigned int read_pattern[4]={0} ;
22171 unsigned int loop=1;
22172 unsigned int start_addr = DDR_TEST_START_ADDR;
22173 unsigned int test_size = DDR_TEST_SIZE;
22174 unsigned int copy_offset= DDR_TEST_SIZE;
22175 unsigned int no_show_info= 0;
22176 unsigned int us_delay_counter= 0;
22177
22178
22179 if (argc == 1)
22180 printf("\nplease read help\n");
22181 else {
22182 if (argc >= 2)
22183 {
22184 // zq0pr0 = argv[1];
22185 write_read= simple_strtoull_ddr(argv[1], &endp, 0);
22186 }
22187
22188 if (argc >= 3)
22189 {
22190 // zq1pr0 = argv[2];
22191 pattern_id= simple_strtoull_ddr(argv[2], &endp, 0);
22192 }
22193 if (argc >= 4)
22194 {
22195 // zq1pr0 = argv[2];
22196 loop= simple_strtoull_ddr(argv[3], &endp, 0);
22197 }
22198 if (argc >=5)
22199 {
22200 // zq1pr0 = argv[2];
22201 start_addr= simple_strtoull_ddr(argv[4], &endp, 0);
22202 }
22203 if (argc >=6)
22204 {
22205 // zq1pr0 = argv[2];
22206 test_size= simple_strtoull_ddr(argv[5], &endp, 0);
22207 }
22208 if (argc >=7)
22209 {
22210 // zq1pr0 = argv[2];
22211 no_show_info= simple_strtoull_ddr(argv[6], &endp, 0);
22212 }
22213 if (argc >=8)
22214 {
22215 // zq1pr0 = argv[2];
22216 us_delay_counter= simple_strtoull_ddr(argv[7], &endp, 0);
22217 }
22218 }
22219 printf("\nwrite_read== 0x%08d\n", write_read);
22220 printf("\npattern_id== 0x%08d\n", pattern_id);
22221 printf("\nloop== 0x%08d\n", loop);
22222 printf("\nstart_addr== 0x%08x\n", start_addr);
22223 printf("\ntest_size== 0x%08x\n", test_size);
22224 printf("\nus_delay_counter== %d\n", us_delay_counter);
22225 copy_offset=test_size;
22226
22227 unsigned int *p;
22228 unsigned int j;
22229
22230
22231 p = (unsigned int * )(int_convter_p(start_addr));
22232
22233 if (pattern_id == 0)
22234 {
22235 pattern[0]=0;
22236 pattern[1]=0;
22237 pattern[2]=0;
22238 pattern[3]=0;
22239 }
22240 if (pattern_id == 1)
22241 {
22242 pattern[0]=0xffffffff;
22243 pattern[1]=0xffffffff;
22244 pattern[2]=0xffffffff;
22245 pattern[3]=0xffffffff;
22246 }
22247
22248
22249 do
22250 {
22251 if (write_read == 0)
22252 {
22253 if (!no_show_info)
22254 printf("\nloop:0x%08x:Start writing at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
22255 for (j=0;j<test_size/4;)
22256 {
22257 *(p+j)=(pattern[0]);
22258 *(p+j+1)=(pattern[1]);
22259 *(p+j+2)=(pattern[2]);
22260 *(p+j+3)=(pattern[3]);
22261 j=j+4;
22262 }
22263 }
22264 if (write_read == 1)
22265 {
22266 if (!no_show_info)
22267 printf("\nloop:0x%08x:Start reading at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
22268 for (j=0;j<test_size/4;)
22269 {
22270 read_pattern[0]= *(p+j);
22271 read_pattern[1]= *(p+j+1);
22272 read_pattern[2]=*(p+j+2);
22273 read_pattern[3]= *(p+j+3);
22274 j=j+4;
22275 }
22276 if (loop == 1) {
22277 if (!no_show_info)
22278 printf(" \nloop:0x%08x:Start reading read_pattern[0] 0x%08x, pattern[1] 0x%08x,pattern[2] 0x%08x,pattern[3] 0x%08x",
22279 loop,read_pattern[0], read_pattern[1],read_pattern[2],read_pattern[3]
22280 ); }
22281 }
22282 if (write_read == 2)
22283 {
22284 if (!no_show_info)
22285 printf("\nloop:0x%08x:Start copying at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
22286 for (j=0;j<test_size/4;)
22287 {
22288 *(p+j+copy_offset/4)= *(p+j);
22289 *(p+j+1+copy_offset/4)= *(p+j+1);
22290 *(p+j+2+copy_offset/4)= *(p+j+2);
22291 *(p+j+3+copy_offset/4)= *(p+j+3);
22292 j=j+4;
22293 }
22294 }
22295 if (us_delay_counter)
22296 {
22297 ddr_udelay(us_delay_counter);
22298 }
22299 }while(loop--);
22300
22301
22302 CLOSE_CHANNEL_A_PHY_CLK();
22303 CLOSE_CHANNEL_B_PHY_CLK();
22304
22305 printf("\ntest end\n");
22306
22307 return 1;
22308 }
22309 //*/
22310}
22311
22312#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
22313
22314#define TEST_MIN_DDR_EE_VOLTAGE 681
22315#define TEST_MAX_DDR_EE_VOLTAGE 962
22316#define G12_AO_PWM_PWM_B (0xff807000 + (0x001 << 2))
22317static int pwm_voltage_table_ee[][2] =
22318{
22319 { 0x1c0000, 681},
22320 { 0x1b0001, 691},
22321 { 0x1a0002, 701},
22322 { 0x190003, 711},
22323 { 0x180004, 721},
22324 { 0x170005, 731},
22325 { 0x160006, 741},
22326 { 0x150007, 751},
22327 { 0x140008, 761},
22328 { 0x130009, 772},
22329 { 0x12000a, 782},
22330 { 0x11000b, 792},
22331 { 0x10000c, 802},
22332 { 0x0f000d, 812},
22333 { 0x0e000e, 822},
22334 { 0x0d000f, 832},
22335 { 0x0c0010, 842},
22336 { 0x0b0011, 852},
22337 { 0x0a0012, 862},
22338 { 0x090013, 872},
22339 { 0x080014, 882},
22340 { 0x070015, 892},
22341 { 0x060016, 902},
22342 { 0x050017, 912},
22343 { 0x040018, 922},
22344 { 0x030019, 932},
22345 { 0x02001a, 942},
22346 { 0x01001b, 952},
22347 { 0x00001c, 962}
22348};
22349uint32_t find_vddee_voltage_index(unsigned int target_voltage)
22350{
22351 unsigned int to;
22352 for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
22353 if (pwm_voltage_table_ee[to][1] >= target_voltage) {
22354 break;
22355 }
22356 }
22357 if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
22358 to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
22359 }
22360 return to;
22361}
22362
22363void set_ee_voltage(uint32_t ee_over_ride_voltage)
22364{
22365 unsigned int to;
22366 for (to = (ARRAY_SIZE(pwm_voltage_table_ee));( to >0); to--) {
22367 if ((pwm_voltage_table_ee[to-1][1]<ee_over_ride_voltage) && (pwm_voltage_table_ee[to][1] >= ee_over_ride_voltage)) {
22368 break;
22369 }
22370 }
22371 if (ee_over_ride_voltage) {
22372 writel(pwm_voltage_table_ee[to][0],G12_AO_PWM_PWM_B);
22373 printf ("\nDDR_override_EE_voltage ==%d mv /n",pwm_voltage_table_ee[to-1][1]);
22374 }
22375}
22376
22377unsigned int read_ee_voltage(void)
22378{
22379 unsigned int to;
22380 unsigned int reg_value=0;
22381 reg_value=readl(G12_AO_PWM_PWM_B);
22382 to=reg_value&0xff;
22383 return pwm_voltage_table_ee[to][1];
22384}
22385uint32_t get_bdlr_100step(uint32_t ddr_frequency)
22386{
22387 uint32_t bdlr_100step=0;
22388 //uint32_t ps=0;
22389 //ps=(rd_reg(DMC_DRAM_FREQ_CTRL))&1;
22390 dwc_ddrphy_apb_wr(((((0<<20)|(2<<16)|(0<<12)|(0xe3)))),0xc00);
22391 bdlr_100step=(100000000/(2*ddr_frequency))/((dwc_ddrphy_apb_rd((((0<<20)|(2<<16)|(0<<12)|(0xe4)))))&0x3ff);
22392 return bdlr_100step;
22393}
22394
22395int do_ddr_test_pwm_bdlr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22396{
22397 char *endp;
22398 printf("\nEnter g12 do_ddr_test_pwm_bdl function\n");
22399 // if(!argc)
22400 // goto DDR_TUNE_DQS_START;
22401 int i=0;
22402 printf("\nargc== 0x%08x\n", argc);
22403 for (i = 0;i<argc;i++)
22404 {
22405 printf("\nargv[%d]=%s\n",i,argv[i]);
22406 }
22407
22408 //if (argc < 2)
22409 // goto usage;
22410
22411
22412 unsigned int argc_count=1;
22413 unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
22414 while (argc_count<argc)
22415 {para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
22416 if (*argv[argc_count] == 0 || *endp != 0) {
22417 para_meter[argc_count-1] = 0;
22418 }
22419 argc_count++;
22420 }
22421
22422 //uint32_t id=para_meter[0];
22423 //uint32_t voltage=para_meter[1];
22424 uint32_t loop=para_meter[0];
22425 uint32_t voltage_min=para_meter[1];
22426 uint32_t voltage_max=para_meter[2];
22427 uint32_t show_count_message=para_meter[3];
22428
22429 //#define PWM_ID_DEFAULT 0<<0
22430 //#define PWM_VOLTAGE_DEFAULT 800<<0
22431#define PWM_LOOP_DEFAULT 10<<0
22432#define PWM_VOLTAGE_MIN_DEFAULT TEST_MIN_DDR_EE_VOLTAGE
22433#define PWM_VOLTAGE_MAX_DEFAULT TEST_MAX_DDR_EE_VOLTAGE
22434
22435
22436 //id=id?id:PWM_ID_DEFAULT;
22437 //voltage=voltage?voltage:PWM_VOLTAGE_DEFAULT;
22438 loop=loop?loop:PWM_LOOP_DEFAULT;
22439 voltage_min=(voltage_min<PWM_VOLTAGE_MIN_DEFAULT)?PWM_VOLTAGE_MIN_DEFAULT:voltage_min;
22440 voltage_max=(voltage_max>PWM_VOLTAGE_MAX_DEFAULT)?PWM_VOLTAGE_MAX_DEFAULT:voltage_max;
22441 voltage_max=(voltage_max<PWM_VOLTAGE_MIN_DEFAULT)?PWM_VOLTAGE_MAX_DEFAULT:voltage_max;
22442
22443 // printf("\nvoltage_min=%d\n",voltage_min);
22444 // printf("\nvoltage_max=%d\n",voltage_max);
22445 uint16_t bdlr_100_min=0;
22446 uint16_t bdlr_100_average=0;
22447 uint16_t bdlr_100_max=0;
22448 uint16_t bdlr_100_cur=0;
22449 //uint16_t cur_ddr_frequency=0;
22450 uint32_t count=1;
22451
22452 bdlr_100_cur=get_bdlr_100step(global_ddr_clk);
22453 bdlr_100_min=bdlr_100_cur;
22454 bdlr_100_max=bdlr_100_cur;
22455 bdlr_100_average=bdlr_100_cur;
22456
22457 unsigned int to=0;
22458 unsigned int to_min=0;
22459 unsigned int to_max=(ARRAY_SIZE(pwm_voltage_table_ee))-1;
22460 //unsigned int temp_count=0;
22461 printf("\nread org_EE_voltage %d mv \n",read_ee_voltage());
22462 to_min=find_vddee_voltage_index(voltage_min);
22463 to_max=find_vddee_voltage_index(voltage_max);
22464 for (to =(to_max+1) ;( to >to_min); to--) {
22465 // printf("\nTO=%d\n",to);
22466 writel(pwm_voltage_table_ee[to-1][0],G12_AO_PWM_PWM_B);
22467 udelay(1000);
22468 bdlr_100_cur=get_bdlr_100step(global_ddr_clk);
22469 bdlr_100_min=bdlr_100_cur;
22470 bdlr_100_max=bdlr_100_cur;
22471 bdlr_100_average=bdlr_100_cur;
22472 count=1;
22473
22474 // printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d,bdlr_100_cur %d \n",pwm_voltage_table_ee[to-1][1],
22475 //bdlr_100_average,bdlr_100_min,bdlr_100_max,count,bdlr_100_cur);
22476
22477 do {
22478 bdlr_100_cur=(100000000/(2*global_ddr_clk))/((dwc_ddrphy_apb_rd((((0<<20)|(2<<16)|(0<<12)|(0xe4)))))&0x3ff);
22479 bdlr_100_min=(bdlr_100_cur<bdlr_100_min)?bdlr_100_cur:bdlr_100_min;
22480 bdlr_100_max=(bdlr_100_cur>bdlr_100_max)?bdlr_100_cur:bdlr_100_max;
22481 bdlr_100_average=(bdlr_100_cur+bdlr_100_average*count)/(count+1);
22482 count++;
22483 if (show_count_message)
22484 printf("%d\n",bdlr_100_cur);
22485
22486 }while(count<loop);
22487 printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d",pwm_voltage_table_ee[to-1][1],
22488 bdlr_100_average,bdlr_100_min,bdlr_100_max,count);
22489
22490
22491 }
22492
22493
22494
22495
22496 return 1;
22497
22498}
22499int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22500{
22501
22502 // if(!argc)
22503 // goto DDR_TUNE_DQS_START;
22504 int i=0;
22505 printf("\nargc== 0x%08x\n", argc);
22506 for (i = 0;i<argc;i++)
22507 printf("\nargv[%d]=%s\n",i,argv[i]);
22508
22509
22510{
22511 uint16_t dq_bit_delay[72];
22512 unsigned char t_count=0;
22513 uint16_t delay_org=0;
22514 uint16_t delay_temp=0;
22515 uint32_t add_offset=0;
22516 dwc_ddrphy_apb_wr(0xd0000,0x0);
22517 bdlr_100step=get_bdlr_100step(global_ddr_clk);
22518 ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32));
22519
22520 {
22521 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
22522 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(1<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
22523 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(2<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
22524 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(3<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
22525 //dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //HwtMRL
22526
22527 printf("\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL");
22528 add_offset=((0<<20)|(0<<16)|(0<<12)|(0x20));
22529 delay_org=dwc_ddrphy_apb_rd(add_offset);
22530 printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
22531 add_offset=((0<<20)|(0<<16)|(1<<12)|(0x20));
22532 delay_org=dwc_ddrphy_apb_rd(add_offset);
22533 printf("\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
22534 add_offset=((0<<20)|(0<<16)|(2<<12)|(0x20));
22535 delay_org=dwc_ddrphy_apb_rd(add_offset);
22536 printf("\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
22537 add_offset=((0<<20)|(0<<16)|(3<<12)|(0x20));
22538 delay_org=dwc_ddrphy_apb_rd(add_offset);
22539 printf("\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
22540 add_offset=((0<<20)|(2<<16)|(0<<12)|(0x20));
22541 delay_org=dwc_ddrphy_apb_rd(add_offset);
22542 printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
22543 }
22544 {
22545 printf("\n count_index delay_value register_add register_value \n ");
22546 printf("\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI",ui_1_32_100step);
22547 for (t_count=0;t_count<10;t_count++)
22548 {
22549 add_offset=((0<<20)|(0<<16)|(t_count<<12)|(0x80));
22550 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22551 delay_org=dq_bit_delay[t_count];
22552 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
22553 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22554 }
22555 }
22556 {
22557 printf("\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI",ui_1_32_100step);
22558 for (t_count=0;t_count<16;t_count++)
22559 {
22560 add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8)));
22561 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22562 delay_org=dq_bit_delay[t_count];
22563 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
22564 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22565 }
22566 }
22567 {
22568 printf("\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse",ui_1_32_100step);
22569 for (t_count=0;t_count<16;t_count++)
22570 {
22571 add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8)));
22572 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22573 delay_org=dq_bit_delay[t_count];
22574 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
22575 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22576 }
22577 }
22578 {
22579 printf("\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U",ui_1_32_100step);
22580 for (t_count=0;t_count<72;t_count++)
22581 {
22582 add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
22583 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22584 delay_org=dq_bit_delay[t_count];
22585 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
22586 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22587 }
22588 }
22589 {
22590 printf("\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse",bdlr_100step);
22591 for (t_count=0;t_count<72;t_count++)
22592 {
22593 add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36)));
22594 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22595 delay_org=dq_bit_delay[t_count];
22596 delay_temp=((delay_org&0x3f));
22597 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22598 }
22599 }
22600 {
22601 printf("\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse",ui_1_32_100step);
22602 for (t_count=0;t_count<16;t_count++)
22603 {
22604 add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8)));
22605 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22606 delay_org=dq_bit_delay[t_count];
22607 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
22608 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22609 }
22610
22611 printf("\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345");
22612 //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
22613 for (t_count=0;t_count<72;t_count++)
22614 {
22615 add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40));
22616 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
22617 delay_org=dq_bit_delay[t_count];
22618 delay_temp=((delay_org));
22619 printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
22620 }
22621 }
22622}
22623
22624{
22625 uint32_t count=0;
22626 uint32_t reg_add_offset=0;
22627 uint16_t reg_value=0;
22628 //ddr_log_serial_puts("\npctl timming:\n",p_dev->ddr_global_message.stick_ddr_log_level);
22629#define DMC_DRAM_TDPD ((0x001d << 2) + 0xff638400)
22630#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xff638400)
22631#define G12_DMC_STICKY_0 ((0x0000 << 2) + 0xff638800)
22632
22633 printf("\n PCTL timming: 0x");
22634
22635 for (count=0;count<(DMC_DRAM_TDPD-DMC_DRAM_TMRD);) {
22636 reg_add_offset=(DMC_DRAM_TMRD+(count));
22637 //ddr_log_serial_puts("\n",p_dev->ddr_global_message.stick_ddr_log_level);
22638 //ddr_log_serial_put_hex(reg_add_offset,32,p_dev->ddr_global_message.stick_ddr_log_level);
22639 //ddr_log_serial_puts(": ",p_dev->ddr_global_message.stick_ddr_log_level);
22640 //ddr_log_serial_put_hex(readl(reg_add_offset),32,p_dev->ddr_global_message.stick_ddr_log_level);
22641 printf("\n reg_add_offset: %08x %08x %08x ",reg_add_offset,readl(reg_add_offset),reg_add_offset);
22642 count=count+4;
22643 }
22644 //ddr_log_serial_puts("\nmrs register: base (0x54000<<1)+fe000000,byte offset\n",p_dev->ddr_global_message.stick_ddr_log_level);
22645 printf("\n mrs register: ");
22646 printf("\n mrs register: base (0x54000<<1)+fe000000,%08x byte offset\n",(0x54000<<1)+0xfe000000);
22647 for (count=0;count<0x80;) {
22648 reg_add_offset=0x54000+count;//dwc_ddrphy_apb_wr(0x54008,0x1001);
22649 //ddr_log_serial_puts("\n",p_dev->ddr_global_message.stick_ddr_log_level);
22650 //ddr_log_serial_put_hex(count,32,p_dev->ddr_global_message.stick_ddr_log_level);
22651 //ddr_log_serial_puts(": ",p_dev->ddr_global_message.stick_ddr_log_level);
22652 reg_value= ((*(volatile uint16_t *)((uint64_t)(((0x54000+(count>>1))) << 1)+0xfe000000))>>(((count)%2)?8:0));//dwc_ddrphy_apb_rd(0x54000+add_offset+1);
22653 reg_value=reg_value&0xff;
22654 //ddr_log_serial_put_hex(reg_value,32,p_dev->ddr_global_message.stick_ddr_log_level);
22655 printf("\n reg_add_offset: %08x %08x %08x",reg_add_offset,reg_value,((((0x54000+(count>>1))) << 1)+0xfe000000));
22656 count=count+1;
22657 }
22658 //ddr_log_serial_puts("\ntiming.c:\n",p_dev->ddr_global_message.stick_ddr_log_level);
22659
22660
22661 printf("\n sticky register: ");
22662 {
22663 uint32_t loop_max = 0;
22664 loop_max=64<<2;//sizeof(ddr_set_t);
22665 //uint32_t loop = 0;
22666 for (count = 0; count < loop_max; count+=4) {
22667 // ddr_log_serial_puts("\n",p_dev->ddr_global_message.stick_ddr_log_level);
22668 // ddr_log_serial_put_hex(count,32,p_dev->ddr_global_message.stick_ddr_log_level);
22669 // ddr_log_serial_puts(": ",p_dev->ddr_global_message.stick_ddr_log_level);
22670 // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_global_message.stick_ddr_log_level);
22671 // count=count+4;
22672 printf("\n reg_add_offset: %08x %08x %08x",count,rd_reg((uint64_t)(G12_DMC_STICKY_0) + count),((G12_DMC_STICKY_0) + count));
22673 }
22674 }
22675
22676 // ddr_log_serial_puts("\n",p_dev->ddr_global_message.stick_ddr_log_level);
22677}
22678
22679 printf("\n ");
22680
22681
22682 ddr_set_t *ddr_set_t_p;
22683 ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
22684 {
22685 printf("\nddr_set_t_p->magic:%08x",ddr_set_t_p->magic);
22686 printf("\nddr_set_t_p->rsv_int0:%08x",ddr_set_t_p->rsv_int0);
22687 printf("\nddr_set_t_p->board_id:%08x",ddr_set_t_p->board_id);
22688 printf("\nddr_set_t_p->version:%08x",ddr_set_t_p->version);
22689 printf("\nddr_set_t_p->DramType:%08x",ddr_set_t_p->DramType);
22690 printf("\nddr_set_t_p->DisabledDbyte:%08x",ddr_set_t_p->DisabledDbyte);
22691 printf("\nddr_set_t_p->Is2Ttiming:%08x",ddr_set_t_p->Is2Ttiming);
22692 printf("\nddr_set_t_p->HdtCtrl:%08x",ddr_set_t_p->HdtCtrl);
22693 printf("\nddr_set_t_p->dram_rank_config:%08x",ddr_set_t_p->dram_rank_config);
22694 printf("\nddr_set_t_p->diagnose:%08x",ddr_set_t_p->diagnose);
22695 printf("\nddr_set_t_p->imem_load_addr:%08x",ddr_set_t_p->imem_load_addr);
22696 printf("\nddr_set_t_p->dmem_load_addr:%08x",ddr_set_t_p->dmem_load_addr);
22697 printf("\nddr_set_t_p->imem_load_size:%08x",ddr_set_t_p->imem_load_size);
22698 printf("\nddr_set_t_p->dmem_load_size:%08x",ddr_set_t_p->dmem_load_size);
22699 printf("\nddr_set_t_p->ddr_base_addr:%08x",ddr_set_t_p->ddr_base_addr);
22700 printf("\nddr_set_t_p->ddr_start_offset:%08x",ddr_set_t_p->ddr_start_offset);
22701 printf("\nddr_set_t_p->dram_cs0_size_MB:%08x",ddr_set_t_p->dram_cs0_size_MB);
22702 printf("\nddr_set_t_p->dram_cs1_size_MB:%08x",ddr_set_t_p->dram_cs1_size_MB);
22703 printf("\nddr_set_t_p->training_SequenceCtrl[0]:%08x",ddr_set_t_p->training_SequenceCtrl[0]);
22704 printf("\nddr_set_t_p->training_SequenceCtrl[1]:%08x",ddr_set_t_p->training_SequenceCtrl[1]);
22705 printf("\nddr_set_t_p->phy_odt_config_rank[0]:%08x",ddr_set_t_p->phy_odt_config_rank[0]);
22706 printf("\nddr_set_t_p->phy_odt_config_rank[1]:%08x",ddr_set_t_p->phy_odt_config_rank[1]);
22707 printf("\nddr_set_t_p->phy_odt_config_rank[2]:%08x",ddr_set_t_p->phy_odt_config_rank[2]);
22708 printf("\nddr_set_t_p->phy_odt_config_rank[3]:%08x",ddr_set_t_p->phy_odt_config_rank[3]);
22709 printf("\nddr_set_t_p->dfi_odt_config:%08x",ddr_set_t_p->dfi_odt_config);
22710 printf("\nddr_set_t_p->DRAMFreq[0]:%08x",ddr_set_t_p->DRAMFreq[0]);
22711 printf("\nddr_set_t_p->DRAMFreq[1]:%08x",ddr_set_t_p->DRAMFreq[1]);
22712 printf("\nddr_set_t_p->DRAMFreq[2]:%08x",ddr_set_t_p->DRAMFreq[2]);
22713 printf("\nddr_set_t_p->DRAMFreq[3]:%08x",ddr_set_t_p->DRAMFreq[3]);
22714 printf("\nddr_set_t_p->PllBypassEn:%08x",ddr_set_t_p->PllBypassEn);
22715 printf("\nddr_set_t_p->ddr_rdbi_wr_enable:%08x",ddr_set_t_p->ddr_rdbi_wr_enable);
22716 printf("\nddr_set_t_p->ddr_rfc_type:%08x",ddr_set_t_p->ddr_rfc_type);
22717 printf("\nddr_set_t_p->enable_lpddr4x_mode:%08x",ddr_set_t_p->enable_lpddr4x_mode);
22718 printf("\nddr_set_t_p->pll_ssc_mode:%08x",ddr_set_t_p->pll_ssc_mode);
22719 printf("\nddr_set_t_p->clk_drv_ohm:%08x",ddr_set_t_p->clk_drv_ohm);
22720 printf("\nddr_set_t_p->cs_drv_ohm:%08x",ddr_set_t_p->cs_drv_ohm);
22721 printf("\nddr_set_t_p->ac_drv_ohm:%08x",ddr_set_t_p->ac_drv_ohm);
22722 printf("\nddr_set_t_p->soc_data_drv_ohm_p:%08x",ddr_set_t_p->soc_data_drv_ohm_p);
22723 printf("\nddr_set_t_p->soc_data_drv_ohm_n:%08x",ddr_set_t_p->soc_data_drv_ohm_n);
22724 printf("\nddr_set_t_p->soc_data_odt_ohm_p:%08x",ddr_set_t_p->soc_data_odt_ohm_p);
22725 printf("\nddr_set_t_p->soc_data_odt_ohm_n:%08x",ddr_set_t_p->soc_data_odt_ohm_n);
22726 printf("\nddr_set_t_p->dram_data_drv_ohm:%08x",ddr_set_t_p->dram_data_drv_ohm);
22727 printf("\nddr_set_t_p->dram_data_odt_ohm:%08x",ddr_set_t_p->dram_data_odt_ohm);
22728 printf("\nddr_set_t_p->dram_ac_odt_ohm:%08x",ddr_set_t_p->dram_ac_odt_ohm);
22729 printf("\nddr_set_t_p->soc_clk_slew_rate:%08x",ddr_set_t_p->soc_clk_slew_rate);
22730 printf("\nddr_set_t_p->soc_cs_slew_rate:%08x",ddr_set_t_p->soc_cs_slew_rate);
22731 printf("\nddr_set_t_p->soc_ac_slew_rate:%08x",ddr_set_t_p->soc_ac_slew_rate);
22732 printf("\nddr_set_t_p->soc_data_slew_rate:%08x",ddr_set_t_p->soc_data_slew_rate);
22733 printf("\nddr_set_t_p->vref_output_permil:%08x",ddr_set_t_p->vref_output_permil);
22734 printf("\nddr_set_t_p->vref_receiver_permil:%08x",ddr_set_t_p->vref_receiver_permil);
22735 printf("\nddr_set_t_p->vref_dram_permil:%08x",ddr_set_t_p->vref_dram_permil);
22736 printf("\nddr_set_t_p->vref_reverse:%08x",ddr_set_t_p->vref_reverse);
22737 printf("\nddr_set_t_p->ac_trace_delay[0]:%08x",ddr_set_t_p->ac_trace_delay[0]);
22738 printf("\nddr_set_t_p->ac_trace_delay[1]:%08x",ddr_set_t_p->ac_trace_delay[1]);
22739 printf("\nddr_set_t_p->ac_trace_delay[2]:%08x",ddr_set_t_p->ac_trace_delay[2]);
22740 printf("\nddr_set_t_p->ac_trace_delay[3]:%08x",ddr_set_t_p->ac_trace_delay[3]);
22741 printf("\nddr_set_t_p->ac_trace_delay[4]:%08x",ddr_set_t_p->ac_trace_delay[4]);
22742 printf("\nddr_set_t_p->ac_trace_delay[5]:%08x",ddr_set_t_p->ac_trace_delay[5]);
22743 printf("\nddr_set_t_p->ac_trace_delay[6]:%08x",ddr_set_t_p->ac_trace_delay[6]);
22744 printf("\nddr_set_t_p->ac_trace_delay[7]:%08x",ddr_set_t_p->ac_trace_delay[7]);
22745 printf("\nddr_set_t_p->ac_trace_delay[8]:%08x",ddr_set_t_p->ac_trace_delay[8]);
22746 printf("\nddr_set_t_p->ac_trace_delay[9]:%08x",ddr_set_t_p->ac_trace_delay[9]);
22747 printf("\nddr_set_t_p->ac_trace_delay[10]:%08x",ddr_set_t_p->ac_trace_delay[10]);
22748 printf("\nddr_set_t_p->ac_trace_delay[11]:%08x",ddr_set_t_p->ac_trace_delay[11]);
22749 //printf("\nddr_set_t_p->ac_pinmux[26]:%08x",ddr_set_t_p->ac_pinmux[26]);
22750 //printf("\nddr_set_t_p->dfi_pinmux[28]:%08x",ddr_set_t_p->dfi_pinmux[28]);
22751 //printf("\nddr_set_t_p->slt_test_function[2]:%08x",ddr_set_t_p->slt_test_function[2]);
22752 printf("\nddr_set_t_p->dq_bdlr_org:%08x",ddr_set_t_p->dq_bdlr_org);
22753 //printf("\nddr_set_t_p->rsv_char1[2]:%08x",ddr_set_t_p->rsv_char1[2]);
22754 printf("\nddr_set_t_p->ddr_dmc_remap[0]:%08x",ddr_set_t_p->ddr_dmc_remap[0]);
22755 printf("\nddr_set_t_p->ddr_dmc_remap[1]:%08x",ddr_set_t_p->ddr_dmc_remap[1]);
22756 printf("\nddr_set_t_p->ddr_dmc_remap[2]:%08x",ddr_set_t_p->ddr_dmc_remap[2]);
22757 printf("\nddr_set_t_p->ddr_dmc_remap[3]:%08x",ddr_set_t_p->ddr_dmc_remap[3]);
22758 printf("\nddr_set_t_p->ddr_dmc_remap[4]:%08x",ddr_set_t_p->ddr_dmc_remap[4]);
22759 printf("\nddr_set_t_p->ddr_lpddr34_ca_remap[0]:%08x",ddr_set_t_p->ddr_lpddr34_ca_remap[0]);
22760 printf("\nddr_set_t_p->ddr_lpddr34_ca_remap[1]:%08x",ddr_set_t_p->ddr_lpddr34_ca_remap[1]);
22761 printf("\nddr_set_t_p->ddr_lpddr34_ca_remap[2]:%08x",ddr_set_t_p->ddr_lpddr34_ca_remap[2]);
22762 printf("\nddr_set_t_p->ddr_lpddr34_ca_remap[3]:%08x",ddr_set_t_p->ddr_lpddr34_ca_remap[3]);
22763 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[0]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[0]);
22764 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[1]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[1]);
22765 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[2]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[2]);
22766 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[3]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[3]);
22767 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[4]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[4]);
22768 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[5]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[5]);
22769 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[6]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[6]);
22770 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[7]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[7]);
22771 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[8]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[8]);
22772 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[9]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[9]);
22773 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[10]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[10]);
22774 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[11]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[11]);
22775 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[12]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[12]);
22776 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[13]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[13]);
22777 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[14]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[14]);
22778 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[15]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[15]);
22779 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[16]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[16]);
22780 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[17]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[17]);
22781 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[18]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[18]);
22782 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[19]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[19]);
22783 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[20]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[20]);
22784 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[21]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[21]);
22785 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[22]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[22]);
22786 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[23]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[23]);
22787 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[24]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[24]);
22788 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[25]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[25]);
22789 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[26]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[26]);
22790 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[27]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[27]);
22791 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[28]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[28]);
22792 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[29]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[29]);
22793 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[30]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[30]);
22794 printf("\nddr_set_t_p->ddr_lpddr34_dq_remap[31]:%08x",ddr_set_t_p->ddr_lpddr34_dq_remap[31]);
22795 printf("\nddr_set_t_p->dram_rtt_nom_wr_park[0]:%08x",ddr_set_t_p->dram_rtt_nom_wr_park[0]);
22796 printf("\nddr_set_t_p->dram_rtt_nom_wr_park[1]:%08x",ddr_set_t_p->dram_rtt_nom_wr_park[1]);
22797 printf("\nddr_set_t_p->ddr_func:%08x",ddr_set_t_p->ddr_func);
22798 //printf("\nddr_set_t_p->rsv_long0[2]:%08x",ddr_set_t_p->rsv_long0[2]);
22799 //printf("\nddr_set_t_p->dqs_adjust[16]:%08x",ddr_set_t_p->dqs_adjust[16]);
22800 //printf("\nddr_set_t_p->dq_bit_delay[72]:%08x",ddr_set_t_p->dq_bit_delay[72]);
22801
22802 }
22803
22804
22805
22806 return 1;
22807
22808
22809}
22810#else
22811int do_ddr_display_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22812{
22813 // if(!argc)
22814 // goto DDR_TUNE_DQS_START;
22815 int i=0;
22816 printf("\nargc== 0x%08x\n", argc);
22817 for (i = 0;i<argc;i++)
22818 printf("\nargv[%d]=%s\n",i,argv[i]);
22819
22820 //writel((0), 0xc8836c00);
22821 OPEN_CHANNEL_A_PHY_CLK();
22822 OPEN_CHANNEL_B_PHY_CLK();
22823 //writel((0), 0xc8836c00);
22824
22825 // char *endp;
22826
22827 unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
22828 unsigned int zq1pr_org = rd_reg(DDR0_PUB_ZQ1PR);
22829 unsigned int zq2pr_org = rd_reg(DDR0_PUB_ZQ2PR);
22830 unsigned int soc_ac_drv3=0;
22831 unsigned int soc_ac_drv4_up=0;
22832 unsigned int soc_ac_drv4_down=0;
22833 unsigned int soc_ac_odt3=0;
22834 unsigned int soc_ac_odt4=0;
22835 unsigned int soc_data01_drv3=0;
22836 unsigned int soc_data01_drv4_up=0;
22837 unsigned int soc_data01_drv4_down=0;
22838 unsigned int soc_data01_odt3=0;
22839 unsigned int soc_data01_odt4=0;
22840
22841 unsigned int soc_data23_drv3=0;
22842 unsigned int soc_data23_drv4_up=0;
22843 unsigned int soc_data23_drv4_down=0;
22844 unsigned int soc_data23_odt3=0;
22845 unsigned int soc_data23_odt4=0;
22846 unsigned int dram_drv=0;
22847 unsigned int dram_odt=0;
22848 unsigned int dram_ddr4_drv=0;
22849 unsigned int dram_ddr4_odt=0;
22850 //unsigned int soc_zq_odt_div=480;
22851
22852 unsigned int pub_dcr= rd_reg(DDR0_PUB_DCR);
22853 unsigned int pub_mr1= rd_reg(DDR0_PUB_MR1);
22854 unsigned int reg_value=0;
22855#define DDR_TYPE_LPDDR2 0
22856#define DDR_TYPE_LPDDR3 1
22857#define DDR_TYPE_DDR3 3
22858#define DDR_TYPE_DDR4 4
22859 unsigned int ddr_type= pub_dcr&0x7; //0 -lpddr2 | 1- lpddr3 | 2- rev | 3 -ddr3 | 4- ddr4
22860
22861 {
22862 if (ddr_type == 0)
22863 printf("\nddr_type==lpddr2\n");
22864 if (ddr_type == 1)
22865 printf("\nddr_type==lpddr3\n");
22866 if (ddr_type == DDR_TYPE_DDR3)
22867 printf("\nddr_type==ddr3\n");
22868 if (ddr_type == DDR_TYPE_DDR4)
22869 printf("\nddr_type==ddr4\n");
22870 if (ddr_type == DDR_TYPE_DDR3)
22871 {//soc_zq_odt_div=360;
22872 }
22873 soc_ac_drv3=zq0pr_org&0xf;
22874 soc_ac_odt3=(zq0pr_org>>4)&0xf;
22875 soc_ac_drv4_up=(zq0pr_org>>8)&0xf;
22876 soc_ac_drv4_down=(zq0pr_org>>12)&0xf;
22877 soc_ac_odt4=(zq0pr_org>>16)&0xf;
22878
22879 soc_data01_drv3=zq1pr_org&0xf;
22880 soc_data01_odt3=(zq1pr_org>>4)&0xf;
22881 soc_data01_drv4_up=(zq1pr_org>>8)&0xf;
22882 soc_data01_drv4_down=(zq1pr_org>>12)&0xf;
22883 soc_data01_odt4=(zq1pr_org>>16)&0xf;
22884
22885 soc_data23_drv3=zq2pr_org&0xf;
22886 soc_data23_odt3=(zq2pr_org>>4)&0xf;
22887 soc_data23_drv4_up=(zq2pr_org>>8)&0xf;
22888 soc_data23_drv4_down=(zq2pr_org>>12)&0xf;
22889 soc_data23_odt4=(zq2pr_org>>16)&0xf;
22890
22891
22892 reg_value=pub_mr1;
22893 if ((((reg_value>>5)&1) == 0))
22894 {
22895 if (((reg_value>>1)&1) == 0)
22896 {
22897 dram_drv=40;
22898 dram_ddr4_drv=34;
22899 }
22900 else
22901 {
22902 dram_drv=34;
22903 dram_ddr4_drv=48;
22904 }
22905 }
22906
22907 if (((reg_value>>8)&7) == 0)
22908 {
22909 dram_ddr4_odt=0;
22910 }
22911 if (((reg_value>>8)&7))
22912 {
22913 dram_ddr4_odt=240/(((reg_value>>10)&1)|(((reg_value>>9)&1)<<1)|(((reg_value>>8)&1)<<2));
22914 }
22915 reg_value=(((reg_value>>9)&1)<<2)|(((reg_value>>6)&1)<<1)|(((reg_value>>2)&1)<<0);
22916 if (reg_value == 1)
22917 {
22918 dram_odt=60;
22919 }
22920 if (reg_value == 2)
22921 {
22922 dram_odt=120;
22923 }
22924 if (reg_value == 3)
22925 {
22926 dram_odt=40;
22927 }
22928 if (reg_value == 4)
22929 {
22930 dram_odt=20;
22931 }
22932 if (reg_value == 5)
22933 {
22934 dram_odt=30;
22935 }
22936
22937 printf("zq0pr_org==%x,zq1pr_org==%x,zq2pr_org==%x,\n",zq0pr_org,zq1pr_org,zq2pr_org);
22938 printf("soc_ac_drv3==%d,soc_ac_odt3==%d,\n",480/(soc_ac_drv3+1),360/(soc_ac_odt3+1));
22939 printf("soc_data01_drv3==%d,soc_data01_odt3==%d,\n",480/(soc_data01_drv3+1),360/(soc_data01_odt3+1));
22940 printf("soc_data23_drv3==%d,soc_data23_odt3==%d,\n",480/(soc_data23_drv3+1),360/(soc_data23_odt3+1));
22941 printf("dram_drv3==%d,dram_odt3==%d,\n\n\n",dram_drv,dram_odt);
22942
22943 printf("soc_ac_drv4_up==%d,soc_ac_drv4_down==%d,soc_ac_odt4==%d,\n",480/(soc_ac_drv4_up+1),480/(soc_ac_drv4_down+1),480/(soc_ac_odt4+1));
22944 printf("soc_data01_drv4_up==%d,soc_data01_drv4_down==%d,soc_data01_odt4==%d,\n",480/(soc_data01_drv4_up+1),480/(soc_data01_drv4_down+1),480/(soc_data01_odt4+1));
22945 printf("soc_data23_drv4_up==%d,soc_data23_drv4_down==%d,soc_data23_odt4==%d,\n",480/(soc_data23_drv4_up+1),480/(soc_data23_drv4_down+1),480/(soc_data23_odt4+1));
22946
22947
22948 printf("dram_ddr4_drv==%d,dram_ddr4_odt==%d,\n",dram_ddr4_drv,dram_ddr4_odt);
22949
22950
22951 }
22952 unsigned int dtedr0[2][4];
22953 unsigned int dtedr1[2][4];
22954 //unsigned int vtdr[2][4];
22955 unsigned int lcdlr_w_setting[2][4];
22956 unsigned int lcdlr_r_setting[2][4];
22957 unsigned int delay_line_100step=0;
22958 if (1) {
22959#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
22960 /*
22961 bl2_print("DDR0_PUB_ACLCDLR: 0x",rd_reg(DDR0_PUB_ACLCDLR), VALUE_HEX, "....\n");
22962 bl2_print("DDR0_PUB_ACBDLR0: 0x", rd_reg(DDR0_PUB_ACBDLR0), VALUE_HEX, "....\n");
22963 bl2_print("DDR0_MDLR: ", ((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF), VALUE_DEC ,"....\n");
22964 bl2_print("DDR0_CLK: ", p_ddr_set->ddr_clk, VALUE_DEC, "MHz\n");
22965 bl2_print("delay_line_10step:", (1000*1000*10/(2*p_ddr_set->ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF), VALUE_DEC, "....\n");
22966 */
22967 //printf("DDR0_MDLR:%8d, CLK:%8dMhz, delay_line_10step:%8d ps\n", ((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF),
22968 //p_ddr_set->ddr_clk ,(1000*1000/(2*p_ddr_set->ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF));
22969 wr_reg(DDR0_PUB_RANKIDR, ((0<<0)|((0<<16))));
22970 ///*
22971 unsigned int i=0;
22972 unsigned int rank=0;
22973 for (rank=0;rank<2;(rank++))
22974 {
22975 printf("DDR0_RANK0==%d,\n",rank);
22976 //bl2_print("DDR0_RANK0: 0x", rank, VALUE_HEX, "\n\n");
22977 wr_reg(DDR0_PUB_RANKIDR, ((rank<<0)|((rank<<16))));
22978 for (i=0;i<4;(i++))
22979 {
22980 //change dtcr0 lane reg map
22981 wr_reg(DDR0_PUB_DTCR0,(((rank<<24)|(i<<16)))|((rd_reg(DDR0_PUB_DTCR0))&(~((1<<11)|(0xf<<16)))));//
22982
22983 printf("DDR0_LANE0: 0x %d\n", i);
22984 // bl2_print("DDR0_PUB_DTEDR0: 0x", rd_reg(DDR0_PUB_DTEDR0), VALUE_HEX, "\n")
22985 // bl2_print("DDR0_PUB_DTEDR1: 0x", rd_reg(DDR0_PUB_DTEDR1), VALUE_HEX, "\n")
22986
22987 // bl2_print("DDR0_PUB_DTEDR2: 0x", rd_reg(DDR0_PUB_DTEDR2), VALUE_HEX, "\n")
22988 dtedr0[rank][i]=(rd_reg(DDR0_PUB_DTEDR0));
22989 dtedr1[rank][i]=(rd_reg(DDR0_PUB_DTEDR1));
22990 //vtdr[rank][i]=(rd_reg(DDR0_PUB_VTDR));
22991 printf("DDR0_PUB_W_Min:%d \n", (rd_reg(DDR0_PUB_DTEDR0))&0x1ff);
22992
22993 printf("DDR0_PUB_W_Max: %d\n", ((rd_reg(DDR0_PUB_DTEDR0))>>9)&0x1ff);
22994
22995 // bl2_print("DDR0_PUB_W_Max: ", ((uint64_t)(DDR0_PUB_DX0LCDLR1+i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1))), VALUE_DEC, "\n\n")
22996 lcdlr_w_setting[rank][i]=((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR1+i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)))));
22997 printf("DDR0_PUB_W_SETTING:%d \n", ((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR1+i*(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)))))&0x1ff);
22998
22999
23000
23001 printf("DDR0_PUB_R_Min: %d\n", (rd_reg(DDR0_PUB_DTEDR1))&0x1ff);
23002
23003 printf("DDR0_PUB_R_Max:%d\n", ((rd_reg(DDR0_PUB_DTEDR1))>>9)&0x1ff);
23004
23005 printf("DDR0_PUB_R_SETTING: %d\n", ((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR3+i*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))))&0x1ff);
23006 lcdlr_r_setting[rank][i]=((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR3+i*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
23007 printf("DDR0_PUB_VTDR: 0x%x\n", (rd_reg(DDR0_PUB_VTDR)));
23008 }
23009 }
23010 wr_reg(DDR0_PUB_RANKIDR, ((0<<0)|((0<<16))));
23011
23012 unsigned int ddr_pll = rd_reg(AM_DDR_PLL_CNTL);
23013 unsigned int ddr_clk =pll_convert_to_ddr_clk(ddr_pll);
23014 ///2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
23015
23016 printf("\nddr_clk== %dMHz\n", ddr_clk);
23017 global_ddr_clk=ddr_clk;
23018 printf("DDR0_PUB_ACBDLR0: 0x%x\n", (rd_reg(DDR0_PUB_ACBDLR0)));
23019 printf("DDR0_PUB_ACLCDLR: 0x%x\n", (rd_reg(DDR0_PUB_ACLCDLR)));
23020
23021 //printf("DDR0_MDLR:%d \n", ((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF));
23022 //printf("DDR0_CLK:%d MHz \n", p_ddr_set->ddr_clk");
23023 //printf("delay_line_10step:%d \n", (1000*1000*10/(2*p_ddr_set->ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF)");
23024
23025 printf("DDR0_MDLR:%8d, CLK:%8dMhz, delay_line_10step:%8d ps,delay_line_100step:%8d ps,\n", ((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF),
23026 global_ddr_clk ,(10000*1000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF),
23027 (1000*100000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF));
23028 delay_line_100step=(1000*100000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF);
23029 for (rank=0;rank<2;(rank++))
23030 {
23031 printf("DDR0_RANK0==%d,\n",rank);
23032
23033 for (i=0;i<4;(i++))
23034 {
23035 //dtedr0[rank][i]=(rd_reg(DDR0_PUB_DTEDR0));
23036 //dtedr1[rank][i]=(rd_reg(DDR0_PUB_DTEDR1));
23037 //vtdr[rank][i]=(rd_reg(DDR0_PUB_VTDR));
23038 printf("%4d ", ((((dtedr0[rank][i])>>9)&0x1ff)-lcdlr_w_setting[rank][i])*delay_line_100step/100
23039 );
23040 printf("%4d ", ((lcdlr_w_setting[rank][i])-(((dtedr0[rank][i])>>0)&0x1ff))*delay_line_100step/100
23041 );
23042
23043 printf("%4d ", ((lcdlr_r_setting[rank][i])-(((dtedr1[rank][i])>>0)&0x1ff))*delay_line_100step/100
23044 );
23045 printf("%4d ", ((((dtedr1[rank][i])>>9)&0x1ff)-lcdlr_r_setting[rank][i])*delay_line_100step/100
23046 );
23047 }
23048 printf("\n");
23049 }
23050 printf("\nend==%d,\n",rank);
23051#endif
23052 }
23053
23054 CLOSE_CHANNEL_A_PHY_CLK();
23055 CLOSE_CHANNEL_B_PHY_CLK();
23056 return 1;
23057}
23058
23059
23060int do_ddr_offset_ddr_lcdlr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23061{
23062
23063 //ddr_test_cmd 0x25 1 1 10 10 10 10 10 10 10 10 10 10
23064#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
23065 // if(!argc)
23066 // goto DDR_TUNE_DQS_START;
23067 int i=0;
23068 char *endp;
23069 unsigned int resume_ddl=0; // 0 pause 1,resume
23070 unsigned int offset_id=0; // 0 left 1 right
23071 unsigned int count=0;
23072 unsigned int reg_add=0;
23073 unsigned int reg_value=0;
23074 unsigned int offset_value[10]={0,0,0,0,0,0,0,0,0,0} ; // ac w clk w lane 0 w r lane 1 w r lane2 w r lane3 w r
23075 printf("\nargc== 0x%08x\n", argc);
23076 for (i = 0;i<argc;i++)
23077 printf("\nargv[%d]=%s\n",i,argv[i]);
23078 if (argc == 1)
23079 printf("\nplease read help\n");
23080 else if (argc > 1)
23081 {
23082 count=0;
23083 resume_ddl= simple_strtoull_ddr(argv[count+1], &endp, 0);
23084 if (*argv[count+1] == 0 || *endp != 0)
23085 {
23086 resume_ddl = 0;
23087 }
23088 // count++;
23089 if (argc > 2)
23090 {
23091 count=1;
23092 offset_id= simple_strtoull_ddr(argv[count+1], &endp, 0);
23093 if (*argv[count+1] == 0 || *endp != 0)
23094 {
23095 offset_id = 0;
23096 }
23097 // count++;
23098 }
23099
23100 if (argc > 3)
23101 {
23102 count=2;
23103 while (count<(argc-1))
23104 {
23105 offset_value[count-2]= simple_strtoull_ddr(argv[count+1], &endp, 0);
23106 if (*argv[count+1] == 0 || *endp != 0)
23107 {
23108 offset_value[count-2] = 0;
23109 }
23110 count++;
23111 }
23112 }
23113
23114 }
23115
23116 printf("resume_ddl=%d,\n",resume_ddl);
23117 if (offset_id)
23118 printf("offset right ++%d,\n",offset_id);
23119 else
23120 printf("offset left --%d,\n",offset_id);
23121
23122 for (i = 0;i<10;i++)
23123 {
23124 printf("offset_value[%d]=%d\n",i,offset_value[i]);
23125 }
23126
23127 {
23128 //writel((0), 0xc8836c00);
23129 OPEN_CHANNEL_A_PHY_CLK();
23130 }
23131
23132 {
23133 OPEN_CHANNEL_B_PHY_CLK();
23134 //writel((0), 0xc8836c00);
23135 }
23136
23137
23138 printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occur error\n", readl(DDR0_PUB_REG_BASE+4));
23139 writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
23140 printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
23141
23142
23143 //if (vref_lcdlr_offset)
23144 for (i = 0;i<10;i++)
23145 {
23146 if (i == 0)
23147 reg_add = DDR0_PUB_ACLCDLR;
23148 if (i == 1)
23149 reg_add = DDR0_PUB_ACBDLR0;
23150 if (i>1)
23151 {
23152 if (i%2) {
23153 reg_add = DDR0_PUB_DX0LCDLR3 + ((DDR0_PUB_DX1LCDLR3 - DDR0_PUB_DX0LCDLR3)*((i-2)/2));}
23154 else{
23155 reg_add = DDR0_PUB_DX0LCDLR1 + ((DDR0_PUB_DX1LCDLR3 - DDR0_PUB_DX0LCDLR3)*((i-2)/2));}
23156 }
23157
23158 printf("\n org reg_add 0x%08x== 0x%08x\n ",(reg_add),
23159 rd_reg(reg_add));
23160 if (offset_id) //offset +
23161 {
23162 wr_reg(reg_add, ( rd_reg(reg_add)+offset_value[i]));
23163 if (i>1)
23164 {if(i%2){wr_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3),
23165 ( rd_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3))+offset_value[i]));
23166 }
23167 }
23168
23169
23170
23171 }
23172 else
23173 {
23174 reg_value=rd_reg(reg_add);
23175 reg_value=( reg_value>offset_value[i])?( reg_value-offset_value[i]):0;
23176 wr_reg(reg_add, reg_value);
23177 if (i>1)
23178 {if(i%2){wr_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3),
23179 ( reg_value));
23180 }
23181 }
23182
23183
23184
23185 }
23186
23187 printf("\n mod reg_add 0x%08x== 0x%08x\n ",(reg_add),
23188 rd_reg(reg_add));
23189 // /*
23190 {
23191
23192
23193
23194 }
23195 //*/
23196 }
23197 // printf("\n read reg==0x%08x\n ",(readl(reg_add)));
23198 printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
23199 if (resume_ddl) {
23200 writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
23201 printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
23202 }
23203
23204
23205
23206
23207
23208#endif
23209 return 1;
23210}
23211
23212
23213#endif
23214int do_ddr_set_watchdog_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23215{
23216 char *endp;
23217 int i=0;
23218 printf("\nargc== 0x%08x\n", argc);
23219 for (i = 0;i<argc;i++)
23220 printf("\nargv[%d]=%s\n",i,argv[i]);
23221
23222 if (argc == 1)
23223 printf("\nplease read help\n");
23224
23225 else if (argc > 1)
23226 {
23227 {
23228 watchdog_time_s = simple_strtoull_ddr(argv[1], &endp, 0);
23229 if (*argv[1] == 0 || *endp != 0)
23230 watchdog_time_s= 20;
23231 }
23232 printf("watchdog_time_s==%d\n",watchdog_time_s);
23233 }
23234
23235 return 1;
23236}
23237
23238
23239#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
23240 #define G12_DATA_READ_OFFSET_MAX (0X3F)
23241 #define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32)
23242
23243 #define DMC_TEST_WINDOW_INDEX_ATXDLY 1
23244 #define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
23245 #define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
23246 #define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
23247 #define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
23248 #define DMC_TEST_WINDOW_INDEX_RXENDLY 6
23249
23250 #define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
23251 #define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12
23252 #define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13
23253
23254 typedef struct training_delay_information{
23255 uint16_t ac_delay[10];
23256 uint16_t txdqs_delay[16];
23257 uint16_t rxdqs_delay[16];
23258 uint16_t txdq_delay[72];
23259 uint16_t rxdq_delay[72];
23260 uint16_t gate_rxdq_delay[72];
23261
23262 } training_delay_t;
23263 training_delay_t training_delay_t_p;
23264
23265 uint16_t lcd_bdl_value[72][4]; //org min max status
23266 // #define LCD_BDLR_ORG 0
23267 #define LCD_BDLR_MIN 0
23268 #define LCD_BDLR_MAX 1
23269 #define LCD_BDLR_STATUS 2
23270
23271 //BYTE0-3
23272 #define TEST_ARG_0_DMC_STICKY_MAGIC 0
23273 #define TEST_ARG_1_CMD0 1
23274 #define TEST_ARG_2_STEP 2 // 0 init 1 test ac 2 test tdqs_write
23275 #define TEST_ARG_3_ALL_TIGHTER 3
23276
23277 //BYTE4-7
23278 #define TEST_ARG_FREQ_NIBBLE_L 4
23279 #define TEST_ARG_FREQ_NIBBLE_H 5
23280
23281 //BYTE8-11
23282 #define TEST_ARG_BOOT_TIMES_L 6
23283 #define TEST_ARG_BOOT_TIMES_H 7
23284
23285 //BYTE12-15
23286 //#define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag
23287 #define TEST_ARG_ERROR_FLAG 63*4 //take 4 byte for kernel test flag
23288
23289 //BYTE16-19
23290 //#define TEST_ARG_16_LCDLR_TEMP_COUNT 16
23291 #define TEST_ARG_CS0_TEST_START_INDEX 12
23292 #define TEST_ARG_CS0_TEST_SIZE_INDEX 16
23293 #define TEST_ARG_CS1_TEST_START_INDEX 20
23294 #define TEST_ARG_CS1_TEST_SIZE_INDEX 24
23295
23296 #define TEST_ARG_WATCHDOG_TIME_SIZE_INDEX 28
23297 #define TEST_ARG_TEST_INDEX_ENALBE_INDEX 30
23298 //#define TEST_ARG_NIBBLE_MASK0_ENALBE_INDEX 32
23299
23300 #define TEST_ARG_ERROR_FLAG_NULL 0
23301 #define TEST_ARG_ERROR_FLAG_FAIL 1
23302 #define TEST_ARG_ERROR_FLAG_PASS 2
23303
23304 #define TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE 32 // 32BYTE
23305 #define TEST_ARG_NIBBLE_WIDTH_BYTE 3 //3///BYTE
23306
23307int do_ddr_test_dqs_window_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23308{
23309 printf("\nEnterddr_test_dqs_window function ddr_test_cmd 0x27 0x1080000 0x800000 0x40000000 0x800000 15 0x6 0 0 0 0 0 0 1/config\n");
23310 printf("\nddr_test_cmd 0x27 cs0_test_start cs0_test_size cs1_test_start cs1_test_size ns test_index_enable nibble_mask0 nibble_mask1 nibble_mask2 dram_type channel_mode config_register all_together--- watchdog should >15s\n");
23311 printf("\n ac write_dqs read_dqs can test together test_index_enable can enable kernel test \n");
23312 // unsigned int channel_b_en = 0;
23313 // unsigned int reg_add=0;
23314 // unsigned int reg_base_adj=0;
23315 unsigned int temp_test_error=0;
23316 unsigned int nibble_save_offset= 0;
23317 unsigned int nibble_step= 0;
23318 unsigned int nibble_max= 16;
23319 unsigned int test_index_enable= 0;
23320 unsigned int test_index= 0;
23321 unsigned int test_index_max= 6;
23322 unsigned int reg_value= 0;
23323 unsigned int dram_type= 0;
23324 unsigned int channel_mode= 0;
23325 unsigned int kernel_watchdog_s= 20;//240;
23326 // unsigned int finish_clear_flag= 0;
23327 unsigned int config_register= 0;
23328 unsigned int all_tighter_enable=0;
23329 unsigned int error_flag_reg_add=0;
23330 char *string_print_flag= " uboot-window-loop \n";
23331 //int argc2;
23332 //char * argv2[30];
23333 char *endp;
23334 char *buf;
23335 buf="";
23336
23337 unsigned int cs0_test_start= 0x1080000;
23338 unsigned int cs0_test_size= DDR_CROSS_TALK_TEST_SIZE;
23339 unsigned int cs1_test_start= 0;
23340 unsigned int cs1_test_size= 0;
23341 unsigned int enable_kernel_test=0;
23342 if (argc >1) {
23343 cs0_test_start = simple_strtoull_ddr(argv[1], &endp, 16);
23344 if (*argv[1] == 0 || *endp != 0)
23345 {
23346 cs0_test_start = 0x1080000;
23347 }
23348 }
23349
23350 if (argc >2) {
23351 cs0_test_size = simple_strtoull_ddr(argv[2], &endp, 16);
23352 if (*argv[2] == 0 || *endp != 0)
23353 {
23354 cs0_test_size = DDR_CROSS_TALK_TEST_SIZE;
23355 }
23356 }
23357
23358 if (argc >3) {
23359 cs1_test_start = simple_strtoull_ddr(argv[3], &endp, 16);
23360 if (*argv[3] == 0 || *endp != 0)
23361 {
23362 cs1_test_start = 0;
23363 }
23364 }
23365 if (argc >4) {
23366 cs1_test_size = simple_strtoull_ddr(argv[4], &endp, 16);
23367 if (*argv[4] == 0 || *endp != 0)
23368 {
23369 cs1_test_size = 0;
23370 }
23371 }
23372
23373 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
23374 ddr_test_size = cs0_test_size;
23375 if (argc >5) {
23376 watchdog_time_s = simple_strtoull_ddr(argv[5], &endp, 0);
23377 if (*argv[5] == 0 || *endp != 0)
23378 {
23379 watchdog_time_s= 20;
23380 }
23381 }
23382 printf("watchdog_time_s==%d\n",watchdog_time_s);
23383
23384 if (argc >6) {
23385 test_index_enable = simple_strtoull_ddr(argv[6], &endp, 0);
23386 if (*argv[5] == 0 || *endp != 0)
23387 {
23388 test_index_enable= 0;
23389 }
23390 }
23391 printf("test_index_enable==0x%08x\n",test_index_enable);
23392 enable_kernel_test=(test_index_enable>>7)&1;
23393 if (enable_kernel_test) {
23394 printf("enable kernel window test\n");
23395 }
23396
23397 unsigned int nibble_mask[3]= {0,0,0};
23398 if (argc >7) {
23399 nibble_mask[0] = simple_strtoull_ddr(argv[7], &endp, 0);
23400 if (*argv[7] == 0 || *endp != 0)
23401 {
23402 nibble_mask[0]= 0;
23403 }
23404 }
23405 printf("nibble_mask[0]==0x%08x\n",nibble_mask[0]);
23406 if (argc >8) {
23407 nibble_mask[1] = simple_strtoull_ddr(argv[8], &endp, 0);
23408 if (*argv[8] == 0 || *endp != 0)
23409 {
23410 nibble_mask[1]= 0;
23411 }
23412 }
23413 printf("nibble_mask[1]==0x%08x\n",nibble_mask[1]);
23414 if (argc >9) {
23415 nibble_mask[2] = simple_strtoull_ddr(argv[9], &endp, 0);
23416 if (*argv[9] == 0 || *endp != 0)
23417 {
23418 nibble_mask[2]= 0;
23419 }
23420 }
23421 printf("nibble_mask[2]==0x%08x\n",nibble_mask[2]);
23422
23423 if (argc >10) {
23424 dram_type = simple_strtoull_ddr(argv[10], &endp, 0);
23425 if (*argv[10] == 0 || *endp != 0)
23426 {
23427 dram_type= 0;
23428 }
23429 }
23430 if (argc >11) {
23431 channel_mode = simple_strtoull_ddr(argv[11], &endp, 0);
23432 if (*argv[11] == 0 || *endp != 0)
23433 {
23434 channel_mode= 0;
23435 }
23436 }
23437 ///*
23438 if (argc >12) {
23439 config_register = simple_strtoull_ddr(argv[12], &endp, 0);
23440 if (*argv[12] == 0 || *endp != 0)
23441 {
23442 config_register= 0;
23443 }
23444 }//*/
23445 ///*
23446 if (argc >13) {
23447 all_tighter_enable = simple_strtoull_ddr(argv[13], &endp, 0);
23448 if (*argv[13] == 0 || *endp != 0)
23449 {
23450 all_tighter_enable= 0;
23451 }
23452 }//*/
23453 printf("all_tighter_enable==0x%08x\n",all_tighter_enable);
23454
23455 if (argc >14) {
23456 error_flag_reg_add = simple_strtoull_ddr(argv[14], &endp, 0);
23457 if (*argv[14] == 0 || *endp != 0)
23458 {
23459 error_flag_reg_add= 0;
23460 }
23461 }
23462 printf("error_flag_reg_add==0x%08x\n",error_flag_reg_add);
23463 printf("\ntest use uboot sticky register\n");
23464
23465 //DMC_STICKY_0
23466 char str[1024]="";
23467 //char str_temp1[1024]="";
23468 //char str_temp2[1024]="";
23469 volatile uint16_t *num_arry=NULL;
23470 //volatile uint16_t *p_num_arry;
23471 int i;
23472 //unsigned int stick_base_add=0;
23473 //uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
23474
23475 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_G12A_0)&0xffff);
23476 //num_arry = (uint16_t *)(uint64_t )(sticky_reg_base_add);
23477 //num_arry=p_num_arry;
23478 for (i = 0; i < 64*4; i++) {
23479 num_arry[i]=ddr_rd_8_16bit_on_32reg(sticky_reg_base_add,8,i);
23480 if ((i == 0) || (i == 32) || (i == (32+10*3)) || (i == (32+10*3+16*3)) || (i == (32+10*3+16*3+16*3)))
23481 {
23482 printf("\n numarry[%d]" ,i);
23483 }
23484 printf(" %d ",num_arry[i]);
23485 }
23486
23487 /*
23488 #define TEST_ARG_1_CMD0 1
23489 //#define TEST_ARG_1_CMD1 1
23490 #define TEST_ARG_2_STEP 2
23491 #define TEST_ARG_3_FREQ 3
23492 #define TEST_ARG_4_STEP_STATUS 4
23493 #define TEST_ARG_5_BOOT_TIMES 5
23494 #define TEST_ARG_6_LCDLR_TEMP_COUNT 6
23495 #define TEST_ARG_7_DMC_STICKY_MAGIC 7
23496 */
23497
23498 uint16_t test_left_max_init_value =32;
23499 uint16_t test_right_max_init_value =32;
23500 uint16_t test_boot_times =0;
23501 uint16_t test_ddr_frequency =0;
23502 //uint16_t temp_sub_value_a =0;
23503 /*
23504 uint16_t test_arg_1_cmd0 =1; //master cmd
23505 uint16_t test_arg_1_cmd1 =0; //min cmd
23506 uint16_t test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
23507 uint16_t test_arg_3_freq =0;
23508 uint16_t test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
23509 test_arg_0_cmd0=num_arry[0];
23510 test_arg_1_cmd1=num_arry[1];
23511 test_arg_2_step=num_arry[2];
23512 test_arg_3_freq=num_arry[3];
23513 test_arg_4_step_status=num_arry[4];
23514 //boot_times=num_arry[5];
23515 //lcdlr_temp_count=num_arry[6];
23516 */
23517 printf("TEST_ARG_0_DMC_STICKY_MAGIC==0x%08x\n",num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]);
23518 printf("\nTEST_ARG_1_CMD0==0x%08x\n",num_arry[TEST_ARG_1_CMD0]);
23519 printf("TEST_ARG_2_STEP==0x%08x\n",num_arry[TEST_ARG_2_STEP]);
23520 printf("TEST_ARG_3_ALL_TIGHTER==0x%08x\n",num_arry[TEST_ARG_3_ALL_TIGHTER]);
23521 printf("TEST_ARG_FREQ_NIBBLE_L==0x%08x\n",num_arry[TEST_ARG_FREQ_NIBBLE_L]);
23522 printf("TEST_ARG_FREQ_NIBBLE_H==0x%08x\n",num_arry[TEST_ARG_FREQ_NIBBLE_H]);
23523 printf("TEST_ARG_BOOT_TIMES_L==0x%08x\n",num_arry[TEST_ARG_BOOT_TIMES_L]);
23524 printf("TEST_ARG_BOOT_TIMES_H==0x%08x\n",num_arry[TEST_ARG_BOOT_TIMES_H]);
23525 printf("TEST_ARG_ERROR_FLAG==0x%08x\n",num_arry[TEST_ARG_ERROR_FLAG]);
23526
23527 printf("TEST_ARG_FREQ==%dM\n",(num_arry[TEST_ARG_FREQ_NIBBLE_H]<<8)|(num_arry[TEST_ARG_FREQ_NIBBLE_L]<<0));
23528 printf("TEST_ARG_BOOT_TIMES==%d\n",(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0));
23529 test_boot_times=(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0);
23530 test_ddr_frequency=(num_arry[TEST_ARG_FREQ_NIBBLE_H]<<8)|(num_arry[TEST_ARG_FREQ_NIBBLE_L]<<0);
23531 if ((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) &&
23532 (num_arry[TEST_ARG_1_CMD0]==(DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) ) //for check magic number make sume enter test command
23533 {
23534 //num_arry[TEST_ARG_5_BOOT_TIMES]++;
23535 test_boot_times++;
23536 num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff;
23537 num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff;
23538 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]);
23539 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]);
23540
23541 if ( test_ddr_frequency != global_ddr_clk) //
23542 {
23543 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_ddr_frequency);
23544 sprintf(str,"d2pll %d",test_ddr_frequency);
23545 printf("\nstr=%s\n",str);
23546 run_command(str,0);
23547 while (1) ;
23548 }
23549 }
23550 else
23551 {
23552 test_boot_times=0;
23553 num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff;
23554 num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff;
23555 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]);
23556 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]);
23557 num_arry[TEST_ARG_2_STEP]=0;
23558 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]);
23559 }
23560 printf("test_sticky is not magic number,boot times==%d\n",test_boot_times);
23561
23562 if (config_register == 1)
23563 {
23564 wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_START_INDEX), cs0_test_start);
23565 wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_SIZE_INDEX), cs0_test_size);
23566 wr_reg((sticky_reg_base_add+TEST_ARG_CS1_TEST_START_INDEX), cs1_test_start);
23567 wr_reg((sticky_reg_base_add+TEST_ARG_CS1_TEST_SIZE_INDEX), cs1_test_size);
23568 {
23569 num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]=watchdog_time_s&0xff;
23570 num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1]=(watchdog_time_s>>8)&0xff;
23571 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_WATCHDOG_TIME_SIZE_INDEX,num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]);
23572 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,(TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1),num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1]);
23573 }
23574 num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]=test_index_enable;
23575 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_TEST_INDEX_ENALBE_INDEX,num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]);
23576 num_arry[TEST_ARG_2_STEP]=0;
23577 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]);
23578 num_arry[TEST_ARG_3_ALL_TIGHTER]=all_tighter_enable;
23579 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_3_ALL_TIGHTER,num_arry[TEST_ARG_3_ALL_TIGHTER]);
23580 }
23581
23582 if (( num_arry[TEST_ARG_2_STEP]) == 0)
23583 {
23584 {
23585 num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]=DMC_STICKY_UBOOT_WINDOW_MAGIC_1;
23586 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_0_DMC_STICKY_MAGIC,num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]);
23587 num_arry[TEST_ARG_1_CMD0]=DMC_STICKY_UBOOT_WINDOW_MAGIC_1;
23588 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_1_CMD0,num_arry[TEST_ARG_1_CMD0]);
23589 num_arry[TEST_ARG_2_STEP]=1;
23590 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]);
23591 {
23592 test_boot_times=0;
23593 num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff;
23594 num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff;
23595 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]);
23596 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]);
23597 }
23598 {
23599 test_ddr_frequency=global_ddr_clk;
23600 num_arry[TEST_ARG_FREQ_NIBBLE_L]=test_ddr_frequency&0xff;
23601 num_arry[TEST_ARG_FREQ_NIBBLE_H]=(test_ddr_frequency>>8)&0xff;
23602 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_FREQ_NIBBLE_L,num_arry[TEST_ARG_FREQ_NIBBLE_L]);
23603 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_FREQ_NIBBLE_H,num_arry[TEST_ARG_FREQ_NIBBLE_H]);
23604 }
23605
23606 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL;
23607 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_ERROR_FLAG,num_arry[TEST_ARG_ERROR_FLAG]);
23608 }
23609
23610
23611 for (nibble_step = 0; nibble_step < 72; nibble_step++)
23612 {
23613 //if(lane_step%2)
23614 {
23615 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_ORG]=0xffff;
23616 test_left_max_init_value=16;
23617 test_right_max_init_value=16;
23618 if (nibble_step<10)
23619 {
23620 test_left_max_init_value=32;
23621 test_right_max_init_value=32;
23622 }
23623 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN]=test_left_max_init_value;
23624 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX]=test_right_max_init_value;
23625 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS]=0;//0
23626 //ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,i,num_arry[i]);
23627 }
23628
23629 {
23630 if (nibble_step<32)
23631 {
23632 if (((nibble_mask[0])>>nibble_step)&1)
23633 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23634 }
23635 else if (nibble_step<64)
23636 {
23637 if (((nibble_mask[1])>>(nibble_step-32))&1)
23638 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23639 }
23640 else if (nibble_step<96)
23641 {
23642 if (((nibble_mask[2])>>(nibble_step-64))&1)
23643 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23644 }
23645 if (all_tighter_enable)
23646 {
23647 if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10+16)))
23648 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=0;
23649 else
23650 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23651 }
23652 }
23653 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS]=0xffff;//0
23654 }
23655
23656 {
23657 //printf("..num_arry[TEST_ARG_1_CMD0]=%d\n",num_arry[TEST_ARG_1_CMD0]);
23658 for (i = TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE; i < 72*TEST_ARG_NIBBLE_WIDTH_BYTE; i++) {
23659 // num_arry[i]=0;
23660 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,i,num_arry[i]);
23661 // ddr_wr_16bit_on_32reg((sticky_reg_base_add+(i<<1)),num_arry[i]);
23662 // printf("num_arry[0x%08x] ==0x%08x\n",i,num_arry[i]);
23663 }
23664
23665 num_arry[TEST_ARG_2_STEP]=1;
23666 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
23667 }
23668
23669 }
23670
23671if (config_register == 1)
23672{
23673 num_arry[TEST_ARG_2_STEP]=0;
23674 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
23675}
23676
23677if (( num_arry[TEST_ARG_2_STEP]))
23678{
23679for (test_index=num_arry[TEST_ARG_2_STEP];test_index<test_index_max ;test_index++ )
23680{
23681 printf("\ntest_index=%d\n",test_index);
23682 if ((((test_index_enable)>>(test_index-1))&1) == 0)
23683 {
23684 num_arry[TEST_ARG_2_STEP]=((num_arry[TEST_ARG_2_STEP])+1);//why can not use ++
23685 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
23686 continue;
23687 }
23688 {
23689 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
23690 {
23691 nibble_save_offset=0;
23692 nibble_max=10;
23693 if ((dram_type == CONFIG_DDR_TYPE_LPDDR3))
23694 {
23695 nibble_mask[0]= 0x3e0;
23696 }
23697 if ((dram_type == CONFIG_DDR_TYPE_LPDDR4))
23698 {
23699 nibble_mask[0]= 0x210;
23700 if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0))
23701 nibble_mask[0]= 0x3f0;
23702 }
23703 test_left_max_init_value=64;
23704 test_right_max_init_value=64;
23705 }
23706 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
23707 {
23708 nibble_save_offset=10;
23709 nibble_max=16;
23710 if ((cs1_test_size == 0))
23711 {
23712 nibble_mask[0]= 0xff00;
23713 }
23714 test_left_max_init_value=16;
23715 test_right_max_init_value=16;
23716 }
23717 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
23718 {
23719 nibble_save_offset=(10)+(16);
23720 if ((cs1_test_size == 0))
23721 {
23722 nibble_mask[0]= 0xff00;
23723 }
23724 nibble_max=16;
23725 test_left_max_init_value=16;
23726 test_right_max_init_value=16;
23727 }
23728 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
23729 {
23730 nibble_save_offset=0;
23731 nibble_max=72;
23732 if ((cs1_test_size == 0))
23733 {
23734 nibble_mask[1]= 0xfffffff0;
23735 nibble_mask[2]= 0xffffffff;
23736 }
23737 test_left_max_init_value=16;
23738 test_right_max_init_value=16;
23739 }
23740 if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
23741 {
23742 nibble_save_offset=0;
23743 nibble_max=72;
23744 if ((cs1_test_size == 0))
23745 {
23746 nibble_mask[1]= 0xfffffff0;
23747 nibble_mask[2]= 0xffffffff;
23748 }
23749
23750 test_left_max_init_value=64;
23751 test_right_max_init_value=64;}
23752 //nibble_max=8;//
23753 // if(nibble_max>30) can not over sticky register size
23754 // nibble_max=30;
23755 for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++))
23756 {
23757 if (nibble_step<32)
23758 {
23759 if (((nibble_mask[0])>>nibble_step)&1)
23760 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23761 }
23762 else if (nibble_step<64)
23763 {
23764 if (((nibble_mask[1])>>(nibble_step-32))&1)
23765 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23766 }
23767 else if (nibble_step<96)
23768 {
23769 if (((nibble_mask[2])>>(nibble_step-64))&1)
23770 num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
23771 }
23772 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23773 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23774 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23775 }
23776 }
23777
23778{
23779 for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++))
23780 {
23781 if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 4)
23782 continue;
23783 printf("nibble_step ==%d\n",nibble_step);
23784
23785 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
23786 {
23787 if (nibble_step%2)
23788 {
23789 //nibble_save_offset
23790 //num_arry[TEST_ARG_2_STEP]=1;
23791 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23792 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
23793 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
23794 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23795 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
23796 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
23797 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23798 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23799 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23800 //nibble_step++;
23801 continue;
23802 }
23803 }
23804 test_start_addr=cs0_test_start;
23805 ddr_test_size=cs0_test_size;
23806 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
23807 {
23808 test_start_addr=cs0_test_start;
23809 ddr_test_size=cs0_test_size;
23810 }
23811
23812 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
23813 {
23814 if (nibble_step>7)
23815 {
23816 test_start_addr=cs1_test_start;
23817 ddr_test_size=cs1_test_size;
23818 }
23819 }
23820 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
23821 {
23822 if (nibble_step>7)
23823 {
23824 test_start_addr=cs1_test_start;
23825 ddr_test_size=cs1_test_size;
23826 }
23827 }
23828 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
23829 {
23830 if (nibble_step>35)
23831 {
23832 test_start_addr=cs1_test_start;
23833 ddr_test_size=cs1_test_size;
23834 }
23835 }
23836 if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
23837 {
23838 if (nibble_step>35)
23839 {
23840 test_start_addr=cs1_test_start;
23841 ddr_test_size=cs1_test_size;
23842 }
23843 }
23844 {
23845 if (nibble_step<32)
23846 {
23847 nibble_mask[0]=((0xffffffff)&(~(1<<nibble_step)));
23848 nibble_mask[1]=((0xffffffff));
23849 nibble_mask[2]=((0xffffffff));
23850 }
23851 else if (nibble_step<64)
23852 {
23853 nibble_mask[0]=((0xffffffff));
23854 nibble_mask[1]=((0xffffffff)&(~(1<<(nibble_step-32))));
23855 nibble_mask[2]=((0xffffffff));
23856 }
23857 else if (nibble_step<96)
23858 {
23859 nibble_mask[0]=((0xffffffff));
23860 nibble_mask[1]=((0xffffffff));
23861 nibble_mask[2]=((0xffffffff)&(~(1<<(nibble_step-64))));
23862 }
23863 }
23864
23865 ddr_test_watchdog_enable(watchdog_time_s); //s
23866 printf("\nenable %ds watchdog \n",watchdog_time_s);
23867 if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff)
23868 ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0)
23869 ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1) )
23870 {
23871 printf("\nnibble_step ==%d ", nibble_step);
23872 if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff)
23873 ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0))
23874 {
23875 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=1;
23876 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23877 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23878 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23879
23880 if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0)
23881 {
23882 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
23883 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23884 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23885 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23886 run_command("reset",0);
23887 }
23888 {
23889 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]=
23890 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]-1;
23891 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23892 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
23893 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
23894 }
23895
23896 {
23897 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL;
23898 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23899 TEST_ARG_ERROR_FLAG,
23900 num_arry[TEST_ARG_ERROR_FLAG]);
23901 }
23902
23903 if (all_tighter_enable)
23904 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT,
23905 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
23906 else
23907 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
23908 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
23909 printf("\nstr=%s\n",str);
23910 ddr_test_watchdog_clear();
23911 run_command(str,0);
23912 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
23913 if (temp_test_error)
23914 {
23915 run_command("reset",0);
23916 }
23917 else
23918 {
23919 //
23920 if (!enable_kernel_test)
23921 {
23922 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
23923 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23924 TEST_ARG_ERROR_FLAG,
23925 num_arry[TEST_ARG_ERROR_FLAG]);
23926 run_command("reset",0);
23927 }
23928 else
23929 {
23930 ddr_test_watchdog_enable(kernel_watchdog_s); //s
23931 printf("\nenable %ds watchdog \n",kernel_watchdog_s);
23932 run_command("run storeboot",0);
23933 }
23934 /*
23935 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
23936 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23937 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23938 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23939 run_command("reset",0);
23940 */
23941 }
23942 }
23943 else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1)
23944 {//go on find left edge
23945
23946 if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0)
23947 {
23948 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
23949 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23950 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23951 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23952 run_command("reset",0);
23953 }
23954
23955 if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS)
23956 {
23957 {
23958 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
23959 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23960 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
23961 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
23962 }
23963 {
23964 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL;
23965 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23966 TEST_ARG_ERROR_FLAG,
23967 num_arry[TEST_ARG_ERROR_FLAG]);
23968 }
23969 run_command("reset",0);
23970 }
23971 if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL)
23972 {
23973 {
23974 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]=
23975 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]-1;
23976 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23977 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
23978 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
23979 }
23980 {
23981 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL;
23982 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
23983 TEST_ARG_ERROR_FLAG,
23984 num_arry[TEST_ARG_ERROR_FLAG]);
23985 }
23986 sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
23987 printf( "%s", buf);
23988 if (all_tighter_enable)
23989 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT,
23990 ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
23991 else
23992 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
23993 ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
23994 printf("\nstr=%s\n",str);
23995 ddr_test_watchdog_clear();
23996 run_command(str,0);
23997 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
23998 if (temp_test_error)
23999 {
24000 run_command("reset",0);
24001 }
24002 else
24003 {
24004 //
24005 if (!enable_kernel_test)
24006 {
24007 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
24008 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24009 TEST_ARG_ERROR_FLAG,
24010 num_arry[TEST_ARG_ERROR_FLAG]);
24011 run_command("reset",0);
24012 }
24013 else
24014 {
24015 ddr_test_watchdog_enable(kernel_watchdog_s); //s
24016 printf("\nenable %ds watchdog \n",kernel_watchdog_s);
24017 run_command("run storeboot",0);
24018 }
24019 /*
24020 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
24021 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24022 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24023 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24024 run_command("reset",0);
24025 */
24026 }
24027 }
24028 }
24029 // run_command("reset",0);
24030 }
24031
24032 if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2) ||
24033 (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3))
24034 {
24035 printf("\nnibble_step ==%d ", nibble_step);
24036 if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2)
24037 ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==2))
24038 {
24039 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=3;
24040 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24041 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24042 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24043
24044 if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0)
24045 {
24046 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
24047 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24048 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24049 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24050 run_command("reset",0);
24051 }
24052 {
24053 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]=
24054 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]-1;
24055 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24056 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
24057 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
24058 }
24059
24060 {
24061 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL;
24062 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24063 TEST_ARG_ERROR_FLAG,
24064 num_arry[TEST_ARG_ERROR_FLAG]);
24065 }
24066 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_RIGHT,
24067 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
24068 printf("\nstr=%s\n",str);
24069 ddr_test_watchdog_clear();
24070 run_command(str,0);
24071 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
24072 if (temp_test_error)
24073 {
24074 run_command("reset",0);
24075 }
24076 else
24077 {
24078 //
24079 if (!enable_kernel_test)
24080 {
24081 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
24082 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24083 TEST_ARG_ERROR_FLAG,
24084 num_arry[TEST_ARG_ERROR_FLAG]);
24085 run_command("reset",0);
24086 }
24087 else
24088 {
24089 ddr_test_watchdog_enable(kernel_watchdog_s); //s
24090 printf("\nenable %ds watchdog \n",kernel_watchdog_s);
24091 run_command("run storeboot",0);
24092 }
24093 /*
24094 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
24095 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24096 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24097 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24098 run_command("reset",0);
24099 */
24100 }
24101 }
24102 else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3)
24103 {//go on find left edge
24104 if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0)
24105 {
24106 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
24107 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24108 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24109 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24110 run_command("reset",0);
24111 }
24112
24113 if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS)
24114 {
24115 {
24116 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
24117 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24118 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24119 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24120 }
24121 {
24122 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL;
24123 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24124 TEST_ARG_ERROR_FLAG,
24125 num_arry[TEST_ARG_ERROR_FLAG]);
24126 }
24127 run_command("reset",0);
24128 }
24129 if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL)
24130 {
24131 {
24132 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]=
24133 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]-1;
24134 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24135 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
24136 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
24137 }
24138 {
24139 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL;
24140 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24141 TEST_ARG_ERROR_FLAG,
24142 num_arry[TEST_ARG_ERROR_FLAG]);
24143 }
24144 sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]));
24145 printf( "%s", buf);
24146 sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_RIGHT,
24147 ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]));
24148 printf("\nstr=%s\n",str);
24149 ddr_test_watchdog_clear();
24150 run_command(str,0);
24151 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
24152 if (temp_test_error)
24153 {
24154 run_command("reset",0);
24155 }
24156 else
24157 {
24158 if (!enable_kernel_test)
24159 {
24160 num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
24161 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24162 TEST_ARG_ERROR_FLAG,
24163 num_arry[TEST_ARG_ERROR_FLAG]);
24164 run_command("reset",0);
24165 }
24166 else
24167 {
24168 ddr_test_watchdog_enable(kernel_watchdog_s); //s
24169 printf("\nenable %ds watchdog \n",kernel_watchdog_s);
24170 run_command("run storeboot",0);
24171 }
24172
24173 /*
24174 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
24175 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
24176 (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
24177 num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
24178 run_command("reset",0);
24179 */
24180 }
24181 }
24182 }
24183 // run_command("reset",0);
24184 }
24185
24186 ddr_test_watchdog_disable(); //s
24187 {
24188 printf("close watchdog\n");
24189 }
24190 }
24191
24192 printf("11num_arry[TEST_ARG_2_STEP]==%d\n",num_arry[TEST_ARG_2_STEP]);
24193 num_arry[TEST_ARG_2_STEP]=(num_arry[TEST_ARG_2_STEP])+1;
24194 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
24195 printf("22num_arry[TEST_ARG_2_STEP]==%d\n",num_arry[TEST_ARG_2_STEP]);
24196 //}
24197
24198 ddr_test_watchdog_disable(); //s
24199 printf("close watchdog\n");
24200 //}
24201 //for(test_index=1;test_index<test_index_max ;test_index++ )
24202 {
24203 unsigned int ui_1_32_100step= 0;
24204 unsigned int bdlr_100step= 0;
24205 ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32));
24206 bdlr_100step=get_bdlr_100step(global_ddr_clk);
24207 //if((((test_index_enable)>>(test_index-1))&1)==0)
24208
24209 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,bdlr_100step=%d ps,ui_1_32_100step=%d ps,\n",0,0,global_ddr_clk,
24210 bdlr_100step,ui_1_32_100step);
24211
24212 printf("\n test result index==");
24213 printf("%08d",test_index);
24214
24215 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
24216 printf(" ac window:");
24217 printf(" step_size ps==");
24218 printf("%08d",ui_1_32_100step);
24219 printf("/100 ps ");
24220 }
24221 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
24222 printf(" txdqs window:");
24223 printf(" step_size ps==");
24224 printf("%08d",ui_1_32_100step);
24225 printf("/100 ps ");
24226 }
24227 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
24228 printf(" rx_clk_window:");
24229 printf(" step_size ps==");
24230 printf("%08d",ui_1_32_100step);
24231 printf("/100 ps ");
24232 }
24233 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
24234 printf(" tx_bit_dq_window:");
24235 printf(" step_size ps==");
24236 printf("%08d",ui_1_32_100step);
24237 printf("/100 ps ");
24238 }
24239 if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
24240 printf(" rx_bit_dq_window");
24241 printf(" step_size ps==");
24242 printf("%08d",bdlr_100step);//480ps
24243 printf("/100 ps ");
24244 }
24245 printf("ddr clk frequency : ");
24246 printf("%08d",(global_ddr_clk));
24247 printf("Mhz ");
24248 printf(string_print_flag);
24249 printf("index org min max left right dec vref_range vref_count");
24250 printf(string_print_flag);
24251
24252 char delay_left_margin=0;
24253 char delay_right_margin=0;
24254 for ( nibble_step=0;nibble_step<nibble_max;nibble_step++)
24255 {
24256 //serial_put_dec_out_align(delay_martix[count].add_index,8);
24257 printf("%08d",nibble_step);
24258 printf(" ");
24259 printf("%08d",0);
24260 //serial_puts(" ");
24261 //if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) )
24262 {
24263 {
24264 printf(" ");
24265 printf("%08d",0//num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN]
24266 );
24267 }
24268 }
24269 {
24270 {
24271 printf(" ");
24272 printf("%08d",0//num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]
24273 );
24274 }
24275 }
24276
24277 // delay_left_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN])?
24278 // (num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]-num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN]):0);
24279 // delay_right_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG])?
24280 // (num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]-num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]):0);
24281 delay_left_margin=num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)];
24282 delay_right_margin=num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)];
24283 printf(" ");
24284 printf("%08d",delay_left_margin);
24285
24286 //serial_put_dec_out_align((delay_martix[count].delay_org>delay_martix[count].delay_min)?(delay_martix[count].delay_org-delay_martix[count].delay_min):0,8);
24287 printf(" ");
24288 printf("%08d",delay_right_margin);
24289 //serial_put_dec_out_align((delay_martix[count].delay_max>delay_martix[count].delay_org)?(delay_martix[count].delay_max-delay_martix[count].delay_org):0,8);
24290 printf(" ");
24291 printf("%08d",0);
24292 printf(" ");
24293 printf("%08d",0);
24294 printf(" 2d-eye"); //p_dev->cur_type
24295 printf(" dramtype ");
24296 printf("%08d",0);
24297 printf(" ");
24298 printf("%08d",(global_ddr_clk));
24299 printf(" M bdl ");
24300 printf("%08d",bdlr_100step);//480ps
24301 printf(" /100 ps ");
24302 printf("1/32step== ");
24303 printf("%08d",ui_1_32_100step);
24304 printf(" /100 ps ");
24305 //serial_puts("bit_init_value ");
24306 //serial_put_dec_out_align((p_dev->ddr_global_message.stick_dmc_ddr_window_test_read_per_bit_init_value),4);
24307 //if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY){
24308 //serial_puts("txdqsdly_second_tune_min_value ");
24309 //serial_put_dec_out_align(txdqsdly_second_tune_value[count],4);
24310 //}
24311 printf(string_print_flag);
24312 //serial_puts("\n");
24313 }
24314 }
24315}
24316}
24317}
24318
24319 if (config_register == 1)
24320 {
24321 if (num_arry[TEST_ARG_2_STEP] == 0)
24322 {
24323 num_arry[TEST_ARG_2_STEP]=1;
24324 ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
24325 }
24326 }
24327 return reg_value;
24328}
24329#else
24330int do_ddr_test_dqs_window_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
24331{
24332 printf("\nEnterddr_test_dqs_window function\n");
24333 printf("\nddr_test_cmd 0x27 a 0 0x80000 ns lane_disable add_test_size --- watchdog should >15s\n");
24334 unsigned int channel_a_en = 0;
24335 unsigned int channel_b_en = 0;
24336 // unsigned int reg_add=0;
24337 // unsigned int reg_base_adj=0;
24338
24339 unsigned int lane_step= 0;
24340 unsigned int reg_value= 0;
24341 //int argc2;
24342 //char * argv2[30];
24343 char *endp;
24344 char *buf;
24345 buf="";
24346
24347 if (argc == 2)
24348 {
24349 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
24350
24351 {channel_a_en = 1;
24352 }
24353 else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
24354
24355 {channel_b_en = 1;
24356 }
24357
24358
24359 }
24360 if (argc > 2)
24361 {
24362 if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
24363
24364 {channel_a_en = 1;
24365 }
24366 if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
24367
24368 {channel_b_en = 1;
24369 }
24370 }
24371 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
24372 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
24373 if (argc >3) {
24374 ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
24375 if (*argv[3] == 0 || *endp != 0)
24376 {
24377 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
24378 }
24379 }
24380
24381
24382
24383 if (argc >4) {
24384 watchdog_time_s = simple_strtoull_ddr(argv[4], &endp, 0);
24385 if (*argv[4] == 0 || *endp != 0)
24386 {
24387 watchdog_time_s= 20;
24388 }
24389 }
24390 printf("watchdog_time_s==%d\n",watchdog_time_s);
24391
24392 unsigned int lane_disable= 0;
24393
24394 if (argc >5) {
24395 lane_disable = simple_strtoull_ddr(argv[5], &endp, 0);
24396 if (*argv[5] == 0 || *endp != 0)
24397 {
24398 lane_disable= 0;
24399 }
24400 }
24401 printf("lane_disable==0x%08x\n",lane_disable);
24402
24403 unsigned int add_test_size= DDR_CROSS_TALK_TEST_SIZE;
24404
24405 if (argc >6) {
24406 add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
24407 if (*argv[6] == 0 || *endp != 0)
24408 {
24409 add_test_size= ddr_test_size;
24410 }
24411 }
24412 printf("add_test_size==0x%08x\n",add_test_size);
24413 //argc2=5;
24414 //for(i = 1;i<(argc);i++)
24415 {
24416 //argv2[i-1]=argv[i];
24417 }
24418
24419 //argv2[0]=argv[1];
24420 //argv2[1]=argv[2];
24421 //argv2[2]=argv[3];
24422 //#include <stdio.h>
24423 // unsigned int wr_adj_per[24] ;
24424 //if(1)
24425
24426 printf("\ntest use uboot sticky register\n");
24427
24428 //DMC_STICKY_0
24429
24430
24431 char str[1024]="";
24432 char str_temp1[1024]="";
24433 char str_temp2[1024]="";
24434 //const char *s;
24435 unsigned int str_to_numarry[48];
24436 //str_buf = (char *)malloc(sizeof(char)*1024);
24437
24438 unsigned int *num_arry;
24439 //unsigned int *num_arry_temp;
24440 //unsigned int *num_arry_lane0=NULL;
24441 //unsigned int *num_arry_lane1=NULL;
24442 //unsigned int *num_arry_lane2=NULL;
24443 //unsigned int *num_arry_lane3=NULL;
24444 //char *name_lane0;
24445 //char *name_lane1;
24446 //char *name_lane2;
24447 //char *name_lane3;
24448 num_arry = (unsigned int *)(&str_to_numarry);
24449 int i;
24450 //char *varname; char *env_lcdlr_temp_count;
24451 unsigned int lcdlr_temp_count=0;
24452 // const char *temp_s;const char *temp_s1;
24453 // int value=0;
24454
24455 //#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
24456 //#define DMC_STICKY_MAGIC_0 0x12345678
24457 //#define DMC_STICKY_MAGIC_1 0xabcdbead
24458 //unsigned int dmc_sticky[64];
24459 //unsigned int sticky_reg_base_add=0;
24460 //varname="env_ddrtest_data_lane";
24461 //name_lane0="ddr_test_data_lane0";
24462 //name_lane1="ddr_test_data_lane1";
24463 //name_lane2="ddr_test_data_lane2";
24464 //name_lane3="ddr_test_data_lane3";
24465 //env_lcdlr_temp_count="lcdlr_temp_count";
24466
24467
24468 {//i=0;
24469 //while(s_temp)
24470 {
24471
24472
24473
24474 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
24475
24476 for (i = 0; i < 63; i++) {
24477 dmc_sticky[i]=rd_reg(sticky_reg_base_add+(i<<2));
24478 //printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
24479 }
24480
24481 for (i = 0; i < 48; i++) {
24482 num_arry[i]=dmc_sticky[i];
24483 printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
24484 }
24485
24486 //lcdlr_temp_count=num_arry[5];
24487
24488
24489
24490 }
24491 }
24492
24493
24494
24495
24496 ///*
24497 //if(1)
24498
24499 unsigned int test_arg_0_cmd0 =0; //master cmd
24500 unsigned int test_arg_1_cmd1 =0; //min cmd
24501 unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
24502 unsigned int test_arg_3_freq =0;
24503 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
24504 // unsigned int lane_step= 0;
24505 //char str[24];
24506 unsigned int boot_times=0;
24507
24508 test_arg_0_cmd0=num_arry[0];
24509 test_arg_1_cmd1=num_arry[1];
24510 test_arg_2_step=num_arry[2];
24511 test_arg_3_freq=num_arry[3];
24512 test_arg_4_step_status=num_arry[4];
24513 boot_times=num_arry[5];
24514 lcdlr_temp_count=num_arry[6];
24515 printf("test_arg_0_cmd0==%d\n",test_arg_0_cmd0);
24516 printf("test_arg_0_cmd1==%d\n",test_arg_1_cmd1);
24517 printf("test_arg_2_step==%d\n",test_arg_2_step);
24518 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
24519 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
24520 printf("test_arg_5 boottimes=%d\n",num_arry[5]);
24521 printf("test_arg_6 lcdlr_temp_count=%d\n",num_arry[6]);
24522 printf("test_arg_7=%d\n",num_arry[7]);
24523
24524 if ((num_arry[7] == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
24525 {boot_times++;
24526
24527 }
24528 else
24529 {boot_times=0;
24530 printf("test_sticky is not magic number,boot times==%d\n",boot_times);
24531 // writel(DMC_STICKY_MAGIC_0,(sticky_reg_base_add+(6<<2)));
24532 writel(DMC_STICKY_MAGIC_1,(sticky_reg_base_add+(7<<2)));
24533 test_arg_2_step=0;
24534 num_arry[6]=0;
24535 lcdlr_temp_count=0;
24536 //return 1;
24537 }
24538 num_arry[5]=boot_times;
24539
24540 writel(num_arry[5],(sticky_reg_base_add+(5<<2)));
24541
24542 //if(test_arg_2_step)
24543 if (test_arg_2_step)
24544 {
24545 if (test_arg_3_freq != global_ddr_clk) //
24546 {
24547 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
24548 sprintf(str,"d2pll %d",test_arg_3_freq);
24549 printf("\nstr=%s\n",str);
24550 run_command(str,0);
24551 while (1) ;
24552 }
24553 }
24554 if (test_arg_2_step == 0)
24555 {
24556 {
24557 test_arg_0_cmd0=0x22;
24558 test_arg_1_cmd1=0;
24559 test_arg_2_step=1;
24560 test_arg_3_freq=global_ddr_clk;
24561 test_arg_4_step_status=0;
24562 lcdlr_temp_count=0;
24563 num_arry[0]=test_arg_0_cmd0;
24564 num_arry[1]=test_arg_1_cmd1;
24565 num_arry[2]=test_arg_2_step;
24566 num_arry[3]=test_arg_3_freq;
24567 num_arry[4]=test_arg_4_step_status;
24568 num_arry[5]=boot_times;
24569 lcdlr_temp_count=num_arry[6];
24570 num_arry[6]=lcdlr_temp_count;
24571 num_arry[7]=DMC_STICKY_MAGIC_1;
24572 for (i = 8; i < 48; i++) {
24573 num_arry[i]=0;
24574 }
24575
24576 for (lane_step = 0; lane_step < 4; lane_step++)
24577 {
24578 //if(lane_step%2)
24579 {
24580#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
24581 dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
24582 DDR0_PUB_DX0LCDLR1)
24583 +DDR0_PUB_DX0LCDLR1))&0xff);
24584 dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
24585 DDR0_PUB_DX0LCDLR1)
24586 +DDR0_PUB_DX0LCDLR1))>>8)&0xff);
24587#else
24588 dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
24589 DDR0_PUB_DX0LCDLR1)
24590 +DDR0_PUB_DX0LCDLR1))&0x1ff);
24591 dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
24592 DDR0_PUB_DX0LCDLR3)
24593 +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff);
24594
24595 printf("lcdlr1 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
24596 DDR0_PUB_DX0LCDLR1)
24597 +DDR0_PUB_DX0LCDLR1),
24598 ((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
24599 DDR0_PUB_DX0LCDLR1)
24600 +DDR0_PUB_DX0LCDLR1))&0x1ff),dq_lcd_bdl_value_wdq_org_a[lane_step]);
24601 printf("lcdlr3 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
24602 DDR0_PUB_DX0LCDLR3)
24603 +DDR0_PUB_DX0LCDLR3),
24604 (((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
24605 DDR0_PUB_DX0LCDLR3)
24606 +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff),dq_lcd_bdl_value_rdqs_org_a[lane_step]);
24607#endif
24608
24609 //printf("lcdlr1 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
24610 //DDR0_PUB_DX0LCDLR1)
24611 //+DDR0_PUB_DX0LCDLR1));
24612 //printf("lcdlr3 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
24613 //DDR0_PUB_DX0LCDLR3)
24614 //+DDR0_PUB_DX0LCDLR3));
24615 //dq_lcd_bdl_value_rdqs_org_a[lane_step]=0;
24616 dq_lcd_bdl_value_rdqs_min_a[lane_step]=0xffff;
24617 dq_lcd_bdl_value_rdqs_max_a[lane_step]=0xffff;
24618 dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
24619 }
24620 //else
24621 {
24622 //dq_lcd_bdl_value_wdq_org_a[lane_step]=0;
24623 dq_lcd_bdl_value_wdq_min_a[lane_step]=0xffff;
24624 dq_lcd_bdl_value_wdq_max_a[lane_step]=0xffff;
24625 dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
24626 }
24627 }
24628
24629 {
24630 dq_lcd_bdl_value_aclcdlr_org_a=((readl(DDR0_PUB_ACLCDLR))&ACLCDLR_MAX);
24631 dq_lcd_bdl_value_aclcdlr_min_a=0xffff;
24632 dq_lcd_bdl_value_aclcdlr_max_a=0xffff;
24633 dq_lcd_bdl_value_aclcdlr_status_a=0;
24634 dq_lcd_bdl_value_bdlr0_org_a=((readl(DDR0_PUB_ACBDLR0))&ACBDLR_MAX);
24635 dq_lcd_bdl_value_bdlr0_min_a=0xffff;
24636 dq_lcd_bdl_value_bdlr0_max_a=0xffff;
24637 dq_lcd_bdl_value_bdlr0_status_a=0;
24638 }
24639
24640
24641
24642#if 1 //( CONFIG_DDR_PHY<P_DDR_PHY_905X)
24643 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
24644 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
24645 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
24646 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
24647 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
24648 lane_disable= lane_disable|1;
24649 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
24650 lane_disable= lane_disable|(1<<1);
24651 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
24652 lane_disable= lane_disable|(1<<2);
24653 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
24654 lane_disable= lane_disable|(1<<3);
24655
24656#endif
24657 if (lane_disable)
24658 {if(lane_disable&0x1){
24659 dq_lcd_bdl_value_wdq_status_a[0]=4;
24660 dq_lcd_bdl_value_rdqs_status_a[0]=4;
24661 }
24662 if (lane_disable&0x2) {
24663 dq_lcd_bdl_value_wdq_status_a[1]=4;
24664 dq_lcd_bdl_value_rdqs_status_a[1]=4;
24665 }
24666 if (lane_disable&0x4) {
24667 dq_lcd_bdl_value_wdq_status_a[2]=4;
24668 dq_lcd_bdl_value_rdqs_status_a[2]=4;
24669 }
24670 if (lane_disable&0x8) {
24671 dq_lcd_bdl_value_wdq_status_a[3]=4;
24672 dq_lcd_bdl_value_rdqs_status_a[3]=4;
24673 }
24674 printf("lane_disable==%x\n",lane_disable);
24675 if (lane_disable&0x10) {
24676 dq_lcd_bdl_value_aclcdlr_status_a=4;
24677 printf("dq_lcd_bdl_value_aclcdlr_status_a==%x\n",dq_lcd_bdl_value_aclcdlr_status_a);
24678 }
24679 if (lane_disable&0x20) {
24680 dq_lcd_bdl_value_bdlr0_status_a=4;
24681 printf("dq_lcd_bdl_value_bdlr0_status_a==%x\n",dq_lcd_bdl_value_bdlr0_status_a);
24682
24683 }
24684 }
24685
24686 {
24687 for (lane_step = 0; lane_step < 4; lane_step++)
24688
24689
24690 {
24691 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
24692 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
24693 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
24694 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
24695 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
24696 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
24697 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
24698 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
24699 }
24700
24701
24702
24703
24704 lane_step=4;
24705 {
24706 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
24707 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
24708 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
24709 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
24710 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
24711 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
24712 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
24713 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
24714 }
24715 }
24716
24717
24718
24719 }
24720
24721
24722
24723
24724 for (i = 0; i < 48; i++) {
24725 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24726 sprintf(str_temp2,"0x%08x",num_arry[i]);
24727 //env_set(str_temp1, str_temp2);
24728 //run_command("save",0);
24729 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24730 }
24731
24732
24733
24734 }
24735
24736 test_arg_2_step++;
24737 num_arry[2]=test_arg_2_step;
24738 sprintf(str, "0x%08x", num_arry[0]);
24739 printf("%d %d\n", 0,num_arry[0]);
24740 for (i = 1; i < 48; i++) {
24741 //num_arry[i]=0;
24742 sprintf(str, "%s;0x%08x", str,num_arry[i]);
24743 printf("%d %d\n", i,num_arry[i]);
24744
24745 }
24746 //sprintf(str, "%lx", value);
24747 printf("%s", str);
24748 // env_set(varname, str);
24749 //run_command("save",0);
24750
24751 for (i = 0; i < 48; i++) {
24752
24753 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24754 }
24755
24756
24757 for (i = 8; i < 48; i++) {
24758 num_arry[i]=readl((sticky_reg_base_add+(i<<2)));
24759 printf("ddr_test_data_num_%04d==%d\n",i,num_arry[i]);
24760 }
24761
24762 ///*
24763 {
24764 for (lane_step = 0; lane_step < 4; lane_step++)
24765 {
24766 {
24767 dq_lcd_bdl_value_wdq_org_a[lane_step]=num_arry[8+lane_step*4*2+0];
24768 dq_lcd_bdl_value_wdq_min_a[lane_step]=num_arry[8+lane_step*4*2+1];
24769 dq_lcd_bdl_value_wdq_max_a[lane_step]=num_arry[8+lane_step*4*2+2];
24770 dq_lcd_bdl_value_wdq_status_a[lane_step]=num_arry[8+lane_step*4*2+3];
24771 }
24772 {
24773 dq_lcd_bdl_value_rdqs_org_a[lane_step]=num_arry[8+lane_step*4*2+4];
24774 dq_lcd_bdl_value_rdqs_min_a[lane_step]=num_arry[8+lane_step*4*2+5];
24775 dq_lcd_bdl_value_rdqs_max_a[lane_step]=num_arry[8+lane_step*4*2+6];
24776 dq_lcd_bdl_value_rdqs_status_a[lane_step]=num_arry[8+lane_step*4*2+7];
24777 }
24778
24779
24780 }
24781 lane_step=4;
24782 {
24783 dq_lcd_bdl_value_aclcdlr_org_a=num_arry[8+lane_step*4*2+0];
24784 dq_lcd_bdl_value_aclcdlr_min_a=num_arry[8+lane_step*4*2+1];
24785 dq_lcd_bdl_value_aclcdlr_max_a=num_arry[8+lane_step*4*2+2];
24786 dq_lcd_bdl_value_aclcdlr_status_a=num_arry[8+lane_step*4*2+3];
24787 dq_lcd_bdl_value_bdlr0_org_a=num_arry[8+lane_step*4*2+4];
24788 dq_lcd_bdl_value_bdlr0_min_a=num_arry[8+lane_step*4*2+5];
24789 dq_lcd_bdl_value_bdlr0_max_a=num_arry[8+lane_step*4*2+6];
24790 dq_lcd_bdl_value_bdlr0_status_a=num_arry[8+lane_step*4*2+7];
24791 }
24792 }
24793 //*/
24794
24795
24796
24797
24798 if (channel_a_en)
24799 {
24800
24801 //*(char *)(argv2[0])="a";
24802 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
24803 printf("\ntest dqs window lane a\n");
24804 for ((lane_step=0);(lane_step<4);(lane_step++))
24805 {
24806 ddr_test_watchdog_enable(watchdog_time_s); //s
24807 printf("\nenable %ds watchdog \n",watchdog_time_s);
24808
24809 /*
24810 {
24811 lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
24812 sprintf(buf, "0x%08x", lcdlr_temp_count);
24813 printf( "%s", buf);
24814 env_set(env_lcdlr_temp_count, buf);
24815 run_command("save",0);
24816 }
24817 */
24818 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
24819 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0)
24820 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
24821 )
24822 {
24823 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
24824 ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0))
24825 { dq_lcd_bdl_value_wdq_status_a[lane_step]=1;
24826 {
24827 {
24828 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
24829 i=8+lane_step*8+3;
24830 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24831 sprintf(str_temp2,"0x%08x",num_arry[i]);
24832 // env_set(str_temp1, str_temp2);
24833 //run_command("save",0);
24834 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24835 }
24836 lcdlr_temp_count=0;
24837 sprintf(buf, "0x%08x", lcdlr_temp_count);
24838 printf( "%s", buf);
24839 // env_set(env_lcdlr_temp_count, buf);
24840 // run_command("save",0);
24841 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
24842 }
24843
24844 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d 1",ddr_test_size,( lane_step*2+0),2);
24845 printf("\nstr=%s\n",str);
24846 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
24847 //printf("\nstr=%s\n",str);
24848 ddr_test_watchdog_clear();
24849 run_command(str,0);
24850 ddr_test_watchdog_clear();
24851 ddr_udelay(2000000);
24852 dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
24853
24854 }
24855 else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
24856 {
24857 // temp_s= env_get(env_lcdlr_temp_count);
24858 // if(temp_s)
24859 // {
24860 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
24861 //
24862 // }
24863 lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
24864 dq_lcd_bdl_value_wdq_min_a[lane_step]=lcdlr_temp_count;
24865 dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
24866 }
24867
24868 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
24869 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
24870 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
24871 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
24872
24873 //ddr_udelay(1000000);
24874 //num_to_env(varname,num_arry);
24875 {
24876 i=8+lane_step*8+1;
24877 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24878 sprintf(str_temp2,"0x%08x",num_arry[i]);
24879 // env_set(str_temp1, str_temp2);
24880 //run_command("save",0);
24881 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24882 i=8+lane_step*8+3;
24883 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24884 sprintf(str_temp2,"0x%08x",num_arry[i]);
24885 // env_set(str_temp1, str_temp2);
24886 // run_command("save",0);
24887 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24888 }
24889
24890
24891 run_command("reset",0);
24892 }
24893
24894 if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 2) ||
24895 (dq_lcd_bdl_value_wdq_status_a[lane_step]==3))
24896 {
24897 // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
24898 // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
24899 // num_to_env(varname,num_arry);
24900 // run_command("reset",0);
24901 // }
24902
24903 {
24904 if (dq_lcd_bdl_value_wdq_status_a[lane_step] == 2)
24905 { dq_lcd_bdl_value_wdq_status_a[lane_step]=3;
24906 {
24907 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
24908 i=8+lane_step*8+3;
24909 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24910 sprintf(str_temp2,"0x%08x",num_arry[i]);
24911 // env_set(str_temp1, str_temp2);
24912 //run_command("save",0);
24913 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24914 }
24915 {
24916 lcdlr_temp_count=0;
24917 sprintf(buf, "0x%08x", lcdlr_temp_count);
24918 printf( "%s", buf);
24919 // env_set(env_lcdlr_temp_count, buf);
24920 // run_command("save",0);
24921 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
24922 }
24923
24924 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d 1",ddr_test_size,( lane_step*2+0),1);
24925 printf("\nstr=%s\n",str);
24926 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
24927 //printf("\nstr=%s\n",str);
24928 ddr_test_watchdog_clear();
24929 run_command(str,0);
24930 ddr_test_watchdog_clear();
24931 ddr_udelay(2000000);
24932 dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
24933
24934 }
24935 else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==3)
24936 {
24937 // temp_s= env_get(env_lcdlr_temp_count);
24938 // if(temp_s)
24939 // {
24940 //
24941 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
24942 // }
24943 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
24944 dq_lcd_bdl_value_wdq_max_a[lane_step]=lcdlr_temp_count;
24945 dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
24946 }
24947
24948 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
24949 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
24950 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
24951 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
24952 //ddr_udelay(1000000);
24953 //num_to_env(varname,num_arry);
24954 {
24955 i=8+lane_step*8+2;
24956 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24957 sprintf(str_temp2,"0x%08x",num_arry[i]);
24958 // env_set(str_temp1, str_temp2);
24959 //run_command("save",0);
24960 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24961 i=8+lane_step*8+3;
24962 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24963 sprintf(str_temp2,"0x%08x",num_arry[i]);
24964 // env_set(str_temp1, str_temp2);
24965 // run_command("save",0);
24966 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24967 }
24968
24969 run_command("reset",0);
24970 }
24971
24972 }
24973
24974
24975 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
24976 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0)
24977 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
24978 )
24979 {
24980 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
24981 ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
24982 { dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
24983 {
24984 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
24985 i=8+lane_step*8+7;
24986 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
24987 sprintf(str_temp2,"0x%08x",num_arry[i]);
24988 // env_set(str_temp1, str_temp2);
24989 //run_command("save",0);
24990 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
24991 }
24992 {
24993 lcdlr_temp_count=0;
24994 sprintf(buf, "0x%08x", lcdlr_temp_count);
24995 printf( "%s", buf);
24996 // env_set(env_lcdlr_temp_count, buf);
24997 // run_command("save",0);
24998 //i=6;
24999 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25000 }
25001
25002 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d 1",ddr_test_size,( lane_step*2+1),2);
25003 printf("\nstr=%s\n",str);
25004 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25005 //printf("\nstr=%s\n",str);
25006 ddr_test_watchdog_clear();
25007 run_command(str,0);
25008 ddr_test_watchdog_clear();
25009 ddr_udelay(2000000);
25010 dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
25011
25012 }
25013 else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
25014 {
25015 // temp_s= env_get(env_lcdlr_temp_count);
25016 // if(temp_s)
25017 // {
25018 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25019 // }
25020 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
25021 dq_lcd_bdl_value_rdqs_min_a[lane_step]=lcdlr_temp_count;
25022 dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
25023 }
25024
25025 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25026 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25027 //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25028 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25029 //ddr_udelay(1000000);
25030 //num_to_env(varname,num_arry);
25031 {
25032 i=8+lane_step*8+5;
25033 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25034 sprintf(str_temp2,"0x%08x",num_arry[i]);
25035 // env_set(str_temp1, str_temp2);
25036 //run_command("save",0);
25037 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25038 i=8+lane_step*8+7;
25039 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25040 sprintf(str_temp2,"0x%08x",num_arry[i]);
25041 // env_set(str_temp1, str_temp2);
25042 // run_command("save",0);
25043 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25044 }
25045
25046 run_command("reset",0);
25047 }
25048
25049 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2) ||
25050 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3))
25051 {
25052
25053 {
25054 if (dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2)
25055 {
25056
25057 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
25058 {
25059 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25060 i=8+lane_step*8+7;
25061 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25062 sprintf(str_temp2,"0x%08x",num_arry[i]);
25063 // env_set(str_temp1, str_temp2);
25064 //run_command("save",0);
25065 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25066 }
25067
25068 {
25069 lcdlr_temp_count=0;
25070 sprintf(buf, "0x%08x", lcdlr_temp_count);
25071 printf( "%s", buf);
25072 // env_set(env_lcdlr_temp_count, buf);
25073 // run_command("save",0);
25074 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25075 }
25076
25077 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d 1",ddr_test_size,( lane_step*2+1),1);
25078 printf("\nstr=%s\n",str);
25079 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25080 //printf("\nstr=%s\n",str);
25081 ddr_test_watchdog_clear();
25082 run_command(str,0);
25083 ddr_test_watchdog_clear();
25084 ddr_udelay(2000000);
25085 dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
25086
25087 }
25088 else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3)
25089 {
25090 // temp_s= env_get(env_lcdlr_temp_count);
25091 // if(temp_s)
25092 // {
25093 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25094 // }
25095 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
25096 dq_lcd_bdl_value_rdqs_max_a[lane_step]=lcdlr_temp_count;
25097 dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
25098 }
25099
25100 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25101 //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25102 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25103 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25104 //ddr_udelay(1000000);
25105 // num_to_env(varname,num_arry);
25106
25107 {
25108 i=8+lane_step*8+6;
25109 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25110 sprintf(str_temp2,"0x%08x",num_arry[i]);
25111 // env_set(str_temp1, str_temp2);
25112 //run_command("save",0);
25113 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25114 i=8+lane_step*8+7;
25115 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25116 sprintf(str_temp2,"0x%08x",num_arry[i]);
25117 // env_set(str_temp1, str_temp2);
25118 // run_command("save",0);
25119 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25120 }
25121 run_command("reset",0);
25122 }
25123
25124 }
25125
25126 /*
25127 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
25128 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
25129 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
25130 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
25131 printf("\nstr=%s\n",str);
25132 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25133 //printf("\nstr=%s\n",str);
25134 ddr_test_watchdog_clear();
25135 run_command(str,0);
25136 ddr_test_watchdog_clear();
25137 dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
25138 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25139 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25140 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25141 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25142 num_to_env(varname,num_arry);
25143 run_command("reset",0);
25144 }
25145
25146 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
25147 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
25148 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
25149 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
25150 printf("\nstr=%s\n",str);
25151 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25152 //printf("\nstr=%s\n",str);
25153 ddr_test_watchdog_clear();
25154 run_command(str,0);
25155 ddr_test_watchdog_clear();
25156 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
25157 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25158 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25159 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25160 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25161 num_to_env(varname,num_arry);
25162 run_command("reset",0);
25163 }
25164 */
25165
25166
25167 ddr_test_watchdog_disable(); //s
25168 {printf("close watchdog\n");
25169 }
25170
25171
25172 }
25173
25174
25175
25176 }
25177
25178 if (channel_a_en)
25179 {
25180
25181 //*(char *)(argv2[0])="a";
25182 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
25183 printf("\ntest lcdlr ac bdlr window lane a...\n");
25184
25185 {
25186 ddr_test_watchdog_enable(watchdog_time_s); //s
25187 printf("\nenable %ds watchdog \n",watchdog_time_s);
25188 printf("\ndq_lcd_bdl_value_aclcdlr_status_a %d \n",dq_lcd_bdl_value_aclcdlr_status_a);
25189 lane_step=4;
25190 //env_lcdlr_temp_count="lcdlr_temp_count_a";
25191 if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
25192 ||(dq_lcd_bdl_value_aclcdlr_status_a==0)
25193 ||(dq_lcd_bdl_value_aclcdlr_status_a==1)
25194 )
25195 {
25196 if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
25197 ||(dq_lcd_bdl_value_aclcdlr_status_a==0))
25198 { dq_lcd_bdl_value_aclcdlr_status_a=1;
25199 {
25200 {
25201 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
25202 i=8+lane_step*8+3;
25203 printf("aclcdlr_status_a==0x%08x\n",num_arry[i]);
25204 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25205 sprintf(str_temp2,"0x%08x",num_arry[i]);
25206 // env_set(str_temp1, str_temp2);
25207 //run_command("save",0);
25208 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25209
25210 }
25211 printf("\n222test lcdlr ac bdlr window lane a...\n");
25212 lcdlr_temp_count=0;
25213 sprintf(buf, "0x%08x", lcdlr_temp_count);
25214 printf( "%s", buf);
25215 // env_set(env_lcdlr_temp_count, buf);
25216 // run_command("save",0);
25217 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25218 }
25219
25220 printf("\n333test lcdlr ac bdlr window lane a...\n");
25221 //ddr_tune_aclcdlr_step
25222 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d 1",add_test_size,( 0),2);
25223 printf("\nstr=%s\n",str);
25224 printf("aclcdlr_status_a1==0x%08x\n",num_arry[i]);
25225 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25226 //printf("\nstr=%s\n",str);
25227 ddr_test_watchdog_clear();
25228 run_command(str,0);
25229 ddr_test_watchdog_clear();
25230 ddr_udelay(2000000);
25231 dq_lcd_bdl_value_aclcdlr_status_a=2;
25232
25233 }
25234 else if (dq_lcd_bdl_value_aclcdlr_status_a==1)
25235 {
25236 // temp_s= env_get(env_lcdlr_temp_count);
25237 // if(temp_s)
25238 // {
25239 //lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25240 // }
25241 lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
25242 dq_lcd_bdl_value_aclcdlr_min_a=lcdlr_temp_count;
25243 dq_lcd_bdl_value_aclcdlr_status_a=2;
25244 }
25245
25246 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
25247 num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
25248 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
25249 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
25250
25251 //ddr_udelay(1000000);
25252 //num_to_env(varname,num_arry);
25253 {
25254 i=8+lane_step*8+1;
25255 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25256 sprintf(str_temp2,"0x%08x",num_arry[i]);
25257 // env_set(str_temp1, str_temp2);
25258 //run_command("save",0);
25259 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25260 i=8+lane_step*8+3;
25261 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25262 sprintf(str_temp2,"0x%08x",num_arry[i]);
25263 // env_set(str_temp1, str_temp2);
25264 // run_command("save",0);
25265 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25266 }
25267
25268
25269 run_command("reset",0);
25270 }
25271
25272 if ((dq_lcd_bdl_value_aclcdlr_status_a == 2) ||
25273 (dq_lcd_bdl_value_aclcdlr_status_a==3))
25274 {
25275 // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
25276 // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
25277 // num_to_env(varname,num_arry);
25278 // run_command("reset",0);
25279 // }
25280
25281 {
25282 if (dq_lcd_bdl_value_aclcdlr_status_a == 2)
25283 { dq_lcd_bdl_value_aclcdlr_status_a=3;
25284 {
25285 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
25286 i=8+lane_step*8+3;
25287 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25288 sprintf(str_temp2,"0x%08x",num_arry[i]);
25289 // env_set(str_temp1, str_temp2);
25290 //run_command("save",0);
25291 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25292 }
25293 {
25294 lcdlr_temp_count=0;
25295 sprintf(buf, "0x%08x", lcdlr_temp_count);
25296 printf( "%s", buf);
25297 // env_set(env_lcdlr_temp_count, buf);
25298 // run_command("save",0);
25299 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25300 }
25301
25302 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d 1",add_test_size,( 0),1);
25303 printf("\nstr=%s\n",str);
25304 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25305 //printf("\nstr=%s\n",str);
25306 ddr_test_watchdog_clear();
25307 run_command(str,0);
25308 ddr_test_watchdog_clear();
25309 ddr_udelay(2000000);
25310 dq_lcd_bdl_value_aclcdlr_status_a=4;
25311
25312 }
25313 else if (dq_lcd_bdl_value_aclcdlr_status_a==3)
25314 {
25315 // temp_s= env_get(env_lcdlr_temp_count);
25316 // if(temp_s)
25317 // {
25318 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25319 // }
25320 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
25321 dq_lcd_bdl_value_aclcdlr_max_a=lcdlr_temp_count;
25322 dq_lcd_bdl_value_aclcdlr_status_a=4;
25323 }
25324
25325 num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
25326 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
25327 num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
25328 num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
25329 //ddr_udelay(1000000);
25330 //num_to_env(varname,num_arry);
25331 {
25332 i=8+lane_step*8+2;
25333 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25334 sprintf(str_temp2,"0x%08x",num_arry[i]);
25335 // env_set(str_temp1, str_temp2);
25336 //run_command("save",0);
25337 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25338 i=8+lane_step*8+3;
25339 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25340 sprintf(str_temp2,"0x%08x",num_arry[i]);
25341 // env_set(str_temp1, str_temp2);
25342 // run_command("save",0);
25343 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25344 }
25345
25346 run_command("reset",0);
25347 }
25348
25349 }
25350
25351
25352 if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
25353 ||(dq_lcd_bdl_value_bdlr0_status_a==0)
25354 ||(dq_lcd_bdl_value_bdlr0_status_a==1)
25355 )
25356 {
25357 if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
25358 ||(dq_lcd_bdl_value_bdlr0_status_a==0))
25359 { dq_lcd_bdl_value_bdlr0_status_a=1;
25360 {
25361 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
25362 i=8+lane_step*8+7;
25363 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25364 sprintf(str_temp2,"0x%08x",num_arry[i]);
25365 // env_set(str_temp1, str_temp2);
25366 //run_command("save",0);
25367 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25368 }
25369 {
25370 lcdlr_temp_count=0;
25371 sprintf(buf, "0x%08x", lcdlr_temp_count);
25372 printf( "%s", buf);
25373 // env_set(env_lcdlr_temp_count, buf);
25374 // run_command("save",0);
25375 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25376 }
25377
25378 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d 1",add_test_size,( 1),2);
25379 printf("\nstr=%s\n",str);
25380 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25381 //printf("\nstr=%s\n",str);
25382 ddr_test_watchdog_clear();
25383 run_command(str,0);
25384 ddr_test_watchdog_clear();
25385 ddr_udelay(2000000);
25386 dq_lcd_bdl_value_bdlr0_status_a=2;
25387
25388 }
25389 else if (dq_lcd_bdl_value_bdlr0_status_a==1)
25390 {
25391 // temp_s= env_get(env_lcdlr_temp_count);
25392 // if(temp_s)
25393 // {
25394 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25395 // }
25396 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
25397 dq_lcd_bdl_value_bdlr0_min_a=lcdlr_temp_count;
25398 dq_lcd_bdl_value_bdlr0_status_a=2;
25399 }
25400
25401 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
25402 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
25403 //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25404 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
25405 //ddr_udelay(1000000);
25406 //num_to_env(varname,num_arry);
25407 {
25408 i=8+lane_step*8+5;
25409 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25410 sprintf(str_temp2,"0x%08x",num_arry[i]);
25411 // env_set(str_temp1, str_temp2);
25412 //run_command("save",0);
25413 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25414 i=8+lane_step*8+7;
25415 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25416 sprintf(str_temp2,"0x%08x",num_arry[i]);
25417 // env_set(str_temp1, str_temp2);
25418 // run_command("save",0);
25419 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25420 }
25421
25422 run_command("reset",0);
25423 }
25424
25425 if ((dq_lcd_bdl_value_bdlr0_status_a == 2) ||
25426 (dq_lcd_bdl_value_bdlr0_status_a==3))
25427 {
25428
25429 {
25430 if (dq_lcd_bdl_value_bdlr0_status_a == 2)
25431 {
25432
25433 dq_lcd_bdl_value_bdlr0_status_a=3;
25434 {
25435 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
25436 i=8+lane_step*8+7;
25437 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25438 sprintf(str_temp2,"0x%08x",num_arry[i]);
25439 // env_set(str_temp1, str_temp2);
25440 //run_command("save",0);
25441 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25442 }
25443
25444 {
25445 lcdlr_temp_count=0;
25446 sprintf(buf, "0x%08x", lcdlr_temp_count);
25447 printf( "%s", buf);
25448 // env_set(env_lcdlr_temp_count, buf);
25449 // run_command("save",0);
25450 writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
25451 }
25452
25453 sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d 1",add_test_size,( 1),1);
25454 printf("\nstr=%s\n",str);
25455 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25456 //printf("\nstr=%s\n",str);
25457 ddr_test_watchdog_clear();
25458 run_command(str,0);
25459 ddr_test_watchdog_clear();
25460 ddr_udelay(2000000);
25461 dq_lcd_bdl_value_bdlr0_status_a=4;
25462
25463 }
25464 else if (dq_lcd_bdl_value_bdlr0_status_a==3)
25465 {
25466 // temp_s= env_get(env_lcdlr_temp_count);
25467 // if(temp_s)
25468 // {
25469 // lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
25470 // }
25471 lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
25472 dq_lcd_bdl_value_bdlr0_max_a=lcdlr_temp_count;
25473 dq_lcd_bdl_value_bdlr0_status_a=4;
25474 }
25475
25476 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
25477 //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25478 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
25479 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
25480 //ddr_udelay(1000000);
25481 // num_to_env(varname,num_arry);
25482
25483 {
25484 i=8+lane_step*8+6;
25485 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25486 sprintf(str_temp2,"0x%08x",num_arry[i]);
25487 // env_set(str_temp1, str_temp2);
25488 //run_command("save",0);
25489 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25490 i=8+lane_step*8+7;
25491 sprintf(str_temp1,"ddr_test_data_num_%04d",i);
25492 sprintf(str_temp2,"0x%08x",num_arry[i]);
25493 // env_set(str_temp1, str_temp2);
25494 // run_command("save",0);
25495 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
25496 }
25497 run_command("reset",0);
25498 }
25499
25500 }
25501
25502 /*
25503 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
25504 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
25505 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
25506 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
25507 printf("\nstr=%s\n",str);
25508 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25509 //printf("\nstr=%s\n",str);
25510 ddr_test_watchdog_clear();
25511 run_command(str,0);
25512 ddr_test_watchdog_clear();
25513 dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
25514 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25515 num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25516 //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25517 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25518 num_to_env(varname,num_arry);
25519 run_command("reset",0);
25520 }
25521
25522 if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
25523 (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
25524 {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
25525 sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
25526 printf("\nstr=%s\n",str);
25527 //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
25528 //printf("\nstr=%s\n",str);
25529 ddr_test_watchdog_clear();
25530 run_command(str,0);
25531 ddr_test_watchdog_clear();
25532 dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
25533 num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
25534 //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
25535 num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
25536 num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
25537 num_to_env(varname,num_arry);
25538 run_command("reset",0);
25539 }
25540 */
25541
25542
25543 ddr_test_watchdog_disable(); //s
25544 {printf("close watchdog\n");
25545 }
25546
25547
25548 }
25549
25550
25551
25552 }
25553
25554 if (channel_b_en)
25555 {//*(char *)(argv2[0])="b";
25556 // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
25557 printf("\ntest dqs window lane b\n");
25558 for ((lane_step=0);(lane_step<8);(lane_step++))
25559 {
25560 //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
25561 //printf("\nstr=%s\n",str);
25562 sprintf(str,"ddr_tune_dqs_step b 0 0x%08x %d 1",ddr_test_size,( lane_step));
25563 printf("\nstr=%s\n",str);
25564 run_command(str,0);
25565
25566 }
25567 }
25568
25569 unsigned int acmdlr= 0;
25570 unsigned int delay_step_x100= 0;
25571 if (channel_a_en)
25572 {
25573 acmdlr=((readl((DDR0_PUB_ACMDLR)))&ACLCDLR_MAX);
25574 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
25575 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
25576 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
25577
25578 for ((lane_step=0);(lane_step<4);(lane_step++))
25579 {
25580 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
25581 lane_step,
25582 dq_lcd_bdl_value_wdq_org_a[lane_step],
25583 dq_lcd_bdl_value_wdq_min_a[lane_step],dq_lcd_bdl_value_wdq_max_a[lane_step],
25584 dq_lcd_bdl_value_rdqs_org_a[lane_step],
25585 dq_lcd_bdl_value_rdqs_min_a[lane_step],dq_lcd_bdl_value_rdqs_max_a[lane_step]);
25586 }
25587 {
25588 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
25589 4,
25590 dq_lcd_bdl_value_aclcdlr_org_a,
25591 dq_lcd_bdl_value_aclcdlr_min_a,dq_lcd_bdl_value_aclcdlr_max_a,
25592 dq_lcd_bdl_value_bdlr0_org_a,
25593 dq_lcd_bdl_value_bdlr0_min_a,dq_lcd_bdl_value_bdlr0_max_a);
25594 }
25595 printf("\n\n-----------------------------------------------------------------------------\n\n");
25596 {
25597 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
25598 clk_setup ps| clk_hold ps|adj_percent[100]\n");
25599
25600 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
25601 4,
25602 dq_lcd_bdl_value_aclcdlr_org_a,
25603 (((dq_lcd_bdl_value_aclcdlr_max_a-dq_lcd_bdl_value_aclcdlr_org_a)*delay_step_x100
25604 )/100),
25605 (((dq_lcd_bdl_value_aclcdlr_org_a-dq_lcd_bdl_value_aclcdlr_min_a)*delay_step_x100
25606 )/100),
25607
25608 0,
25609 0,
25610 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
25611 2*dq_lcd_bdl_value_aclcdlr_org_a));
25612 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
25613 4,
25614 dq_lcd_bdl_value_bdlr0_org_a,
25615 0,
25616 0,
25617 (((dq_lcd_bdl_value_bdlr0_org_a-dq_lcd_bdl_value_bdlr0_min_a)*delay_step_x100
25618 )/100),
25619 (((dq_lcd_bdl_value_bdlr0_max_a-dq_lcd_bdl_value_bdlr0_org_a)*delay_step_x100
25620 )/100),
25621
25622 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
25623 2*dq_lcd_bdl_value_bdlr0_org_a));
25624 }
25625 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
25626 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
25627
25628
25629 for ((lane_step=0);(lane_step<4);(lane_step++))
25630 {
25631 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
25632 lane_step,
25633 dq_lcd_bdl_value_wdq_org_a[lane_step],
25634 (((dq_lcd_bdl_value_wdq_max_a[lane_step]-dq_lcd_bdl_value_wdq_org_a[lane_step])*delay_step_x100
25635 )/100),
25636 (((dq_lcd_bdl_value_wdq_org_a[lane_step]-dq_lcd_bdl_value_wdq_min_a[lane_step])*delay_step_x100
25637 )/100),
25638
25639 0,
25640 0,
25641 100*(dq_lcd_bdl_value_wdq_max_a[lane_step]+dq_lcd_bdl_value_wdq_min_a[lane_step])/(
25642 2*dq_lcd_bdl_value_wdq_org_a[lane_step]));
25643
25644 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
25645 lane_step,
25646 dq_lcd_bdl_value_rdqs_org_a[lane_step],
25647 0,
25648 0,
25649
25650 (((dq_lcd_bdl_value_rdqs_org_a[lane_step]-dq_lcd_bdl_value_rdqs_min_a[lane_step])*delay_step_x100
25651 )/100),
25652 (((dq_lcd_bdl_value_rdqs_max_a[lane_step]-dq_lcd_bdl_value_rdqs_org_a[lane_step])*delay_step_x100
25653 )/100),
25654 100*(dq_lcd_bdl_value_rdqs_max_a[lane_step]+dq_lcd_bdl_value_rdqs_min_a[lane_step])/(
25655 2*dq_lcd_bdl_value_rdqs_org_a[lane_step]));
25656
25657
25658
25659 }
25660 }
25661
25662
25663
25664 if (channel_b_en)
25665 {
25666 for ((lane_step=0);(lane_step<4);(lane_step++))
25667 {;
25668 }
25669 }
25670
25671 return reg_value;
25672}
25673
25674
25675unsigned int do_ddr_uboot_window_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
25676{
25677 char *endp;
25678 unsigned temp_count=0;
25679 for (;temp_count<argc;temp_count++)
25680 {
25681 printf("arg[%d]==%s;\n",argc,argv[temp_count]);
25682 }
25683
25684 if (argc >1) {
25685 g_ddr_test_struct->ddr_data_source = simple_strtoull_ddr(argv[1], &endp, 16);
25686 if (*argv[1] == 0 || *endp != 0)
25687 {
25688 g_ddr_test_struct->ddr_data_source = DDR_PARAMETER_SOURCE_FROM_DMC_STICKY;
25689 }
25690 }
25691 if (argc >2) {
25692 g_ddr_test_struct->ddr_data_source = simple_strtoull_ddr(argv[2], &endp, 16);
25693 if (*argv[2] == 0 || *endp != 0)
25694 {
25695 g_ddr_test_struct->ddr_data_test_size = DDR_CROSS_TALK_TEST_SIZE;
25696 }
25697 }
25698 /*
25699 g_ddr_test_struct->ddr_data_source =
25700 g_ddr_test_struct->ddr_data_test_size =
25701 g_ddr_test_struct->ddr_address_test_size =
25702 g_ddr_test_struct->ddr_test_watchdog_times_s =
25703 g_ddr_test_struct->ddr_test_lane_disable =
25704 g_ddr_test_struct->ddr_address_test_size =
25705 g_ddr_test_struct->ddr_address_test_size =
25706 */
25707
25708 return 1;
25709}
25710
25711unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_index,unsigned int lcdlr_value,unsigned int read_write_flag )
25712{
25713 //char *endp;
25714 unsigned read_value=0;
25715
25716 //return read_value;
25717
25718#if 1
25719 unsigned reg_add=0;
25720 {
25721#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
25722 {
25723 reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
25724 DDR0_PUB_DX0LCDLR1)
25725 +DDR0_PUB_DX0LCDLR1);
25726 if ((data_index%2) == 0)
25727 {
25728 if (read_write_flag == DDR_PARAMETER_READ)
25729 {
25730 lcdlr_value=((readl(reg_add))&0xff);
25731 }
25732 if (read_write_flag == DDR_PARAMETER_WRITE)
25733 {
25734 wr_reg(reg_add, ((readl(reg_add))&0xffffff00)|(lcdlr_value&0xff));
25735 }
25736 }
25737 if ((data_index%2) == 1)
25738 {
25739 if (read_write_flag == DDR_PARAMETER_READ)
25740 {
25741 lcdlr_value=(((readl(reg_add))>>8)&0xff);
25742 }
25743 if (read_write_flag == DDR_PARAMETER_WRITE)
25744 {
25745 wr_reg(reg_add, ((readl(reg_add))&0xffff00ff)|((lcdlr_value&0xff)<<8));
25746 }
25747 }
25748 }
25749
25750#else
25751
25752 if ((data_index%2) == 0)
25753 {
25754 reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
25755 DDR0_PUB_DX0LCDLR1)
25756 +DDR0_PUB_DX0LCDLR1);
25757
25758 }
25759 if ((data_index%2) == 1)
25760 {
25761 reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
25762 DDR0_PUB_DX0LCDLR1)
25763 +DDR0_PUB_DX0LCDLR3);
25764
25765 }
25766 if (read_write_flag == DDR_PARAMETER_READ)
25767 {
25768 lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
25769 }
25770 if (read_write_flag == DDR_PARAMETER_WRITE)
25771 {
25772 wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
25773 }
25774
25775#endif
25776 }
25777
25778
25779
25780 printf("lcdlr %d %08x,%08x\n", data_index,reg_add,
25781 (readl(reg_add)));
25782 read_value=lcdlr_value;
25783
25784 return read_value;
25785
25786#endif
25787}
25788unsigned int do_ddr_read_acmdlr(void )
25789{
25790
25791 unsigned reg_value=0;
25792#if ( CONFIG_DDR_PHY<=P_DDR_PHY_905X)
25793 reg_value=(readl(DDR0_PUB_ACMDLR0));
25794 reg_value=(reg_value>>16)&0x1ff;
25795#endif
25796 return reg_value;
25797}
25798unsigned int do_ddr_read_write_ddr_add_window_lcdlr(unsigned int rank_index,unsigned int add_index,unsigned int lcdlr_value,unsigned int read_write_flag )
25799{
25800 unsigned reg_add=0;
25801
25802 if (add_index == 0)
25803 reg_add=(DDR0_PUB_ACLCDLR);
25804 if (add_index == 1)
25805 reg_add=(DDR0_PUB_ACBDLR0);
25806 {
25807 if (read_write_flag == DDR_PARAMETER_READ)
25808 {
25809 lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
25810 }
25811 if (read_write_flag == DDR_PARAMETER_WRITE)
25812 {
25813 wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
25814 }
25815
25816 }
25817 printf("lcdlr %d %08x,%08x\n", add_index,reg_add,
25818 (readl(reg_add)));
25819 return lcdlr_value;
25820}
25821
25822int do_ddr_uboot_window_use_source_quick_method(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
25823{
25824
25825 //env_set bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
25826 printf("\nsetenv bootcmd ddr_test_cmd 0x32 2 6 20 0 0x100000 0x4000000 \n");
25827 printf("\nEnter do_ddr_uboot_window_use_source function\n");
25828 printf("\n--- watchdog should >15s\n");
25829#define DDR_TEST_NULL 0
25830#define DDR_TEST_PASS 1
25831#define DDR_TEST_FAIL 2
25832
25833 char *endp;
25834 unsigned int lane_disable= 0;
25835 unsigned int data_source= 0;
25836 unsigned int ddr_data_test_size=0x1000000;
25837 unsigned int ddr_add_test_size=0x10000000;
25838 unsigned int ddr_test_size=0x10000000;
25839
25840 unsigned int address_test_watchdog_time_s=15;
25841 unsigned int test_watchdog_time_s=15;
25842
25843 error_outof_count_flag =1; //for quick out of error
25844 if (argc >1) {
25845 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
25846 if (*argv[1] == 0 || *endp != 0)
25847 {
25848 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
25849 }
25850 }
25851 if (argc >2) {
25852 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
25853 if (*argv[2] == 0 || *endp != 0)
25854 {
25855 watchdog_time_s= 15;
25856 }
25857 }
25858 printf("watchdog_time_s==%d\n",watchdog_time_s);
25859 test_watchdog_time_s=watchdog_time_s;
25860 //test_watchdog_time_s=address_test_watchdog_time_s;
25861 if (argc >3) {
25862 address_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
25863 if (*argv[3] == 0 || *endp != 0)
25864 {
25865 address_test_watchdog_time_s= watchdog_time_s;
25866 }
25867 }
25868 printf("address_test_watchdog_time_s==%d\n",address_test_watchdog_time_s);
25869 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
25870 if (argc >4) {
25871 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
25872 if (*argv[4] == 0 || *endp != 0)
25873 {
25874 lane_disable= 0;
25875 }
25876 }
25877 printf("lane_disable==0x%08x\n",lane_disable);
25878
25879 if (argc >5) {
25880 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
25881 if (*argv[5] == 0 || *endp != 0)
25882 {
25883 ddr_data_test_size= 0x100000;
25884 }
25885 }
25886 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
25887 if (argc >6) {
25888 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
25889 if (*argv[6] == 0 || *endp != 0)
25890 {
25891 ddr_add_test_size= 0x10000000;
25892 }
25893 }
25894 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
25895
25896 unsigned int rank_index=0;
25897 unsigned int temp_count=0;
25898 unsigned int ddr_test_data_array_max=100;
25899 unsigned int num_array[100];//8 flag 32_data add_8 32_data add_8
25900
25901 unsigned int temp_test_error=0;
25902 unsigned int lcdlr_min=0;
25903 unsigned int lcdlr_max=0;
25904 memset(num_array, 0, sizeof(num_array));
25905 char str[1024]="";
25906
25907 if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
25908 ddr_test_data_array_max=64;
25909 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
25910 {
25911 num_array[temp_count]= read_write_window_test_parameter(data_source,
25912 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
25913 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
25914 }
25915
25916 unsigned int test_arg_0_ab_best_lcdlr_value =0; //best_lcdlr_value
25917 unsigned int test_arg_1_test_error_flag =0; //min cmd
25918 unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
25919 unsigned int test_arg_3_freq =0;
25920 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
25921 unsigned int test_arg_5_ab_edge_lcdlr_value =0;
25922 unsigned int test_arg_6_lcdlr_temp_count =0;
25923 unsigned int test_arg_7_magic_number =0;
25924 unsigned int org_lcdlr_value_temp=0;
25925 unsigned int acmdlr=0;
25926 acmdlr=do_ddr_read_acmdlr();
25927
25928 test_arg_0_ab_best_lcdlr_value=num_array[0];
25929 test_arg_1_test_error_flag=num_array[1];
25930 test_arg_2_step=num_array[2];
25931 test_arg_3_freq=num_array[3];
25932 test_arg_4_step_status=num_array[4];
25933 test_arg_5_ab_edge_lcdlr_value=num_array[5];
25934 test_arg_6_lcdlr_temp_count=num_array[6];
25935 test_arg_7_magic_number=num_array[7];
25936 printf("test_arg_0_ab_best_lcdlr_value==%d\n",test_arg_0_ab_best_lcdlr_value);
25937 printf("test_arg_1_test_error_flag==%d\n",test_arg_1_test_error_flag);
25938 printf("test_arg_2_step==%d\n",test_arg_2_step);
25939 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
25940 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
25941 printf("test_arg_5_ab_edge_lcdlr_value=%d\n",num_array[5]);
25942 printf("test_arg_6_lcdlr_temp_count=%d\n",num_array[6]);
25943 printf("test_arg_7_magic_number=%d\n",num_array[7]);
25944
25945
25946
25947 if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
25948 {
25949 }
25950 else
25951 {
25952
25953 test_arg_0_ab_best_lcdlr_value=0;
25954 test_arg_5_ab_edge_lcdlr_value=0;
25955 test_arg_2_step=0;
25956 test_arg_6_lcdlr_temp_count=0;
25957 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
25958 }
25959 //printf("boot times==%d\n",test_arg_5_ab_edge_lcdlr_value);
25960 num_array[0] = test_arg_0_ab_best_lcdlr_value ;
25961 num_array[1] = test_arg_1_test_error_flag ;
25962 num_array[2] = test_arg_2_step ;
25963 num_array[3] = test_arg_3_freq ;
25964 num_array[4] = test_arg_4_step_status ;
25965 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
25966 num_array[6] = test_arg_6_lcdlr_temp_count ;
25967 num_array[7] = test_arg_7_magic_number ;
25968
25969 for (temp_count= 0;temp_count < 8; temp_count++)
25970 {
25971 read_write_window_test_parameter(data_source,
25972 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
25973 }
25974
25975
25976
25977 if (test_arg_2_step)
25978 {
25979 if (test_arg_3_freq != global_ddr_clk) //
25980 {
25981 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
25982 sprintf(str,"d2pll %d",test_arg_3_freq);
25983 printf("\nstr=%s\n",str);
25984 run_command(str,0);
25985 while (1) ;
25986 }
25987 }
25988 if (test_arg_2_step == 0)
25989 {
25990 {
25991 test_arg_0_ab_best_lcdlr_value=0;
25992 test_arg_1_test_error_flag=0;
25993 test_arg_2_step=1;
25994 test_arg_3_freq=global_ddr_clk;
25995 test_arg_4_step_status=0;
25996 test_arg_5_ab_edge_lcdlr_value=0;
25997 test_arg_6_lcdlr_temp_count=lcdlr_min;
25998 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
25999 num_array[0] = test_arg_0_ab_best_lcdlr_value ;
26000 num_array[1] = test_arg_1_test_error_flag ;
26001 num_array[2] = test_arg_2_step ;
26002 num_array[3] = test_arg_3_freq ;
26003 num_array[4] = test_arg_4_step_status ;
26004 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
26005 num_array[6] = test_arg_6_lcdlr_temp_count ;
26006 num_array[7] = test_arg_7_magic_number ;
26007
26008
26009 for (temp_count= 0;temp_count < 8; temp_count++)
26010 {
26011 read_write_window_test_parameter(data_source,
26012 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26013 }
26014
26015
26016 //for (temp_count = 8; temp_count< 48;temp_count++) {
26017 // num_array[temp_count]=0;
26018 //}
26019
26020 for (temp_count = 8; temp_count < (32+8); temp_count++) //data
26021 {
26022 //printf("1temp_count=%d\n",temp_count);
26023
26024 if ((temp_count%4) == 0) //org
26025 {
26026 if (((temp_count-8)/4)<8)
26027 {
26028 lcdlr_min=0;
26029 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26030 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26031 //if(lane_step==9)
26032 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
26033 }
26034 else if(((temp_count-8)/4)<10)
26035 {
26036 lcdlr_min=0;
26037 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26038 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26039 if (((temp_count-8)/4) == 9)
26040 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
26041 }
26042 //printf("2temp_count=%d\n",temp_count);
26043 //num_array[temp_count]=0;
26044 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
26045 num_array[temp_count]=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,((temp_count-8)>>2),num_array[temp_count],DDR_PARAMETER_READ);
26046 num_array[temp_count+1]=lcdlr_min;
26047 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
26048 num_array[temp_count+3]=0;
26049 //temp_count=temp_count+4;
26050 }
26051
26052
26053
26054 }
26055
26056 for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
26057 {
26058 if ((temp_count%4) == 0) //org
26059 {
26060 if (((temp_count-8)/4)<8)
26061 {
26062 lcdlr_min=0;
26063 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26064 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26065 //if(lane_step==9)
26066 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
26067 }
26068 else if(((temp_count-8)/4)<10)
26069 {
26070 lcdlr_min=0;
26071 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26072 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26073 if (((temp_count-8)/4) == 9)
26074 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
26075 }
26076 //num_array[temp_count]=0;
26077 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
26078 num_array[temp_count]=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,((temp_count-8-32)>>2),num_array[temp_count],DDR_PARAMETER_READ);
26079 num_array[temp_count+1]=lcdlr_min;
26080 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
26081 num_array[temp_count+3]=0;
26082 }
26083
26084
26085 }
26086
26087
26088
26089
26090#if (CONFIG_DDR_PHY<=P_DDR_PHY_905X)
26091 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
26092 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
26093 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
26094 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
26095 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
26096 lane_disable= lane_disable|1;
26097 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
26098 lane_disable= lane_disable|(1<<1);
26099 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
26100 lane_disable= lane_disable|(1<<2);
26101 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
26102 lane_disable= lane_disable|(1<<3);
26103
26104#endif
26105 if (lane_disable)
26106 {if(lane_disable&0x1){
26107 num_array[8+3]=0xffff;
26108 num_array[8+4+3]=0xffff;
26109 }
26110 if (lane_disable&0x2) {
26111 num_array[8+3+8]=0xffff;
26112 num_array[8+4+3+8]=0xffff;
26113 }
26114 if (lane_disable&0x4) {
26115 num_array[8+3+8+8]=0xffff;
26116 num_array[8+4+3+8+8]=0xffff;
26117 }
26118 if (lane_disable&0x8) {
26119 num_array[8+3+8+8+8]=0xffff;
26120 num_array[8+4+3+8+8+8]=0xffff;
26121 }
26122 printf("lane_disable==%x\n",lane_disable);
26123 if (lane_disable&0x10) {
26124 num_array[8+3+8+8+8+8]=0xffff;
26125 }
26126 if (lane_disable&0x20) {
26127 num_array[8+4+3+8+8+8+8]=0xffff;
26128
26129 }
26130 }
26131
26132
26133 }
26134
26135
26136
26137
26138 for (temp_count= 0; temp_count< 48;temp_count++) {
26139 num_array[temp_count]= read_write_window_test_parameter(data_source,
26140 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26141 }
26142 }
26143
26144 test_arg_2_step++;
26145 num_array[2]=test_arg_2_step;
26146 for (temp_count = 1; temp_count < 48; temp_count++)
26147 {
26148 printf("%d %d\n", temp_count,num_array[temp_count]);
26149 }
26150 temp_count=2;
26151 num_array[temp_count]= read_write_window_test_parameter(data_source,
26152 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26153 //for (i = 0; i < 48; i++) {
26154
26155 // writel(num_array[i],(sticky_reg_base_add+(i<<2)));
26156 //}
26157
26158
26159 //for (i = 8; i < 48; i++) {
26160 //num_array[i]=readl((sticky_reg_base_add+(i<<2)));
26161 //printf("ddr_test_data_num_%04d==%d\n",i,num_array[i]);
26162 //}
26163
26164 ///*
26165 unsigned int lane_step=0;
26166
26167 printf("\nstart loop test\n");
26168
26169 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
26170 {
26171 if ((num_array[(lane_step<<2)+3+8]<0x4))
26172 {break;
26173 }
26174 }
26175 printf("\nstart test lane_step =%d\n",lane_step);
26176 if (lane_step<10)
26177 {
26178 if (lane_step<8)
26179 {
26180 test_watchdog_time_s=watchdog_time_s;
26181 ddr_test_size=ddr_data_test_size;
26182 //lcdlr_min=0;
26183 //lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);//do_ddr_read_acmdlr();
26184 }
26185 else
26186 {
26187 test_watchdog_time_s=address_test_watchdog_time_s;
26188 ddr_test_size=ddr_add_test_size;
26189 //lcdlr_min=0;
26190 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26191 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
26192 //if(lane_step==9)
26193 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
26194 }
26195
26196 if ((num_array[8+(lane_step<<2)+3] == 0)) //test left edge begin
26197 {
26198 /*
26199 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
26200 num_array[2] = test_arg_2_step ;
26201 num_array[3] = test_arg_3_freq ;
26202 num_array[4] = test_arg_4_step_status ;
26203 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
26204 num_array[6] = test_arg_6_lcdlr_temp_count ;
26205 num_array[7] = test_arg_7_magic_number ;
26206 */
26207 // test_arg_0_ab_best_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
26208 // num_array[0]=test_arg_0_ab_best_lcdlr_value;
26209 // temp_count=0;
26210 // read_write_window_test_parameter(data_source,
26211 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26212
26213 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
26214 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26215 temp_count=1;
26216 read_write_window_test_parameter(data_source,
26217 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26218
26219 num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
26220 temp_count=5;
26221 read_write_window_test_parameter(data_source,
26222 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26223
26224 (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
26225 temp_count=8+(lane_step<<2)+1;
26226 read_write_window_test_parameter(data_source,
26227 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26228
26229
26230 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+0])>>1);
26231 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
26232 temp_count=6;
26233 read_write_window_test_parameter(data_source, //temp_lcdlr
26234 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26235
26236 num_array[8+(lane_step<<2)+3]=1;
26237 temp_count=8+(lane_step<<2)+3;
26238 read_write_window_test_parameter(data_source, //lane status
26239 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26240 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26241 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26242 ddr_test_watchdog_clear();
26243 if (lane_step<8)
26244 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26245 else if(lane_step<10)
26246 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26247
26248 //here will dead
26249 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26250
26251 if (temp_test_error)
26252 {
26253 run_command("reset",0);
26254 while (1) ;
26255 }
26256 else
26257 {
26258 ddr_test_watchdog_clear();
26259 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26260 if (lane_step<8)
26261 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26262 else if(lane_step<10)
26263 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26264
26265 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26266 temp_count=1;
26267 read_write_window_test_parameter(data_source,
26268 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26269 run_command("reset",0);
26270 while (1) ;
26271
26272 }
26273 }
26274 else if((num_array[8+(lane_step<<2)+3]==1)) //test left edge ongoing -loop
26275 {
26276
26277 if ((num_array[5]+1) >= (num_array[6]))
26278 {
26279 if (num_array[1] == DDR_TEST_NULL)
26280 {printf("default value not stable ,or recovery sticky?\n");
26281 }
26282
26283
26284 num_array[8+(lane_step<<2)+3]=2; //update status
26285 temp_count=8+(lane_step<<2)+3;
26286 read_write_window_test_parameter(data_source,
26287 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26288
26289 num_array[5]=0; //update edge lcdlr
26290 temp_count=5;
26291 read_write_window_test_parameter(data_source,
26292 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26293 if (num_array[1] == DDR_TEST_FAIL)
26294 num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
26295 if (num_array[1] == DDR_TEST_PASS)
26296 num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
26297 temp_count=8+(lane_step<<2)+1;
26298 read_write_window_test_parameter(data_source,
26299 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26300
26301 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
26302 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
26303 temp_count=6;
26304 read_write_window_test_parameter(data_source,
26305 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26306 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
26307 temp_count=1; //update test error flag
26308 read_write_window_test_parameter(data_source,
26309 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26310
26311 // test_arg_0_ab_best_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
26312 // num_array[0]=test_arg_0_ab_best_lcdlr_value;
26313 // temp_count=0;
26314 // read_write_window_test_parameter(data_source,
26315 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26316 run_command("reset",0);
26317 while (1) ;
26318
26319 }
26320 else
26321 {
26322 if (num_array[1] == DDR_TEST_NULL)
26323 {printf("default value not stable ,or recovery sticky?\n");
26324 }
26325 else if(num_array[1]==DDR_TEST_FAIL)
26326 {
26327
26328
26329
26330 {
26331 num_array[8+(lane_step<<2)+3]=1; //update status
26332 temp_count=8+(lane_step<<2)+3;
26333 read_write_window_test_parameter(data_source,
26334 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26335
26336
26337 num_array[5]=num_array[6]; //update edge lcdlr
26338 temp_count=5;
26339 read_write_window_test_parameter(data_source,
26340 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26341
26342 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
26343 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
26344 temp_count=6;
26345 read_write_window_test_parameter(data_source,
26346 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26347
26348 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
26349 // temp_count=8+(lane_step<<2)+1;
26350 // read_write_window_test_parameter(data_source,
26351 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26352 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26353 temp_count=1; //update test error flag
26354 read_write_window_test_parameter(data_source,
26355 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26356
26357 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26358 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26359 ddr_test_watchdog_clear();
26360 if (lane_step<8)
26361 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26362 else if(lane_step<10)
26363 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26364
26365 //here will dead
26366 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26367
26368 if (temp_test_error)
26369 {
26370 run_command("reset",0);
26371 while (1) ;
26372 }
26373 else
26374 {
26375 ddr_test_watchdog_clear();
26376 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26377 if (lane_step<8)
26378 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26379 else if(lane_step<10)
26380 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26381
26382 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26383 temp_count=1;
26384 read_write_window_test_parameter(data_source,
26385 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26386 run_command("reset",0);
26387 while (1) ;
26388
26389 }
26390 }
26391 }
26392
26393 else if(num_array[1]==DDR_TEST_PASS)
26394 {
26395 num_array[8+(lane_step<<2)+3]=1; //update status
26396 temp_count=8+(lane_step<<2)+3;
26397 read_write_window_test_parameter(data_source,
26398 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26399
26400 num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
26401 temp_count=8+(lane_step<<2)+1;
26402 read_write_window_test_parameter(data_source,
26403 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26404
26405 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
26406 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
26407 temp_count=6;
26408 read_write_window_test_parameter(data_source,
26409 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26410
26411 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26412 temp_count=1; //update test error flag
26413 read_write_window_test_parameter(data_source,
26414 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26415
26416 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26417 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26418 ddr_test_watchdog_clear();
26419 if (lane_step<8)
26420 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26421 else if(lane_step<10)
26422 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26423
26424 //here will dead
26425 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26426
26427 if (temp_test_error)
26428 {
26429 run_command("reset",0);
26430 while (1) ;
26431 }
26432 else
26433 {
26434 ddr_test_watchdog_clear();
26435 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26436 if (lane_step<8)
26437 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26438 else if(lane_step<10)
26439 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26440
26441 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26442 temp_count=1;
26443 read_write_window_test_parameter(data_source,
26444 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26445 run_command("reset",0);
26446 while (1) ;
26447
26448 }
26449
26450 }
26451 }
26452
26453
26454 }
26455
26456 else if((num_array[8+(lane_step<<2)+3]==2)) //test right edge begin
26457 {
26458 /*
26459 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
26460 num_array[2] = test_arg_2_step ;
26461 num_array[3] = test_arg_3_freq ;
26462 num_array[4] = test_arg_4_step_status ;
26463 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
26464 num_array[6] = test_arg_6_lcdlr_temp_count ;
26465 num_array[7] = test_arg_7_magic_number ;
26466 */
26467 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
26468 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26469 temp_count=1;
26470 read_write_window_test_parameter(data_source,
26471 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26472
26473 num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
26474 temp_count=5;
26475 read_write_window_test_parameter(data_source,
26476 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26477
26478 num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
26479 temp_count=8+(lane_step<<2)+2;
26480 read_write_window_test_parameter(data_source,
26481 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26482
26483 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
26484 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
26485 temp_count=6;
26486 read_write_window_test_parameter(data_source, //temp_lcdlr
26487 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26488
26489 num_array[8+(lane_step<<2)+3]=3;
26490 temp_count=8+(lane_step<<2)+3;
26491 read_write_window_test_parameter(data_source, //lane status
26492 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26493 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26494 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26495 ddr_test_watchdog_clear();
26496 if (lane_step<8)
26497 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26498 else if(lane_step<10)
26499 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26500
26501 //here will dead
26502 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26503
26504 if (temp_test_error)
26505 {
26506 run_command("reset",0);
26507 while (1) ;
26508 }
26509 else
26510 {
26511 ddr_test_watchdog_clear();
26512 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26513 if (lane_step<8)
26514 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26515 else if(lane_step<10)
26516 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26517
26518 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26519 temp_count=1;
26520 read_write_window_test_parameter(data_source,
26521 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26522 run_command("reset",0);
26523 while (1) ;
26524
26525 }
26526 }
26527 else if((num_array[8+(lane_step<<2)+3]==3)) //test right edge ongoing -loop
26528 {
26529
26530 if ((num_array[6]+1) >= (num_array[5]))
26531 {
26532 if (num_array[1] == DDR_TEST_NULL)
26533 {printf("default value not stable ,or recovery sticky?\n");
26534 }
26535 num_array[8+(lane_step<<2)+3]=4; //update status
26536 temp_count=8+(lane_step<<2)+3;
26537 read_write_window_test_parameter(data_source,
26538 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26539
26540 num_array[5]=0; //update edge lcdlr
26541 temp_count=5;
26542 read_write_window_test_parameter(data_source,
26543 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26544 if (num_array[1] == DDR_TEST_FAIL)
26545 num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
26546 if (num_array[1] == DDR_TEST_PASS)
26547 num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
26548 temp_count=8+(lane_step<<2)+2;
26549 read_write_window_test_parameter(data_source,
26550 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26551
26552 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
26553 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
26554 temp_count=6;
26555 read_write_window_test_parameter(data_source,
26556 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26557 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
26558 temp_count=1; //update test error flag
26559 read_write_window_test_parameter(data_source,
26560 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26561
26562 run_command("reset",0);
26563 while (1) ;
26564 }
26565 else
26566 {
26567 if (num_array[1] == DDR_TEST_NULL)
26568 {printf("default value not stable ,or recovery sticky?\n");
26569 }
26570 else if(num_array[1]==DDR_TEST_FAIL)
26571 {
26572
26573
26574
26575 {
26576 num_array[8+(lane_step<<2)+3]=3; //update status
26577 temp_count=8+(lane_step<<2)+3;
26578 read_write_window_test_parameter(data_source,
26579 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26580
26581
26582 num_array[5]=num_array[6]; //update edge lcdlr
26583 temp_count=5;
26584 read_write_window_test_parameter(data_source,
26585 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26586
26587 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
26588 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
26589 temp_count=6;
26590 read_write_window_test_parameter(data_source,
26591 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26592
26593 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
26594 // temp_count=8+(lane_step<<2)+1;
26595 // read_write_window_test_parameter(data_source,
26596 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26597 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26598 temp_count=1; //update test error flag
26599 read_write_window_test_parameter(data_source,
26600 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26601
26602 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26603 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26604 ddr_test_watchdog_clear();
26605 if (lane_step<8)
26606 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26607 else if(lane_step<10)
26608 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26609
26610 //here will dead
26611 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26612
26613 if (temp_test_error)
26614 {
26615 run_command("reset",0);
26616 while (1) ;
26617 }
26618 else
26619 {
26620 ddr_test_watchdog_clear();
26621 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26622 if (lane_step<8)
26623 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26624 else if(lane_step<10)
26625 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26626
26627 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26628 temp_count=1;
26629 read_write_window_test_parameter(data_source,
26630 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26631 run_command("reset",0);
26632 while (1) ;
26633
26634 }
26635 }
26636 }
26637
26638 else if(num_array[1]==DDR_TEST_PASS)
26639 {
26640 num_array[8+(lane_step<<2)+3]=3; //update status
26641 temp_count=8+(lane_step<<2)+3;
26642 read_write_window_test_parameter(data_source,
26643 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26644
26645 num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
26646 temp_count=8+(lane_step<<2)+2;
26647 read_write_window_test_parameter(data_source,
26648 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26649
26650 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
26651 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
26652 temp_count=6;
26653 read_write_window_test_parameter(data_source,
26654 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26655
26656 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
26657 temp_count=1; //update test error flag
26658 read_write_window_test_parameter(data_source,
26659 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26660
26661 ddr_test_watchdog_enable(test_watchdog_time_s); //s
26662 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
26663 ddr_test_watchdog_clear();
26664 if (lane_step<8)
26665 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26666 else if(lane_step<10)
26667 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
26668
26669 //here will dead
26670 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
26671
26672 if (temp_test_error)
26673 {
26674 run_command("reset",0);
26675 while (1) ;
26676 }
26677 else
26678 {
26679 ddr_test_watchdog_clear();
26680 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
26681 if (lane_step<8)
26682 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26683 else if(lane_step<10)
26684 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
26685
26686 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
26687 temp_count=1;
26688 read_write_window_test_parameter(data_source,
26689 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26690 run_command("reset",0);
26691 while (1) ;
26692
26693 }
26694
26695 }
26696 }
26697
26698
26699 }
26700 }
26701
26702 if (lane_step >= 10) //finish
26703 {
26704 ddr_test_watchdog_disable(); //s
26705 printf("close watchdog\n");
26706 }
26707
26708 // unsigned int acmdlr= 0;
26709 unsigned int delay_step_x100= 0;
26710
26711 {
26712 //acmdlr=do_ddr_read_acmdlr();
26713 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
26714 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
26715 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
26716
26717 for ((lane_step=0);(lane_step<4);(lane_step++))
26718 {
26719 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
26720 lane_step,
26721 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
26722 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
26723 }
26724 lane_step=4;
26725 {
26726 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
26727 4,
26728 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
26729 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
26730 }
26731 printf("\n\n-----------------------------------------------------------------------------\n\n");
26732 {
26733 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
26734 clk_setup ps| clk_hold ps|adj_percent[100]\n");
26735
26736 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
26737 4,
26738 num_array[8+(lane_step)*8+0],
26739 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
26740 )/100),
26741 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
26742 )/100),
26743
26744 0,
26745 0,
26746 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
26747 2*num_array[8+(lane_step)*8+0]));
26748 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
26749 4,
26750 num_array[8+(lane_step)*8+4],
26751 0,
26752 0,
26753 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
26754 )/100),
26755 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
26756 )/100),
26757
26758 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
26759 2*num_array[8+(lane_step)*8+4]));
26760 }
26761 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
26762 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
26763
26764
26765 for ((lane_step=0);(lane_step<4);(lane_step++))
26766 {
26767 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
26768 lane_step,
26769 num_array[8+(lane_step)*8+0],
26770 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
26771 )/100),
26772 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
26773 )/100),
26774
26775 0,
26776 0,
26777 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
26778 2*num_array[8+(lane_step)*8+0]));
26779
26780 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
26781 lane_step,
26782 num_array[8+(lane_step)*8+4],
26783 0,
26784 0,
26785
26786 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
26787 )/100),
26788 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
26789 )/100),
26790 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
26791 2*num_array[8+(lane_step)*8+4]));
26792
26793
26794
26795 }
26796 }
26797
26798 test_arg_2_step=0x10000;
26799 num_array[2]=test_arg_2_step;
26800
26801
26802
26803 temp_count=2;
26804 read_write_window_test_parameter(data_source,
26805 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26806
26807 return 1;
26808}
26809
26810int do_ddr_uboot_window_use_source(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
26811{
26812
26813 //env_set bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
26814 printf("\nsetenv bootcmd ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000 \n");
26815 printf("\nEnter do_ddr_uboot_window_use_source function\n");
26816 printf("\n--- watchdog should >15s\n");
26817
26818 char *endp;
26819 unsigned int lane_disable= 0;
26820 unsigned int data_source= 0;
26821 unsigned int ddr_data_test_size=0x1000000;
26822 unsigned int ddr_add_test_size=0x10000000;
26823 unsigned int ddr_test_size=0x10000000;
26824
26825 unsigned int address_test_watchdog_time_s=15;
26826 unsigned int test_watchdog_time_s=15;
26827
26828 error_outof_count_flag =1; //for quick out of error
26829 if (argc >1) {
26830 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
26831 if (*argv[1] == 0 || *endp != 0)
26832 {
26833 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
26834 }
26835 }
26836 if (argc >2) {
26837 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
26838 if (*argv[2] == 0 || *endp != 0)
26839 {
26840 watchdog_time_s= 15;
26841 }
26842 }
26843 printf("watchdog_time_s==%d\n",watchdog_time_s);
26844 test_watchdog_time_s=watchdog_time_s;
26845 //test_watchdog_time_s=address_test_watchdog_time_s;
26846 if (argc >3) {
26847 address_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
26848 if (*argv[3] == 0 || *endp != 0)
26849 {
26850 address_test_watchdog_time_s= watchdog_time_s;
26851 }
26852 }
26853 printf("address_test_watchdog_time_s==%d\n",address_test_watchdog_time_s);
26854 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
26855 if (argc >4) {
26856 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
26857 if (*argv[4] == 0 || *endp != 0)
26858 {
26859 lane_disable= 0;
26860 }
26861 }
26862 printf("lane_disable==0x%08x\n",lane_disable);
26863
26864 if (argc >5) {
26865 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
26866 if (*argv[5] == 0 || *endp != 0)
26867 {
26868 ddr_data_test_size= 0x100000;
26869 }
26870 }
26871 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
26872 if (argc >6) {
26873 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
26874 if (*argv[6] == 0 || *endp != 0)
26875 {
26876 ddr_add_test_size= 0x10000000;
26877 }
26878 }
26879 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
26880
26881 unsigned int rank_index=0;
26882 unsigned int temp_count=0;
26883 unsigned int ddr_test_data_array_max=100;
26884 unsigned int num_array[100];//8 flag 32_data add_8 32_data add_8
26885
26886 unsigned int temp_test_error=0;
26887 unsigned int lcdlr_min=0;
26888 unsigned int lcdlr_max=0;
26889 memset(num_array, 0, sizeof(num_array));
26890 char str[1024]="";
26891
26892 if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
26893 ddr_test_data_array_max=64;
26894 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
26895 {
26896 num_array[temp_count]= read_write_window_test_parameter(data_source,
26897 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
26898 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
26899 }
26900
26901 unsigned int test_arg_0_cmd0 =0; //master cmd
26902 unsigned int test_arg_1_cmd1 =0; //min cmd
26903 unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
26904 unsigned int test_arg_3_freq =0;
26905 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
26906 unsigned int test_arg_5_boottimes =0;
26907 unsigned int test_arg_6_lcdlr_temp_count =0;
26908 unsigned int test_arg_7_magic_number =0;
26909 unsigned int org_lcdlr_value_temp=0;
26910 unsigned int acmdlr=0;
26911 acmdlr=do_ddr_read_acmdlr();
26912
26913 test_arg_0_cmd0=num_array[0];
26914 test_arg_1_cmd1=num_array[1];
26915 test_arg_2_step=num_array[2];
26916 test_arg_3_freq=num_array[3];
26917 test_arg_4_step_status=num_array[4];
26918 test_arg_5_boottimes=num_array[5];
26919 test_arg_6_lcdlr_temp_count=num_array[6];
26920 test_arg_7_magic_number=num_array[7];
26921 printf("test_arg_0_cmd0==%d\n",test_arg_0_cmd0);
26922 printf("test_arg_0_cmd1==%d\n",test_arg_1_cmd1);
26923 printf("test_arg_2_step==%d\n",test_arg_2_step);
26924 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
26925 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
26926 printf("test_arg_5_boottimes=%d\n",num_array[5]);
26927 printf("test_arg_6_lcdlr_temp_count=%d\n",num_array[6]);
26928 printf("test_arg_7_magic_number=%d\n",num_array[7]);
26929
26930
26931
26932 if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
26933 {test_arg_5_boottimes++;
26934
26935 }
26936 else
26937 {test_arg_5_boottimes=0;
26938 test_arg_2_step=0;
26939 test_arg_6_lcdlr_temp_count=0;
26940 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
26941 }
26942 printf("boot times==%d\n",test_arg_5_boottimes);
26943 num_array[0] = test_arg_0_cmd0 ;
26944 num_array[1] = test_arg_1_cmd1 ;
26945 num_array[2] = test_arg_2_step ;
26946 num_array[3] = test_arg_3_freq ;
26947 num_array[4] = test_arg_4_step_status ;
26948 num_array[5] = test_arg_5_boottimes ;
26949 num_array[6] = test_arg_6_lcdlr_temp_count ;
26950 num_array[7] = test_arg_7_magic_number ;
26951
26952 for (temp_count= 0;temp_count < 8; temp_count++)
26953 {
26954 read_write_window_test_parameter(data_source,
26955 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26956 }
26957
26958
26959
26960 if (test_arg_2_step)
26961 {
26962 if (test_arg_3_freq != global_ddr_clk) //
26963 {
26964 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
26965 sprintf(str,"d2pll %d",test_arg_3_freq);
26966 printf("\nstr=%s\n",str);
26967 run_command(str,0);
26968 while (1) ;
26969 }
26970 }
26971 if (test_arg_2_step == 0)
26972 {
26973 {
26974 test_arg_0_cmd0=0X31;//DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_WINDOW;
26975 test_arg_1_cmd1=0;
26976 test_arg_2_step=1;
26977 test_arg_3_freq=global_ddr_clk;
26978 test_arg_4_step_status=0;
26979 test_arg_6_lcdlr_temp_count=lcdlr_min;
26980 num_array[0] = test_arg_0_cmd0 ;
26981 num_array[1] = test_arg_1_cmd1 ;
26982 num_array[2] = test_arg_2_step ;
26983 num_array[3] = test_arg_3_freq ;
26984 num_array[4] = test_arg_4_step_status ;
26985 num_array[5] = test_arg_5_boottimes ;
26986 num_array[6] = test_arg_6_lcdlr_temp_count ;
26987 num_array[7] = test_arg_7_magic_number ;
26988
26989 for (temp_count= 0;temp_count < 8; temp_count++)
26990 {
26991 read_write_window_test_parameter(data_source,
26992 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
26993 }
26994
26995
26996 //for (temp_count = 8; temp_count< 48;temp_count++) {
26997 // num_array[temp_count]=0;
26998 //}
26999
27000 for (temp_count = 8; temp_count < (32+8); temp_count++) //data
27001 {
27002 //printf("1temp_count=%d\n",temp_count);
27003 if ((temp_count%4) == 0) //org
27004 {
27005 //printf("2temp_count=%d\n",temp_count);
27006 //num_array[temp_count]=0;
27007 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
27008 num_array[temp_count]=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,((temp_count-8)>>2),num_array[temp_count],DDR_PARAMETER_READ);
27009
27010 }
27011 if ((temp_count%4) == 1) //min
27012 {
27013 num_array[temp_count]=0;
27014 }
27015 if ((temp_count%4) == 2) //max
27016 {
27017 num_array[temp_count]=acmdlr;
27018 }
27019 if ((temp_count%4) == 3) //status
27020 {
27021 num_array[temp_count]=0;
27022 }
27023
27024
27025 }
27026
27027 for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
27028 {
27029 if ((temp_count%4) == 0) //org
27030 {
27031 //num_array[temp_count]=0;
27032 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
27033 num_array[temp_count]=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,((temp_count-8-32)>>2),num_array[temp_count],DDR_PARAMETER_READ);
27034
27035 }
27036 if ((temp_count%4) == 1) //min
27037 {
27038 num_array[temp_count]=0;
27039 }
27040 if ((temp_count%4) == 2) //max
27041 {
27042 num_array[temp_count]=acmdlr*3;
27043 if (temp_count == (32+8+4+2))
27044 num_array[temp_count]=0x3f;//bdlr0 max value
27045 }
27046 if ((temp_count%4) == 3) //status
27047 {
27048 num_array[temp_count]=0;
27049 }
27050
27051
27052 }
27053
27054
27055
27056
27057#if (CONFIG_DDR_PHY<=P_DDR_PHY_905X)
27058 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
27059 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
27060 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
27061 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
27062 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
27063 lane_disable= lane_disable|1;
27064 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
27065 lane_disable= lane_disable|(1<<1);
27066 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
27067 lane_disable= lane_disable|(1<<2);
27068 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
27069 lane_disable= lane_disable|(1<<3);
27070
27071#endif
27072 if (lane_disable)
27073 {if(lane_disable&0x1){
27074 num_array[8+3]=0xffff;
27075 num_array[8+4+3]=0xffff;
27076 }
27077 if (lane_disable&0x2) {
27078 num_array[8+3+8]=0xffff;
27079 num_array[8+4+3+8]=0xffff;
27080 }
27081 if (lane_disable&0x4) {
27082 num_array[8+3+8+8]=0xffff;
27083 num_array[8+4+3+8+8]=0xffff;
27084 }
27085 if (lane_disable&0x8) {
27086 num_array[8+3+8+8+8]=0xffff;
27087 num_array[8+4+3+8+8+8]=0xffff;
27088 }
27089 printf("lane_disable==%x\n",lane_disable);
27090 if (lane_disable&0x10) {
27091 num_array[8+3+8+8+8+8]=0xffff;
27092 }
27093 if (lane_disable&0x20) {
27094 num_array[8+4+3+8+8+8+8]=0xffff;
27095
27096 }
27097 }
27098
27099
27100 }
27101
27102
27103
27104
27105 for (temp_count= 0; temp_count< 48;temp_count++) {
27106 num_array[temp_count]= read_write_window_test_parameter(data_source,
27107 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27108 }
27109 }
27110
27111 test_arg_2_step++;
27112 num_array[2]=test_arg_2_step;
27113 for (temp_count = 1; temp_count < 48; temp_count++)
27114 {
27115 printf("%d %d\n", temp_count,num_array[temp_count]);
27116 }
27117 temp_count=2;
27118 num_array[temp_count]= read_write_window_test_parameter(data_source,
27119 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27120 //for (i = 0; i < 48; i++) {
27121
27122 // writel(num_array[i],(sticky_reg_base_add+(i<<2)));
27123 //}
27124
27125
27126 //for (i = 8; i < 48; i++) {
27127 //num_array[i]=readl((sticky_reg_base_add+(i<<2)));
27128 //printf("ddr_test_data_num_%04d==%d\n",i,num_array[i]);
27129 //}
27130
27131 ///*
27132 unsigned int lane_step=0;
27133
27134 printf("\nstart loop test\n");
27135
27136 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
27137 {
27138 if ((num_array[(lane_step<<2)+3+8]<0x4))
27139 {break;
27140 }
27141 }
27142 printf("\nstart test lane_step =%d\n",lane_step);
27143 if (lane_step<10)
27144 {
27145 if (lane_step<8)
27146 {
27147 test_watchdog_time_s=watchdog_time_s;
27148 ddr_test_size=ddr_data_test_size;
27149 lcdlr_min=0;
27150 lcdlr_max=(num_array[(lane_step<<2)+2+8]);//do_ddr_read_acmdlr();
27151 }
27152 else
27153 {
27154 test_watchdog_time_s=address_test_watchdog_time_s;
27155 ddr_test_size=ddr_add_test_size;
27156 lcdlr_min=0;
27157 lcdlr_max=(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27158 }
27159
27160 if ((num_array[8+(lane_step<<2)+3] == 0)) //test left edge begin
27161 {
27162 num_array[8+(lane_step<<2)+3]=1;
27163 test_arg_6_lcdlr_temp_count=lcdlr_min;
27164 num_array[6]=test_arg_6_lcdlr_temp_count;
27165
27166 temp_count=6;
27167 read_write_window_test_parameter(data_source,
27168 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27169 temp_count=8+(lane_step<<2)+3;
27170 read_write_window_test_parameter(data_source,
27171 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27172 ddr_test_watchdog_enable(test_watchdog_time_s); //s
27173 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
27174 ddr_test_watchdog_clear();
27175 if (lane_step<8)
27176 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27177 else if(lane_step<10)
27178 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27179
27180 //here will dead
27181 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
27182
27183 if (temp_test_error)
27184 {
27185 run_command("reset",0);
27186 }
27187 else
27188 {
27189 ddr_test_watchdog_clear();
27190 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
27191 if (lane_step<8)
27192 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27193 else if(lane_step<10)
27194 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27195
27196
27197 num_array[8+(lane_step<<2)+3]=2; //left finish
27198
27199 temp_count=8+(lane_step<<2)+3;
27200 read_write_window_test_parameter(data_source,
27201 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27202
27203 temp_count=8+(lane_step<<2)+1;
27204 num_array[temp_count]=test_arg_6_lcdlr_temp_count;
27205 read_write_window_test_parameter(data_source,
27206 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27207
27208 test_arg_6_lcdlr_temp_count=0;
27209 num_array[6]=test_arg_6_lcdlr_temp_count;
27210
27211 temp_count=6;
27212 read_write_window_test_parameter(data_source,
27213 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27214 run_command("reset",0);
27215
27216
27217
27218 }
27219 }
27220 else if((num_array[8+(lane_step<<2)+3]==1)) //test left edge ongoing -loop
27221 {
27222 num_array[8+(lane_step<<2)+3]=1;
27223 test_arg_6_lcdlr_temp_count++;
27224 num_array[6]=test_arg_6_lcdlr_temp_count;
27225
27226 temp_count=6;
27227 read_write_window_test_parameter(data_source,
27228 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27229 temp_count=8+(lane_step<<2)+3;
27230 read_write_window_test_parameter(data_source,
27231 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27232 ddr_test_watchdog_enable(test_watchdog_time_s); //s
27233 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
27234 ddr_test_watchdog_clear();
27235 if (lane_step<8)
27236 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27237 else if(lane_step<10)
27238 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27239
27240 //here will dead
27241 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
27242
27243 if (temp_test_error)
27244 {
27245 run_command("reset",0);
27246 }
27247 else
27248 {
27249 ddr_test_watchdog_clear();
27250 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
27251 if (lane_step<8)
27252 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27253 else if(lane_step<10)
27254 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27255
27256 num_array[8+(lane_step<<2)+3]=2; //left finish
27257
27258 temp_count=8+(lane_step<<2)+3;
27259 read_write_window_test_parameter(data_source,
27260 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27261
27262 temp_count=8+(lane_step<<2)+1;
27263 num_array[temp_count]=test_arg_6_lcdlr_temp_count;
27264 read_write_window_test_parameter(data_source,
27265 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27266
27267 test_arg_6_lcdlr_temp_count=0;
27268 num_array[6]=test_arg_6_lcdlr_temp_count;
27269
27270 temp_count=6;
27271 read_write_window_test_parameter(data_source,
27272 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27273 run_command("reset",0);
27274
27275
27276
27277 }
27278 }
27279 else if((num_array[8+(lane_step<<2)+3]==2)) //test right edge begin
27280 {
27281 num_array[8+(lane_step<<2)+3]=3;
27282 test_arg_6_lcdlr_temp_count=lcdlr_max;
27283 num_array[6]=test_arg_6_lcdlr_temp_count;
27284
27285 temp_count=6;
27286 read_write_window_test_parameter(data_source,
27287 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27288 temp_count=8+(lane_step<<2)+3;
27289 read_write_window_test_parameter(data_source,
27290 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27291 ddr_test_watchdog_enable(test_watchdog_time_s); //s
27292 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
27293 ddr_test_watchdog_clear();
27294 if (lane_step<8)
27295 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27296 else if(lane_step<10)
27297 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27298
27299 //here will dead
27300 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
27301
27302 if (temp_test_error)
27303 {
27304 run_command("reset",0);
27305 }
27306 else
27307 {
27308 ddr_test_watchdog_clear();
27309 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
27310 if (lane_step<8)
27311 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27312 else if(lane_step<10)
27313 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27314
27315 num_array[8+(lane_step<<2)+3]=4; //right finish
27316
27317 temp_count=8+(lane_step<<2)+3;
27318 read_write_window_test_parameter(data_source,
27319 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27320
27321 temp_count=8+(lane_step<<2)+2;
27322 num_array[temp_count]=test_arg_6_lcdlr_temp_count;
27323 read_write_window_test_parameter(data_source,
27324 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27325
27326 test_arg_6_lcdlr_temp_count=0;
27327 num_array[6]=test_arg_6_lcdlr_temp_count;
27328
27329 temp_count=6;
27330 read_write_window_test_parameter(data_source,
27331 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27332 run_command("reset",0);
27333
27334
27335
27336 }
27337 }
27338 else if((num_array[8+(lane_step<<2)+3]==3)) //test right edge ongoing -loop
27339 {
27340 num_array[8+(lane_step<<2)+3]=3;
27341 test_arg_6_lcdlr_temp_count--;
27342 num_array[6]=test_arg_6_lcdlr_temp_count;
27343
27344 temp_count=6;
27345 read_write_window_test_parameter(data_source,
27346 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27347 temp_count=8+(lane_step<<2)+3;
27348 read_write_window_test_parameter(data_source,
27349 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27350 ddr_test_watchdog_enable(test_watchdog_time_s); //s
27351 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
27352 ddr_test_watchdog_clear();
27353 if (lane_step<8)
27354 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27355 else if(lane_step<10)
27356 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
27357
27358 //here will dead
27359 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
27360
27361 if (temp_test_error)
27362 {
27363 run_command("reset",0);
27364 }
27365 else
27366 {
27367 ddr_test_watchdog_clear();
27368 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
27369 if (lane_step<8)
27370 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27371 else if(lane_step<10)
27372 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
27373
27374 num_array[8+(lane_step<<2)+3]=4; //right finish
27375
27376 temp_count=8+(lane_step<<2)+3;
27377 read_write_window_test_parameter(data_source,
27378 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27379
27380 temp_count=8+(lane_step<<2)+2;
27381 num_array[temp_count]=test_arg_6_lcdlr_temp_count;
27382 read_write_window_test_parameter(data_source,
27383 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27384
27385 test_arg_6_lcdlr_temp_count=0;
27386 num_array[6]=test_arg_6_lcdlr_temp_count;
27387
27388 temp_count=6;
27389 read_write_window_test_parameter(data_source,
27390 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27391 run_command("reset",0);
27392
27393
27394
27395 }
27396 }
27397 }
27398
27399 if (lane_step >= 10) //finish
27400 {
27401 ddr_test_watchdog_disable(); //s
27402 printf("close watchdog\n");
27403 }
27404
27405 // unsigned int acmdlr= 0;
27406 unsigned int delay_step_x100= 0;
27407
27408 {
27409 //acmdlr=do_ddr_read_acmdlr();
27410 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
27411 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
27412 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
27413
27414 for ((lane_step=0);(lane_step<4);(lane_step++))
27415 {
27416 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
27417 lane_step,
27418 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
27419 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
27420 }
27421 lane_step=4;
27422 {
27423 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
27424 4,
27425 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
27426 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
27427 }
27428 printf("\n\n-----------------------------------------------------------------------------\n\n");
27429 {
27430 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
27431 clk_setup ps| clk_hold ps|adj_percent[100]\n");
27432
27433 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
27434 4,
27435 num_array[8+(lane_step)*8+0],
27436 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
27437 )/100),
27438 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
27439 )/100),
27440
27441 0,
27442 0,
27443 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
27444 2*num_array[8+(lane_step)*8+0]));
27445 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
27446 4,
27447 num_array[8+(lane_step)*8+4],
27448 0,
27449 0,
27450 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
27451 )/100),
27452 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
27453 )/100),
27454
27455 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
27456 2*num_array[8+(lane_step)*8+4]));
27457 }
27458 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
27459 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
27460
27461
27462 for ((lane_step=0);(lane_step<4);(lane_step++))
27463 {
27464 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
27465 lane_step,
27466 num_array[8+(lane_step)*8+0],
27467 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
27468 )/100),
27469 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
27470 )/100),
27471
27472 0,
27473 0,
27474 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
27475 2*num_array[8+(lane_step)*8+0]));
27476
27477 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
27478 lane_step,
27479 num_array[8+(lane_step)*8+4],
27480 0,
27481 0,
27482
27483 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
27484 )/100),
27485 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
27486 )/100),
27487 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
27488 2*num_array[8+(lane_step)*8+4]));
27489
27490
27491
27492 }
27493 }
27494
27495 test_arg_2_step=0x10000;
27496 num_array[2]=test_arg_2_step;
27497
27498
27499
27500 temp_count=2;
27501 read_write_window_test_parameter(data_source,
27502 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27503
27504 return 1;
27505}
27506
27507
27508int do_ddr_uboot_kernel_window_use_source_quick_method(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
27509{
27510 //env_set storeboot "ddr_test_cmd 0x33 2 6 20 0 0x100000 0x4000000"
27511 printf("\nsetenv bootcmd ddr_test_cmd 0x33 2 6 20 0 0x100000 0x4000000 \n");
27512 printf("\nEnter do_ddr_uboot_window_use_source function\n");
27513 printf("\n--- watchdog should >15s\n");
27514#define DDR_TEST_NULL 0
27515#define DDR_TEST_PASS 1
27516#define DDR_TEST_FAIL 2
27517
27518#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
27519#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
27520 //PREG_STICKY_REG5
27521
27522
27523#define DDR_TEST_STATUS_UBOOT_ONGOING 1
27524#define DDR_TEST_STATUS_UBOOT_FINISH 2
27525#define DDR_TEST_STATUS_KERNEL_ONGING 3
27526#define DDR_TEST_STATUS_KERNEL_FINISH 4
27527
27528#define DDR_TEST_METHOD_DIVIDER_2 1 //AB METHOD A is failing B is passing value
27529#define DDR_TEST_METHOD_DECREASE 2
27530
27531 char *endp;
27532 unsigned int lane_disable= 0;
27533 unsigned int data_source= 0;
27534 unsigned int ddr_data_test_method=DDR_TEST_METHOD_DIVIDER_2;
27535 unsigned int ddr_add_test_method=DDR_TEST_METHOD_DIVIDER_2;
27536 unsigned int ddr_test_method=DDR_TEST_METHOD_DIVIDER_2;
27537
27538 unsigned int ddr_data_test_size=0x1000000;
27539 unsigned int ddr_add_test_size=0x10000000;
27540 unsigned int ddr_test_size=0x10000000;
27541
27542 unsigned int address_test_watchdog_time_s=15;
27543 unsigned int test_watchdog_time_s=15;
27544
27545 error_outof_count_flag =1; //for quick out of error
27546 if (argc >1) {
27547 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
27548 if (*argv[1] == 0 || *endp != 0)
27549 {
27550 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
27551 }
27552 }
27553 if (argc >2) {
27554 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
27555 if (*argv[2] == 0 || *endp != 0)
27556 {
27557 watchdog_time_s= 15;
27558 }
27559 }
27560 printf("watchdog_time_s==%d\n",watchdog_time_s);
27561 test_watchdog_time_s=watchdog_time_s;
27562 //test_watchdog_time_s=address_test_watchdog_time_s;
27563 if (argc >3) {
27564 address_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
27565 if (*argv[3] == 0 || *endp != 0)
27566 {
27567 address_test_watchdog_time_s= watchdog_time_s;
27568 }
27569 }
27570 printf("address_test_watchdog_time_s==%d\n",address_test_watchdog_time_s);
27571 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
27572 if (argc >4) {
27573 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
27574 if (*argv[4] == 0 || *endp != 0)
27575 {
27576 lane_disable= 0;
27577 }
27578 }
27579 printf("lane_disable==0x%08x\n",lane_disable);
27580
27581 if (argc >5) {
27582 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
27583 if (*argv[5] == 0 || *endp != 0)
27584 {
27585 ddr_data_test_size= 0x100000;
27586 }
27587 }
27588 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
27589 if (argc >6) {
27590 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
27591 if (*argv[6] == 0 || *endp != 0)
27592 {
27593 ddr_add_test_size= 0x10000000;
27594 }
27595 }
27596 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
27597 if (argc >7) {
27598 ddr_data_test_method = simple_strtoull_ddr(argv[7], &endp, 0);
27599 if (*argv[7] == 0 || *endp != 0)
27600 {
27601 ddr_data_test_method= DDR_TEST_METHOD_DIVIDER_2;
27602 }
27603 }
27604 printf("ddr_data_test_method==0x%08x\n",ddr_data_test_method);
27605 if (argc >8) {
27606 ddr_add_test_method = simple_strtoull_ddr(argv[8], &endp, 0);
27607 if (*argv[8] == 0 || *endp != 0)
27608 {
27609 ddr_add_test_method= DDR_TEST_METHOD_DIVIDER_2;
27610 }
27611 }
27612 printf("ddr_add_test_method==0x%08x\n",ddr_add_test_method);
27613
27614 unsigned int rank_index=0;
27615 unsigned int temp_count=0;
27616 unsigned int ddr_test_data_array_max=100;
27617 unsigned int num_array[100];//8 flag 32_data add_8 32_data add_8
27618
27619 unsigned int temp_test_error=0;
27620 unsigned int lcdlr_min=0;
27621 unsigned int lcdlr_max=0;
27622 memset(num_array, 0, sizeof(num_array));
27623 char str[1024]="";
27624
27625 if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
27626 ddr_test_data_array_max=64;
27627 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
27628 {
27629 num_array[temp_count]= read_write_window_test_parameter(data_source,
27630 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
27631 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
27632 }
27633
27634 unsigned int test_arg_0_ab_best_lcdlr_value =0; //best_lcdlr_value
27635 unsigned int test_arg_1_test_error_flag =0; //min cmd
27636 unsigned int test_arg_2_step =0; //step 0 init -1 UBOOT ONGOING 2 UBOOT FINISH 3 KERNEL ONGOING 4 KERNEL FINISH
27637 unsigned int test_arg_3_freq =0;
27638 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
27639 unsigned int test_arg_5_ab_edge_lcdlr_value =0;
27640 unsigned int test_arg_6_lcdlr_temp_count =0;
27641 unsigned int test_arg_7_magic_number =0;
27642 unsigned int org_lcdlr_value_temp=0;
27643 unsigned int acmdlr=0;
27644 acmdlr=do_ddr_read_acmdlr();
27645
27646 test_arg_0_ab_best_lcdlr_value=num_array[0];
27647 test_arg_1_test_error_flag=num_array[1];
27648 test_arg_2_step=num_array[2];
27649 test_arg_3_freq=num_array[3];
27650 test_arg_4_step_status=num_array[4];
27651 test_arg_5_ab_edge_lcdlr_value=num_array[5];
27652 test_arg_6_lcdlr_temp_count=num_array[6];
27653 test_arg_7_magic_number=num_array[7];
27654 printf("test_arg_0_ab_best_lcdlr_value==%d\n",test_arg_0_ab_best_lcdlr_value);
27655 printf("test_arg_1_test_error_flag==%d\n",test_arg_1_test_error_flag);
27656 printf("test_arg_2_step==%d\n",test_arg_2_step);
27657 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
27658 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
27659 printf("test_arg_5_ab_edge_lcdlr_value=%d\n",num_array[5]);
27660 printf("test_arg_6_lcdlr_temp_count=%d\n",num_array[6]);
27661 printf("test_arg_7_magic_number=%d\n",num_array[7]);
27662
27663
27664
27665 if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
27666 {
27667 }
27668 else
27669 {
27670
27671 test_arg_0_ab_best_lcdlr_value=0;
27672 test_arg_5_ab_edge_lcdlr_value=0;
27673 test_arg_2_step=0;
27674 test_arg_6_lcdlr_temp_count=0;
27675 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
27676 }
27677 //printf("boot times==%d\n",test_arg_5_ab_edge_lcdlr_value);
27678 num_array[0] = test_arg_0_ab_best_lcdlr_value ;
27679 num_array[1] = test_arg_1_test_error_flag ;
27680 num_array[2] = test_arg_2_step ;
27681 num_array[3] = test_arg_3_freq ;
27682 num_array[4] = test_arg_4_step_status ;
27683 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
27684 num_array[6] = test_arg_6_lcdlr_temp_count ;
27685 num_array[7] = test_arg_7_magic_number ;
27686
27687 for (temp_count= 0;temp_count < 8; temp_count++)
27688 {
27689 read_write_window_test_parameter(data_source,
27690 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27691 }
27692
27693
27694
27695 if (test_arg_2_step)
27696 {
27697 if (test_arg_3_freq != global_ddr_clk) //
27698 {
27699 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
27700 sprintf(str,"d2pll %d",test_arg_3_freq);
27701 printf("\nstr=%s\n",str);
27702 run_command(str,0);
27703 while (1) ;
27704 }
27705 }
27706 if (test_arg_2_step == 0)
27707 {
27708 {
27709
27710
27711
27712 test_arg_0_ab_best_lcdlr_value=0;
27713 test_arg_1_test_error_flag=0;
27714 test_arg_2_step=DDR_TEST_STATUS_UBOOT_ONGOING;
27715 test_arg_3_freq=global_ddr_clk;
27716 test_arg_4_step_status=0;
27717 test_arg_5_ab_edge_lcdlr_value=0;
27718 test_arg_6_lcdlr_temp_count=lcdlr_min;
27719 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
27720 num_array[0] = test_arg_0_ab_best_lcdlr_value ;
27721 num_array[1] = test_arg_1_test_error_flag ;
27722 num_array[2] = test_arg_2_step ;
27723 num_array[3] = test_arg_3_freq ;
27724 num_array[4] = test_arg_4_step_status ;
27725 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
27726 num_array[6] = test_arg_6_lcdlr_temp_count ;
27727 num_array[7] = test_arg_7_magic_number ;
27728
27729
27730 for (temp_count= 0;temp_count < 8; temp_count++)
27731 {
27732 read_write_window_test_parameter(data_source,
27733 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27734 }
27735
27736 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
27737 // DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
27738 //for (temp_count = 8; temp_count< 48;temp_count++) {
27739 // num_array[temp_count]=0;
27740 //}
27741
27742 for (temp_count = 8; temp_count < (32+8); temp_count++) //data
27743 {
27744 //printf("1temp_count=%d\n",temp_count);
27745
27746 if ((temp_count%4) == 0) //org
27747 {
27748 if (((temp_count-8)/4)<8)
27749 {
27750 lcdlr_min=0;
27751 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27752 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27753 //if(lane_step==9)
27754 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
27755 }
27756 else if(((temp_count-8)/4)<10)
27757 {
27758 lcdlr_min=0;
27759 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27760 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27761 if (((temp_count-8)/4) == 9)
27762 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
27763 }
27764 //printf("2temp_count=%d\n",temp_count);
27765 //num_array[temp_count]=0;
27766 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
27767 num_array[temp_count]=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,((temp_count-8)>>2),num_array[temp_count],DDR_PARAMETER_READ);
27768 num_array[temp_count+1]=lcdlr_min;
27769 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
27770 num_array[temp_count+3]=0;
27771 //temp_count=temp_count+4;
27772 }
27773
27774
27775
27776 }
27777
27778 for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
27779 {
27780 if ((temp_count%4) == 0) //org
27781 {
27782 if (((temp_count-8)/4)<8)
27783 {
27784 lcdlr_min=0;
27785 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27786 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27787 //if(lane_step==9)
27788 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
27789 }
27790 else if(((temp_count-8)/4)<10)
27791 {
27792 lcdlr_min=0;
27793 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27794 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27795 if (((temp_count-8)/4) == 9)
27796 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
27797 }
27798 //num_array[temp_count]=0;
27799 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
27800 num_array[temp_count]=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,((temp_count-8-32)>>2),num_array[temp_count],DDR_PARAMETER_READ);
27801 num_array[temp_count+1]=lcdlr_min;
27802 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
27803 num_array[temp_count+3]=0;
27804 }
27805
27806
27807 }
27808
27809
27810
27811
27812#if (CONFIG_DDR_PHY<=P_DDR_PHY_905X)
27813 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
27814 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
27815 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
27816 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
27817 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
27818 lane_disable= lane_disable|1;
27819 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
27820 lane_disable= lane_disable|(1<<1);
27821 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
27822 lane_disable= lane_disable|(1<<2);
27823 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
27824 lane_disable= lane_disable|(1<<3);
27825
27826#endif
27827 if (lane_disable)
27828 {if(lane_disable&0x1){
27829 num_array[8+3]=0xffff;
27830 num_array[8+4+3]=0xffff;
27831 }
27832 if (lane_disable&0x2) {
27833 num_array[8+3+8]=0xffff;
27834 num_array[8+4+3+8]=0xffff;
27835 }
27836 if (lane_disable&0x4) {
27837 num_array[8+3+8+8]=0xffff;
27838 num_array[8+4+3+8+8]=0xffff;
27839 }
27840 if (lane_disable&0x8) {
27841 num_array[8+3+8+8+8]=0xffff;
27842 num_array[8+4+3+8+8+8]=0xffff;
27843 }
27844 printf("lane_disable==%x\n",lane_disable);
27845 if (lane_disable&0x10) {
27846 num_array[8+3+8+8+8+8]=0xffff;
27847 }
27848 if (lane_disable&0x20) {
27849 num_array[8+4+3+8+8+8+8]=0xffff;
27850
27851 }
27852 }
27853
27854
27855 }
27856
27857
27858
27859
27860 for (temp_count= 0; temp_count< 48;temp_count++) {
27861 num_array[temp_count]= read_write_window_test_parameter(data_source,
27862 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27863 }
27864 }
27865
27866 //test_arg_2_step++;
27867 num_array[2]=test_arg_2_step;
27868 for (temp_count = 1; temp_count < 48; temp_count++)
27869 {
27870 printf("%d %d\n", temp_count,num_array[temp_count]);
27871 }
27872 temp_count=2;
27873 num_array[temp_count]= read_write_window_test_parameter(data_source,
27874 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27875 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
27876 // DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
27877 //for (i = 0; i < 48; i++) {
27878
27879 // writel(num_array[i],(sticky_reg_base_add+(i<<2)));
27880 //}
27881
27882
27883 //for (i = 8; i < 48; i++) {
27884 //num_array[i]=readl((sticky_reg_base_add+(i<<2)));
27885 //printf("ddr_test_data_num_%04d==%d\n",i,num_array[i]);
27886 //}
27887
27888 ///*
27889 unsigned int lane_step=0;
27890
27891 printf("\nstart loop test\n");
27892
27893 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
27894 {
27895 if (test_arg_2_step<DDR_TEST_STATUS_KERNEL_ONGING)
27896 {
27897 if ((num_array[(lane_step<<2)+3+8]<(0x4)))
27898 {break;
27899 }
27900 }
27901 }
27902
27903 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_ONGOING)
27904 {if(lane_step>9)
27905 {
27906 test_arg_2_step=DDR_TEST_STATUS_UBOOT_FINISH;
27907 printf("uboot test result: \n");
27908 }
27909 }
27910
27911 if (test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
27912 {
27913 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
27914 {
27915
27916 {
27917 if ((num_array[(lane_step<<2)+3+8]<(0x4+4)))
27918 {break;
27919 }
27920 }
27921 }
27922 }
27923
27924 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
27925 {
27926 //test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
27927 }
27928 else
27929 {
27930 printf("\nstart test lane_step =%d\n",lane_step);
27931 if (lane_step<10)
27932 {
27933 if (lane_step<8)
27934 {
27935 test_watchdog_time_s=watchdog_time_s;
27936 ddr_test_size=ddr_data_test_size;
27937 ddr_test_method=ddr_data_test_method;
27938 //lcdlr_min=0;
27939 //lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);//do_ddr_read_acmdlr();
27940 }
27941 else
27942 {
27943 test_watchdog_time_s=address_test_watchdog_time_s;
27944 ddr_test_size=ddr_add_test_size;
27945 ddr_test_method=ddr_add_test_method;
27946 //lcdlr_min=0;
27947 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27948 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
27949 //if(lane_step==9)
27950 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
27951 }
27952
27953 if (num_array[8+(lane_step<<2)+3]>4) //from kernel
27954 {
27955 num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
27956 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
27957 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
27958 // DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
27959 }
27960
27961 if (((num_array[8+(lane_step<<2)+3] == 0)) || ((num_array[8+(lane_step<<2)+3] == 4))) //test left edge begin
27962 {
27963 /*
27964 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
27965 num_array[2] = test_arg_2_step ;
27966 num_array[3] = test_arg_3_freq ;
27967 num_array[4] = test_arg_4_step_status ;
27968 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
27969 num_array[6] = test_arg_6_lcdlr_temp_count ;
27970 num_array[7] = test_arg_7_magic_number ;
27971 */
27972 // test_arg_0_ab_best_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
27973 // num_array[0]=test_arg_0_ab_best_lcdlr_value;
27974 // temp_count=0;
27975 // read_write_window_test_parameter(data_source,
27976 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27977
27978 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
27979 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
27980 temp_count=1;
27981 read_write_window_test_parameter(data_source,
27982 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27983
27984 if (num_array[8+(lane_step<<2)+3]>4)
27985 {
27986 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
27987 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
27988 }
27989
27990 read_write_window_test_flag(data_source,
27991 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27992
27993 num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
27994 temp_count=5;
27995 read_write_window_test_parameter(data_source,
27996 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
27997
27998 (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
27999 temp_count=8+(lane_step<<2)+1;
28000 read_write_window_test_parameter(data_source,
28001 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28002
28003 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28004 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+0])>>1);
28005 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28006 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
28007
28008 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
28009 temp_count=6;
28010 read_write_window_test_parameter(data_source, //temp_lcdlr
28011 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28012
28013 num_array[8+(lane_step<<2)+3]=(num_array[8+(lane_step<<2)+3]+1);
28014 temp_count=8+(lane_step<<2)+3;
28015 read_write_window_test_parameter(data_source, //lane status
28016 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28017
28018
28019 {
28020 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28021 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28022 ddr_test_watchdog_clear();
28023 }
28024 if (lane_step<8)
28025 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28026 else if(lane_step<10)
28027 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28028
28029 //here will dead
28030
28031 {
28032 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28033 }
28034 //if( num_array[8+(lane_step<<2)+3]>4)
28035
28036
28037 if (temp_test_error)
28038 {
28039 run_command("reset",0);
28040 while (1) ;
28041 }
28042 else
28043 {
28044 if ( num_array[8+(lane_step<<2)+3]>4)
28045 {
28046 ddr_test_watchdog_disable(); //s
28047 run_command("run storeboot",0);
28048 while (1) ;
28049 }
28050 else
28051 {
28052 ddr_test_watchdog_clear();
28053 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28054 if (lane_step<8)
28055 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28056 else if(lane_step<10)
28057 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28058
28059 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28060 temp_count=1;
28061 read_write_window_test_parameter(data_source,
28062 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28063 if (num_array[8+(lane_step<<2)+3]>4)
28064 {
28065 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28066 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28067 }
28068
28069 run_command("reset",0);
28070 while (1) ;
28071 }
28072 }
28073 }
28074 else if((num_array[8+(lane_step<<2)+3]==1)||((num_array[8+(lane_step<<2)+3]==5))) //test left edge begin) //test left edge ongoing -loop
28075 {
28076
28077 if ((num_array[6]+1) >= (num_array[8+(lane_step<<2)+1]))
28078 {
28079 if (num_array[1] == DDR_TEST_NULL)
28080 {printf("default value not stable ,or recovery sticky?\n");
28081 }
28082
28083
28084 num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
28085 temp_count=8+(lane_step<<2)+3;
28086 read_write_window_test_parameter(data_source,
28087 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28088
28089 num_array[5]=0; //update edge lcdlr
28090 temp_count=5;
28091 read_write_window_test_parameter(data_source,
28092 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28093
28094 if (num_array[1] == DDR_TEST_FAIL)
28095 num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
28096 if (num_array[1] == DDR_TEST_PASS)
28097 num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
28098 temp_count=8+(lane_step<<2)+1;
28099 read_write_window_test_parameter(data_source,
28100 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28101
28102 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
28103 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
28104 temp_count=6;
28105 read_write_window_test_parameter(data_source,
28106 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28107 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
28108 temp_count=1; //update test error flag
28109 read_write_window_test_parameter(data_source,
28110 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28111
28112 if (num_array[8+(lane_step<<2)+3]>4)
28113 {
28114 // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28115 // DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
28116 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28117 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28118 }
28119
28120 // test_arg_0_ab_best_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
28121 // num_array[0]=test_arg_0_ab_best_lcdlr_value;
28122 // temp_count=0;
28123 // read_write_window_test_parameter(data_source,
28124 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28125 run_command("reset",0);
28126 while (1) ;
28127
28128 }
28129 else
28130 {
28131 if (num_array[1] == DDR_TEST_NULL)
28132 {printf("default value not stable ,or recovery sticky?\n");
28133 }
28134 else if(num_array[1]==DDR_TEST_FAIL)
28135 {
28136
28137
28138
28139 {
28140 // num_array[8+(lane_step<<2)+3]=1; //update status
28141 temp_count=8+(lane_step<<2)+3;
28142 read_write_window_test_parameter(data_source,
28143 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28144
28145
28146 num_array[5]=num_array[6]; //update edge lcdlr
28147 temp_count=5;
28148 read_write_window_test_parameter(data_source,
28149 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28150
28151 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28152 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
28153 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28154 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
28155 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
28156 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
28157 temp_count=6;
28158 read_write_window_test_parameter(data_source,
28159 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28160
28161 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
28162 // temp_count=8+(lane_step<<2)+1;
28163 // read_write_window_test_parameter(data_source,
28164 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28165 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
28166 temp_count=1; //update test error flag
28167 read_write_window_test_parameter(data_source,
28168 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28169
28170 if (num_array[8+(lane_step<<2)+3]>4)
28171 {
28172 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28173 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28174 }
28175
28176
28177 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28178 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28179 ddr_test_watchdog_clear();
28180 if (lane_step<8)
28181 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28182 else if(lane_step<10)
28183 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28184
28185 //here will dead
28186 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28187
28188 if (temp_test_error)
28189 {
28190 run_command("reset",0);
28191 while (1) ;
28192 }
28193 else
28194 {
28195 if ( num_array[8+(lane_step<<2)+3]>4)
28196 {
28197 ddr_test_watchdog_disable(); //s
28198 run_command("run storeboot",0);
28199 while (1) ;
28200 }
28201 else
28202 {
28203
28204 ddr_test_watchdog_clear();
28205 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28206 if (lane_step<8)
28207 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28208 else if(lane_step<10)
28209 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28210
28211 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28212 temp_count=1;
28213 read_write_window_test_parameter(data_source,
28214 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28215
28216 if (num_array[8+(lane_step<<2)+3]>4)
28217 {
28218 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28219 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28220 }
28221
28222
28223 run_command("reset",0);
28224 while (1) ;
28225 }
28226
28227 }
28228 }
28229 }
28230
28231 else if(num_array[1]==DDR_TEST_PASS)
28232 {
28233 // num_array[8+(lane_step<<2)+3]=1; //update status
28234 temp_count=8+(lane_step<<2)+3;
28235 read_write_window_test_parameter(data_source,
28236 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28237
28238 num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
28239 temp_count=8+(lane_step<<2)+1;
28240 read_write_window_test_parameter(data_source,
28241 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28242
28243 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28244 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
28245 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28246 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
28247 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
28248 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
28249 temp_count=6;
28250 read_write_window_test_parameter(data_source,
28251 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28252
28253 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
28254 temp_count=1; //update test error flag
28255 read_write_window_test_parameter(data_source,
28256 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28257
28258 if (num_array[8+(lane_step<<2)+3]>4)
28259 {
28260 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28261 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28262 }
28263
28264
28265 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28266 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28267 ddr_test_watchdog_clear();
28268 if (lane_step<8)
28269 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28270 else if(lane_step<10)
28271 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28272
28273 //here will dead
28274 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28275
28276 if (temp_test_error)
28277 {
28278 run_command("reset",0);
28279 while (1) ;
28280 }
28281 else
28282 {
28283 if ( num_array[8+(lane_step<<2)+3]>4)
28284 {
28285 ddr_test_watchdog_disable(); //s
28286 run_command("run storeboot",0);
28287 while (1) ;
28288 }
28289 else
28290 {
28291 ddr_test_watchdog_clear();
28292 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28293 if (lane_step<8)
28294 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28295 else if(lane_step<10)
28296 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28297
28298 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28299 temp_count=1;
28300 read_write_window_test_parameter(data_source,
28301 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28302
28303 if (num_array[8+(lane_step<<2)+3]>4)
28304 {
28305 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28306 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28307 }
28308
28309 run_command("reset",0);
28310 while (1) ;
28311 }
28312 }
28313
28314 }
28315 }
28316
28317
28318 }
28319
28320 else if((num_array[8+(lane_step<<2)+3]==2)||((num_array[8+(lane_step<<2)+3]==6))) //test right edge begin
28321 {
28322 /*
28323 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
28324 num_array[2] = test_arg_2_step ;
28325 num_array[3] = test_arg_3_freq ;
28326 num_array[4] = test_arg_4_step_status ;
28327 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
28328 num_array[6] = test_arg_6_lcdlr_temp_count ;
28329 num_array[7] = test_arg_7_magic_number ;
28330 */
28331 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
28332 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
28333 temp_count=1;
28334 read_write_window_test_parameter(data_source,
28335 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28336
28337 if (num_array[8+(lane_step<<2)+3]>4)
28338 {
28339 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28340 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28341 }
28342
28343
28344 num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
28345 temp_count=5;
28346 read_write_window_test_parameter(data_source,
28347 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28348
28349 num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
28350 temp_count=8+(lane_step<<2)+2;
28351 read_write_window_test_parameter(data_source,
28352 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28353
28354 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28355 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
28356 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28357 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
28358 //test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
28359 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
28360 temp_count=6;
28361 read_write_window_test_parameter(data_source, //temp_lcdlr
28362 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28363
28364 num_array[8+(lane_step<<2)+3]=num_array[8+(lane_step<<2)+3]+1;
28365 temp_count=8+(lane_step<<2)+3;
28366 read_write_window_test_parameter(data_source, //lane status
28367 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28368 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28369 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28370 ddr_test_watchdog_clear();
28371 if (lane_step<8)
28372 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28373 else if(lane_step<10)
28374 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28375
28376 //here will dead
28377 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28378
28379 if (temp_test_error)
28380 {
28381 run_command("reset",0);
28382 while (1) ;
28383 }
28384 else
28385 {
28386
28387 if ( num_array[8+(lane_step<<2)+3]>4)
28388 {
28389 ddr_test_watchdog_disable(); //s
28390 run_command("run storeboot",0);
28391 while (1) ;
28392 }
28393 else
28394 {
28395
28396 ddr_test_watchdog_clear();
28397 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28398 if (lane_step<8)
28399 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28400 else if(lane_step<10)
28401 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28402
28403 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28404 temp_count=1;
28405 read_write_window_test_parameter(data_source,
28406 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28407 if (num_array[8+(lane_step<<2)+3]>4)
28408 {
28409 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28410 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28411 }
28412
28413 run_command("reset",0);
28414 while (1) ;
28415 }
28416
28417 }
28418 }
28419 else if((num_array[8+(lane_step<<2)+3]==3)||(num_array[8+(lane_step<<2)+3]==7)) //test right edge ongoing -loop
28420 {
28421
28422 if ((num_array[8+(lane_step<<2)+2]+1) >= (num_array[6]))
28423 {
28424 if (num_array[1] == DDR_TEST_NULL)
28425 {printf("default value not stable ,or recovery sticky?\n");
28426 }
28427 num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
28428 temp_count=8+(lane_step<<2)+3;
28429 read_write_window_test_parameter(data_source,
28430 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28431
28432 num_array[5]=0; //update edge lcdlr
28433 temp_count=5;
28434 read_write_window_test_parameter(data_source,
28435 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28436 if (num_array[1] == DDR_TEST_FAIL)
28437 num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
28438 if (num_array[1] == DDR_TEST_PASS)
28439 num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
28440 temp_count=8+(lane_step<<2)+2;
28441 read_write_window_test_parameter(data_source,
28442 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28443
28444 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
28445 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
28446 temp_count=6;
28447 read_write_window_test_parameter(data_source,
28448 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28449 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
28450 temp_count=1; //update test error flag
28451 read_write_window_test_parameter(data_source,
28452 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28453 if (num_array[8+(lane_step<<2)+3]>4)
28454 {
28455 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28456 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28457 }
28458
28459
28460 run_command("reset",0);
28461 while (1) ;
28462 }
28463 else
28464 {
28465 if (num_array[1] == DDR_TEST_NULL)
28466 {printf("default value not stable ,or recovery sticky?\n");
28467 }
28468 else if(num_array[1]==DDR_TEST_FAIL)
28469 {
28470
28471
28472
28473 {
28474 // num_array[8+(lane_step<<2)+3]=3; //update status
28475 temp_count=8+(lane_step<<2)+3;
28476 read_write_window_test_parameter(data_source,
28477 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28478
28479
28480 num_array[5]=num_array[6]; //update edge lcdlr
28481 temp_count=5;
28482 read_write_window_test_parameter(data_source,
28483 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28484
28485 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28486 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
28487 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28488 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
28489 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
28490 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
28491 temp_count=6;
28492 read_write_window_test_parameter(data_source,
28493 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28494
28495 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
28496 // temp_count=8+(lane_step<<2)+1;
28497 // read_write_window_test_parameter(data_source,
28498 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28499 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
28500 temp_count=1; //update test error flag
28501 read_write_window_test_parameter(data_source,
28502 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28503
28504 if (num_array[8+(lane_step<<2)+3]>4)
28505 {
28506 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28507 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28508 }
28509
28510
28511 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28512 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28513 ddr_test_watchdog_clear();
28514 if (lane_step<8)
28515 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28516 else if(lane_step<10)
28517 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28518
28519 //here will dead
28520 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28521
28522 if (temp_test_error)
28523 {
28524 run_command("reset",0);
28525 while (1) ;
28526 }
28527 else
28528 {
28529 if ( num_array[8+(lane_step<<2)+3]>4)
28530 {
28531 ddr_test_watchdog_disable(); //s
28532 run_command("run storeboot",0);
28533 while (1) ;
28534 }
28535 else
28536 {
28537
28538 ddr_test_watchdog_clear();
28539 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28540 if (lane_step<8)
28541 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28542 else if(lane_step<10)
28543 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28544
28545 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28546 temp_count=1;
28547 read_write_window_test_parameter(data_source,
28548 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28549
28550 if (num_array[8+(lane_step<<2)+3]>4)
28551 {
28552 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28553 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28554 }
28555
28556 run_command("reset",0);
28557 while (1) ;
28558 }
28559
28560 }
28561 }
28562 }
28563
28564 else if(num_array[1]==DDR_TEST_PASS)
28565 {
28566 // num_array[8+(lane_step<<2)+3]=3; //update status
28567 temp_count=8+(lane_step<<2)+3;
28568 read_write_window_test_parameter(data_source,
28569 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28570
28571 num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
28572 temp_count=8+(lane_step<<2)+2;
28573 read_write_window_test_parameter(data_source,
28574 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28575
28576 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
28577 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
28578 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
28579 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
28580 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
28581 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
28582 temp_count=6;
28583 read_write_window_test_parameter(data_source,
28584 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28585
28586 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
28587 temp_count=1; //update test error flag
28588 read_write_window_test_parameter(data_source,
28589 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28590 if (num_array[8+(lane_step<<2)+3]>4)
28591 {
28592 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28593 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28594 }
28595
28596
28597 ddr_test_watchdog_enable(test_watchdog_time_s); //s
28598 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
28599 ddr_test_watchdog_clear();
28600 if (lane_step<8)
28601 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28602 else if(lane_step<10)
28603 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
28604
28605 //here will dead
28606 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
28607
28608 if (temp_test_error)
28609 {
28610 run_command("reset",0);
28611 while (1) ;
28612 }
28613 else
28614 {
28615 if ( num_array[8+(lane_step<<2)+3]>4)
28616 {
28617 ddr_test_watchdog_disable(); //s
28618 run_command("run storeboot",0);
28619 while (1) ;
28620 }
28621 else
28622 {
28623 ddr_test_watchdog_clear();
28624 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
28625 if (lane_step<8)
28626 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28627 else if(lane_step<10)
28628 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
28629
28630 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
28631 temp_count=1;
28632 read_write_window_test_parameter(data_source,
28633 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28634 if (num_array[8+(lane_step<<2)+3]>4)
28635 {
28636 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28637 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28638 }
28639
28640 run_command("reset",0);
28641 while (1) ;
28642 }
28643
28644 }
28645
28646 }
28647 }
28648
28649
28650 }
28651 }
28652 }
28653 if (lane_step >= 10) //finish
28654 {
28655 ddr_test_watchdog_disable(); //s
28656 printf("close watchdog\n");
28657 }
28658
28659 // unsigned int acmdlr= 0;
28660 unsigned int delay_step_x100= 0;
28661
28662 {
28663 //acmdlr=do_ddr_read_acmdlr();
28664 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
28665 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
28666 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
28667
28668 for ((lane_step=0);(lane_step<4);(lane_step++))
28669 {
28670 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
28671 lane_step,
28672 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
28673 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
28674 }
28675 lane_step=4;
28676 {
28677 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
28678 4,
28679 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
28680 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
28681 }
28682 printf("\n\n-----------------------------------------------------------------------------\n\n");
28683 {
28684 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
28685 clk_setup ps| clk_hold ps|adj_percent[100]\n");
28686
28687 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
28688 4,
28689 num_array[8+(lane_step)*8+0],
28690 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
28691 )/100),
28692 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
28693 )/100),
28694
28695 0,
28696 0,
28697 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
28698 2*num_array[8+(lane_step)*8+0]));
28699 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
28700 4,
28701 num_array[8+(lane_step)*8+4],
28702 0,
28703 0,
28704 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
28705 )/100),
28706 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
28707 )/100),
28708
28709 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
28710 2*num_array[8+(lane_step)*8+4]));
28711 }
28712 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
28713 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
28714
28715
28716 for ((lane_step=0);(lane_step<4);(lane_step++))
28717 {
28718 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
28719 lane_step,
28720 num_array[8+(lane_step)*8+0],
28721 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
28722 )/100),
28723 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
28724 )/100),
28725
28726 0,
28727 0,
28728 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
28729 2*num_array[8+(lane_step)*8+0]));
28730
28731 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
28732 lane_step,
28733 num_array[8+(lane_step)*8+4],
28734 0,
28735 0,
28736
28737 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
28738 )/100),
28739 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
28740 )/100),
28741 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
28742 2*num_array[8+(lane_step)*8+4]));
28743
28744
28745
28746 }
28747 }
28748
28749
28750 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
28751 {
28752 test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
28753 num_array[2]=test_arg_2_step;
28754 temp_count=2;
28755 read_write_window_test_parameter(data_source,
28756 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28757 run_command("reset",0);
28758 while (1) ;
28759
28760 }
28761
28762 if (test_arg_2_step == DDR_TEST_STATUS_KERNEL_ONGING)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
28763 {
28764 test_arg_2_step=DDR_TEST_STATUS_KERNEL_FINISH;
28765 num_array[2]=test_arg_2_step;
28766 temp_count=2;
28767 read_write_window_test_parameter(data_source,
28768 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28769
28770 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28771 DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
28772 num_array[1]=DDR_TEST_NULL;
28773 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
28774 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
28775 {
28776 ddr_test_watchdog_disable(); //s
28777 run_command("run storeboot",0);
28778 while (1) ;
28779 }
28780 }
28781
28782
28783
28784
28785
28786
28787 // if( num_array[8+(lane_step<<2)+3]>4)
28788
28789
28790
28791 return 1;
28792}
28793
28794
28795int do_ddr_uboot_kernel_window_use_source_quick_methods(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
28796{
28797 //env_set storeboot "ddr_test_cmd 0x34 2 6 20 0 0x100000 0x4000000"
28798 printf("\nsetenv bootcmd ddr_test_cmd 0x34 2 6 20 0 0x100000 0x4000000 \n");
28799 printf("\nEnter do_ddr_uboot_window_use_source function\n");
28800 printf("\n--- watchdog should >15s\n");
28801#define DDR_TEST_NULL 0
28802#define DDR_TEST_PASS 1
28803#define DDR_TEST_FAIL 2
28804
28805#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
28806#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
28807 //PREG_STICKY_REG5
28808
28809
28810#define DDR_TEST_STATUS_UBOOT_ONGOING 1
28811#define DDR_TEST_STATUS_UBOOT_FINISH 2
28812#define DDR_TEST_STATUS_KERNEL_ONGING 3
28813#define DDR_TEST_STATUS_KERNEL_FINISH 4
28814
28815#define DDR_TEST_METHOD_DIVIDER_2 1 //AB METHOD A is failing B is passing value
28816#define DDR_TEST_METHOD_DECREASE 2
28817#define DDR_TEST_METHOD_DECREASE_ALL_SAMETIME 3
28818
28819 char *endp;
28820 unsigned int lane_disable= 0;
28821 unsigned int data_source= 0;
28822 unsigned int ddr_data_test_method=DDR_TEST_METHOD_DIVIDER_2;
28823 unsigned int ddr_add_test_method=DDR_TEST_METHOD_DIVIDER_2;
28824 unsigned int ddr_test_method=DDR_TEST_METHOD_DIVIDER_2;
28825
28826 unsigned int ddr_enable_kernel_window_test_flag=0;
28827
28828 unsigned int ddr_data_test_size=0x1000000;
28829 unsigned int ddr_add_test_size=0x10000000;
28830 unsigned int ddr_test_size=0x10000000;
28831 unsigned int ddr_lcdlr_test_offset=0;
28832 //unsigned int ddr_lcdlr_test_org_save=0;
28833 unsigned int ddr_lcdlr_test_temp_value=0;
28834
28835 unsigned int address_test_watchdog_time_s=15;
28836 unsigned int test_watchdog_time_s=15;
28837
28838 error_outof_count_flag =1; //for quick out of error
28839 if (argc >1) {
28840 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
28841 if (*argv[1] == 0 || *endp != 0)
28842 {
28843 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
28844 }
28845 }
28846 if (argc >2) {
28847 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
28848 if (*argv[2] == 0 || *endp != 0)
28849 {
28850 watchdog_time_s= 15;
28851 }
28852 }
28853 printf("watchdog_time_s==%d\n",watchdog_time_s);
28854 test_watchdog_time_s=watchdog_time_s;
28855 //test_watchdog_time_s=address_test_watchdog_time_s;
28856 if (argc >3) {
28857 address_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
28858 if (*argv[3] == 0 || *endp != 0)
28859 {
28860 address_test_watchdog_time_s= watchdog_time_s;
28861 }
28862 }
28863 printf("address_test_watchdog_time_s==%d\n",address_test_watchdog_time_s);
28864 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
28865 if (argc >4) {
28866 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
28867 if (*argv[4] == 0 || *endp != 0)
28868 {
28869 lane_disable= 0;
28870 }
28871 }
28872 printf("lane_disable==0x%08x\n",lane_disable);
28873
28874 if (argc >5) {
28875 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
28876 if (*argv[5] == 0 || *endp != 0)
28877 {
28878 ddr_data_test_size= 0x100000;
28879 }
28880 }
28881 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
28882 if (argc >6) {
28883 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
28884 if (*argv[6] == 0 || *endp != 0)
28885 {
28886 ddr_add_test_size= 0x10000000;
28887 }
28888 }
28889 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
28890 if (argc >7) {
28891 ddr_data_test_method = simple_strtoull_ddr(argv[7], &endp, 0);
28892 if (*argv[7] == 0 || *endp != 0)
28893 {
28894 ddr_data_test_method= DDR_TEST_METHOD_DIVIDER_2;
28895 }
28896 }
28897 printf("ddr_data_test_method==0x%08x\n",ddr_data_test_method);
28898 if (argc >8) {
28899 ddr_add_test_method = simple_strtoull_ddr(argv[8], &endp, 0);
28900 if (*argv[8] == 0 || *endp != 0)
28901 {
28902 ddr_add_test_method= DDR_TEST_METHOD_DIVIDER_2;
28903 }
28904 }
28905 printf("ddr_add_test_method==0x%08x\n",ddr_add_test_method);
28906
28907 if (argc >9) {
28908 ddr_enable_kernel_window_test_flag = simple_strtoull_ddr(argv[9], &endp, 0);
28909 if (*argv[9] == 0 || *endp != 0)
28910 {
28911 ddr_enable_kernel_window_test_flag= 0;
28912 }
28913 }
28914 printf("ddr_enable_kernel_window_test_flag==0x%08x\n",ddr_enable_kernel_window_test_flag);
28915
28916 unsigned int rank_index=0;
28917 unsigned int temp_count=0;
28918 unsigned int ddr_test_data_array_max=100;
28919 unsigned int num_array[100];//8 flag 32_data add_8 32_data add_8
28920
28921 unsigned int temp_test_error=0;
28922 unsigned int lcdlr_min=0;
28923 unsigned int lcdlr_max=0;
28924 memset(num_array, 0, sizeof(num_array));
28925 char str[1024]="";
28926
28927 if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
28928 ddr_test_data_array_max=64;
28929 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
28930 {
28931 num_array[temp_count]= read_write_window_test_parameter(data_source,
28932 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
28933 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
28934 }
28935
28936 unsigned int test_arg_0_orgt_store_lcdlr_value =0; //best_lcdlr_value
28937 unsigned int test_arg_1_test_error_flag =0; //min cmd
28938 unsigned int test_arg_2_step =0; //step 0 init -1 UBOOT ONGOING 2 UBOOT FINISH 3 KERNEL ONGOING 4 KERNEL FINISH
28939 unsigned int test_arg_3_freq =0;
28940 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
28941 unsigned int test_arg_5_ab_edge_lcdlr_value =0;
28942 unsigned int test_arg_6_lcdlr_temp_count =0;
28943 unsigned int test_arg_7_magic_number =0;
28944 unsigned int org_lcdlr_value_temp=0;
28945 unsigned int acmdlr=0;
28946 acmdlr=do_ddr_read_acmdlr();
28947
28948 test_arg_0_orgt_store_lcdlr_value=num_array[0];
28949 test_arg_1_test_error_flag=num_array[1];
28950 test_arg_2_step=num_array[2];
28951 test_arg_3_freq=num_array[3];
28952 test_arg_4_step_status=num_array[4];
28953 test_arg_5_ab_edge_lcdlr_value=num_array[5];
28954 test_arg_6_lcdlr_temp_count=num_array[6];
28955 test_arg_7_magic_number=num_array[7];
28956 printf("test_arg_0_orgt_store_lcdlr_value==%d\n",test_arg_0_orgt_store_lcdlr_value);
28957 printf("test_arg_1_test_error_flag==%d\n",test_arg_1_test_error_flag);
28958 printf("test_arg_2_step==%d\n",test_arg_2_step);
28959 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
28960 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
28961 printf("test_arg_5_ab_edge_lcdlr_value=%d\n",num_array[5]);
28962 printf("test_arg_6_lcdlr_temp_count=%d\n",num_array[6]);
28963 printf("test_arg_7_magic_number=%d\n",num_array[7]);
28964
28965
28966
28967 if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
28968 {
28969 }
28970 else
28971 {
28972
28973 test_arg_0_orgt_store_lcdlr_value=0;
28974 test_arg_5_ab_edge_lcdlr_value=0;
28975 test_arg_2_step=0;
28976 test_arg_6_lcdlr_temp_count=0;
28977 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
28978 }
28979 //printf("boot times==%d\n",test_arg_5_ab_edge_lcdlr_value);
28980 num_array[0] = test_arg_0_orgt_store_lcdlr_value ;
28981 num_array[1] = test_arg_1_test_error_flag ;
28982 num_array[2] = test_arg_2_step ;
28983 num_array[3] = test_arg_3_freq ;
28984 num_array[4] = test_arg_4_step_status ;
28985 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
28986 num_array[6] = test_arg_6_lcdlr_temp_count ;
28987 num_array[7] = test_arg_7_magic_number ;
28988
28989 for (temp_count= 0;temp_count < 8; temp_count++)
28990 {
28991 read_write_window_test_parameter(data_source,
28992 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
28993 }
28994
28995
28996
28997 if (test_arg_2_step)
28998 {
28999 if (test_arg_3_freq != global_ddr_clk) //
29000 {
29001 printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
29002 sprintf(str,"d2pll %d",test_arg_3_freq);
29003 printf("\nstr=%s\n",str);
29004 run_command(str,0);
29005 while (1) ;
29006 }
29007 }
29008 if (test_arg_2_step == 0)
29009 {
29010 {
29011
29012
29013
29014 test_arg_0_orgt_store_lcdlr_value=0;
29015 test_arg_1_test_error_flag=0;
29016 test_arg_2_step=DDR_TEST_STATUS_UBOOT_ONGOING;
29017 test_arg_3_freq=global_ddr_clk;
29018 test_arg_4_step_status=0;
29019 test_arg_5_ab_edge_lcdlr_value=0;
29020 test_arg_6_lcdlr_temp_count=lcdlr_min;
29021 test_arg_7_magic_number=DMC_STICKY_MAGIC_1;
29022 num_array[0] = test_arg_0_orgt_store_lcdlr_value ;
29023 num_array[1] = test_arg_1_test_error_flag ;
29024 num_array[2] = test_arg_2_step ;
29025 num_array[3] = test_arg_3_freq ;
29026 num_array[4] = test_arg_4_step_status ;
29027 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
29028 num_array[6] = test_arg_6_lcdlr_temp_count ;
29029 num_array[7] = test_arg_7_magic_number ;
29030
29031
29032 for (temp_count= 0;temp_count < 8; temp_count++)
29033 {
29034 read_write_window_test_parameter(data_source,
29035 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29036 }
29037
29038 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29039 // DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
29040 //for (temp_count = 8; temp_count< 48;temp_count++) {
29041 // num_array[temp_count]=0;
29042 //}
29043
29044 for (temp_count = 8; temp_count < (32+8); temp_count++) //data
29045 {
29046 //printf("1temp_count=%d\n",temp_count);
29047
29048 if ((temp_count%4) == 0) //org
29049 {
29050 if (((temp_count-8)/4)<8)
29051 {
29052 lcdlr_min=0;
29053 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29054 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29055 //if(lane_step==9)
29056 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
29057 }
29058 else if(((temp_count-8)/4)<10)
29059 {
29060 lcdlr_min=0;
29061 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29062 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29063 if (((temp_count-8)/4) == 9)
29064 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
29065 }
29066 //printf("2temp_count=%d\n",temp_count);
29067 //num_array[temp_count]=0;
29068 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
29069 num_array[temp_count]=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,((temp_count-8)>>2),num_array[temp_count],DDR_PARAMETER_READ);
29070 num_array[temp_count+1]=lcdlr_min;
29071 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
29072 num_array[temp_count+3]=0;
29073 //temp_count=temp_count+4;
29074 }
29075
29076
29077
29078 }
29079
29080 for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
29081 {
29082 if ((temp_count%4) == 0) //org
29083 {
29084 if (((temp_count-8)/4)<8)
29085 {
29086 lcdlr_min=0;
29087 lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29088 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29089 //if(lane_step==9)
29090 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
29091 }
29092 else if(((temp_count-8)/4)<10)
29093 {
29094 lcdlr_min=0;
29095 lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29096 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29097 if (((temp_count-8)/4) == 9)
29098 lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
29099 }
29100 //num_array[temp_count]=0;
29101 //unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
29102 num_array[temp_count]=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,((temp_count-8-32)>>2),num_array[temp_count],DDR_PARAMETER_READ);
29103 num_array[temp_count+1]=lcdlr_min;
29104 num_array[temp_count+2]=lcdlr_max;//num_array[temp_count];
29105 num_array[temp_count+3]=0;
29106 }
29107
29108
29109 }
29110
29111
29112
29113
29114#if (CONFIG_DDR_PHY<=P_DDR_PHY_905X)
29115 printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
29116 printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
29117 printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
29118 printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
29119 if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
29120 lane_disable= lane_disable|1;
29121 if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
29122 lane_disable= lane_disable|(1<<1);
29123 if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
29124 lane_disable= lane_disable|(1<<2);
29125 if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
29126 lane_disable= lane_disable|(1<<3);
29127
29128#endif
29129 if (lane_disable)
29130 {if(lane_disable&0x1){
29131 num_array[8+3]=0xffff;
29132 num_array[8+4+3]=0xffff;
29133 }
29134 if (lane_disable&0x2) {
29135 num_array[8+3+8]=0xffff;
29136 num_array[8+4+3+8]=0xffff;
29137 }
29138 if (lane_disable&0x4) {
29139 num_array[8+3+8+8]=0xffff;
29140 num_array[8+4+3+8+8]=0xffff;
29141 }
29142 if (lane_disable&0x8) {
29143 num_array[8+3+8+8+8]=0xffff;
29144 num_array[8+4+3+8+8+8]=0xffff;
29145 }
29146 printf("lane_disable==%x\n",lane_disable);
29147 if (lane_disable&0x10) {
29148 num_array[8+3+8+8+8+8]=0xffff;
29149 }
29150 if (lane_disable&0x20) {
29151 num_array[8+4+3+8+8+8+8]=0xffff;
29152
29153 }
29154 }
29155
29156
29157 }
29158
29159
29160
29161
29162 for (temp_count= 0; temp_count< 48;temp_count++) {
29163 num_array[temp_count]= read_write_window_test_parameter(data_source,
29164 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29165 }
29166 }
29167
29168 //test_arg_2_step++;
29169 num_array[2]=test_arg_2_step;
29170 for (temp_count = 1; temp_count < 48; temp_count++)
29171 {
29172 printf("%d %d\n", temp_count,num_array[temp_count]);
29173 }
29174 temp_count=2;
29175 num_array[temp_count]= read_write_window_test_parameter(data_source,
29176 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29177 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29178 // DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
29179 //for (i = 0; i < 48; i++) {
29180
29181 // writel(num_array[i],(sticky_reg_base_add+(i<<2)));
29182 //}
29183
29184
29185 //for (i = 8; i < 48; i++) {
29186 //num_array[i]=readl((sticky_reg_base_add+(i<<2)));
29187 //printf("ddr_test_data_num_%04d==%d\n",i,num_array[i]);
29188 //}
29189
29190 ///*
29191 unsigned int lane_step=0;
29192 unsigned int lane_step_count=0;
29193
29194 printf("\nstart loop test\n");
29195
29196 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
29197 {
29198 if (ddr_enable_kernel_window_test_flag == 0)
29199 {
29200 if ((num_array[(lane_step<<2)+3+8]<(0x4)))
29201 {break;
29202 }
29203 }
29204 else if(test_arg_2_step<DDR_TEST_STATUS_KERNEL_ONGING)
29205 {
29206 if ((num_array[(lane_step<<2)+3+8]<(0x4)))
29207 {break;
29208 }
29209 }
29210 }
29211
29212 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_ONGOING)
29213 {if(lane_step>9)
29214 {
29215 test_arg_2_step=DDR_TEST_STATUS_UBOOT_FINISH;
29216 printf("uboot test result: \n");
29217 }
29218 }
29219
29220
29221 if (ddr_enable_kernel_window_test_flag)
29222 {
29223 if (test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
29224 {
29225 for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
29226 {
29227
29228 {
29229 if ((num_array[(lane_step<<2)+3+8]<(0x4+4)))
29230 {break;
29231 }
29232 }
29233 }
29234 }
29235 }
29236
29237 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
29238 {
29239 //test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
29240 }
29241 else
29242 {
29243 printf("\nstart test lane_step =%d\n",lane_step);
29244 if (lane_step<10)
29245 {
29246 if (lane_step<8)
29247 {
29248 test_watchdog_time_s=watchdog_time_s;
29249 ddr_test_size=ddr_data_test_size;
29250 ddr_test_method=ddr_data_test_method;
29251 //lcdlr_min=0;
29252 //lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);//do_ddr_read_acmdlr();
29253 }
29254 else
29255 {
29256 test_watchdog_time_s=address_test_watchdog_time_s;
29257 ddr_test_size=ddr_add_test_size;
29258 ddr_test_method=ddr_add_test_method;
29259 //lcdlr_min=0;
29260 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29261 //lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
29262 //if(lane_step==9)
29263 //lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
29264 }
29265
29266 if (num_array[8+(lane_step<<2)+3]>4) //from kernel
29267 {
29268 num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29269 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
29270 // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29271 // DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29272 }
29273
29274 if (((num_array[8+(lane_step<<2)+3] == 0)) || ((num_array[8+(lane_step<<2)+3] == 4))) //test left edge begin
29275 {
29276 /*
29277 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
29278 num_array[2] = test_arg_2_step ;
29279 num_array[3] = test_arg_3_freq ;
29280 num_array[4] = test_arg_4_step_status ;
29281 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
29282 num_array[6] = test_arg_6_lcdlr_temp_count ;
29283 num_array[7] = test_arg_7_magic_number ;
29284 */
29285 // test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
29286 // num_array[0]=test_arg_0_orgt_store_lcdlr_value;
29287 // temp_count=0;
29288 // read_write_window_test_parameter(data_source,
29289 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29290
29291
29292 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29293 {
29294 test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+1]);
29295 num_array[0]=test_arg_0_orgt_store_lcdlr_value;
29296 temp_count=0;
29297 read_write_window_test_parameter(data_source,
29298 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29299 }
29300
29301 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
29302 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
29303 temp_count=1;
29304 read_write_window_test_parameter(data_source,
29305 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29306
29307 if (num_array[8+(lane_step<<2)+3]>4)
29308 {
29309 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29310 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29311 }
29312
29313 read_write_window_test_flag(data_source,
29314 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29315
29316 num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
29317 temp_count=5;
29318 read_write_window_test_parameter(data_source,
29319 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29320
29321 (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
29322 temp_count=8+(lane_step<<2)+1;
29323 read_write_window_test_parameter(data_source,
29324 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29325
29326 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
29327 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+0])>>1);
29328 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
29329 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29330 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29331 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29332
29333 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
29334 temp_count=6;
29335 read_write_window_test_parameter(data_source, //temp_lcdlr
29336 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29337
29338 num_array[8+(lane_step<<2)+3]=(num_array[8+(lane_step<<2)+3]+1);
29339 temp_count=8+(lane_step<<2)+3;
29340 read_write_window_test_parameter(data_source, //lane status
29341 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29342
29343
29344 {
29345 ddr_test_watchdog_enable(test_watchdog_time_s); //s
29346 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
29347 ddr_test_watchdog_clear();
29348 }
29349
29350 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29351 {
29352 ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//test_arg_0_orgt_store_lcdlr_value;//num_array[8+(lane_step<<2)+1];
29353 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
29354 (num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29355 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
29356 {
29357 if (num_array[8+(lane_step_count<<2)+3]<9)
29358 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29359 (num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29360 }
29361 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29362 {
29363 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
29364 if (lane_step_count == 9)
29365 {if (ddr_lcdlr_test_temp_value>0x3f)
29366 ddr_lcdlr_test_temp_value=0x3f;
29367 }
29368 if (num_array[8+(lane_step_count<<2)+3]<9)
29369 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29370 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29371 }
29372 }
29373 else
29374 {
29375 if (lane_step<8)
29376 {
29377 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29378 }
29379 else if(lane_step<10)
29380 {
29381 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29382 }
29383 }
29384
29385 //here will dead
29386
29387 {
29388 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
29389 }
29390 //if( num_array[8+(lane_step<<2)+3]>4)
29391
29392
29393 if (temp_test_error)
29394 {
29395 run_command("reset",0);
29396 while (1) ;
29397 }
29398 else
29399 {
29400 if ( num_array[8+(lane_step<<2)+3]>4)
29401 {
29402 ddr_test_watchdog_disable(); //s
29403 run_command("run storeboot",0);
29404 while (1) ;
29405 }
29406 else
29407 {
29408 ddr_test_watchdog_clear();
29409 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
29410
29411 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29412 {
29413 ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
29414 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
29415 {
29416 if (num_array[8+(lane_step_count<<2)+3]<9)
29417 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29418 (num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29419 }
29420 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29421 {
29422 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
29423 if (lane_step_count == 9)
29424 {if (ddr_lcdlr_test_temp_value>0x3f)
29425 ddr_lcdlr_test_temp_value=0x3f;
29426 }
29427 if (num_array[8+(lane_step_count<<2)+3]<9)
29428 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29429 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29430 }
29431 }
29432 else
29433 {
29434
29435 if (lane_step<8)
29436 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29437 else if(lane_step<10)
29438 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29439 }
29440
29441 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
29442 temp_count=1;
29443 read_write_window_test_parameter(data_source,
29444 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29445 if (num_array[8+(lane_step<<2)+3]>4)
29446 {
29447 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29448 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29449 }
29450
29451 run_command("reset",0);
29452 while (1) ;
29453 }
29454 }
29455 }
29456 else if((num_array[8+(lane_step<<2)+3]==1)||((num_array[8+(lane_step<<2)+3]==5))) //test left edge begin) //test left edge ongoing -loop
29457 {
29458
29459 if ((num_array[6]+1) >= (num_array[8+(lane_step<<2)+1]))
29460 {
29461 if (num_array[1] == DDR_TEST_NULL)
29462 {printf("default value not stable ,or recovery sticky?\n");
29463 }
29464
29465
29466
29467 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29468 {
29469 //ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
29470 for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
29471 {
29472
29473 num_array[8+(lane_step_count<<2)+3]= num_array[8+(lane_step_count<<2)+3]+1; //update status
29474 lane_step_count=8+(lane_step_count<<2)+3;
29475 if (num_array[8+(lane_step_count<<2)+3]<9)
29476 read_write_window_test_parameter(data_source,
29477 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29478 }
29479
29480
29481 }
29482 else
29483 {
29484 num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
29485 temp_count=8+(lane_step<<2)+3;
29486 read_write_window_test_parameter(data_source,
29487 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29488 }
29489
29490 num_array[5]=0; //update edge lcdlr
29491 temp_count=5;
29492 read_write_window_test_parameter(data_source,
29493 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29494
29495 // if(num_array[1]==DDR_TEST_FAIL)
29496 // num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
29497 // if(num_array[1]==DDR_TEST_PASS)
29498 // num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
29499 // temp_count=8+(lane_step<<2)+1;
29500
29501
29502 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29503 {
29504
29505 test_arg_0_orgt_store_lcdlr_value= num_array[0];
29506 if (num_array[1] == DDR_TEST_FAIL)
29507 {
29508 ddr_lcdlr_test_offset=num_array[8+(lane_step<<2)+1]+1-test_arg_0_orgt_store_lcdlr_value;
29509 }
29510 if (num_array[1] == DDR_TEST_PASS)
29511 {
29512 ddr_lcdlr_test_offset=num_array[8+(lane_step<<2)+1]+0-test_arg_0_orgt_store_lcdlr_value;
29513 }
29514 temp_count=8+(lane_step<<2)+2;
29515 read_write_window_test_parameter(data_source,
29516 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29517 for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
29518 {
29519 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]+ddr_lcdlr_test_offset);
29520 if (lane_step_count == 9)
29521 {
29522 if ((num_array[8+(lane_step_count<<2)+2]+ddr_lcdlr_test_offset)>0x3f)
29523 ddr_lcdlr_test_temp_value=0x3f;
29524 }
29525 if (num_array[8+(lane_step_count<<2)+3]<9)
29526 read_write_window_test_parameter(data_source,
29527 (8+(lane_step_count<<2)+2) ,ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29528 }
29529
29530
29531 }
29532 else
29533 {
29534 if (num_array[1] == DDR_TEST_FAIL)
29535 num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
29536 if (num_array[1] == DDR_TEST_PASS)
29537 num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
29538 temp_count=8+(lane_step<<2)+1;
29539 read_write_window_test_parameter(data_source,
29540 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29541 }
29542
29543 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
29544 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
29545 temp_count=6;
29546 read_write_window_test_parameter(data_source,
29547 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29548 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
29549 temp_count=1; //update test error flag
29550 read_write_window_test_parameter(data_source,
29551 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29552
29553 if (num_array[8+(lane_step<<2)+3]>4)
29554 {
29555 // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29556 // DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
29557 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29558 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29559 }
29560
29561 // test_arg_0_orgt_store_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
29562 // num_array[0]=test_arg_0_orgt_store_lcdlr_value;
29563 // temp_count=0;
29564 // read_write_window_test_parameter(data_source,
29565 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29566 run_command("reset",0);
29567 while (1) ;
29568
29569 }
29570 else
29571 {
29572 if (num_array[1] == DDR_TEST_NULL)
29573 {printf("default value not stable ,or recovery sticky?\n");
29574 }
29575 else if(num_array[1]==DDR_TEST_FAIL)
29576 {
29577
29578
29579
29580 {
29581 // num_array[8+(lane_step<<2)+3]=1; //update status
29582 temp_count=8+(lane_step<<2)+3;
29583 read_write_window_test_parameter(data_source,
29584 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29585
29586
29587 num_array[5]=num_array[6]; //update edge lcdlr
29588 temp_count=5;
29589 read_write_window_test_parameter(data_source,
29590 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29591
29592 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
29593 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
29594 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
29595 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29596 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29597 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29598 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
29599 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
29600 temp_count=6;
29601 read_write_window_test_parameter(data_source,
29602 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29603
29604 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
29605 // temp_count=8+(lane_step<<2)+1;
29606 // read_write_window_test_parameter(data_source,
29607 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29608 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
29609 temp_count=1; //update test error flag
29610 read_write_window_test_parameter(data_source,
29611 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29612
29613 if (num_array[8+(lane_step<<2)+3]>4)
29614 {
29615 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29616 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29617 }
29618
29619
29620 ddr_test_watchdog_enable(test_watchdog_time_s); //s
29621 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
29622 ddr_test_watchdog_clear();
29623
29624 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29625 {
29626
29627 ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//tnum_array[8+(lane_step<<2)+1];
29628 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
29629 (num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29630 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
29631 {
29632 if (num_array[8+(lane_step_count<<2)+3]<9)
29633 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29634 (num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29635 }
29636 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29637 {
29638 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
29639 if (lane_step_count == 9)
29640 {if (ddr_lcdlr_test_temp_value>0x3f)
29641 ddr_lcdlr_test_temp_value=0x3f;
29642 }
29643 if (num_array[8+(lane_step_count<<2)+3]<9)
29644 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29645 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29646 }
29647 }
29648 else
29649 {
29650
29651 if (lane_step<8)
29652 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29653 else if(lane_step<10)
29654 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29655
29656 }
29657 //here will dead
29658 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
29659
29660 if (temp_test_error)
29661 {
29662 run_command("reset",0);
29663 while (1) ;
29664 }
29665 else
29666 {
29667 if ( num_array[8+(lane_step<<2)+3]>4)
29668 {
29669 ddr_test_watchdog_disable(); //s
29670 run_command("run storeboot",0);
29671 while (1) ;
29672 }
29673 else
29674 {
29675
29676 ddr_test_watchdog_clear();
29677 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
29678
29679 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29680 {
29681 ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
29682 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
29683 {
29684 if (num_array[8+(lane_step_count<<2)+3]<9)
29685 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29686 (num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29687 }
29688 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29689 {
29690 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
29691 if (lane_step_count == 9)
29692 {if (ddr_lcdlr_test_temp_value>0x3f)
29693 ddr_lcdlr_test_temp_value=0x3f;
29694 }
29695 if (num_array[8+(lane_step_count<<2)+3]<9)
29696 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29697 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29698 }
29699 }
29700 else
29701 {
29702 if (lane_step<8)
29703 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29704 else if(lane_step<10)
29705 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29706 }
29707
29708 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
29709 temp_count=1;
29710 read_write_window_test_parameter(data_source,
29711 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29712
29713 if (num_array[8+(lane_step<<2)+3]>4)
29714 {
29715 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29716 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29717 }
29718
29719
29720 run_command("reset",0);
29721 while (1) ;
29722 }
29723
29724 }
29725 }
29726 }
29727
29728 else if(num_array[1]==DDR_TEST_PASS)
29729 {
29730 // num_array[8+(lane_step<<2)+3]=1; //update status
29731 temp_count=8+(lane_step<<2)+3;
29732 read_write_window_test_parameter(data_source,
29733 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29734
29735 num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
29736 temp_count=8+(lane_step<<2)+1;
29737 read_write_window_test_parameter(data_source,
29738 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29739
29740 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
29741 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
29742 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
29743 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29744 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29745 test_arg_6_lcdlr_temp_count=((num_array[5])+1);
29746 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //current_test +B //(A+B)/2
29747 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
29748 temp_count=6;
29749 read_write_window_test_parameter(data_source,
29750 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29751
29752 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
29753 temp_count=1; //update test error flag
29754 read_write_window_test_parameter(data_source,
29755 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29756
29757 if (num_array[8+(lane_step<<2)+3]>4)
29758 {
29759 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29760 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29761 }
29762
29763
29764 ddr_test_watchdog_enable(test_watchdog_time_s); //s
29765 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
29766 ddr_test_watchdog_clear();
29767
29768 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29769 {
29770 ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//tnum_array[8+(lane_step<<2)+1];
29771 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
29772 (num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29773 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
29774 {
29775 if (num_array[8+(lane_step_count<<2)+3]<9)
29776 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29777 (num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29778 }
29779 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29780 {
29781 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
29782 if (lane_step_count == 9)
29783 {if (ddr_lcdlr_test_temp_value>0x3f)
29784 ddr_lcdlr_test_temp_value=0x3f;
29785 }
29786 if (num_array[8+(lane_step_count<<2)+3]<9)
29787 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29788 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29789 }
29790 }
29791 else
29792 {
29793 if (lane_step<8)
29794 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29795 else if(lane_step<10)
29796 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29797 }
29798 //here will dead
29799 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
29800
29801 if (temp_test_error)
29802 {
29803 run_command("reset",0);
29804 while (1) ;
29805 }
29806 else
29807 {
29808 if ( num_array[8+(lane_step<<2)+3]>4)
29809 {
29810 ddr_test_watchdog_disable(); //s
29811 run_command("run storeboot",0);
29812 while (1) ;
29813 }
29814 else
29815 {
29816 ddr_test_watchdog_clear();
29817 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
29818 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29819 {
29820 ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
29821 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
29822 {
29823 if (num_array[8+(lane_step_count<<2)+3]<9)
29824 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29825 (num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29826 }
29827 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29828 {
29829 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
29830 if (lane_step_count == 9)
29831 {if (ddr_lcdlr_test_temp_value>0x3f)
29832 ddr_lcdlr_test_temp_value=0x3f;
29833 }
29834 if (num_array[8+(lane_step_count<<2)+3]<9)
29835 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29836 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29837 }
29838 }
29839 else
29840 {
29841 if (lane_step<8)
29842 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29843 else if(lane_step<10)
29844 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
29845 }
29846
29847 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
29848 temp_count=1;
29849 read_write_window_test_parameter(data_source,
29850 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29851
29852 if (num_array[8+(lane_step<<2)+3]>4)
29853 {
29854 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29855 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29856 }
29857
29858 run_command("reset",0);
29859 while (1) ;
29860 }
29861 }
29862
29863 }
29864 }
29865
29866
29867 }
29868
29869 else if((num_array[8+(lane_step<<2)+3]==2)||((num_array[8+(lane_step<<2)+3]==6))) //test right edge begin
29870 {
29871 /*
29872 num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
29873 num_array[2] = test_arg_2_step ;
29874 num_array[3] = test_arg_3_freq ;
29875 num_array[4] = test_arg_4_step_status ;
29876 num_array[5] = test_arg_5_ab_edge_lcdlr_value ;
29877 num_array[6] = test_arg_6_lcdlr_temp_count ;
29878 num_array[7] = test_arg_7_magic_number ;
29879 */
29880
29881 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29882 {
29883 test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+2]);
29884 num_array[0]=test_arg_0_orgt_store_lcdlr_value;
29885 temp_count=0;
29886 read_write_window_test_parameter(data_source,
29887 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29888 }
29889 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
29890 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
29891 temp_count=1;
29892 read_write_window_test_parameter(data_source,
29893 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29894
29895 if (num_array[8+(lane_step<<2)+3]>4)
29896 {
29897 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
29898 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
29899 }
29900
29901
29902 num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
29903 temp_count=5;
29904 read_write_window_test_parameter(data_source,
29905 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29906
29907 num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
29908 temp_count=8+(lane_step<<2)+2;
29909 read_write_window_test_parameter(data_source,
29910 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29911
29912 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
29913 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
29914 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
29915 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
29916 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29917 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
29918 //test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
29919 num_array[6]=test_arg_6_lcdlr_temp_count; //temp_lcdlr
29920 temp_count=6;
29921 read_write_window_test_parameter(data_source, //temp_lcdlr
29922 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29923
29924 num_array[8+(lane_step<<2)+3]=num_array[8+(lane_step<<2)+3]+1;
29925 temp_count=8+(lane_step<<2)+3;
29926 read_write_window_test_parameter(data_source, //lane status
29927 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
29928 ddr_test_watchdog_enable(test_watchdog_time_s); //s
29929 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
29930 ddr_test_watchdog_clear();
29931
29932 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29933 {
29934 ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
29935 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
29936 (num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29937 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
29938 {
29939 if (num_array[8+(lane_step_count<<2)+3]<9)
29940 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29941 (num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29942 }
29943 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29944 {
29945 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
29946 //if(lane_step_count==9)
29947 {if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
29948 ddr_lcdlr_test_temp_value=0;
29949 }
29950 if (num_array[8+(lane_step_count<<2)+3]<9)
29951 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
29952 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
29953 }
29954 }
29955 else
29956 {
29957 if (lane_step<8)
29958 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29959 else if(lane_step<10)
29960 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
29961 }
29962 //here will dead
29963 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
29964
29965 if (temp_test_error)
29966 {
29967 run_command("reset",0);
29968 while (1) ;
29969 }
29970 else
29971 {
29972
29973 if ( num_array[8+(lane_step<<2)+3]>4)
29974 {
29975 ddr_test_watchdog_disable(); //s
29976 run_command("run storeboot",0);
29977 while (1) ;
29978 }
29979 else
29980 {
29981
29982 ddr_test_watchdog_clear();
29983 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
29984 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
29985 {
29986 ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
29987 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
29988 {
29989 if (num_array[8+(lane_step_count<<2)+3]<9)
29990 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
29991 (num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
29992 }
29993 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
29994 {
29995 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
29996 //if(lane_step_count==9)
29997 // {if ((num_array[8+(lane_step_count<<2)+2]<ddr_lcdlr_test_offset)
29998 // ddr_lcdlr_test_temp_value=0;
29999 // }
30000 if (num_array[8+(lane_step_count<<2)+3]<9)
30001 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
30002 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30003 }
30004 }
30005 else
30006 {
30007 if (lane_step<8)
30008 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30009 else if(lane_step<10)
30010 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30011 }
30012 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
30013 temp_count=1;
30014 read_write_window_test_parameter(data_source,
30015 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30016 if (num_array[8+(lane_step<<2)+3]>4)
30017 {
30018 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30019 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30020 }
30021
30022 run_command("reset",0);
30023 while (1) ;
30024 }
30025
30026 }
30027 }
30028 else if((num_array[8+(lane_step<<2)+3]==3)||(num_array[8+(lane_step<<2)+3]==7)) //test right edge ongoing -loop
30029 {
30030
30031 if ((num_array[8+(lane_step<<2)+2]+1) >= (num_array[6]))
30032 {
30033 if (num_array[1] == DDR_TEST_NULL)
30034 {printf("default value not stable ,or recovery sticky?\n");
30035 }
30036
30037
30038 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30039 {
30040 //ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
30041 for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
30042 {
30043
30044 num_array[8+(lane_step_count<<2)+3]= num_array[8+(lane_step_count<<2)+3]+1; //update status
30045 lane_step_count=8+(lane_step_count<<2)+3;
30046 if (num_array[8+(lane_step_count<<2)+3]<9)
30047 read_write_window_test_parameter(data_source,
30048 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30049 }
30050
30051
30052 }
30053 else
30054 {
30055 num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
30056 temp_count=8+(lane_step<<2)+3;
30057 read_write_window_test_parameter(data_source,
30058 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30059 }
30060
30061 num_array[5]=0; //update edge lcdlr
30062 temp_count=5;
30063 read_write_window_test_parameter(data_source,
30064 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30065
30066 // if(num_array[1]==DDR_TEST_FAIL)
30067 // num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
30068 // if(num_array[1]==DDR_TEST_PASS)
30069 // num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
30070 // temp_count=8+(lane_step<<2)+2;
30071 // read_write_window_test_parameter(data_source,
30072 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30073
30074
30075 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30076 {
30077
30078 test_arg_0_orgt_store_lcdlr_value= num_array[0];
30079 if (num_array[1] == DDR_TEST_FAIL)
30080 {
30081 ddr_lcdlr_test_offset=test_arg_0_orgt_store_lcdlr_value-num_array[8+(lane_step<<2)+2]+1;
30082 }
30083 if (num_array[1] == DDR_TEST_PASS)
30084 {
30085 ddr_lcdlr_test_offset=test_arg_0_orgt_store_lcdlr_value-num_array[8+(lane_step<<2)+2]+0;
30086 }
30087 temp_count=8+(lane_step<<2)+2;
30088 read_write_window_test_parameter(data_source,
30089 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30090 for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
30091 {
30092 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
30093 if (num_array[8+(lane_step_count<<2)+2]<ddr_lcdlr_test_offset)
30094 ddr_lcdlr_test_temp_value=0;
30095 if (num_array[8+(lane_step_count<<2)+3]<9)
30096 read_write_window_test_parameter(data_source,
30097 (8+(lane_step_count<<2)+2) ,ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30098 }
30099
30100
30101 }
30102 else
30103 {
30104 if (num_array[1] == DDR_TEST_FAIL)
30105 num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
30106 if (num_array[1] == DDR_TEST_PASS)
30107 num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
30108 temp_count=8+(lane_step<<2)+2;
30109 read_write_window_test_parameter(data_source,
30110 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30111 }
30112
30113
30114 test_arg_6_lcdlr_temp_count=0; //current_test +B //(A+B)/2
30115 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
30116 temp_count=6;
30117 read_write_window_test_parameter(data_source,
30118 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30119 num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
30120 temp_count=1; //update test error flag
30121 read_write_window_test_parameter(data_source,
30122 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30123 if (num_array[8+(lane_step<<2)+3]>4)
30124 {
30125 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30126 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30127 }
30128
30129
30130 run_command("reset",0);
30131 while (1) ;
30132 }
30133 else
30134 {
30135 if (num_array[1] == DDR_TEST_NULL)
30136 {printf("default value not stable ,or recovery sticky?\n");
30137 }
30138 else if(num_array[1]==DDR_TEST_FAIL)
30139 {
30140
30141
30142
30143 {
30144 // num_array[8+(lane_step<<2)+3]=3; //update status
30145 temp_count=8+(lane_step<<2)+3;
30146 read_write_window_test_parameter(data_source,
30147 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30148
30149
30150 num_array[5]=num_array[6]; //update edge lcdlr
30151 temp_count=5;
30152 read_write_window_test_parameter(data_source,
30153 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30154
30155 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
30156 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
30157 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
30158 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
30159 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30160 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
30161 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
30162 num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
30163 temp_count=6;
30164 read_write_window_test_parameter(data_source,
30165 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30166
30167 // num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
30168 // temp_count=8+(lane_step<<2)+1;
30169 // read_write_window_test_parameter(data_source,
30170 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30171 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
30172 temp_count=1; //update test error flag
30173 read_write_window_test_parameter(data_source,
30174 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30175
30176 if (num_array[8+(lane_step<<2)+3]>4)
30177 {
30178 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30179 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30180 }
30181
30182
30183 ddr_test_watchdog_enable(test_watchdog_time_s); //s
30184 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
30185 ddr_test_watchdog_clear();
30186
30187 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30188 {
30189 ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
30190 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
30191 (num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30192 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
30193 {
30194 if (num_array[8+(lane_step_count<<2)+3]<9)
30195 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
30196 (num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30197 }
30198 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
30199 {
30200 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
30201 //if(lane_step_count==9)
30202 {if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
30203 ddr_lcdlr_test_temp_value=0;
30204 }
30205 if (num_array[8+(lane_step_count<<2)+3]<9)
30206 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
30207 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30208 }
30209 }
30210 else
30211 {
30212 if (lane_step<8)
30213 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
30214 else if(lane_step<10)
30215 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
30216 }
30217 //here will dead
30218 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
30219
30220 if (temp_test_error)
30221 {
30222 run_command("reset",0);
30223 while (1) ;
30224 }
30225 else
30226 {
30227 if ( num_array[8+(lane_step<<2)+3]>4)
30228 {
30229 ddr_test_watchdog_disable(); //s
30230 run_command("run storeboot",0);
30231 while (1) ;
30232 }
30233 else
30234 {
30235
30236 ddr_test_watchdog_clear();
30237 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
30238 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30239 {
30240 ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
30241 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
30242 {
30243 if (num_array[8+(lane_step_count<<2)+3]<9)
30244 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
30245 (num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30246 }
30247 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
30248 {
30249 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
30250 //if(lane_step_count==9)
30251 // {if ((num_array[8+(lane_step_count<<2)+0]<ddr_lcdlr_test_offset)
30252 // ddr_lcdlr_test_temp_value=0;
30253 // }
30254 if (num_array[8+(lane_step_count<<2)+3]<9)
30255 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
30256 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30257 }
30258 }
30259 else
30260 {
30261 if (lane_step<8)
30262 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30263 else if(lane_step<10)
30264 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30265 }
30266 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
30267 temp_count=1;
30268 read_write_window_test_parameter(data_source,
30269 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30270
30271 if (num_array[8+(lane_step<<2)+3]>4)
30272 {
30273 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30274 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30275 }
30276
30277 run_command("reset",0);
30278 while (1) ;
30279 }
30280
30281 }
30282 }
30283 }
30284
30285 else if(num_array[1]==DDR_TEST_PASS)
30286 {
30287 // num_array[8+(lane_step<<2)+3]=3; //update status
30288 temp_count=8+(lane_step<<2)+3;
30289 read_write_window_test_parameter(data_source,
30290 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30291
30292 num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
30293 temp_count=8+(lane_step<<2)+2;
30294 read_write_window_test_parameter(data_source,
30295 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30296
30297 if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
30298 test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
30299 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
30300 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
30301 else if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30302 test_arg_6_lcdlr_temp_count=((num_array[5])-1);
30303 // test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //current_test +B //(A+B)/2
30304 num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
30305 temp_count=6;
30306 read_write_window_test_parameter(data_source,
30307 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30308
30309 num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
30310 temp_count=1; //update test error flag
30311 read_write_window_test_parameter(data_source,
30312 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30313 if (num_array[8+(lane_step<<2)+3]>4)
30314 {
30315 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30316 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30317 }
30318
30319
30320 ddr_test_watchdog_enable(test_watchdog_time_s); //s
30321 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
30322 ddr_test_watchdog_clear();
30323 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30324 {
30325 ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
30326 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
30327 (num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30328 for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
30329 {
30330 if (num_array[8+(lane_step_count<<2)+3]<9)
30331 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
30332 (num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30333 }
30334 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
30335 {
30336 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
30337 //if(lane_step_count==9)
30338 {if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
30339 ddr_lcdlr_test_temp_value=0;
30340 }
30341 if (num_array[8+(lane_step_count<<2)+3]<9)
30342 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
30343 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30344 }
30345 }
30346 else
30347 {
30348 if (lane_step<8)
30349 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
30350 else if(lane_step<10)
30351 test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
30352 }
30353 //here will dead
30354 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
30355
30356 if (temp_test_error)
30357 {
30358 run_command("reset",0);
30359 while (1) ;
30360 }
30361 else
30362 {
30363 if ( num_array[8+(lane_step<<2)+3]>4)
30364 {
30365 ddr_test_watchdog_disable(); //s
30366 run_command("run storeboot",0);
30367 while (1) ;
30368 }
30369 else
30370 {
30371 ddr_test_watchdog_clear();
30372 org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
30373 if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
30374 {
30375 ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
30376 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
30377 {
30378 if (num_array[8+(lane_step_count<<2)+3]<9)
30379 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
30380 (num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
30381 }
30382 for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
30383 {
30384 ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
30385 //if(lane_step_count==9)
30386 // {if ((num_array[8+(lane_step_count<<2)+0]<ddr_lcdlr_test_offset)
30387 // ddr_lcdlr_test_temp_value=0;
30388 // }
30389 if (num_array[8+(lane_step_count<<2)+3]<9)
30390 do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
30391 ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
30392 }
30393 }
30394 else
30395 {
30396 if (lane_step<8)
30397 org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30398 else if(lane_step<10)
30399 org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
30400 }
30401 num_array[1]=DDR_TEST_PASS; //pass 2 error 1
30402 temp_count=1;
30403 read_write_window_test_parameter(data_source,
30404 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30405 if (num_array[8+(lane_step<<2)+3]>4)
30406 {
30407 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30408 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30409 }
30410
30411 run_command("reset",0);
30412 while (1) ;
30413 }
30414
30415 }
30416
30417 }
30418 }
30419
30420
30421 }
30422 }
30423 }
30424 if (lane_step >= 10) //finish
30425 {
30426 ddr_test_watchdog_disable(); //s
30427 printf("close watchdog\n");
30428 }
30429
30430 // unsigned int acmdlr= 0;
30431 unsigned int delay_step_x100= 0;
30432
30433 {
30434 //acmdlr=do_ddr_read_acmdlr();
30435 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
30436 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
30437 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
30438
30439 for ((lane_step=0);(lane_step<4);(lane_step++))
30440 {
30441 printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
30442 lane_step,
30443 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
30444 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
30445 }
30446 lane_step=4;
30447 {
30448 printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
30449 4,
30450 num_array[8+(lane_step)*8+0],num_array[8+(lane_step)*8+1],num_array[8+(lane_step)*8+2],
30451 num_array[8+(lane_step)*8+4],num_array[8+(lane_step)*8+5],num_array[8+(lane_step)*8+6]);
30452 }
30453 printf("\n\n-----------------------------------------------------------------------------\n\n");
30454 {
30455 printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
30456 clk_setup ps| clk_hold ps|adj_percent[100]\n");
30457
30458 printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
30459 4,
30460 num_array[8+(lane_step)*8+0],
30461 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
30462 )/100),
30463 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
30464 )/100),
30465
30466 0,
30467 0,
30468 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
30469 2*num_array[8+(lane_step)*8+0]));
30470 printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
30471 4,
30472 num_array[8+(lane_step)*8+4],
30473 0,
30474 0,
30475 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
30476 )/100),
30477 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
30478 )/100),
30479
30480 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
30481 2*num_array[8+(lane_step)*8+4]));
30482 }
30483 printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
30484 rd_setup ps|rd_hold x ps|adj_percent[100]\n");
30485
30486
30487 for ((lane_step=0);(lane_step<4);(lane_step++))
30488 {
30489 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
30490 lane_step,
30491 num_array[8+(lane_step)*8+0],
30492 (((num_array[8+(lane_step)*8+2]-num_array[8+(lane_step)*8+0])*delay_step_x100
30493 )/100),
30494 (((num_array[8+(lane_step)*8+0]-num_array[8+(lane_step)*8+1])*delay_step_x100
30495 )/100),
30496
30497 0,
30498 0,
30499 100*(num_array[8+(lane_step)*8+2]+num_array[8+(lane_step)*8+1])/(
30500 2*num_array[8+(lane_step)*8+0]));
30501
30502 printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
30503 lane_step,
30504 num_array[8+(lane_step)*8+4],
30505 0,
30506 0,
30507
30508 (((num_array[8+(lane_step)*8+4]-num_array[8+(lane_step)*8+5])*delay_step_x100
30509 )/100),
30510 (((num_array[8+(lane_step)*8+6]-num_array[8+(lane_step)*8+4])*delay_step_x100
30511 )/100),
30512 100*(num_array[8+(lane_step)*8+6]+num_array[8+(lane_step)*8+5])/(
30513 2*num_array[8+(lane_step)*8+4]));
30514
30515
30516
30517 }
30518 }
30519
30520
30521 if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
30522 {
30523 test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
30524 num_array[2]=test_arg_2_step;
30525 temp_count=2;
30526 read_write_window_test_parameter(data_source,
30527 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30528 run_command("reset",0);
30529 while (1) ;
30530
30531 }
30532
30533 if (test_arg_2_step == DDR_TEST_STATUS_KERNEL_ONGING)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
30534 {
30535 test_arg_2_step=DDR_TEST_STATUS_KERNEL_FINISH;
30536 num_array[2]=test_arg_2_step;
30537 temp_count=2;
30538 read_write_window_test_parameter(data_source,
30539 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30540
30541 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30542 DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
30543 num_array[1]=DDR_TEST_NULL;
30544 read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
30545 DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
30546 {
30547 ddr_test_watchdog_disable(); //s
30548 run_command("run storeboot",0);
30549 while (1) ;
30550 }
30551 }
30552
30553
30554
30555
30556
30557
30558 // if( num_array[8+(lane_step<<2)+3]>4)
30559
30560
30561
30562 return 1;
30563}
30564
30565int do_ddr_uboot_window_use_source_all_same_increase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
30566{
30567 printf("\nsetenv bootcmd ddr_test_cmd 0x35 4 6 60 0 0x100000 0x4000000 0 0x100010 0\n");
30568 printf("\nEnter do_ddr_uboot_window_use_source function\n");
30569 printf("\n--- watchdog should >15s\n");
30570
30571#define DDR_TEST_NULL 0
30572#define DDR_TEST_PASS 1
30573#define DDR_TEST_FAIL 2
30574
30575
30576#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
30577#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
30578 //PREG_STICKY_REG4
30579 //PREG_STICKY_REG5
30580
30581#define DDR_TEST_STATUS_UBOOT_ONGOING 1
30582#define DDR_TEST_STATUS_UBOOT_FINISH 2
30583#define DDR_TEST_STATUS_KERNEL_ONGING 3
30584#define DDR_TEST_STATUS_KERNEL_FINISH 4
30585 //#define DDR_TEST_FAIL 2
30586
30587
30588 char *endp;
30589 unsigned int lane_disable= 0;
30590 unsigned int data_source= 0;
30591 unsigned int ddr_data_test_size=0x1000000;
30592 unsigned int ddr_add_test_size=0x10000000;
30593 unsigned int ddr_test_size=0x10000000;
30594
30595 unsigned int ddr_test_clear_flag=0;
30596 unsigned int ddr_test_init_offset=0;
30597 unsigned int ddr_test_uboot_kernel_enable_mask=0;
30598
30599 unsigned int ddr_test_uboot_loop=0;
30600
30601 unsigned int kernel_test_watchdog_time_s=60;
30602 unsigned int test_watchdog_time_s=15;
30603
30604
30605 error_outof_count_flag =1; //for quick out of error
30606 if (argc >1) {
30607 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
30608 if (*argv[1] == 0 || *endp != 0)
30609 {
30610 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
30611 }
30612 }
30613 if (argc >2) {
30614 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
30615 if (*argv[2] == 0 || *endp != 0)
30616 {
30617 watchdog_time_s= 15;
30618 }
30619 }
30620 printf("watchdog_time_s==%d\n",watchdog_time_s);
30621 test_watchdog_time_s=watchdog_time_s;
30622 //test_watchdog_time_s=address_test_watchdog_time_s;
30623 if (argc >3) {
30624 kernel_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
30625 if (*argv[3] == 0 || *endp != 0)
30626 {
30627 kernel_test_watchdog_time_s= watchdog_time_s;
30628 }
30629 }
30630 printf("kernel_test_watchdog_time_s==%d\n",kernel_test_watchdog_time_s);
30631 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
30632 if (argc >4) {
30633 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
30634 if (*argv[4] == 0 || *endp != 0)
30635 {
30636 lane_disable= 0;
30637 }
30638 }
30639 printf("lane_disable==0x%08x\n",lane_disable);
30640
30641 if (argc >5) {
30642 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
30643 if (*argv[5] == 0 || *endp != 0)
30644 {
30645 ddr_data_test_size= 0x100000;
30646 }
30647 }
30648 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
30649 if (argc >6) {
30650 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
30651 if (*argv[6] == 0 || *endp != 0)
30652 {
30653 ddr_add_test_size= 0x10000000;
30654 }
30655 }
30656 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
30657
30658 if (argc >7) {
30659 ddr_test_clear_flag = simple_strtoull_ddr(argv[7], &endp, 0);
30660 if (*argv[7] == 0 || *endp != 0)
30661 {
30662 ddr_test_clear_flag= 0x10000000;
30663 }
30664 }
30665 printf("ddr_test_clear_flag==0x%08x\n",ddr_test_clear_flag);
30666
30667 if (argc >8) {
30668 ddr_test_init_offset = simple_strtoull_ddr(argv[8], &endp, 0);
30669 if (*argv[8] == 0 || *endp != 0)
30670 {
30671 ddr_test_init_offset= 0;
30672 }
30673 }
30674 printf("ddr_test_init_offset==0x%08x\n",ddr_test_init_offset);
30675
30676 if (argc >9) {
30677 ddr_test_uboot_kernel_enable_mask = simple_strtoull_ddr(argv[9], &endp, 0);
30678 if (*argv[9] == 0 || *endp != 0)
30679 {
30680 ddr_test_uboot_kernel_enable_mask= 0;
30681 }
30682 }
30683 printf("ddr_test_uboot_kernel_enable_mask==0x%08x\n",ddr_test_uboot_kernel_enable_mask);
30684
30685 if (argc >10) {
30686 ddr_test_uboot_loop = simple_strtoull_ddr(argv[10], &endp, 0);
30687 if (*argv[10] == 0 || *endp != 0)
30688 {
30689 ddr_test_uboot_loop= 0;
30690 }
30691 }
30692 printf("ddr_test_uboot_loop==0x%08x\n",ddr_test_uboot_loop);
30693
30694 unsigned int rank_index=0;
30695 unsigned int temp_count=0;
30696 unsigned int ddr_test_data_array_max=10;
30697 unsigned int num_array[10];//8 flag 32_data add_8 32_data add_8
30698
30699 unsigned int temp_test_error=0;
30700 //unsigned int lcdlr_min=0;
30701 //unsigned int lcdlr_max=0;
30702 memset(num_array, 0, sizeof(num_array));
30703 //char str[1024]="";
30704
30705
30706 ddr_test_data_array_max=10;
30707
30708 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
30709 {
30710 num_array[temp_count]= read_write_window_test_parameter(data_source,
30711 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
30712 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
30713 }
30714
30715 unsigned int reg_def_value_data[4]; //write_lcdlr_value+read_lcdlr_value<<16;
30716
30717 //#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
30718 //#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
30719
30720 unsigned int test_arg_4_step_flag_add_sticky_offset =0; //use for kernel
30721 unsigned int test_arg_5_pass_fail_flag_add_sticky_offset =0; //use for kernel
30722
30723 unsigned int test_arg_6_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
30724 unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
30725 unsigned int test_arg_7_lcdlr_offset_l =0; //left_lcdlr
30726 unsigned int test_arg_7_lcdlr_offset_r=0; //right_lcdlr
30727 unsigned int delay_step_x100= 0;
30728
30729 //unsigned int test_arg_6_lcdlr_temp_count =0;
30730 unsigned int test_lcdlr_temp_value1 =0;
30731 unsigned int test_lcdlr_temp_value2 =0;
30732 unsigned int test_lcdlr_temp_value =0;
30733 unsigned int test_lcdlr_reach_lcdlr_limited_flag =0;
30734
30735 unsigned int acmdlr=0;
30736 acmdlr=do_ddr_read_acmdlr();
30737
30738 test_lcdlr_reach_lcdlr_limited_flag=0;
30739 reg_def_value_data[0]=num_array[0];
30740 reg_def_value_data[1]=num_array[1];
30741 reg_def_value_data[2]=num_array[2];
30742 reg_def_value_data[3]=num_array[3];
30743 test_arg_4_step_flag_add_sticky_offset=num_array[4];
30744 test_arg_5_pass_fail_flag_add_sticky_offset=num_array[5];
30745 test_arg_6_step_status=num_array[6];
30746 test_arg_7_lcdlr_offset=num_array[7];
30747
30748
30749
30750 printf("reg_def_value_data[0]==0x%08x\n",num_array[0]);
30751 printf("reg_def_value_data[1]==0x%08x\n",num_array[1]);
30752 printf("reg_def_value_data[2]==0x%08x\n",num_array[2]);
30753 printf("reg_def_value_data[3]==0x%08x\n",num_array[3]);
30754 printf("test_arg_4_step_flag_add_sticky_offset=%d\n",num_array[4]);
30755 printf("test_arg_5_pass_fail_flag_add_sticky_offset=%d\n",num_array[5]);
30756 printf("test_arg_6_step_status=%d\n",num_array[6]);
30757 printf("\ntest_arg_7_lcdlr_offset=0x%08x\n",num_array[7]);
30758
30759
30760
30761
30762 //for (temp_count= 0;temp_count < 8; temp_count++)
30763 // {
30764 // read_write_window_test_parameter(data_source,
30765 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30766 //}
30767
30768
30769 if (ddr_test_clear_flag)
30770 { test_arg_6_step_status=0;
30771 num_array[6] = test_arg_6_step_status ;
30772 temp_count=6;
30773 read_write_window_test_parameter(data_source,
30774 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30775 printf("\n clear sticky register should reset,then over write ....\n");
30776 run_command("reset",0);
30777 while (1) ;
30778 }
30779
30780 if (test_arg_6_step_status == 0)
30781 {
30782 {
30783
30784 //test_arg_6_step_status=1;
30785
30786
30787 for (temp_count = 0; temp_count < (8); temp_count++) //data
30788 {
30789 test_lcdlr_temp_value1=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,temp_count,test_lcdlr_temp_value1,DDR_PARAMETER_READ);
30790 temp_count=temp_count+1;
30791 test_lcdlr_temp_value2=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,(temp_count),test_lcdlr_temp_value2,DDR_PARAMETER_READ);
30792 reg_def_value_data[temp_count/2]=test_lcdlr_temp_value1|(test_lcdlr_temp_value2<<16);
30793 printf("num_array[%d]=%08x\n",temp_count/2,num_array[temp_count/2]);
30794 }
30795
30796 }
30797 test_arg_4_step_flag_add_sticky_offset=0;
30798 test_arg_5_pass_fail_flag_add_sticky_offset=0;
30799 test_arg_6_step_status=0;
30800 test_arg_7_lcdlr_offset=0;
30801 if (ddr_test_init_offset)
30802 {test_arg_7_lcdlr_offset=ddr_test_init_offset;
30803 }
30804 num_array[0] = reg_def_value_data[0] ;
30805 num_array[1] = reg_def_value_data[1] ;
30806 num_array[2] = reg_def_value_data[2] ;
30807 num_array[3] = reg_def_value_data[3] ;
30808 num_array[4] = test_arg_4_step_flag_add_sticky_offset ; //use for kernel
30809 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;//use for kernel
30810 num_array[6] = test_arg_6_step_status ;
30811 num_array[7] = test_arg_7_lcdlr_offset ;
30812
30813
30814
30815 for (temp_count= 0;temp_count < 8; temp_count++)
30816 {
30817 read_write_window_test_parameter(data_source,
30818 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30819 }
30820
30821
30822 }
30823 else
30824 {
30825 for (temp_count = 0; temp_count < (8); temp_count++) //data
30826 {
30827 test_lcdlr_temp_value1=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,temp_count,test_lcdlr_temp_value1,DDR_PARAMETER_READ);
30828 temp_count=temp_count+1;
30829 test_lcdlr_temp_value2=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,(temp_count),test_lcdlr_temp_value2,DDR_PARAMETER_READ);
30830 reg_def_value_data[temp_count/2]=test_lcdlr_temp_value1|(test_lcdlr_temp_value2<<16);
30831 num_array[temp_count/2]=reg_def_value_data[temp_count/2];
30832 printf("re-num_array[%d]=%08x\n",temp_count/2,num_array[temp_count/2]);
30833 }
30834 }
30835
30836 if (ddr_test_uboot_kernel_enable_mask&1)
30837 {printf("skip uboot test should init kernel offset value==0x%08x\n",num_array[7]);
30838 }
30839
30840 test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
30841 test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
30842 unsigned int lane_step_count=0;
30843 {
30844
30845 {
30846 test_watchdog_time_s=watchdog_time_s;
30847 ddr_test_size=ddr_data_test_size;
30848
30849 }
30850
30851 printf("reg_def_value_data[0]==0x%08x\n",num_array[0]);
30852 printf("reg_def_value_data[1]==0x%08x\n",num_array[1]);
30853 printf("reg_def_value_data[2]==0x%08x\n",num_array[2]);
30854 printf("reg_def_value_data[3]==0x%08x\n",num_array[3]);
30855 printf("test_arg_4_step_flag_add_sticky_offset=%d\n",num_array[4]);
30856 printf("test_arg_5_pass_fail_flag_add_sticky_offset=%d\n",num_array[5]);
30857 printf("test_arg_6_step_status=%d\n",num_array[6]);
30858 printf("test_arg_7_lcdlr_offset=%d\n",num_array[7]);
30859
30860 if (test_arg_6_step_status == 4) //uboot finish
30861 {
30862 ddr_test_watchdog_disable(); //s
30863 printf("close watchdog\n");
30864
30865 // unsigned int acmdlr= 0;
30866
30867
30868 {
30869 //acmdlr=do_ddr_read_acmdlr();
30870 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
30871 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
30872 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
30873
30874
30875 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ,test_arg_7_lcdlr_offset_r=%4d ",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l,test_arg_7_lcdlr_offset_r);
30876 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ps,test_arg_7_lcdlr_offset_r=%4d ps",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l*delay_step_x100/100,test_arg_7_lcdlr_offset_r*delay_step_x100/100);
30877
30878 printf("\n\n-----------------------------------------------------------------------------\n\n");
30879
30880
30881 }
30882 if (ddr_test_uboot_kernel_enable_mask&2)
30883 {
30884 if (ddr_test_uboot_loop)
30885 {
30886 { test_arg_6_step_status=0;
30887 num_array[6] = test_arg_6_step_status ;
30888 temp_count=6;
30889 read_write_window_test_parameter(data_source,
30890 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30891 printf("\n clear sticky register should reset,then over write ....\n");
30892 run_command("reset",0);
30893 while (1) ;
30894 }
30895 run_command("reset",0);
30896 while (1) ;
30897 }
30898 else
30899 return 1;
30900 }
30901 }
30902
30903
30904
30905 //if((test_arg_6_step_status==0)) //0 test left edge begin 1 test left edge ongoing 2//left_finish 3 right edge ongoing 4 right finish //5 kernel left edge ongoing 6 kernel left finish 7 kernel right ongoing
30906 // uboot find from pass to fail offset 0->max
30907 //kernel find from fail to pass offset from max ->0
30908 if ((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
30909 {
30910 if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
30911 ||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
30912 )
30913 {
30914 test_arg_6_step_status=test_arg_6_step_status+1;
30915 num_array[6] = test_arg_6_step_status ;
30916 temp_count=6;
30917 read_write_window_test_parameter(data_source,
30918 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30919 }
30920
30921 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
30922 {
30923 if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
30924 {
30925 // test_arg_6_step_status=test_arg_6_step_status+1;
30926
30927 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
30928 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
30929 temp_count=5;
30930 read_write_window_test_parameter(data_source,
30931 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30932
30933 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
30934 {
30935
30936 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
30937 {
30938 if ((lane_step_count%2) == 0)
30939 {
30940
30941 if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
30942 {
30943 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
30944 }
30945 }
30946 if ((lane_step_count%2) == 1)
30947 {
30948 if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
30949 {
30950 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
30951 }
30952 }
30953
30954 }
30955
30956
30957
30958
30959 }
30960 if (test_lcdlr_reach_lcdlr_limited_flag)
30961 {
30962 test_arg_6_step_status=test_arg_6_step_status+1;
30963 num_array[6] = test_arg_6_step_status ;
30964 temp_count=6;
30965 read_write_window_test_parameter(data_source,
30966 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30967 run_command("reset",0);
30968 while (1) ;
30969 }
30970 }
30971
30972 else if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL) //pass 1 error 2
30973 {
30974
30975 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
30976 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
30977 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
30978 {
30979 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
30980 }
30981 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
30982 {
30983 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
30984 }
30985 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
30986 num_array[7] = test_arg_7_lcdlr_offset ;
30987 temp_count=7;
30988 read_write_window_test_parameter(data_source,
30989 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30990
30991
30992
30993 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
30994 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
30995 temp_count=5;
30996 read_write_window_test_parameter(data_source,
30997 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
30998
30999 test_arg_6_step_status=test_arg_6_step_status+1;
31000 num_array[6] = test_arg_6_step_status ;
31001 temp_count=6;
31002 read_write_window_test_parameter(data_source,
31003 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31004 run_command("reset",0);
31005 while (1) ;
31006 }
31007 }
31008
31009
31010
31011 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
31012 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
31013 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
31014 {
31015 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l+1;
31016 }
31017 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
31018 {
31019 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
31020 }
31021 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
31022 num_array[7] = test_arg_7_lcdlr_offset ;
31023 temp_count=7;
31024 read_write_window_test_parameter(data_source,
31025 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31026
31027 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
31028 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31029 temp_count=5;
31030 read_write_window_test_parameter(data_source,
31031 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31032
31033 ddr_test_watchdog_enable(test_watchdog_time_s); //s
31034 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
31035 ddr_test_watchdog_clear();
31036
31037
31038 {
31039
31040 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
31041 {
31042 printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
31043 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
31044 {
31045 if ((lane_step_count%2) == 0)
31046 {
31047 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
31048 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
31049 {test_lcdlr_temp_value=0;
31050 }
31051 }
31052 if ((lane_step_count%2) == 1)
31053 {
31054 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
31055 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
31056 {test_lcdlr_temp_value=0;
31057 }
31058 }
31059 }
31060
31061 if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
31062 {
31063 if ((lane_step_count%2) == 0)
31064 {
31065 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
31066 }
31067 if ((lane_step_count%2) == 1)
31068 {
31069 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
31070
31071 }
31072 }
31073
31074
31075
31076 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
31077 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
31078 }
31079
31080
31081
31082
31083 }
31084
31085 //here will dead
31086 if (test_arg_6_step_status>4)
31087 {
31088 //ddr_test_watchdog_disable(); //s
31089 ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
31090 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
31091 // num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31092 // temp_count=5;
31093 // read_write_window_test_parameter(data_source,
31094 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31095 run_command("run storeboot",0);
31096 while (1) ;
31097 } else
31098 {
31099 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
31100 }
31101
31102 if (temp_test_error)
31103 {
31104 run_command("reset",0);
31105 while (1) ;
31106 }
31107 else
31108 {
31109 ddr_test_watchdog_clear();
31110
31111
31112
31113 {
31114 //write org value
31115 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
31116 {
31117 if ((lane_step_count%2) == 0)
31118 {
31119 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
31120 }
31121 if ((lane_step_count%2) == 1)
31122 {
31123 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
31124 }
31125 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
31126 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
31127 }
31128
31129
31130
31131
31132 }
31133
31134 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
31135 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31136 temp_count=5;
31137 read_write_window_test_parameter(data_source,
31138 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31139 run_command("reset",0);
31140 while (1) ;
31141
31142
31143
31144
31145
31146 }
31147 }
31148
31149
31150 if ((test_arg_6_step_status == 4) || (test_arg_6_step_status == 6))
31151 {
31152 test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_UBOOT_FINISH;
31153 num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
31154 temp_count=4;
31155 read_write_window_test_parameter(data_source,
31156 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31157
31158 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;//DDR_TEST_NULL;
31159 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31160 temp_count=5;
31161 read_write_window_test_parameter(data_source,
31162 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31163
31164 }
31165 if ((test_arg_6_step_status >= 4)) ////kernel find from fail to pass offset from max ->0
31166 {
31167 if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
31168 ||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
31169 )
31170 {
31171 test_arg_6_step_status=test_arg_6_step_status+1;
31172 num_array[6] = test_arg_6_step_status ;
31173 temp_count=6;
31174 read_write_window_test_parameter(data_source,
31175 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31176 }
31177
31178 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
31179 {
31180 if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
31181 {
31182 // test_arg_6_step_status=test_arg_6_step_status+1;
31183
31184 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
31185 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31186 temp_count=5;
31187 read_write_window_test_parameter(data_source,
31188 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31189
31190 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
31191 {
31192
31193 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
31194 {
31195 if ((lane_step_count%2) == 0)
31196 {
31197
31198 if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
31199 {
31200 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
31201 }
31202 }
31203 if ((lane_step_count%2) == 1)
31204 {
31205 if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
31206 {
31207 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
31208 }
31209 }
31210
31211 }
31212
31213
31214
31215
31216 }
31217 // if(test_lcdlr_reach_lcdlr_limited_flag)
31218 {
31219 test_arg_6_step_status=test_arg_6_step_status+1;
31220 num_array[6] = test_arg_6_step_status ;
31221 temp_count=6;
31222 read_write_window_test_parameter(data_source,
31223 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31224 run_command("reset",0);
31225 while (1) ;
31226 }
31227 }
31228
31229 else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
31230 //||(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL))//pass 2 error 1
31231 )
31232 {
31233
31234 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
31235 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
31236 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
31237 {
31238 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
31239 }
31240 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
31241 {
31242 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
31243 }
31244 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
31245 num_array[7] = test_arg_7_lcdlr_offset ;
31246 temp_count=7;
31247 read_write_window_test_parameter(data_source,
31248 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31249
31250
31251
31252 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
31253 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;
31254 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31255 temp_count=5;
31256 read_write_window_test_parameter(data_source,
31257 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31258
31259
31260 }
31261 else if (test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL)//pass 2 error 1
31262 {printf("\nfind drop power,test_arg_5_pass_fail_flag_add_sticky_offset=%d \n",test_arg_5_pass_fail_flag_add_sticky_offset);
31263 }
31264
31265 ddr_test_watchdog_enable(test_watchdog_time_s); //s
31266 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
31267 ddr_test_watchdog_clear();
31268
31269 {
31270
31271 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
31272 {
31273 printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
31274 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
31275 {
31276 if ((lane_step_count%2) == 0)
31277 {
31278 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
31279 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
31280 {test_lcdlr_temp_value=0;
31281 }
31282 }
31283 if ((lane_step_count%2) == 1)
31284 {
31285 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
31286 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
31287 {test_lcdlr_temp_value=0;
31288 }
31289 }
31290 }
31291
31292 if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
31293 {
31294 if ((lane_step_count%2) == 0)
31295 {
31296 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
31297 }
31298 if ((lane_step_count%2) == 1)
31299 {
31300 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
31301
31302 }
31303 }
31304
31305
31306
31307 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
31308 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
31309 }
31310
31311
31312
31313
31314 }
31315
31316 //here will dead
31317 if (test_arg_6_step_status>4)
31318 {
31319 //ddr_test_watchdog_disable(); //s
31320 ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
31321 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
31322 // num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31323 // temp_count=5;
31324 // read_write_window_test_parameter(data_source,
31325 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31326 run_command("run storeboot",0);
31327 while (1) ;
31328 } else
31329 {
31330 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
31331 }
31332
31333 if (temp_test_error)
31334 {
31335 run_command("reset",0);
31336 while (1) ;
31337 }
31338 else
31339 {
31340 ddr_test_watchdog_clear();
31341 {
31342 //write org value
31343 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
31344 {
31345 if ((lane_step_count%2) == 0)
31346 {
31347 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
31348 }
31349 if ((lane_step_count%2) == 1)
31350 {
31351 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
31352 }
31353 do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
31354 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
31355 }
31356
31357 }
31358
31359 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
31360 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
31361 temp_count=5;
31362 read_write_window_test_parameter(data_source,
31363 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31364 run_command("reset",0);
31365 while (1) ;
31366
31367 }
31368 }
31369 }
31370 }
31371
31372 if (test_arg_6_step_status >= 8) //finish
31373 {
31374 ddr_test_watchdog_disable(); //s
31375 printf("close watchdog\n");
31376
31377
31378
31379 {
31380 //acmdlr=do_ddr_read_acmdlr();
31381 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
31382 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
31383 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
31384
31385
31386 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ,test_arg_7_lcdlr_offset_r=%4d ",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l,test_arg_7_lcdlr_offset_r);
31387 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ps,test_arg_7_lcdlr_offset_r=%4d ps",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l*delay_step_x100/100,test_arg_7_lcdlr_offset_r*delay_step_x100/100);
31388 printf("\n\n-----------------------------------------------------------------------------\n\n");
31389
31390 test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_KERNEL_FINISH;
31391 num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
31392 temp_count=4;
31393 read_write_window_test_parameter(data_source,
31394 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31395 }
31396 }
31397
31398 test_arg_6_step_status=0xffff;
31399 {
31400 // test_arg_6_step_status=test_arg_6_step_status+1;
31401 num_array[6] = test_arg_6_step_status ;
31402 temp_count=6;
31403 read_write_window_test_parameter(data_source,
31404 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
31405 }
31406 ddr_test_watchdog_disable(); //s
31407 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
31408 run_command("run storeboot",0);
31409 while (1) ;
31410 return 1;
31411}
31412
31413
31414int do_ddr4_test_dram_clk_use_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
31415{
31416 ///*
31417 int i=0;
31418 printf("\nargc== 0x%08x\n", argc);
31419 for (i = 0;i<argc;i++)
31420 printf("\nargv[%d]=%s\n",i,argv[i]);
31421 char *endp;
31422
31423#define TEST_DRAM_CLK_USE_ENV 1
31424 printf("\ntune ddr CLK use uboot sticky register\n");
31425
31426#define DDR_CROSS_TALK_TEST_SIZE 0x20000
31427#define DDR_TEST_MIN_FREQ_LIMITED 50
31428#define DDR_TEST_MIN_FREQ 300
31429 // #define DDR_TEST_MAX_FREQ 3000
31430
31431 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
31432 unsigned int start_freq=DDR_TEST_MIN_FREQ;
31433 unsigned int end_freq=DDR_TEST_MAX_FREQ;
31434 unsigned int test_loops=1;
31435 if (argc == 1)
31436 {
31437 printf("\nplease read help\n");
31438 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
31439 start_freq=DDR_TEST_MIN_FREQ;
31440 end_freq=DDR_TEST_MAX_FREQ;
31441
31442 }
31443
31444 if (argc == 2)
31445 {
31446 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
31447 start_freq=DDR_TEST_MIN_FREQ;
31448 end_freq=DDR_TEST_MAX_FREQ;
31449 }
31450 if (argc== 3)
31451 {
31452 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
31453 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
31454 end_freq=DDR_TEST_MAX_FREQ;
31455
31456 }
31457 if (argc== 4)
31458 {
31459 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
31460 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
31461 end_freq=simple_strtoull_ddr(argv[3], &endp, 0);
31462
31463 }
31464 if (argc> 4)
31465 {
31466 ddr_test_size = simple_strtoull_ddr(argv[1], &endp, 0);
31467 start_freq= simple_strtoull_ddr(argv[2], &endp, 0);
31468 end_freq=simple_strtoull_ddr(argv[3], &endp, 0);
31469 test_loops=simple_strtoull_ddr(argv[4], &endp, 0);
31470 }
31471 unsigned int temp_test_error=0x0;
31472 unsigned int ddr_pll=0;
31473 unsigned int ddr_clk_org=0;
31474 unsigned int ddr_clk_hope_test=0;
31475 ddr_pll = rd_reg(AM_DDR_PLL_CNTL);
31476 //ddr_pll=ddr_pll_org;
31477 unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
31478 ddr_clk_org=ddr_clk;
31479 printf("\nddr_clk== %dMHz\n", ddr_clk);
31480 printf("\nstart_freq== %dMHz\n", start_freq);
31481 printf("\nend_freq== %dMHz\n", end_freq);
31482 ddr_pll = ddr_clk_convert_to_pll(ddr_clk);
31483 // {
31484 // wr_reg(AM_DDR_PLL_CNTL, (((rd_reg(AM_DDR_PLL_CNTL))&(~(0xfffff)))|(ddr_pll)));
31485 // ddr_udelay(2000);
31486 //}
31487
31488
31489 unsigned int freq_table_test_value[(DDR_TEST_MAX_FREQ)/24]; // step =0 init ,1 test fail, ,2 test pass,3 test skip;
31490 // char char_freq_name_table[30];
31491 // const char *p_char_freq_table;
31492
31493 // const char *p_char_ddr_test_step;
31494 // const char * p_char_freq_org;
31495 char char_freq_org[30];
31496 int ddr_feq_test_step=0; // step =0 init ,1 going ,2 done;
31497
31498 // const char * p_char_freq_name_table;
31499 char char_freq_name_table[30];
31500 char char_cmd_table[100];
31501 //char * p_char_store_boot;
31502 // char char_freq_store_boot[200];
31503
31504 //const char *p_freq_table_int;
31505 //char char_ddr_feq_test_step[]="ddr_feq_test_step";
31506 // const char *varname;
31507 // const char *varvalue;
31508 unsigned int temp_count=0;
31509 unsigned int temp_count_sub=0;
31510
31511
31512
31513 unsigned int str_to_numarry[64];
31514 unsigned int *num_arry;
31515
31516 num_arry = (unsigned int *)(&str_to_numarry);
31517 //int i;
31518
31519 unsigned int lcdlr_temp_count=0;
31520 {
31521 {
31522
31523 sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
31524
31525 for (i = 0; i < 63; i++) {
31526 dmc_sticky[i]=rd_reg(sticky_reg_base_add+(i<<2));
31527 //printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
31528 }
31529
31530 for (i = 0; i < 63; i++) {
31531 num_arry[i]=dmc_sticky[i];
31532 printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
31533 }
31534
31535 }
31536 }
31537
31538#define DDR_FEQ_TEST_STEP_OFFSET 8
31539 //#define DDR_FEQ_TEST_STEP_OFFSET 8
31540 unsigned int test_arg_0_cmd0 =0; //master cmd
31541 unsigned int test_arg_1_cmd1 =0; //min cmd
31542 unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
31543 unsigned int test_arg_3_freq =0;
31544 unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
31545 // unsigned int lane_step= 0;
31546 //char str[24];
31547 unsigned int boot_times=0;
31548
31549 test_arg_0_cmd0=num_arry[0];
31550 test_arg_1_cmd1=num_arry[1];
31551 test_arg_2_step=num_arry[2];
31552 test_arg_3_freq=num_arry[3];
31553 test_arg_4_step_status=num_arry[4];
31554 boot_times=num_arry[5];
31555 lcdlr_temp_count=num_arry[6];
31556 printf("test_arg_0_cmd0==%d\n",test_arg_0_cmd0);
31557 printf("test_arg_0_cmd1==%d\n",test_arg_1_cmd1);
31558 printf("test_arg_2_step==%d\n",test_arg_2_step);
31559 printf("test_arg_3_freq==%d\n",test_arg_3_freq);
31560 printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
31561 printf("test_arg_5 boottimes=%d\n",num_arry[5]);
31562 printf("test_arg_6 lcdlr_temp_count=%d\n",num_arry[6]);
31563 printf("test_arg_7=%d\n",num_arry[7]);
31564
31565 if ((num_arry[7] == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
31566 {boot_times++;
31567
31568 }
31569 else
31570 {boot_times=0;
31571 printf("test_sticky is not magic number,boot times==%d\n",boot_times);
31572 // writel(DMC_STICKY_MAGIC_0,(sticky_reg_base_add+(6<<2)));
31573 writel(DMC_STICKY_MAGIC_1,(sticky_reg_base_add+(7<<2)));
31574 test_arg_2_step=0;
31575 num_arry[6]=0;
31576 lcdlr_temp_count=0;
31577 //return 1;
31578 }
31579 num_arry[5]=boot_times;
31580
31581 writel(num_arry[5],(sticky_reg_base_add+(5<<2)));
31582
31583
31584
31585 if (test_arg_2_step == 0)
31586 {
31587
31588 test_arg_0_cmd0=0x28;
31589 test_arg_1_cmd1=0;
31590 test_arg_2_step=1;
31591 test_arg_3_freq=global_ddr_clk;
31592 test_arg_4_step_status=0;
31593 lcdlr_temp_count=0;
31594 num_arry[0]=test_arg_0_cmd0;
31595 num_arry[1]=test_arg_1_cmd1;
31596 num_arry[2]=test_arg_2_step;
31597 num_arry[3]=test_arg_3_freq;
31598 num_arry[4]=test_arg_4_step_status;
31599 num_arry[5]=boot_times;
31600 lcdlr_temp_count=num_arry[6];
31601 num_arry[6]=lcdlr_temp_count;
31602 num_arry[7]=DMC_STICKY_MAGIC_1;
31603 for (i = 8; i < 63; i++) {
31604 num_arry[i]=0;
31605 }
31606 }
31607
31608 for (i = 0; i < 63; i++) {
31609
31610 writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
31611 }
31612
31613
31614 ddr_feq_test_step=rd_reg(sticky_reg_base_add+(8<<2));
31615 //
31616 //p_char_ddr_test_step= env_get("ddr_feq_test_step");
31617 // if (p_char_ddr_test_step)
31618 {
31619 // printf("%s",p_char_ddr_test_step);
31620
31621 // ddr_feq_test_step = simple_strtoull_ddr(p_char_ddr_test_step, &endp, 0);
31622 printf("ddr_feq_test_step=%d\n",ddr_feq_test_step);
31623 }
31624 if (ddr_feq_test_step) {
31625 //p_char_freq_org= env_get("ddr_feq_org");
31626 //if (p_char_freq_org)
31627 {
31628 //printf("%s",p_char_freq_org);
31629
31630 // ddr_clk_org = simple_strtoull_ddr(p_char_freq_org, &endp, 10); //must use 10 ,freq 0792 maybe not read successful use 0 auto read
31631 ddr_clk_org=rd_reg(sticky_reg_base_add+(9<<2));
31632 printf("ddr_clk_org=%d\n",ddr_clk_org);
31633 }
31634 }
31635 if (ddr_feq_test_step == 0)
31636 {
31637 ddr_feq_test_step=1;
31638 ddr_clk_org=ddr_clk;
31639 sprintf(char_freq_org,"%04d",ddr_clk);
31640 printf("\nddr_org_freq=%s\n",char_freq_org);
31641 //env_set("ddr_feq_org", char_freq_org);
31642 writel(ddr_clk,(sticky_reg_base_add+(9<<2)));
31643
31644
31645 temp_count=(start_freq/24);
31646 while (temp_count<(DDR_TEST_MAX_FREQ/24)) {
31647
31648 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
31649 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31650 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31651 //env_set(char_freq_name_table, "0");
31652 //env_set("ddr_feq_test_step", "1");
31653 writel(0,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31654 writel(1,(sticky_reg_base_add+(8<<2)));
31655 temp_count++;
31656 }
31657 temp_count=(start_freq/24);
31658 while (temp_count<((start_freq)/24)) {
31659
31660 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
31661 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31662 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31663 //env_set(char_freq_name_table, "3");
31664 //env_set("ddr_feq_test_step", "1");
31665 writel(3,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31666 writel(1,(sticky_reg_base_add+(8<<2)));
31667 temp_count++;
31668 }
31669 while (temp_count>((end_freq)/24)) {
31670
31671 // sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
31672 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31673 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31674 //env_set(char_freq_name_table, "3");
31675 //env_set("ddr_feq_test_step", "1");
31676 writel(3,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31677 writel(1,(sticky_reg_base_add+(8<<2)));
31678 temp_count++;
31679 }
31680
31681 //p_char_store_boot= env_get("storeboot");
31682 //if (p_char_store_boot)
31683 //printf("storeboot %s\n",p_char_store_boot);
31684 // sprintf(char_cmd_table,"ddr_test_cmd 0x1c 0x%08x %d %d %d;%s;",ddr_test_size,start_freq,end_freq,test_loops,p_char_store_boot);
31685 // env_set("storeboot", char_cmd_table);
31686
31687 // run_command("save",0);
31688
31689
31690
31691 {
31692 }
31693
31694 }
31695
31696 if (ddr_feq_test_step == 1)
31697 {
31698
31699 temp_count=(start_freq/24);
31700 while (temp_count<((DDR_TEST_MAX_FREQ)/24)) {
31701
31702 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31703 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31704 ddr_feq_test_step=rd_reg(sticky_reg_base_add+(8<<2));
31705 // p_char_freq_name_table= env_get(char_freq_name_table);
31706 // if (p_char_freq_name_table)
31707 {
31708 // printf("%s\n",p_char_freq_name_table);
31709
31710 // freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
31711 freq_table_test_value[temp_count] =rd_reg(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2));
31712 printf("%s | %d\n",char_freq_name_table,freq_table_test_value[temp_count]);
31713
31714
31715 }
31716 temp_count++;
31717 }
31718
31719 temp_count=(start_freq/24);
31720 while (temp_count<((DDR_TEST_MAX_FREQ)/24)) {
31721 ddr_clk_hope_test=(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24)));
31722 if (freq_table_test_value[temp_count] ==1)
31723 {
31724 temp_count_sub=temp_count+1;
31725 while ((pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*24))) ==
31726 (pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))))
31727 {temp_count_sub=temp_count_sub+1;
31728 }
31729 while (temp_count_sub<((DDR_TEST_MAX_FREQ)/24)) {
31730 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*24))));
31731 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31732 // freq_table_test_value[temp_count_sub] =1;
31733 // env_set(char_freq_name_table, "3");
31734 writel(3,(sticky_reg_base_add+((10+temp_count_sub-(start_freq/24))<<2)));
31735
31736 temp_count_sub++;
31737 }
31738 {
31739 ddr_feq_test_step++;
31740 //env_set("ddr_feq_test_step", "2");
31741 // run_command("save",0);
31742 writel(2,(sticky_reg_base_add+(8<<2)));
31743
31744 }
31745 {ddr_clk_hope_test=ddr_clk_org;
31746 }
31747 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
31748 printf("\nchar_cmd_table=%s\n",char_cmd_table);
31749 run_command(char_cmd_table,0);
31750
31751 }
31752 if (freq_table_test_value[temp_count] ==0)
31753 {
31754 if ((ddr_clk_hope_test) != (ddr_clk))
31755 {
31756 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
31757 printf("\nchar_cmd_table=%s\n",char_cmd_table);
31758 run_command(char_cmd_table,0);
31759 }
31760 if ((ddr_clk_hope_test) == (ddr_clk))
31761 {
31762
31763 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31764 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31765 freq_table_test_value[temp_count] =1;
31766 // env_set(char_freq_name_table, "1");
31767 // run_command("save",0);
31768 writel(1,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31769
31770
31771 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
31772 while (test_loops--) {
31773 temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
31774 }
31775 //temp_test_error=temp_test_error+ddr_test_s_add_cross_talk_pattern(ddr_test_size);
31776
31777 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31778 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31779 if (temp_test_error)
31780 {
31781 freq_table_test_value[temp_count] =1;
31782 // env_set(char_freq_name_table, "1");
31783 writel(1,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31784 }
31785 else
31786 {
31787 freq_table_test_value[temp_count] =2;
31788 // env_set(char_freq_name_table, "2");
31789 writel(2,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
31790 }
31791 // run_command("save",0);
31792
31793 ddr_clk_hope_test=(temp_count*24)+24;
31794 while ((pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(ddr_clk_hope_test))) ==
31795 (pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))))
31796 {ddr_clk_hope_test=ddr_clk_hope_test+24;
31797 }
31798 if (temp_test_error)
31799 {ddr_clk_hope_test=ddr_clk_org;
31800 }
31801 sprintf(char_cmd_table,"ddr_test_cmd 0x17 %d 0 0 0",ddr_clk_hope_test);
31802 printf("\nchar_cmd_table=%s\n",char_cmd_table);
31803 run_command(char_cmd_table,0);
31804 }
31805
31806 }
31807
31808
31809
31810
31811
31812 temp_count++;
31813 }
31814 ddr_feq_test_step++;
31815 //env_set("ddr_feq_test_step", "2");
31816 //run_command("save",0);
31817 writel(2,(sticky_reg_base_add+(8<<2)));
31818
31819 }
31820
31821 if (ddr_feq_test_step >= 2)
31822 {
31823 printf("\nfinish test ddr_feq_test_step=%d\n",ddr_feq_test_step);
31824 temp_count=(start_freq/24);
31825 while (temp_count<((DDR_TEST_MAX_FREQ)/24)) {
31826
31827 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31828 printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
31829
31830 // p_char_freq_name_table= env_get(char_freq_name_table);
31831 // if (p_char_freq_name_table)
31832 {
31833 // printf("%s\n",p_char_freq_name_table);
31834
31835 // freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
31836 freq_table_test_value[temp_count] =rd_reg(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2));
31837 printf("%s | %d\n",char_freq_name_table,freq_table_test_value[temp_count]);
31838 }
31839 temp_count++;
31840 }
31841
31842 printf("\nprint test ddr_feq_test_result!!!\n");
31843 temp_count=(start_freq/24);
31844 while (temp_count<((DDR_TEST_MAX_FREQ)/24)) {
31845
31846 sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
31847 // p_char_freq_name_table= env_get(char_freq_name_table);
31848 // if (p_char_freq_name_table)
31849 {
31850 // printf("%s\n",p_char_freq_name_table);
31851
31852 // freq_table_test_value[temp_count] = simple_strtoull_ddr(p_char_freq_name_table, &endp, 0);
31853 freq_table_test_value[temp_count] =rd_reg(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2));
31854
31855 //printf("%d\n",freq_table_test_value[temp_count]);
31856 if ( (freq_table_test_value[temp_count]) == 0) {
31857 printf("%04d no init %d \n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))),freq_table_test_value[temp_count]);
31858 }
31859 if ( (freq_table_test_value[temp_count]) == 1) {
31860 printf("%04d fail %d\n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))),freq_table_test_value[temp_count]);
31861 }
31862 if ( (freq_table_test_value[temp_count]) == 2) {
31863 printf("%04d pass %d\n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))),freq_table_test_value[temp_count]);
31864 }
31865 if ( (freq_table_test_value[temp_count]) >= 3) {
31866 printf("%04d skip test %d \n",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))),freq_table_test_value[temp_count]);
31867 }
31868 temp_count++;
31869 }
31870 }
31871
31872 }
31873 //sprintf(str,"ddr_test_ac_bit_setup_hold_window a 0 0x%08x %d 0x%08x",ddr_test_size,test_ac_setup_hold,( lane_step));
31874 // printf("\nstr=%s\n",str);
31875
31876 //sprintf(str, "%lx", value);
31877 // env_set("env_ddrtest", str);
31878
31879 //run_command("save",0);
31880 //*/
31881 return 1;
31882
31883}
31884
31885
31886int do_ddr4_test_bist_test_use_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
31887{
31888
31889#define DDR_TEST_CMD_TEST_ZQ 0
31890#define DDR_TEST_CMD_TEST_AC_BIT_SETUP 1
31891#define DDR_TEST_CMD_TEST_AC_BIT_HOLD 2
31892#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_SETUP 3
31893#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_HOLD 4
31894#define DDR_TEST_CMD_TEST_DATA_READ_BIT_SETUP 5
31895#define DDR_TEST_CMD_TEST_DATA_READ_BIT_HOLD 6
31896#define DDR_TEST_CMD_TEST_DATA_VREF 7
31897#define DDR_TEST_CMD_TEST_CLK_INVETER 8
31898
31899#define DDR_TEST_CMD_TEST_FULLTEST 0xffffffff
31900 char *endp;
31901 unsigned int pll, zqcr;
31902 unsigned int zqpr_soc_dram=0;
31903 unsigned int ddr_test_cmd_soc_vref=0;
31904 unsigned int ddr_test_cmd_dram_vref=0;//0x3f;
31905 unsigned int ddr_test_cmd_zq_vref=0;//0x3f;
31906
31907
31908 unsigned int ddr_full_test_enable=0;
31909 /*
31910#define DDR3_DRV_40OHM 0
31911#define DDR3_DRV_34OHM 1
31912#define DDR3_ODT_0OHM 0
31913#define DDR3_ODT_60OHM 1
31914#define DDR3_ODT_120OHM 2
31915#define DDR3_ODT_40OHM 3
31916#define DDR3_ODT_20OHM 4
31917#define DDR3_ODT_30OHM 5
31918
31919 // lpddr2 drv odt
31920#define LPDDR2_DRV_34OHM 1
31921#define LPDDR2_DRV_40OHM 2
31922#define LPDDR2_DRV_48OHM 3
31923#define LPDDR2_DRV_60OHM 4
31924#define LPDDR2_DRV_80OHM 6
31925#define LPDDR2_DRV_120OHM 7
31926#define LPDDR2_ODT_0OHM 0
31927
31928 // lpddr3 drv odt
31929#define LPDDR3_DRV_34OHM 1
31930#define LPDDR3_DRV_40OHM 2
31931#define LPDDR3_DRV_48OHM 3
31932#define LPDDR3_DRV_60OHM 4
31933#define LPDDR3_DRV_80OHM 6
31934#define LPDDR3_DRV_34_40OHM 9
31935#define LPDDR3_DRV_40_48OHM 10
31936#define LPDDR3_DRV_34_48OHM 11
31937#define LPDDR3_ODT_0OHM 0
31938#define LPDDR3_ODT_60OHM 1
31939#define LPDDR3_ODT_12OHM 2
31940#define LPDDR3_ODT_240HM 3
31941
31942#define DDR4_DRV_34OHM 0
31943#define DDR4_DRV_48OHM 1
31944#define DDR4_ODT_0OHM 0
31945#define DDR4_ODT_60OHM 1
31946#define DDR4_ODT_120OHM 2
31947#define DDR4_ODT_40OHM 3
31948#define DDR4_ODT_240OHM 4
31949#define DDR4_ODT_48OHM 5
31950#define DDR4_ODT_80OHM 6
31951#define DDR4_ODT_34OHM 7
31952*/
31953 printf("\nargc== 0x%08x\n", argc);
31954 int i ;
31955 for (i = 0;i<argc;i++)
31956 {
31957 printf("\nargv[%d]=%s\n",i,argv[i]);
31958 }
31959
31960 unsigned int soc_data_drv_odt = 0;
31961 unsigned int bist_test_dq_index = 0xff;
31962 //unsigned int dram_drv = 0;
31963 //unsigned int dram_odt = 0;
31964 /* need at least two arguments */
31965 if (argc < 2)
31966 goto usage;
31967
31968 pll = simple_strtoull_ddr(argv[1], &endp,0);
31969 if (*argv[1] == 0 || *endp != 0) {
31970 printf ("Error: Wrong format parament!\n");
31971 return 1;
31972 }
31973 if (argc >2)
31974 {
31975 zqcr = simple_strtoull_ddr(argv[2], &endp, 0);
31976 if (*argv[2] == 0 || *endp != 0) {
31977 zqcr = 0;
31978 }
31979 }
31980 else
31981 {
31982 zqcr = 0;
31983 }
31984 bist_test_dq_index=0xff;
31985 if (zqcr == 0xffffffff)
31986 {
31987 ddr_full_test_enable=1;
31988 zqcr=0;}
31989
31990 else if(zqcr>>24)
31991 {
31992 bist_test_dq_index=0+(zqcr>>24);
31993 zqcr=zqcr&0x00ffffff;
31994 }
31995
31996 printf("bist_test_dq_index[%d],\n", bist_test_dq_index);
31997
31998 if (argc >3)
31999 {
32000 // soc_data_drv_odt=zqpr_soc_dram&0xfffff;
32001 // dram_drv=(zqpr_soc_dram>>20)&0xf;
32002 // dram_odt=(zqpr_soc_dram>>24)&0xf;
32003 //bit28 enable soc_zqpr ,bit 29 enable dram_drv bit 30 enable dram_odt
32004 zqpr_soc_dram = simple_strtoull_ddr(argv[3], &endp, 0);
32005 if (*argv[3] == 0 || *endp != 0) {
32006 zqpr_soc_dram = 0;
32007 }
32008 }
32009 else
32010 {
32011 zqpr_soc_dram = 0;
32012 }
32013
32014 if (argc >4)
32015 {
32016 ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
32017 if (*argv[4] == 0 || *endp != 0) {
32018 ddr_test_cmd_soc_vref = 0;
32019 }
32020 }
32021 else
32022 {
32023 ddr_test_cmd_soc_vref = 0;
32024 }
32025 if (argc >5)
32026 {
32027 ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
32028 if (*argv[5] == 0 || *endp != 0) {
32029 ddr_test_cmd_dram_vref = 0;
32030 }
32031 }
32032 unsigned int soc_dram_hex_dec=0;
32033 if (argc >6)
32034 {
32035 soc_dram_hex_dec = simple_strtoull_ddr(argv[6], &endp, 0);
32036 if (*argv[6] == 0 || *endp != 0) {
32037 soc_dram_hex_dec = 0;
32038 }
32039 }
32040 if (argc >7)
32041 {
32042 ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
32043 if (*argv[7] == 0 || *endp != 0) {
32044 ddr_test_cmd_zq_vref = 0;
32045 }
32046 }
32047 unsigned int soc_dram_drv_odt_use_vlaue=0;
32048 unsigned int soc_ac_drv=0;
32049 unsigned int soc_ac_odt=0;
32050 unsigned int soc_data_drv=0;
32051 unsigned int soc_data_odt=0;
32052 unsigned int dram_drv=0;
32053 unsigned int dram_odt=0;
32054 unsigned int soc_data_drv_odt_adj_enable=0;
32055 unsigned int dram_data_drv_adj_enable=0;
32056 unsigned int dram_data_odt_adj_enable=0;
32057
32058 unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
32059 unsigned int zq1pr_org = rd_reg(DDR0_PUB_ZQ1PR);
32060 unsigned int pub_dcr= rd_reg(DDR0_PUB_DCR);
32061#define DDR_TYPE_LPDDR2 0
32062#define DDR_TYPE_LPDDR3 1
32063#define DDR_TYPE_DDR3 3
32064#define DDR_TYPE_DDR4 4
32065 unsigned int ddr_type= pub_dcr&0x7; //0 -lpddr2 | 1- lpddr3 | 2- rev | 3 -ddr3 | 4- ddr4
32066 // unsigned int zq2pr_org = rd_reg(DDR0_PUB_ZQ2PR);
32067 if (argc >8)
32068 {
32069 soc_dram_drv_odt_use_vlaue = simple_strtoull_ddr(argv[8], &endp, 0);
32070 if (*argv[8] == 0 || *endp != 0) {
32071 soc_dram_drv_odt_use_vlaue = 0;
32072 }
32073 }
32074 if (soc_dram_drv_odt_use_vlaue)
32075 {if(zqcr)
32076 {printf("zqcr[0x%08x],\n", zqcr);
32077 {
32078 soc_ac_drv=zqcr%100;
32079 if (soc_ac_drv>100)
32080 {soc_ac_drv=0;}
32081 if (soc_ac_drv == 0)
32082 {soc_ac_drv=1;}
32083 soc_ac_drv=(480/soc_ac_drv)-1;
32084
32085 if (ddr_type == DDR_TYPE_DDR3)
32086 {
32087 if (soc_ac_drv>0xf)
32088 {soc_ac_drv=zq0pr_org&0xf;}
32089 }
32090 if (ddr_type == DDR_TYPE_DDR4)
32091 {
32092 if (soc_ac_drv>0xf)
32093 {soc_ac_drv=(zq0pr_org>>8)&0xf;}
32094 }
32095 }
32096
32097
32098 {
32099 soc_ac_odt=zqcr/100;
32100 if (soc_ac_odt>240)
32101 {soc_ac_odt=480;}
32102 if (soc_ac_odt == 0)
32103 {soc_ac_odt=1;}
32104
32105
32106 if (ddr_type == DDR_TYPE_DDR3)
32107 {
32108 soc_ac_odt=(360/soc_ac_odt)-1;
32109 if (soc_ac_odt>0xf)
32110 {soc_ac_odt=(zq0pr_org>>4)&0xf;}
32111 }
32112 if (ddr_type == DDR_TYPE_DDR4)
32113 {
32114 soc_ac_odt=(480/soc_ac_odt)-1;
32115 if (soc_ac_odt>0xf)
32116 {soc_ac_odt=(zq0pr_org>>16)&0xf;}
32117 }
32118 }
32119
32120 zqcr=(soc_ac_odt<<16)|(soc_ac_drv<<12)|(soc_ac_drv<<8)|(soc_ac_odt<<4)|(soc_ac_drv);
32121 printf("zqcr[0x%08x],soc_ac_odt [0x%08x],soc_ac_drv [0x%08x]\n", zqcr,soc_ac_odt,soc_ac_drv);
32122 }
32123 if (zqpr_soc_dram)
32124 {printf("zqpr_soc_dram[0x%08x],\n", zqpr_soc_dram);
32125 {
32126 soc_data_drv=zqpr_soc_dram%100;
32127 printf("soc_data_drv[%d],\n", soc_data_drv);
32128 if (soc_data_drv>100)
32129 {soc_data_drv=0;
32130
32131 }
32132 if (soc_data_drv == 0)
32133 {soc_data_drv=1;
32134 //soc_data_drv_odt_adj_enable=0;
32135 }
32136 else
32137 {//soc_data_drv_odt_adj_enable=1;
32138 }
32139 soc_data_drv=(480/soc_data_drv)-1;
32140
32141 if (ddr_type == DDR_TYPE_DDR3)
32142 {
32143 if (soc_data_drv>0xf)
32144 {soc_data_drv=zq1pr_org&0xf;}
32145 }
32146 if (ddr_type == DDR_TYPE_DDR4)
32147 {
32148 if (soc_data_drv>0xf)
32149 {soc_data_drv=(zq1pr_org>>8)&0xf;}
32150 }
32151 }
32152
32153
32154 {
32155 soc_data_odt=(zqpr_soc_dram/100)%1000;
32156 printf("soc_data_odt[%d],\n", soc_data_odt);
32157 if (soc_data_odt>240)
32158 {soc_data_odt=360;}
32159 if (soc_data_odt == 0)
32160 {soc_data_odt=1;}
32161
32162
32163 if (ddr_type == DDR_TYPE_DDR3)
32164 {
32165 soc_data_odt=(360/soc_data_odt)-1;
32166 if (soc_data_odt>0xf)
32167 {soc_data_odt=(zq1pr_org>>4)&0xf;}
32168 }
32169 if (ddr_type == DDR_TYPE_DDR4)
32170 {
32171 soc_data_odt=(480/soc_data_odt)-1;
32172 if (soc_data_odt>0xf)
32173 {soc_data_odt=(zq1pr_org>>16)&0xf;}
32174 }
32175
32176 }
32177
32178 soc_data_drv_odt_adj_enable=1;
32179
32180 {
32181 dram_drv=(zqpr_soc_dram/100000)%100;
32182 printf("dram_drv[%d],\n", dram_drv);
32183
32184 if (dram_drv>100)
32185 {dram_drv=0;}
32186 if (dram_drv == 0)
32187 {
32188 dram_data_drv_adj_enable=0;}
32189 else
32190 {dram_data_drv_adj_enable=1;
32191 }
32192
32193 if (ddr_type == DDR_TYPE_DDR3)
32194 {
32195 if (dram_drv >= 40)
32196 {dram_drv=0;}
32197
32198 else
32199 {dram_drv=1;
32200 }
32201 }
32202
32203
32204 if (ddr_type == DDR_TYPE_DDR4)
32205 {
32206 if (dram_drv<48)
32207 {dram_drv=0;}
32208
32209 else
32210 {dram_drv=1;
32211 }
32212 }
32213 }
32214
32215
32216 {
32217 dram_odt=(zqpr_soc_dram/100000)/100;
32218 printf("dram_odt[%d],\n", dram_odt);
32219 if (dram_odt>240)
32220 {dram_odt=480;}
32221 if (dram_odt == 0)
32222 {
32223 dram_data_odt_adj_enable=0;
32224 }
32225 else
32226 {dram_data_odt_adj_enable=1;
32227 }
32228
32229
32230 if (ddr_type == DDR_TYPE_DDR3)
32231 {
32232 if (dram_odt>160)
32233 {dram_odt=0;}
32234 else if (dram_odt>90)
32235 {dram_odt=2;}
32236 else if (dram_odt>50)
32237 {dram_odt=1;}
32238 else if (dram_odt>35)
32239 {dram_odt=3;}
32240 else if (dram_odt>25)
32241 {dram_odt=5;}
32242 else if (dram_odt<=25)
32243 {dram_odt=4;}
32244
32245 }
32246 if (ddr_type == DDR_TYPE_DDR4)
32247 {
32248 if (dram_odt>280)
32249 {dram_odt=0;}
32250 else if (dram_odt>180)
32251 {dram_odt=4;}
32252 else if (dram_odt>100)
32253 {dram_odt=2;}
32254 else if (dram_odt>70)
32255 {dram_odt=6;}
32256 else if (dram_odt>54)
32257 {dram_odt=1;}
32258 else if (dram_odt>44)
32259 {dram_odt=5;}
32260 else if (dram_odt>37)
32261 {dram_odt=3;}
32262 else if (dram_odt<=34)
32263 {dram_odt=7;}
32264
32265 }
32266
32267
32268
32269 }
32270
32271 zqpr_soc_dram=(dram_data_odt_adj_enable<<30)|(dram_data_drv_adj_enable<<29)|(soc_data_drv_odt_adj_enable<<28)|
32272 (dram_odt<<24)|(dram_drv<<20)|(soc_data_odt<<16)|(soc_data_drv<<12)|(soc_data_drv<<8)|(soc_data_odt<<4)|(soc_data_drv);
32273 }
32274 }
32275
32276
32277 if (soc_dram_hex_dec)
32278 {
32279 if (argc >4)
32280 {
32281 ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
32282 if (*argv[4] == 0 || *endp != 0) {
32283 ddr_test_cmd_soc_vref = 0;
32284 }
32285 }
32286 else
32287 {
32288 ddr_test_cmd_soc_vref = 0;
32289 }
32290 if (argc >5)
32291 {
32292 ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
32293 if (*argv[5] == 0 || *endp != 0) {
32294 ddr_test_cmd_dram_vref = 0;
32295 }
32296 }
32297 if (argc >7)
32298 {
32299 ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
32300 if (*argv[7] == 0 || *endp != 0) {
32301 ddr_test_cmd_zq_vref = 0;
32302 }
32303 }
32304 if (ddr_test_cmd_soc_vref)
32305 {
32306 if (ddr_test_cmd_soc_vref<45)
32307 ddr_test_cmd_soc_vref=45;
32308 if (ddr_test_cmd_soc_vref>88)
32309 ddr_test_cmd_soc_vref=88;
32310 ddr_test_cmd_soc_vref=(ddr_test_cmd_soc_vref*100-4407)/70;
32311 }
32312
32313 if (ddr_test_cmd_dram_vref)
32314 {
32315 if (ddr_test_cmd_dram_vref<45)
32316 ddr_test_cmd_dram_vref=45;
32317 if (ddr_test_cmd_dram_vref>92)
32318 ddr_test_cmd_dram_vref=92;
32319 if (ddr_test_cmd_dram_vref>60) {
32320 ddr_test_cmd_dram_vref=(ddr_test_cmd_dram_vref*100-6000)/65;
32321 }
32322 else{
32323 ddr_test_cmd_dram_vref=((ddr_test_cmd_dram_vref*100-4500)/65)|(1<<6);
32324 }
32325 }
32326
32327
32328 printf("\nSet ddr_test_cmd_dram_vref [0x%08x]\n",ddr_test_cmd_dram_vref);
32329 if (ddr_test_cmd_zq_vref == 0)
32330 ddr_test_cmd_zq_vref=0;
32331 if (ddr_test_cmd_zq_vref) {
32332 if (ddr_test_cmd_zq_vref<45)
32333 ddr_test_cmd_zq_vref=45;
32334 if (ddr_test_cmd_zq_vref>88)
32335 ddr_test_cmd_zq_vref=88;
32336 ddr_test_cmd_zq_vref=(ddr_test_cmd_zq_vref*100-4407)/70;
32337 }
32338 }
32339
32340 //if(ddr_test_cmd_type==DDR_TEST_CMD_TEST_AC_BIT_HOLD)
32341 //{if (ddr_test_cmd_clk_seed ==0)
32342 //ddr_test_cmd_clk_seed = 0x3f;
32343 //if (ddr_test_cmd_acbdl_x_seed ==0)
32344 //ddr_test_cmd_acbdl_x_seed = 0x3f;
32345 //}
32346
32347#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
32348 writel(zqcr | (0x3c << 24), PREG_STICKY_REG0);
32349#else
32350 writel(zqcr | (0xf14 << 20), PREG_STICKY_REG0);
32351#endif
32352#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
32353 writel((ddr_test_cmd_zq_vref<<24)|(ddr_test_cmd_soc_vref<<8)|ddr_test_cmd_dram_vref , PREG_STICKY_REG9);
32354 writel((zqpr_soc_dram<<0) , PREG_STICKY_REG8);
32355 soc_data_drv_odt=zqpr_soc_dram&0xfffff;
32356 dram_drv=(zqpr_soc_dram>>20)&0xf;
32357 dram_odt=(zqpr_soc_dram>>24)&0xf;
32358 printf("setting zqpr_soc_dram [0x%08x],..bit28 enable soc_zqpr , bit 29 enable dram_drv, bit 30 enable dram_odt\n", zqpr_soc_dram);
32359 printf("soc_data_drv_odt [0x%08x],dram_drv [0x%08x],dram_odt [0x%08x]\n", soc_data_drv_odt,dram_drv,dram_odt);
32360 pll=pll|(bist_test_dq_index<<12);
32361
32362 if (ddr_full_test_enable)
32363 {
32364 pll=(ddr_full_test_enable<<21)|pll;
32365 printf("ddr_full_test_enable %08x,set sticky reg1 bit 21 1\n", ddr_full_test_enable);
32366 }
32367
32368#endif
32369
32370
32371 writel(pll, PREG_STICKY_REG1);
32372
32373 printf("Set pll done [0x%08x]\n", readl(PREG_STICKY_REG1));
32374 printf("STICKY_REG1 pll bit 12-19 use for bist dq index test 0xff is all 1 --> dq0 ,2--->dq1 \n");
32375 printf("Set STICKY_REG0 [0x%08x]\n", readl(PREG_STICKY_REG0));
32376 printf("Set STICKY_REG1 [0x%08x]\n", readl(PREG_STICKY_REG1));
32377#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
32378 printf("Set STICKY_REG9 [0x%08x]\n", readl(PREG_STICKY_REG9));
32379 printf("Set STICKY_REG8 [0x%08x]\n", readl(PREG_STICKY_REG8));
32380
32381#endif
32382 printf("\nbegin reset 111...........\n");
32383 printf("\nbegin reset 2...........\n");
32384 printf("\nbegin reset 3...........\n");
32385
32386#ifdef CONFIG_M8B
32387 printf(" t1 \n");
32388 writel(0xf080000 | 2000, WATCHDOG_TC);
32389#else
32390 printf(" t2 \n");
32391 // writel(WATCHDOG_TC, 0xf400000 | 2000);
32392 // *P_WATCHDOG_RESET = 0;
32393 ddr_test_watchdog_reset_system();
32394#endif
32395 while (1) ;
32396 return 0;
32397
32398usage:
32399
32400 printf(" ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n");
32401 printf("example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n");
32402 printf("or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
32403 printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n");
32404 printf("setting zqpr_soc_dram ,..bit28 enable soc_zqpr , bit 29 enabe dram_drv, bit 30 enable dram_odt\n");
32405 printf("setting zqpr_soc_dram ,bit0-bit19 soc_data_drv_odt,bit20-bit24 dram_drv , bit24-bit28 dram_odt\n");
32406 printf("setting zqpr_soc_dram ,bit0-bit19 bit 0-7 use for ddr3��bit8-19 use for ddr4,odt_down_up\n");
32407 printf("setting zqpr_soc_dram ,soc_drv=(480/((setting)+1));ddr4---soc_odt=(480/(setting)+1));ddr3---soc_odt=(360/(setting)+1));\n");
32408
32409 printf(" DDR3_DRV_40OHM 0\n");
32410 printf(" DDR3_DRV_34OHM 1\n\n");
32411
32412 printf(" DDR3_ODT_0OHM 0\n");
32413 printf(" DDR3_ODT_60OHM 1\n");
32414 printf(" DDR3_ODT_120OHM 2\n");
32415 printf(" DDR3_ODT_40OHM 3\n");
32416 printf(" DDR3_ODT_20OHM 4\n");
32417 printf(" DDR3_ODT_30OHM 5\n\n\n");
32418
32419 printf(" LPDDR2_DRV_34OHM 1\n");
32420 printf(" LPDDR2_DRV_40OHM 2\n");
32421 printf(" LPDDR2_DRV_48OHM 3\n");
32422 printf(" LPDDR2_DRV_60OHM 4\n");
32423 printf(" LPDDR2_DRV_80OHM 6\n");
32424 printf(" LPDDR2_DRV_120OHM 7\n\n");
32425
32426 printf(" LPDDR2_ODT_0OHM 0\n\n\n");
32427
32428
32429 printf(" LPDDR3_DRV_34OHM 1\n");
32430 printf(" LPDDR3_DRV_40OHM 2\n");
32431 printf(" LPDDR3_DRV_48OHM 3\n");
32432 printf(" LPDDR3_DRV_60OHM 4\n");
32433 printf(" LPDDR3_DRV_80OHM 6\n");
32434 printf(" LPDDR3_DRV_34_40OHM 9\n");
32435 printf(" LPDDR3_DRV_40_48OHM 10\n");
32436 printf(" LPDDR3_DRV_34_48OHM 11\n\n");
32437
32438 printf(" LPDDR3_ODT_0OHM 0\n");
32439 printf(" LPDDR3_ODT_60OHM 1\n");
32440 printf(" LPDDR3_ODT_12OHM 2\n");
32441 printf(" LPDDR3_ODT_240HM 3\n\n\n");
32442
32443 printf(" DDR4_DRV_34OHM 0\n");
32444 printf(" DDR4_DRV_48OHM 1\n\n");
32445
32446 printf(" DDR4_ODT_0OHM 0\n");
32447 printf(" DDR4_ODT_60OHM 1\n");
32448 printf(" DDR4_ODT_120OHM 2\n");
32449 printf(" DDR4_ODT_40OHM 3\n");
32450 printf(" DDR4_ODT_240OHM 4\n");
32451 printf(" DDR4_ODT_48OHM 5\n");
32452 printf(" DDR4_ODT_80OHM 6\n");
32453 printf(" DDR4_ODT_34OHM 7\n\n\n\n");
32454
32455
32456 cmd_usage(cmdtp);
32457 return 1;
32458}
32459
32460
32461int do_ddr_set_bist_test_size_use_sticky_6(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
32462{
32463 char *endp;
32464
32465 unsigned int ddr_bist_test_size=0;
32466
32467 printf("\nargc== 0x%08x\n", argc);
32468 int i ;
32469 for (i = 0;i<argc;i++)
32470 {
32471 printf("\nargv[%d]=%s\n",i,argv[i]);
32472 }
32473
32474 ddr_bist_test_size = simple_strtoull_ddr(argv[1], &endp,0);
32475 ddr_bist_test_size=ddr_bist_test_size&0xffffffe0;
32476 if (*argv[1] == 0 || *endp != 0) {
32477 ddr_bist_test_size=0x3f0*2;
32478 }
32479
32480 printf("ddr_bist_test_size 0x[%08x],\n", ddr_bist_test_size);
32481
32482#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
32483 writel((ddr_bist_test_size<<0) , PREG_STICKY_REG6);
32484 printf("Set STICKY_REG6 [0x%08x]\n", readl(PREG_STICKY_REG6));
32485#endif
32486
32487 return 1;
32488}
32489
32490unsigned int do_ddr_read_write_ddr_add__data_window_lcdlr(unsigned int rank_index,unsigned int add_index,unsigned int lcdlr_value,unsigned int read_write_flag )
32491{
32492 unsigned reg_add=0;
32493
32494 if (add_index == 0)
32495 reg_add=(DDR0_PUB_ACLCDLR);
32496 if (add_index == 1)
32497 reg_add=(DDR0_PUB_ACBDLR0);
32498 {
32499 if (read_write_flag == DDR_PARAMETER_READ)
32500 {
32501 lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
32502 }
32503 if (read_write_flag == DDR_PARAMETER_WRITE)
32504 {
32505 wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
32506 }
32507
32508 }
32509 printf("lcdlr %d %08x,%08x\n", add_index,reg_add,
32510 (readl(reg_add)));
32511 return lcdlr_value;
32512}
32513
32514#endif
32515
32516#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))=((uint16_t)dat)
32517#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))
32518#define ACX_MAX 0x80
32519
32520//dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0),0);
32521//dwc_ddrphy_apb_wr(0xd0000,0);
32522//dwc_ddrphy_apb_wr(0xd0000,1);
32523
32524//*(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);
32525//dwc_ddrphy_apb_wr((ps<<20)|(0<<16)|(instance_num<<12)|(0x80),);
32526
32527//ddr_test_acx_g12a a length step test_mode ACx
32528//ddr_test_acx_g12a a 0x8000000 1 0 0x1
32529//argv[0] argv[1] argv[2] argv[3] argv[4] argv[5]
32530//argv[1],a
32531//argv[2],test length
32532//argv[3],test step
32533//argv[4],test_mode,direction,0,up; 1,down; 2,down first,up follow;
32534//argv[5],ACx;0-AC0,1-AC1,2-AC2...,9-AC9
32535
32536#if 0
32537int do_ddr_test_acx_g12a(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
32538{
32539 printf("\nEnter test ddr ac bit window function\n");
32540 printf("\nargc== 0x%08x\n", argc);
32541 //unsigned int ddl_100step_ps= 0;
32542
32543 unsigned int temp_test_error= 0;
32544 unsigned int temp_count= 0;
32545 //unsigned int temp_reg_value[40];
32546
32547 char *endp;
32548 unsigned int test_mode=0;
32549 unsigned int test_ACx=0;
32550 unsigned int reg_add=0;
32551 unsigned int reg_base_adj=0;
32552
32553 unsigned int acbdlr_x_reg_org=0;
32554 unsigned int acbdlr_x_reg_min=0;
32555 unsigned int acbdlr_x_reg_max=0;
32556
32557 uint16_t dq_lcd_bdl_temp_reg_value=0;
32558 uint16_t test_step=1;
32559 unsigned int ddr_test_size= DDR_CROSS_TALK_TEST_SIZE;
32560
32561 if (argc <= 2)
32562 {
32563 goto usage;
32564 }
32565 else
32566 {
32567 ddr_test_size = simple_strtoull_ddr(argv[2], &endp, 16);
32568 if (*argv[2] == 0 || *endp != 0)
32569 {
32570 ddr_test_size = DDR_CROSS_TALK_TEST_SIZE;
32571 }
32572 }
32573 if (argc >3)
32574 {
32575 test_step = simple_strtoull_ddr(argv[3], &endp, 16);
32576 if (*argv[3] == 0 || *endp != 0)
32577 {
32578 test_step = 1;
32579 }
32580 }
32581 if (argc >4)
32582 {
32583 test_mode = simple_strtoull_ddr(argv[4], &endp, 16); //���Է���
32584 if (*argv[4] == 0 || *endp != 0)
32585 {
32586 test_mode = 0;
32587 }
32588 if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
32589 {
32590 test_mode = 2;
32591 }
32592 }
32593 if (test_mode >2) test_mode = 2;
32594
32595 test_ACx =0;
32596 if (argc >5)
32597 {
32598
32599 test_ACx= simple_strtoull_ddr(argv[5], &endp, 16);
32600 if (*argv[5] == 0 || *endp != 0)
32601 {
32602 test_ACx = 0;
32603 }
32604 if (test_ACx>9)
32605 test_ACx =0;//default test AC0
32606 }
32607
32608 printf("ddr_test_size = 0x%08x\n", ddr_test_size);
32609 printf("test_mode = 0x%08x\n", test_mode);
32610 printf("test_ACx = 0x%08x\n", test_ACx);
32611 dwc_ddrphy_apb_wr(0xd0000,0);//mw fe1a0000 0
32612 reg_base_adj=0xfe000000;
32613 reg_add=(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj;
32614
32615 {
32616
32617 {
32618 printf("test AC%d window start\n ",test_ACx);
32619
32620 if ((test_mode == 1) || (test_mode == 2))
32621 {
32622 dq_lcd_bdl_temp_reg_value=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(test_ACx<<12)|(0x80));
32623 reg_add=((((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj);
32624 acbdlr_x_reg_org=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(test_ACx<<12)|(0x80));;
32625 while (dq_lcd_bdl_temp_reg_value>0)
32626 {
32627 temp_test_error=0;
32628 for (temp_count=0;temp_count < test_step;temp_count++)
32629 {
32630 if (dq_lcd_bdl_temp_reg_value == 0) break;
32631 dq_lcd_bdl_temp_reg_value--;
32632 };
32633 dq_lcd_bdl_temp_reg_value--;
32634 printf("\n reg_add==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_add,dq_lcd_bdl_temp_reg_value,
32635 dq_lcd_bdl_temp_reg_value-acbdlr_x_reg_org);
32636 {
32637 dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80)),dq_lcd_bdl_temp_reg_value);
32638 }
32639 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
32640
32641 if (temp_test_error)
32642 {
32643 dq_lcd_bdl_temp_reg_value++;
32644 temp_test_error = 0;
32645 break;
32646 }
32647 }
32648 printf("\n left edge detect ,reg==0x%08x\n",reg_add);
32649 printf("\n org==0x%08x,left edge==0x%08x\n ",acbdlr_x_reg_org,dq_lcd_bdl_temp_reg_value);
32650
32651 acbdlr_x_reg_min= (int)dq_lcd_bdl_temp_reg_value;
32652 printf("acbdlr_x_reg_min==0x%08x\n",acbdlr_x_reg_min);
32653
32654 dq_lcd_bdl_temp_reg_value=0;
32655 //�ָ�Ĭ��ֵ
32656 dwc_ddrphy_apb_wr((0<<20)|(0<<16)|(test_ACx<<12)|(0x80),(uint16_t)acbdlr_x_reg_org);
32657 }
32658
32659 if ((test_mode == 0) || (test_mode == 2))
32660 {
32661 dq_lcd_bdl_temp_reg_value=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(test_ACx<<12)|(0x80));
32662 reg_add=((((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj);
32663 acbdlr_x_reg_org=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(test_ACx<<12)|(0x80));
32664 while (dq_lcd_bdl_temp_reg_value<ACX_MAX)
32665 {
32666 temp_test_error = 0;
32667 for (temp_count=0;temp_count < test_step;temp_count++)
32668 {
32669 if (dq_lcd_bdl_temp_reg_value >= ACX_MAX) break;
32670 dq_lcd_bdl_temp_reg_value++;
32671 };
32672 printf("\n reg_add==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_add,dq_lcd_bdl_temp_reg_value,
32673 dq_lcd_bdl_temp_reg_value-acbdlr_x_reg_org);
32674 {
32675 dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80)),dq_lcd_bdl_temp_reg_value);
32676 }
32677 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
32678
32679 if (temp_test_error)
32680 {
32681 dq_lcd_bdl_temp_reg_value--;
32682 temp_test_error = 0;
32683 break;
32684 }
32685 }
32686 printf("right edge detect ,reg = 0x%08x\n",reg_add);
32687 printf("org = 0x%08x,right edge = 0x%08x,value = 0x%08x\n ",acbdlr_x_reg_org,dq_lcd_bdl_temp_reg_value,
32688 dq_lcd_bdl_temp_reg_value-acbdlr_x_reg_org);
32689
32690 acbdlr_x_reg_max=(int)dq_lcd_bdl_temp_reg_value;
32691 printf("acbdlr_x_reg_max = 0x%08x\n",acbdlr_x_reg_max);
32692
32693 dq_lcd_bdl_temp_reg_value=0;
32694 //�ָ�Ĭ��ֵ
32695 dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80)),(uint)acbdlr_x_reg_org);
32696 }
32697 if (test_mode == 2)
32698 {
32699 //�����²⣬�����ϲ⣬���Խ�������ӡ���
32700 printf("test AC%d window finish\n ",test_ACx);
32701 printf("acbdlr_x_reg_min = 0x%08x\n",acbdlr_x_reg_min);
32702 printf("acbdlr_x_reg_max = 0x%08x\n",acbdlr_x_reg_max);
32703 }
32704 }
32705 dwc_ddrphy_apb_wr(0xd0000,1);
32706 return dq_lcd_bdl_temp_reg_value;
32707
32708usage:
32709 cmd_usage(cmdtp);
32710 return 1;
32711
32712 }
32713
32714}
32715
32716U_BOOT_CMD(
32717 ddr_test_acx_g12a, 8, 1, do_ddr_test_acx_g12a,
32718 "ddr_test_acx_g12a a length step direction ACx",
32719 "ddr_test_acx_g12a a 0x8000000 1 0 0 \n"
32720);
32721
32722//ddr_read_write_acx_g12a a rd/wr AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9
32723//ddr_test_acx_g12a a 0 1 0 0x1
32724//argv[0] argv[1] argv[2] argv[3] argv[4] argv[5]
32725//argv[1],a ,no use,reserve,just for flag
32726//argv[2],rd/wr,0=read,1=write
32727//argv[3],AC0
32728//argv[4],AC1
32729//argv[5],AC2;...,9-AC9
32730
32731int do_ddr_read_write_acx_g12a(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
32732{
32733 unsigned int read_write_flag= 0;
32734 //unsigned int temp_test_error= 0;
32735 unsigned int temp_count= 0;
32736 //unsigned int temp_reg_value[40];
32737 uint16_t ACx[10];
32738 char *endp;
32739
32740 printf("Enter ddr_read_write_acx_g12a function\n");
32741 printf("argc== 0x%08x\n", argc);
32742
32743 if (argc <= 2)
32744 {
32745 goto usage;
32746 }
32747 else
32748 {
32749 read_write_flag = simple_strtoull_ddr(argv[2], &endp, 16);
32750 if (*argv[2] == 0 || *endp != 0)
32751 {
32752 read_write_flag = 0;
32753 }
32754 }
32755 if ((argc >12) && (read_write_flag == 1))
32756 {
32757 for (temp_count=0;temp_count < 10;temp_count++)
32758 {
32759 //read AC0-AC9 to ACx[0-9]
32760 ACx[temp_count] = simple_strtoull_ddr(argv[temp_count+3], &endp, 16);
32761 }
32762 }
32763 else
32764 {
32765 read_write_flag = 0;
32766 }
32767
32768 dwc_ddrphy_apb_wr(0xd0000,0);//mw fe1a0000 0
32769 //0xfe000000;
32770 //(((0<<20)|(0<<16)|(test_acbdl<<12)|(0x80))<<1) + 0xfe000000;
32771 {
32772 if (read_write_flag == 0)
32773 {
32774 for (temp_count=0;temp_count < 10;temp_count++)
32775 {
32776 ACx[temp_count]=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(temp_count<<12)|(0x80));
32777 printf("Read: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,ACx[temp_count]);
32778 };
32779 }
32780
32781 if (read_write_flag == 1)
32782 {
32783
32784 for (temp_count=0;temp_count < 10;temp_count++)
32785 {
32786 dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(temp_count<<12)|(0x80)),ACx[temp_count]);
32787 printf("Write: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(temp_count<<12)|(0x80)));
32788 };
32789 }
32790 dwc_ddrphy_apb_wr(0xd0000,1);
32791 return 0;
32792
32793usage:
32794 cmd_usage(cmdtp);
32795 return 1;
32796 }
32797}
32798
32799U_BOOT_CMD(
32800 ddr_read_write_acx_g12a, 18, 1, do_ddr_read_write_acx_g12a,
32801 "ddr_read_write_acx_g12a a rd/wr ac0-ac9",
32802 "ddr_read_write_acx_g12a a 0 3 3 3 \n"
32803);
32804#endif
32805#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
32806#define G12_DATA_READ_OFFSET_MAX (0X3F)
32807#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32)
32808
32809#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
32810#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
32811#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
32812#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
32813#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
32814#define DMC_TEST_WINDOW_INDEX_RXENDLY 6
32815
32816#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
32817#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12
32818#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13
32819
32820uint32_t ddr_cacl_phy_delay_all_step(char test_index,uint32_t value)
32821{
32822 //#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
32823 //#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
32824 //#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
32825 //#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
32826 //#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
32827 uint32_t result=0;
32828 /*
32829 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
32830 result=32*(((value>>6)&1)+((value>>5)&1))+value&0x1f;
32831 }
32832 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
32833 result=32*(((value>>6)&0xf)+((value>>5)&1))+value&0x1f;
32834 }
32835 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
32836 result=32*(((value>>6)&0xf)+((value>>5)&1))+value&0x1f;
32837 }
32838 */
32839#if 0
32840 if ((test_index <= DMC_TEST_WINDOW_INDEX_TXDQDLY) ) {
32841 result=(32*(((value>>6)&0xf)+((value>>5)&1))+(value&0x1f));
32842 }
32843 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
32844 result=(32*(((value>>6)&0xf)+(((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
32845 //result=(32*((((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
32846 }
32847
32848 if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) {
32849 result=(32*(((value>>6)&0x1f)+(((value>>5)&1)*1))+(value&0x1f));
32850 }
32851 if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
32852 result=value&0x3f;
32853 }
32854
32855#else
32856 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
32857 result=(32*(((value>>6)&1)+((value>>5)&1)))+(value&0x1f);
32858 }
32859 //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
32860 else if( (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)||(test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)) {
32861 result=(32*(((value>>6)&7)))+(value&0x3f);
32862 }
32863 else //other register bit5 is effect ,but can not modify coarse delay why ? jiaxing 20180814
32864 result=value&0x3f;
32865#endif
32866 if (test_index >= DMC_TEST_WINDOW_INDEX_EE_VOLTAGE) {
32867 result=value;
32868 }
32869 return result;
32870}
32871
32872uint32_t ddr_cacl_phy_over_ride_back_reg(char test_index,uint32_t value )
32873{
32874 //#define DMC_TEST_WINDOW_INDEX_ATXDLY
32875 //#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
32876 //#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
32877 //#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
32878 //#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
32879 uint32_t result=0;
32880 if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) ) {
32881 if (value<64) {
32882 result=((value/32)<<6)+value%32;
32883 }
32884 else {
32885 result=(3<<5)+(value%32);
32886 }
32887 }
32888 /*
32889 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
32890 result=((value/32)<<6)+value%32;
32891 }
32892 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
32893 result=((value/32)<<6)+value%32;
32894 }
32895 */
32896 else if((test_index==DMC_TEST_WINDOW_INDEX_TXDQDLY)
32897 ||(test_index==DMC_TEST_WINDOW_INDEX_RXCLKDLY)
32898 ||(test_index==DMC_TEST_WINDOW_INDEX_RXENDLY)) {
32899 //result=((value/32)<<6)+value%64;
32900 result=value%64;
32901 if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
32902 result=((value/32)<<6)+value%32;
32903 }
32904 }
32905 else if(test_index==DMC_TEST_WINDOW_INDEX_RXPBDLY) {
32906 result=value&0x3f;
32907 }
32908 else if(test_index==DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
32909#if 1
32910 result=((value/32)<<6)+value%32;
32911 /*
32912 if (enable_bit5)
32913 {
32914 if ((result>>6)&1)
32915 {result=(result&0xffbf)|(1<<5);
32916 }
32917 }
32918 */
32919#else
32920 result=value%64;
32921#endif
32922 }
32923 else if(test_index>DMC_TEST_WINDOW_INDEX_RXPBDLY) {
32924 result=value;
32925 }
32926
32927 return result;
32928}
32929
32930unsigned int do_ddr_g12_read_write_ddr_add_window_lcdlr(unsigned int rank_index,unsigned int add_index,unsigned int lcdlr_value,unsigned int read_write_flag )
32931{
32932 dwc_ddrphy_apb_wr(0xd0000,0);//mw fe1a0000 0
32933 // reg_base_adj=0xfe000000;
32934 // reg_add=(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj;
32935 if (read_write_flag == DDR_PARAMETER_READ)
32936 {
32937
32938 lcdlr_value=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(add_index<<12)|(0x80));
32939 }
32940 if (read_write_flag == DDR_PARAMETER_WRITE)
32941 {
32942
32943 dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(add_index<<12)|(0x80)), lcdlr_value);
32944 }
32945
32946 printf("rank_index %d add_index %d lcdlr== %d \n", rank_index,add_index,lcdlr_value);
32947 return lcdlr_value;
32948}
32949
32950void dwc_window_reg_after_training_update(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_value)
32951{
32952 uint32_t delay_old_value=0;
32953 uint32_t delay_reg_value=0;
32954 uint64_t reg_add=0;
32955 // if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
32956 //p_dev->ddr_global_message.stick_ddr_log_level=0;
32957 //serial_puts("\nstick_test_ddr_window_delay_override_before_after_training_setting==");
32958 //serial_put_dec(p_dev->ddr_global_message.stick_test_ddr_window_delay_override_before_after_training_setting);
32959 //serial_puts("\n");
32960
32961 if (!over_ride_index) {
32962 return;
32963 }
32964 //ddr_dmc_update_delay_register_before();
32965 //char enable_bit5=0;
32966 // if ((p_dev->p_ddrs->DramType == CONFIG_DDR_TYPE_LPDDR4) && (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY))
32967 // {enable_bit5=1;}
32968 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value);
32969 if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
32970 reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80));
32971 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
32972 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
32973 }
32974
32975 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
32976 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
32977 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
32978 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value);
32979 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value);
32980
32981 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
32982 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0));
32983
32984 // {enable_bit5=(delay_old_value>>5)&1;}
32985 //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5);
32986
32987 }
32988 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
32989 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
32990 delay_old_value=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
32991 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
32992 dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value);
32993 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x18c+(over_ride_sub_index/4)),(delay_reg_value|(delay_old_value&0xffc0))-p_dev->ddr_global_message.stick_phy_read_dqs_nibble_offset);
32994 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x90+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)),(delay_reg_value|(delay_old_value&0xffc0)));
32995 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x190+(over_ride_sub_index/4)),(delay_reg_value|(delay_old_value&0xffc0))-p_dev->ddr_global_message.stick_phy_read_dqs_nibble_offset);
32996 }
32997 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
32998 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
32999 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33000 //dwc_ddrphy_apb_wr(((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))),delay_reg_value|(delay_old_value&0xffc0));
33001 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33002 }
33003 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
33004 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33005 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33006 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33007 }
33008
33009 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
33010 reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8)));
33011 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33012 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33013 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x180+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0));
33014 }
33015 if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
33016 // delay_old_value= init_soc_vref(p_dev->cur_type ,(over_ride_value>>8)&0xff, over_ride_value, over_ride_sub_index ,p_dev->ddr_global_message.stick_ddr_log_level);
33017 // set_soc_vref( p_dev->cur_type , (over_ride_value>>8)&0xff, over_ride_value, over_ride_sub_index );
33018 dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value);
33019 }
33020
33021 printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+0xfe000000)),
33022 delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
33023 (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, delay_reg_value));
33024}
33025
33026void dwc_window_reg_after_training_update_increas_sub(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease,
33027 uint32_t step_value)
33028{
33029 uint32_t delay_old_value=0;
33030 uint32_t delay_reg_value=0;
33031
33032 uint64_t reg_add=0;
33033 if (!over_ride_index)
33034 return;
33035 if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
33036
33037 reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80));
33038 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33039 //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value);
33040 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33041 if (over_ride_increase_decrease == 0)
33042 {
33043 delay_reg_value=delay_reg_value+step_value;
33044 if (delay_reg_value>95)
33045 delay_reg_value=95;
33046 }
33047 if (over_ride_increase_decrease == 1)
33048 {
33049 if (delay_reg_value >= step_value)
33050 delay_reg_value=delay_reg_value-step_value;
33051 else
33052 delay_reg_value=0;
33053 }
33054 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33055 dwc_ddrphy_apb_wr((reg_add),delay_reg_value);
33056 }
33057 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
33058 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
33059 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33060 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value);
33061 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value);
33062 if (over_ride_increase_decrease == 0)
33063 // if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value))
33064 {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0));
33065 if (((delay_old_value&0x3f)+step_value)>0x3f)
33066 dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0));
33067 }
33068 else
33069 {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
33070 if (((delay_old_value&0x3f)<step_value))
33071 dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0));
33072 }
33073 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0));
33074
33075 // {enable_bit5=(delay_old_value>>5)&1;}
33076 //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5);
33077 }
33078 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
33079 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33080 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33081 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33082 if (over_ride_increase_decrease == 0)
33083 {
33084 delay_reg_value=delay_reg_value+step_value;
33085 if (delay_reg_value>255)
33086 delay_reg_value=255;
33087 }
33088 if (over_ride_increase_decrease == 1)
33089 {
33090 if (delay_reg_value>step_value)
33091 delay_reg_value=delay_reg_value-step_value;
33092 else
33093 delay_reg_value=0;
33094 }
33095 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33096 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33097 // dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value);
33098
33099 }
33100 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
33101 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
33102 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33103 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33104 if (over_ride_increase_decrease == 0)
33105 {
33106 delay_reg_value=delay_reg_value+step_value;
33107 if (delay_reg_value>95)
33108 delay_reg_value=95;
33109 }
33110 if (over_ride_increase_decrease == 1)
33111 {
33112 if (delay_reg_value>step_value)
33113 delay_reg_value=delay_reg_value-step_value;
33114 else
33115 delay_reg_value=0;
33116 }
33117 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33118 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33119 dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value);
33120
33121 }
33122 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
33123 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33124 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33125 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33126 if (over_ride_increase_decrease == 0)
33127 {
33128 delay_reg_value=delay_reg_value+step_value;
33129 if (delay_reg_value>63)
33130 delay_reg_value=63;
33131 }
33132 if (over_ride_increase_decrease == 1)
33133 {
33134 if (delay_reg_value>step_value)
33135 delay_reg_value=delay_reg_value-step_value;
33136 else
33137 delay_reg_value=0;
33138 }
33139 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33140 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33141 }
33142 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
33143 ///*
33144 reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8)));
33145 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33146 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33147 if (over_ride_increase_decrease == 0)
33148 // if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value))
33149 {
33150 dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0));
33151 if (((delay_old_value&0x3f)+step_value)>0x3f)
33152 dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0));
33153 }
33154 else
33155 {
33156 dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
33157 if (((delay_old_value&0x3f)<step_value))
33158 dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0));
33159 }
33160 // delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33161 // dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
33162 //*/
33163 }
33164
33165 if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
33166 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value);
33167 //reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33168 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40));
33169 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33170 delay_reg_value=delay_old_value;
33171 if (over_ride_increase_decrease == 0)
33172 {
33173 delay_reg_value=delay_reg_value+step_value;
33174 if (delay_reg_value>127)
33175 delay_reg_value=127;
33176 }
33177 if (over_ride_increase_decrease == 1)
33178 {
33179 if (delay_reg_value >= step_value)
33180 delay_reg_value=delay_reg_value-step_value;
33181 else
33182 delay_reg_value=0;
33183 }
33184//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33185 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33186 }
33187 printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+0xfe000000)),
33188 delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
33189 (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
33190
33191}
33192
33193
33194void dwc_window_reg_after_training_update_increas(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease,
33195 uint32_t offset_value)
33196{
33197 uint32_t delay_old_value=0;
33198 //uint32_t delay_reg_value=0;
33199 uint32_t temp_count_3=0;
33200 // uint32_t delay_old_value_cacl=0;
33201 // uint32_t delay_reg_value_cacl=0;
33202 //uint32_t over_ride_value=0;
33203 // if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
33204 //p_dev->ddr_global_message.stick_ddr_log_level=0;
33205 //serial_puts("\nstick_test_ddr_window_delay_override_before_after_training_setting==");
33206 //serial_put_dec(p_dev->ddr_global_message.stick_test_ddr_window_delay_override_before_after_training_setting);
33207 //serial_puts("\n");
33208 uint64_t reg_add=0;
33209 if (!over_ride_index) {
33210 return;
33211 }
33212
33213 //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value);
33214 if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
33215 reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80));
33216 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33217 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33218 {
33219 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33220 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33221 }
33222 }
33223
33224 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
33225 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
33226 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33227 /*
33228 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value);
33229 // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value);
33230 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33231 if (over_ride_increase_decrease == 0)
33232 {
33233 delay_reg_value=delay_reg_value+offset_value;
33234 if (delay_reg_value>96)
33235 delay_reg_value=96;
33236 }
33237 if (over_ride_increase_decrease == 1)
33238 {
33239 if (delay_reg_value >= offset_value)
33240 delay_reg_value=delay_reg_value-offset_value;
33241 else
33242 delay_reg_value=0;
33243 }
33244 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33245 dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
33246 //dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value|(delay_old_value&0xffc0));
33247
33248 // {enable_bit5=(delay_old_value>>5)&1;}
33249 //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5);
33250 */
33251 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33252 {
33253 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33254 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33255 }
33256 }
33257 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
33258 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
33259 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33260 /*
33261 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33262 if (over_ride_increase_decrease == 0)
33263 {
33264 delay_reg_value=delay_reg_value+offset_value;
33265 if (delay_reg_value>96)
33266 delay_reg_value=96;
33267 }
33268 if (over_ride_increase_decrease == 1)
33269 {
33270 if (delay_old_value >= offset_value)
33271 delay_reg_value=delay_reg_value-offset_value;
33272 else
33273 delay_reg_value=0;
33274 }
33275 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33276 dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
33277 dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value|(delay_old_value&0xffc0));
33278 */
33279 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33280 {
33281 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33282 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33283 }
33284
33285 /*
33286 delay_old_value=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8)));
33287 if (over_ride_increase_decrease == 0)
33288 delay_reg_value=delay_old_value+1;
33289 if (over_ride_increase_decrease == 1)
33290 delay_reg_value=delay_old_value-1;
33291 dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0));
33292 dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x190+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0));
33293 */
33294 }
33295 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
33296 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33297 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33298 /*
33299 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33300 if (over_ride_increase_decrease == 0)
33301 {
33302 delay_reg_value=delay_reg_value+offset_value;
33303 if (delay_reg_value>96)
33304 delay_reg_value=96;
33305 }
33306 if (over_ride_increase_decrease == 1)
33307 {
33308 if (delay_reg_value >= offset_value)
33309 delay_reg_value=delay_reg_value-offset_value;
33310 else
33311 delay_reg_value=0;
33312 }
33313 //delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)+1;
33314 //if(over_ride_increase_decrease==1)
33315 //delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)-1;
33316 //dwc_ddrphy_apb_wr(((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))),delay_reg_value|(delay_old_value&0xffc0));
33317delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33318 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33319 */
33320 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33321 {
33322 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33323 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33324 }
33325
33326 }
33327 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
33328 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33329 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33330 /*
33331 delay_reg_value=delay_old_value;
33332 if (over_ride_increase_decrease == 0)
33333 {
33334 delay_reg_value=delay_reg_value+offset_value;
33335 if (delay_reg_value>96)
33336 delay_reg_value=96;
33337 }
33338 if (over_ride_increase_decrease == 1)
33339 {
33340 if (delay_reg_value >= offset_value)
33341 delay_reg_value=delay_reg_value-offset_value;
33342 else
33343 delay_reg_value=0;
33344 }
33345delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33346 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33347 */
33348 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33349 {
33350 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33351 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33352 }
33353 }
33354
33355 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
33356
33357 reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8)));
33358 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33359 /*
33360 delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
33361 if (over_ride_increase_decrease == 0)
33362 {
33363 delay_reg_value=delay_reg_value+offset_value;
33364 if (delay_reg_value>96)
33365 delay_reg_value=96;
33366 }
33367 if (over_ride_increase_decrease == 1)
33368 {
33369 if (delay_reg_value >= offset_value)
33370 delay_reg_value=delay_reg_value-offset_value;
33371 else
33372 delay_reg_value=0;
33373 }
33374 delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33375 dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
33376 */
33377 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33378 {
33379 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33380 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33381 }
33382 }
33383
33384
33385if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
33386
33387 //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value);
33388 //reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
33389 reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40));
33390 delay_old_value=dwc_ddrphy_apb_rd(reg_add);
33391 /*
33392 delay_reg_value=delay_old_value;
33393 if (over_ride_increase_decrease == 0)
33394 {
33395 delay_reg_value=delay_reg_value+offset_value;
33396 if (delay_reg_value>127)
33397 delay_reg_value=127;
33398 }
33399 if (over_ride_increase_decrease == 1)
33400 {
33401 if (delay_reg_value >= offset_value)
33402 delay_reg_value=delay_reg_value-offset_value;
33403 else
33404 delay_reg_value=0;
33405 }
33406//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
33407 dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
33408*/
33409 for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
33410 {
33411 dwc_window_reg_after_training_update_increas_sub(over_ride_index
33412 ,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
33413 }
33414 }
33415
33416printf("over_ride_increase_decrease==%d\n",over_ride_increase_decrease);
33417
33418if (over_ride_increase_decrease == 1)
33419{
33420unsigned int org_cacl_value=(delay_old_value)&0x3f;
33421printf("org_cacl_value==%d\n",org_cacl_value);
33422printf("offset_value==%d\n",offset_value);
33423 if ((org_cacl_value&0x3f)<offset_value) {
33424
33425 char temp_test_index_2=0;
33426 char temp_count_4=0;
33427 char temp_count_2=0;
33428 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
33429 {
33430 temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQDLY;
33431 if (over_ride_sub_index%2 == 0) {
33432 for (temp_count_2=0;temp_count_2<9;temp_count_2++)
33433 {for(temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++)
33434{
33435 dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
33436 ,((over_ride_sub_index>>1)*9+temp_count_2), 0,1) ;
33437 }
33438 }
33439 }
33440/*
33441 temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQSDLY;
33442 dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
33443 ,((over_ride_index%2)?
33444 (over_ride_index-1):
33445 (over_ride_index+1)), 0) ;
33446 }
33447*/
33448 }
33449if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
33450{
33451 temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY;
33452
33453for ( temp_count_2=0;temp_count_2<4;temp_count_2++)
33454 for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*ui_1_32_100step)/bdlr_100step);temp_count_4++)
33455 {
33456{
33457 dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
33458 ,((over_ride_sub_index/2)*9+
33459 temp_count_2+(over_ride_sub_index%2)*4), 0,1) ;
33460
33461 }
33462 }
33463}
33464
33465 if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
33466 {
33467 temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY;
33468
33469 for ( temp_count_2=0;temp_count_2<4;temp_count_2++)
33470 {
33471 if (temp_count_2 == ((over_ride_sub_index%9)%4))
33472 temp_count_2++;
33473for (temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++)
33474 dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
33475 ,((over_ride_sub_index/9)*9+
33476 temp_count_2+(((over_ride_sub_index%9)>3)?4:0)), 0,1) ;
33477
33478 }
33479 //bdlr_100step (org_cacl_value<offset_value)
33480 if ((((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step))
33481 {
33482 temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXCLKDLY;
33483 for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step);temp_count_4++)
33484 dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
33485 ,(((over_ride_sub_index/9)<<1)+
33486 (((over_ride_sub_index%9)>3)?1:0)
33487 ), 0,1) ;
33488 }
33489 }
33490 }
33491}
33492 printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+0xfe000000)),
33493 delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
33494 ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
33495 //ddr_log_serial_puts(" ",0);
33496 //ddr_log_serial_put_hex(delay_reg_value,16,0);
33497 //ddr_log_serial_puts(" ",0);
33498 // ddr_dmc_update_delay_register_after();
33499}
33500
33501int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
33502{
33503#define DMC_WINDOW_CMD 20180010 //g12_d2pll 1584 0 0 0 0 0x8
33504 //g12_d2pll 1600 5 0 0x10 1
33505 //g12_d2pll 1600 0 0 0 0 0x10 0 1
33506 //g12_d2pll 1400 0 0 0 0 0 0 0 0 1 1200 1900 test ddr frequency
33507 //g12_d2pll 1400 0 0 0 0 0 0 0 0 3 1200 1900 test ddr frequency with EE voltage
33508 //g12_d2pll 1600 0 0 0 0 0 0 0 1 //full test
33509 //g12_d2pll 1600 0 0 0 0 0 0 0 1 0 0 0 872 //full test with 872mv EE
33510 //g12_d2pll 1600 0 0 0 0 0x10 0 3 //only test spec sub_index delay window
33511 //g12_d2pll 1600 cmd_index cmd_para1 cmd_para2....
33512 //g12_d2pll 1600 0x1 override_option_ac_data_delay_vref override_index over_ride_value
33513 //g12_d2pll 1600 0x2 override plus fulltest
33514 //g12_d2pll 1600 0x3 override plus...other function
33515 //g12_d2pll 1600 0x11 window_test
33516 //g12_d2pll 1600 0x21 frequency table test
33517 //g12_d2pll 1600 0x31 sweep_ee_voltage_frequency table test
33518
33519
33520 //g12_d2pll 1800 1 //dmc fulltest
33521 //g12_d2pll 1800 2 1 1 1 03 2 2 142 0x11 0 950 override after_training_flag override_index sub_index value override_index2 sub_index2 value2 override_index3 sub_index3 value3
33522 //override 1 2 3 4 5 0x11
33523 //g12_d2pll 1800 2 1 0x12 0x1 0x0f6 override_soc_vref pin_index (vref_range<<8)|(vref_value)
33524
33525 //g12_d2pll 1800 4 4/5/a //override_training_hdtl_ctl value
33526
33527 //g12_d2pll 1800 0x21 //dmc suspend test
33528 //g12_d2pll 1800 0x11 0x1f 0 0 0 10 0x20 //dmc window test mask1 mask2 mask3 sub_index read_bit_init_value(use for very high speed)
33529 //g12_d2pll 1800 0x32 1300 1500 790 820 //dmc sweep freq and ee voltage test frequency_min frequency_max ee_voltage_min ee_voltage_max
33530 //g12_d2pll 1800 0x41 2 0 0xfe 0 0 1 0x01 0 0 1 2 0x100000 //dmc eye_test_enable init_range_0 range0 _value vref_start vref_end
33531 //init_range_2 range2_value vref_start2 vref_end2 pin_index_min pin_index_max test_size
33532
33533
33534#define G12_D2PLL_CMD_DMC_FULL_TEST 0x01
33535#define G12_D2PLL_CMD_OVER_RIDE 0x02
33536#define G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST 0x03
33537#define G12_D2PLL_CMD_OVER_RIDE_TRAINING_HDTL 0x04
33538#define G12_D2PLL_CMD_WINDOW_TEST 0x11
33539#define G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE 0x12
33540#define G12_D2PLL_CMD_SUSPEND_TEST 0x21
33541 //#define G12_D2PLL_CMD_FREQUENCY_TABLE_TEST 0x31
33542#define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST 0x32
33543#define G12_D2PLL_CMD_DDR_EYE_TEST 0x41
33544#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE 0x42
33545
33546
33547#define G12_D2PLL_CMD_DDR_DVFS_TEST 0x51
33548
33549 //OVERRIDE_OPTION
33550#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
33551#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
33552#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
33553#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
33554#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
33555
33556#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
33557
33558 char *endp;
33559 unsigned int pll;
33560 unsigned int window_test_stick_cmd_value=0;
33561#if 0
33562 unsigned int stick_test_cmd_index=0; // 1 override_cmd 2
33563 unsigned int stick_test_ddr_window_delay_override_enable=0; // bit 0 ac 1 data dqs write 2 data dqs read 3 data bit write 4 data bit read 5//data write vref 6 //data read vref
33564 unsigned int stick_test_ddr_window_delay_override_index=0;
33565 unsigned int stick_test_ddr_window_delay_override_value=0;
33566 unsigned int stick_test_ddr_window_delay_override_before_after_training_setting=0; //0 before ,1 after training
33567 unsigned int stick_dmc_ddr_window_test_enable=0;
33568 unsigned int stick_dmc_ddr_window_test_enable_mask=0;
33569 unsigned int stick_dmc_ddr_window_test_enable_spec_sub_index=0;
33570 unsigned int stick_dmc_ddr_window_test_dmc_full_test_enable=0;
33571 unsigned int stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable=0;
33572
33573 unsigned int stick_dmc_ddr_bl2_sweep_frequency_min=0;
33574 unsigned int stick_dmc_ddr_bl2_sweep_frequency_max=0;
33575 unsigned int stick_dmc_ddr_bl2_ee_voltage=0;
33576#endif
33577 //if(window_test_stick_value)
33578 {
33579 //stick_test_ddr_window_delay_override_enable=((window_test_stick_value>>24)&0xf);//bit 0 ac bit1 write dq bit 2 read dq
33580 //stick_test_ddr_window_delay_override_index=((window_test_stick_value>>16)&0xff);
33581 //stick_test_ddr_window_delay_override_value=(window_test_stick_value&0xff);
33582 }
33583 /* need at least two arguments */
33584 if (argc < 2)
33585 goto usage;
33586
33587 pll = simple_strtoul(argv[1], &endp,0);
33588 if (*argv[1] == 0 || *endp != 0) {
33589 printf ("Error: Wrong format parament!pll=0x%08x\n",pll);
33590 return 1;
33591 }
33592 unsigned int argc_count=1;
33593 unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
33594 while (argc_count<argc)
33595 {para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
33596 if (*argv[argc_count] == 0 || *endp != 0) {
33597 para_meter[argc_count-1] = 0;
33598 }
33599 argc_count++;
33600 }
33601
33602 //if(stick_test_cmd_index==)
33603#if 0
33604 if (argc >4)
33605 {
33606 stick_test_ddr_window_delay_override_enable=0;
33607 stick_test_ddr_window_delay_override_enable = simple_strtoul(argv[2], &endp, 0);
33608 if (*argv[2] == 0 || *endp != 0) {
33609 stick_test_ddr_window_delay_override_enable = 0;
33610 }
33611 stick_test_ddr_window_delay_override_index = simple_strtoul(argv[3], &endp, 0);
33612 if (*argv[3] == 0 || *endp != 0) {
33613 stick_test_ddr_window_delay_override_index = 0;
33614 }
33615 stick_test_ddr_window_delay_override_value = simple_strtoul(argv[4], &endp, 0);
33616 if (*argv[4] == 0 || *endp != 0) {
33617 stick_test_ddr_window_delay_override_value = 0;
33618 }
33619 }
33620 else
33621 { stick_test_ddr_window_delay_override_enable=0;
33622 stick_test_ddr_window_delay_override_index = 0;
33623 stick_test_ddr_window_delay_override_value = 0;
33624 }
33625
33626 if (argc >5)
33627 {
33628 stick_test_ddr_window_delay_override_before_after_training_setting = simple_strtoul(argv[5], &endp, 0);
33629 if (*argv[5] == 0 || *endp != 0) {
33630 stick_test_ddr_window_delay_override_before_after_training_setting = 0;
33631 }
33632 }
33633 if (argc >6)
33634 {
33635 stick_dmc_ddr_window_test_enable = simple_strtoul(argv[6], &endp, 0);
33636 if (*argv[6] == 0 || *endp != 0) {
33637 stick_dmc_ddr_window_test_enable = 0;
33638 }
33639 }
33640 if (argc >7)
33641 {
33642 stick_dmc_ddr_window_test_enable_mask = simple_strtoul(argv[7], &endp, 0);
33643 if (*argv[7] == 0 || *endp != 0) {
33644 stick_dmc_ddr_window_test_enable_mask = 0;
33645 }
33646 }
33647 if (argc >8)
33648 {
33649 stick_dmc_ddr_window_test_enable_spec_sub_index = simple_strtoul(argv[8], &endp, 0);
33650 if (*argv[8] == 0 || *endp != 0) {
33651 stick_dmc_ddr_window_test_enable_spec_sub_index = 0;
33652 }
33653 }
33654 if (argc >9)
33655 {
33656 stick_dmc_ddr_window_test_dmc_full_test_enable = simple_strtoul(argv[9], &endp, 0);
33657 if (*argv[9] == 0 || *endp != 0) {
33658 stick_dmc_ddr_window_test_dmc_full_test_enable = 0;
33659 }
33660 }
33661 if (argc >10)
33662 {
33663 stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable = simple_strtoul(argv[10], &endp, 0);
33664 if (*argv[10] == 0 || *endp != 0) {
33665 stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable = 0;
33666 }
33667 }
33668 if (argc >11)
33669 {
33670 stick_dmc_ddr_bl2_sweep_frequency_min = simple_strtoul(argv[11], &endp, 0);
33671 if (*argv[11] == 0 || *endp != 0) {
33672 stick_dmc_ddr_bl2_sweep_frequency_min = 0;
33673 }
33674 }
33675 if (argc >12)
33676 {
33677 stick_dmc_ddr_bl2_sweep_frequency_max = simple_strtoul(argv[12], &endp, 0);
33678 if (*argv[12] == 0 || *endp != 0) {
33679 stick_dmc_ddr_bl2_sweep_frequency_max = 0;
33680 }
33681 }
33682 if (argc >13)
33683 {
33684 stick_dmc_ddr_bl2_ee_voltage = simple_strtoul(argv[13], &endp, 0);
33685 if (*argv[13] == 0 || *endp != 0) {
33686 stick_dmc_ddr_bl2_ee_voltage = 0;
33687 }
33688 }
33689
33690
33691#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
33692 wr_reg( PREG_STICKY_REG0,0 | (0x3c << 24));
33693#else
33694 wr_reg(PREG_STICKY_REG0,0 | (0xf13 << 20));
33695#endif
33696
33697 if (stick_dmc_ddr_window_test_enable)
33698 {
33699 wr_reg(PREG_STICKY_REG0,((stick_dmc_ddr_window_test_enable_spec_sub_index&0xff)<<8)|(stick_dmc_ddr_window_test_enable&0xff) | (0xf12<< 20));
33700 }
33701 //wr_reg(PREG_STICKY_REG1,pll | (rd_reg(PREG_STICKY_REG1)));
33702 wr_reg(PREG_STICKY_REG1,pll );
33703 wr_reg(PREG_STICKY_REG2,(stick_test_ddr_window_delay_override_value&0xffff) |((stick_test_ddr_window_delay_override_index&0xff)<<16)
33704 |((stick_test_ddr_window_delay_override_enable&0x7)<<29)
33705 |((stick_test_ddr_window_delay_override_before_after_training_setting&0x1)<<28));
33706 if (stick_dmc_ddr_window_test_enable_mask)
33707 {
33708 wr_reg(PREG_STICKY_REG3,(stick_dmc_ddr_window_test_enable_mask));
33709 }
33710 // if(stick_dmc_ddr_window_test_dmc_full_test_enable)
33711 {
33712 wr_reg(PREG_STICKY_REG4,(stick_dmc_ddr_window_test_dmc_full_test_enable<<31)|(stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable<<29));
33713 }
33714 if (stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable)
33715 {
33716 wr_reg(PREG_STICKY_REG5,(stick_dmc_ddr_bl2_sweep_frequency_min<<0)|(stick_dmc_ddr_bl2_sweep_frequency_max<<16));
33717 }
33718 if (stick_dmc_ddr_bl2_ee_voltage)
33719 {
33720 wr_reg(PREG_STICKY_REG6,(stick_dmc_ddr_bl2_ee_voltage<<0));
33721 }
33722#endif
33723 argc_count=2;
33724 window_test_stick_cmd_value=para_meter[argc_count-1];
33725 if ((window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE) || (window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST))
33726 {
33727 para_meter[3]=(para_meter[3]<<24)|(para_meter[4]<<16)|(para_meter[5]<<0);
33728 para_meter[4]=(para_meter[6]<<24)|(para_meter[7]<<16)|(para_meter[8]<<0);
33729 para_meter[5]=(para_meter[9]<<24)|(para_meter[10]<<16)|(para_meter[11]<<0);
33730
33731 }
33732 if ((window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE))
33733 {
33734 //para_meter[8] size 9 stick_dmc_ddr_window_test_no_use_dqs_dq_correction 10 disable_scramble_use_define_pattern 11 stick_dmc_window_test_loop_flag window loop test
33735 //12 if reinit when test dq
33736 para_meter[5]=(para_meter[9]<<28)|(para_meter[10]<<24)|(para_meter[11]<<20)|(para_meter[12]<<21)|(para_meter[5]<<0);
33737
33738 }
33739 if ((window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE))
33740 {
33741
33742 para_meter[3]=(para_meter[3]<<0)|(para_meter[4]<<8)|(para_meter[5]<<16)|(para_meter[6]<<24);
33743 para_meter[4]=(para_meter[7]<<0)|(para_meter[8]<<8)|(para_meter[9]<<16)|(para_meter[10]<<24);
33744 para_meter[5]=para_meter[11];//(para_meter[11]<<0)|(para_meter[12]<<8)|(para_meter[13]<<16)|(para_meter[14]<<24);
33745 para_meter[6]=para_meter[12];//para_meter[15];
33746 para_meter[7]=para_meter[13];//para_meter[16];
33747 para_meter[8]=para_meter[14];//para_meter[17];
33748 }
33749 wr_reg(PREG_STICKY_REG0,(rd_reg(PREG_STICKY_REG0)&0xffff) | (0xf13 << 20));
33750 argc_count=0;
33751 printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,(PREG_STICKY_REG0+(argc_count<<2)),rd_reg(PREG_STICKY_REG0+(argc_count<<2)));
33752 argc_count=1;
33753 //while(argc_count<argc)
33754 while (argc_count<10)
33755 {
33756 wr_reg(PREG_STICKY_REG0+(argc_count<<2),para_meter[argc_count-1]);
33757 printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,(PREG_STICKY_REG0+(argc_count<<2)),rd_reg(PREG_STICKY_REG0+(argc_count<<2)));
33758 argc_count++;
33759 }
33760 /*
33761 printf("P_PREG_STICKY_REG0 [0x%08x]\n", rd_reg(PREG_STICKY_REG0));
33762 printf("P_PREG_STICKY_REG1 [0x%08x]\n", rd_reg(PREG_STICKY_REG1));
33763 printf("P_PREG_STICKY_REG2 [0x%08x]\n", rd_reg(PREG_STICKY_REG2));
33764 printf("P_PREG_STICKY_REG3 [0x%08x]\n", rd_reg(PREG_STICKY_REG3));
33765 printf("P_PREG_STICKY_REG4 [0x%08x]\n", rd_reg(PREG_STICKY_REG4));
33766 printf("P_PREG_STICKY_REG5 [0x%08x]\n", rd_reg(PREG_STICKY_REG5));
33767 printf("P_PREG_STICKY_REG6 [0x%08x]\n", rd_reg(PREG_STICKY_REG6));
33768 */
33769 printf("reset...\n");
33770
33771 ddr_test_watchdog_reset_system();
33772
33773
33774 return 0;
33775
33776usage:
33777 cmd_usage(cmdtp);
33778 return 1;
33779}
33780
33781
33782U_BOOT_CMD(
33783 g12_d2pll, 18, 1, do_ddr2pll_g12_cmd,
33784 "g12_d2pll 1300 1 0x10 0",
33785 "g12_d2pll clk delay_index delay_value before_after_training_setting\n"
33786);
33787
33788int do_ddr_g12_uboot_dmc_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
33789{
33790 return 1;
33791
33792 /*
33793 // if(!argc)
33794 // goto DDR_TUNE_DQS_START;
33795 int i=0;
33796 printf("\nargc== 0x%08x\n", argc);
33797 for (i = 0;i<argc;i++)
33798 {
33799 printf("\nargv[%d]=%s\n",i,argv[i]);
33800 }
33801
33802 if (argc < 2)
33803 goto usage;
33804
33805
33806 unsigned int argc_count=1;
33807 unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
33808 while (argc_count<argc)
33809 {para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
33810 if (*argv[argc_count] == 0 || *endp != 0) {
33811 para_meter[argc_count-1] = 0;
33812 }
33813 argc_count++;
33814 }
33815
33816 uint32_t dmc_test_start_add=para_meter[0];
33817 uint32_t dmc_test_start_end=para_meter[1];
33818 uint32_t test_write_loops=para_meter[2];
33819 uint32_t test_read_loops=para_meter[3];
33820#define DMC_TEST_START_ADD_DEFAULT 1<<20
33821#define DMC_TEST_END_ADD_DEFAULT 512<<20
33822#define DMC_TEST_WRITE_LOOP_DEFAULT 1
33823#define DMC_TEST_READ_LOOP_DEFAULT 1
33824dmc_test_start_add=dmc_test_start_add?dmc_test_start_add:DMC_TEST_START_ADD_DEFAULT;
33825dmc_test_start_end=dmc_test_start_end?dmc_test_start_end:DMC_TEST_END_ADD_DEFAULT;
33826test_write_loops=test_write_loops?test_write_loops:DMC_TEST_WRITE_LOOP_DEFAULT;
33827test_read_loops=test_read_loops?test_read_loops:DMC_TEST_READ_LOOP_DEFAULT;
33828
33829while ((test_write_loops) || (test_read_loops))
33830{
33831
33832if (test_write_loops)
33833ddr_bist_test_error=dmc_ddr_test(dram_base,1,0,0,test_size,1,0)+ddr_bist_test_error;
33834
33835
33836_udelay(test_delay_time_ms*1000);
33837
33838
33839
33840
33841#ifdef CFG_ENABLE_DDR_DMC_TEST
33842if (test_read_loops)
33843ddr_bist_test_error=dmc_ddr_test(dram_base,0,1,1,test_size,1,0)+ddr_bist_test_error;
33844serial_puts("\ndmc full test result==");
33845serial_put_dec(ddr_bist_test_error);
33846serial_puts("\n");
33847#endif
33848if (test_write_loops)
33849test_write_loops--;
33850if (test_read_loops)
33851test_read_loops--;
33852}
33853
33854{
33855
33856uint16_t dq_bit_delay[72];
33857unsigned char t_count=0;
33858uint16_t delay_org=0;
33859uint16_t delay_temp=0;
33860uint32_t add_offset=0;
33861dwc_ddrphy_apb_wr(0xd0000,0x0);
33862
33863 {printf("\n write dq_bit delay * 1/32UI");
33864 for (t_count=0;t_count<72;t_count++)
33865 {
33866 add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
33867 dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
33868 delay_org=dq_bit_delay[t_count];
33869 delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
33870 printf("\n t_count: %d %d",t_count,delay_temp);
33871 }
33872 }
33873
33874}
33875
33876
33877
33878
33879
33880
33881
33882return 1;
33883*/
33884
33885}
33886#endif
33887
33888#if 0
33889int do_ddr_uboot_window_g12a_use_source_test_add_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
33890{
33891 printf("\nsetenv bootcmd ddr_test_cmd 0x36 4 6 60 0 0x100000 0x4000000 0 0x100010 0\n");
33892 printf("\nEnter do_ddr_uboot_window_use_source function\n");
33893 printf("\n--- watchdog should >15s\n");
33894
33895#define DDR_TEST_NULL 0
33896#define DDR_TEST_PASS 1
33897#define DDR_TEST_FAIL 2
33898
33899
33900#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
33901#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
33902 //PREG_STICKY_REG4
33903 //PREG_STICKY_REG5
33904
33905#define DDR_TEST_STATUS_UBOOT_ONGOING 1
33906#define DDR_TEST_STATUS_UBOOT_FINISH 2
33907#define DDR_TEST_STATUS_KERNEL_ONGING 3
33908#define DDR_TEST_STATUS_KERNEL_FINISH 4
33909 //#define DDR_TEST_FAIL 2
33910
33911
33912 char *endp;
33913 unsigned int lane_disable= 0;
33914 unsigned int data_source= 0;
33915 unsigned int ddr_data_test_size=0x1000000;
33916 unsigned int ddr_add_test_size=0x10000000;
33917 unsigned int ddr_test_size=0x10000000;
33918
33919 unsigned int ddr_test_clear_flag=0;
33920 unsigned int ddr_test_init_offset=0;
33921 unsigned int ddr_test_uboot_kernel_enable_mask=0;
33922
33923 unsigned int ddr_test_uboot_loop=0;
33924
33925 unsigned int kernel_test_watchdog_time_s=60;
33926 unsigned int test_watchdog_time_s=15;
33927
33928 //uint32_t stick_test_ddr_window_delay_override_enable=0;
33929 uint32_t stick_test_ddr_window_delay_override_index=0;
33930 uint32_t stick_test_ddr_window_delay_override_value=0;
33931
33932 char str[1024]="";
33933
33934 error_outof_count_flag =1; //for quick out of error
33935 if (argc >1) {
33936 data_source = simple_strtoull_ddr(argv[1], &endp, 0);
33937 if (*argv[1] == 0 || *endp != 0)
33938 {
33939 data_source= DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV;
33940 }
33941 }
33942 if (argc >2) {
33943 watchdog_time_s = simple_strtoull_ddr(argv[2], &endp, 0);
33944 if (*argv[2] == 0 || *endp != 0)
33945 {
33946 watchdog_time_s= 15;
33947 }
33948 }
33949 printf("watchdog_time_s==%d\n",watchdog_time_s);
33950 test_watchdog_time_s=watchdog_time_s;
33951 //test_watchdog_time_s=address_test_watchdog_time_s;
33952 if (argc >3) {
33953 kernel_test_watchdog_time_s = simple_strtoull_ddr(argv[3], &endp, 0);
33954 if (*argv[3] == 0 || *endp != 0)
33955 {
33956 kernel_test_watchdog_time_s= watchdog_time_s;
33957 }
33958 }
33959 printf("kernel_test_watchdog_time_s==%d\n",kernel_test_watchdog_time_s);
33960 //lane_disable=g_ddr_test_struct->ddr_test_lane_disable;
33961 if (argc >4) {
33962 lane_disable = simple_strtoull_ddr(argv[4], &endp, 0);
33963 if (*argv[4] == 0 || *endp != 0)
33964 {
33965 lane_disable= 0;
33966 }
33967 }
33968 printf("lane_disable==0x%08x\n",lane_disable);
33969
33970 if (argc >5) {
33971 ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
33972 if (*argv[5] == 0 || *endp != 0)
33973 {
33974 ddr_data_test_size= 0x100000;
33975 }
33976 }
33977 printf("ddr_data_test_size==0x%08x\n",ddr_data_test_size);
33978 if (argc >6) {
33979 ddr_add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
33980 if (*argv[6] == 0 || *endp != 0)
33981 {
33982 ddr_add_test_size= 0x10000000;
33983 }
33984 }
33985 printf("ddr_add_test_size==0x%08x\n",ddr_add_test_size);
33986
33987 if (argc >7) {
33988 ddr_test_clear_flag = simple_strtoull_ddr(argv[7], &endp, 0);
33989 if (*argv[7] == 0 || *endp != 0)
33990 {
33991 ddr_test_clear_flag= 0x10000000;
33992 }
33993 }
33994 printf("ddr_test_clear_flag==0x%08x\n",ddr_test_clear_flag);
33995
33996 if (argc >8) {
33997 ddr_test_init_offset = simple_strtoull_ddr(argv[8], &endp, 0);
33998 if (*argv[8] == 0 || *endp != 0)
33999 {
34000 ddr_test_init_offset= 0;
34001 }
34002 }
34003 printf("ddr_test_init_offset==0x%08x\n",ddr_test_init_offset);
34004
34005 if (argc >9) {
34006 ddr_test_uboot_kernel_enable_mask = simple_strtoull_ddr(argv[9], &endp, 0);
34007 if (*argv[9] == 0 || *endp != 0)
34008 {
34009 ddr_test_uboot_kernel_enable_mask= 0;
34010 }
34011 }
34012 printf("ddr_test_uboot_kernel_enable_mask==0x%08x\n",ddr_test_uboot_kernel_enable_mask);
34013
34014 if (argc >10) {
34015 ddr_test_uboot_loop = simple_strtoull_ddr(argv[10], &endp, 0);
34016 if (*argv[10] == 0 || *endp != 0)
34017 {
34018 ddr_test_uboot_loop= 0;
34019 }
34020 }
34021 printf("ddr_test_uboot_loop==0x%08x\n",ddr_test_uboot_loop);
34022
34023 if (argc >11) {
34024 stick_test_ddr_window_delay_override_index = simple_strtoull_ddr(argv[11], &endp, 0);
34025 if (*argv[11] == 0 || *endp != 0)
34026 {
34027 stick_test_ddr_window_delay_override_index= 0;
34028 }
34029 }
34030 printf("stick_test_ddr_window_delay_override_index==0x%08x\n",stick_test_ddr_window_delay_override_index);
34031
34032
34033 unsigned int rank_index=0;
34034 unsigned int temp_count=0;
34035 unsigned int ddr_test_data_array_max=10;
34036 unsigned int num_array[10];//8 flag 32_data add_8 32_data add_8
34037
34038 unsigned int temp_test_error=0;
34039 //unsigned int lcdlr_min=0;
34040 //unsigned int lcdlr_max=0;
34041 memset(num_array, 0, sizeof(num_array));
34042 //char str[1024]="";
34043
34044
34045 ddr_test_data_array_max=8;
34046
34047 for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
34048 {
34049 num_array[temp_count]= read_write_window_test_parameter(data_source,
34050 temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
34051 printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
34052 }
34053
34054 unsigned int reg_def_value_data[4]; //write_lcdlr_value+read_lcdlr_value<<16;
34055
34056 //#define DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET 4 // PREG_STICKY_REG4
34057 //#define DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET 5 //45// PREG_STICKY_REG4
34058
34059 unsigned int test_arg_4_step_flag_add_sticky_offset =0; //use for kernel
34060 unsigned int test_arg_5_pass_fail_flag_add_sticky_offset =0; //use for kernel
34061
34062 unsigned int test_arg_6_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
34063 unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
34064 unsigned int test_arg_7_lcdlr_offset_l =0; //left_lcdlr
34065 unsigned int test_arg_7_lcdlr_offset_r=0; //right_lcdlr
34066 unsigned int delay_step_x100= 0;
34067
34068 //unsigned int test_arg_6_lcdlr_temp_count =0;
34069 unsigned int test_lcdlr_temp_value1 =0;
34070 //unsigned int test_lcdlr_temp_value2 =0;
34071 unsigned int test_lcdlr_temp_value =0;
34072 unsigned int test_lcdlr_reach_lcdlr_limited_flag =0;
34073
34074
34075 test_lcdlr_reach_lcdlr_limited_flag=0;
34076 reg_def_value_data[0]=num_array[0];
34077 reg_def_value_data[1]=num_array[1];
34078 reg_def_value_data[2]=num_array[2];
34079 reg_def_value_data[3]=num_array[3];
34080 test_arg_4_step_flag_add_sticky_offset=num_array[4];
34081 test_arg_5_pass_fail_flag_add_sticky_offset=num_array[5];
34082 test_arg_6_step_status=num_array[6];
34083 test_arg_7_lcdlr_offset=num_array[7];
34084
34085
34086
34087 printf("reg_def_value_data[0]==0x%08x\n",num_array[0]);
34088 printf("reg_def_value_data[1]==0x%08x\n",num_array[1]);
34089 printf("reg_def_value_data[2]==0x%08x\n",num_array[2]);
34090 printf("reg_def_value_data[3]==0x%08x\n",num_array[3]);
34091 printf("test_arg_4_step_flag_add_sticky_offset=%d\n",num_array[4]);
34092 printf("test_arg_5_pass_fail_flag_add_sticky_offset=%d\n",num_array[5]);
34093 printf("test_arg_6_step_status=%d\n",num_array[6]);
34094 printf("\ntest_arg_7_lcdlr_offset=0x%08x\n",num_array[7]);
34095
34096
34097
34098
34099 //for (temp_count= 0;temp_count < 8; temp_count++)
34100 // {
34101 // read_write_window_test_parameter(data_source,
34102 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34103 //}
34104
34105
34106 if (ddr_test_clear_flag)
34107 { test_arg_6_step_status=0;
34108 num_array[6] = test_arg_6_step_status ;
34109 temp_count=6;
34110 read_write_window_test_parameter(data_source,
34111 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34112 printf("\n clear sticky register should reset,then over write ....\n");
34113 run_command("reset",0);
34114 while (1) ;
34115 }
34116
34117 if (test_arg_6_step_status == 0)
34118 {
34119 {
34120
34121 //test_arg_6_step_status=1;
34122
34123
34124 //for (temp_count = 0; temp_count < (8); temp_count++) //data
34125
34126 {
34127 temp_count=stick_test_ddr_window_delay_override_index;
34128 test_lcdlr_temp_value1=do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,temp_count,test_lcdlr_temp_value1,DDR_PARAMETER_READ);
34129 //reg_def_value_data[3]=test_lcdlr_temp_value1;
34130 reg_def_value_data[3]=test_lcdlr_temp_value1;
34131 num_array[3] = reg_def_value_data[3] ;
34132 printf("num_array[%d]=%08x\n",3,num_array[3]);
34133 }
34134
34135 }
34136 test_arg_4_step_flag_add_sticky_offset=0;
34137 test_arg_5_pass_fail_flag_add_sticky_offset=0;
34138 test_arg_6_step_status=0;
34139 test_arg_7_lcdlr_offset=0;
34140 if (ddr_test_init_offset)
34141 {test_arg_7_lcdlr_offset=ddr_test_init_offset;
34142 }
34143 //num_array[0] = reg_def_value_data[0] ;
34144 //num_array[1] = reg_def_value_data[1] ;
34145 //num_array[2] = reg_def_value_data[2] ;
34146 num_array[3] = reg_def_value_data[3] ;
34147 num_array[4] = test_arg_4_step_flag_add_sticky_offset ; //use for kernel
34148 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;//use for kernel
34149 num_array[6] = test_arg_6_step_status ;
34150 num_array[7] = test_arg_7_lcdlr_offset ;
34151
34152
34153
34154 for (temp_count= 0;temp_count < 8; temp_count++)
34155 {
34156 read_write_window_test_parameter(data_source,
34157 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34158 }
34159
34160
34161 }
34162 else
34163 {
34164 //for (temp_count = 0; temp_count < (8); temp_count++) //data
34165 {
34166 //temp_count=4;
34167 //test_lcdlr_temp_value1=do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,temp_count,test_lcdlr_temp_value1,DDR_PARAMETER_READ);
34168 //temp_count=temp_count+1;
34169 //temp_count=5;
34170 //test_lcdlr_temp_value2=do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,(temp_count),test_lcdlr_temp_value2,DDR_PARAMETER_READ);
34171 //reg_def_value_data[3]=test_lcdlr_temp_value1|(test_lcdlr_temp_value2<<16);
34172 //num_array[3]=reg_def_value_data[3];
34173 printf("re-num_array[%d]=%08x\n",3,num_array[3]);
34174 }
34175 }
34176
34177 if (ddr_test_uboot_kernel_enable_mask&1)
34178 {printf("skip uboot test should init kernel offset value==0x%08x\n",num_array[7]);
34179 }
34180
34181 test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
34182 test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
34183 unsigned int lane_step_count=0;
34184 {
34185
34186 {
34187 test_watchdog_time_s=watchdog_time_s;
34188 ddr_test_size=ddr_data_test_size;
34189
34190 }
34191
34192 printf("reg_def_value_data[0]==0x%08x\n",num_array[0]);
34193 printf("reg_def_value_data[1]==0x%08x\n",num_array[1]);
34194 printf("reg_def_value_data[2]==0x%08x\n",num_array[2]);
34195 printf("reg_def_value_data[3]==0x%08x\n",num_array[3]);
34196 printf("test_arg_4_step_flag_add_sticky_offset=%d\n",num_array[4]);
34197 printf("test_arg_5_pass_fail_flag_add_sticky_offset=%d\n",num_array[5]);
34198 printf("test_arg_6_step_status=%d\n",num_array[6]);
34199 printf("test_arg_7_lcdlr_offset=%d\n",num_array[7]);
34200
34201 if (test_arg_6_step_status == 4) //uboot finish
34202 {
34203 ddr_test_watchdog_disable(); //s
34204 printf("close watchdog\n");
34205
34206 // unsigned int acmdlr= 0;
34207
34208
34209 {
34210 //acmdlr=do_ddr_read_acmdlr();
34211 unsigned int acmdlr=32;
34212 delay_step_x100=100*1000000/(2*global_ddr_clk*32); //100*/32 ps
34213 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
34214 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
34215
34216
34217 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ,test_arg_7_lcdlr_offset_r=%4d ",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l,test_arg_7_lcdlr_offset_r);
34218 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ps,test_arg_7_lcdlr_offset_r=%4d ps",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l*delay_step_x100/100,test_arg_7_lcdlr_offset_r*delay_step_x100/100);
34219
34220 printf("\n\n-----------------------------------------------------------------------------\n\n");
34221
34222
34223 }
34224 if (ddr_test_uboot_kernel_enable_mask&2)
34225 {
34226 if (ddr_test_uboot_loop)
34227 {
34228 { test_arg_6_step_status=0;
34229 num_array[6] = test_arg_6_step_status ;
34230 temp_count=6;
34231 read_write_window_test_parameter(data_source,
34232 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34233 printf("\n clear sticky register should reset,then over write ....\n");
34234 run_command("reset",0);
34235 while (1) ;
34236 }
34237 run_command("reset",0);
34238 while (1) ;
34239 }
34240 else
34241 return 1;
34242 }
34243 }
34244
34245
34246
34247 //if((test_arg_6_step_status==0)) //0 test left edge begin 1 test left edge ongoing 2//left_finish 3 right edge ongoing 4 right finish //5 kernel left edge ongoing 6 kernel left finish 7 kernel right ongoing
34248 // uboot find from pass to fail offset 0->max
34249 //kernel find from fail to pass offset from max ->0
34250 if ((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
34251 {
34252 if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
34253 ||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
34254 )
34255 {
34256 test_arg_6_step_status=test_arg_6_step_status+1;
34257 num_array[6] = test_arg_6_step_status ;
34258 temp_count=6;
34259 read_write_window_test_parameter(data_source,
34260 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34261 }
34262
34263 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
34264 {
34265 if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
34266 {
34267 // test_arg_6_step_status=test_arg_6_step_status+1;
34268
34269 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
34270 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34271 temp_count=5;
34272 read_write_window_test_parameter(data_source,
34273 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34274
34275 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
34276 {
34277
34278 // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34279 {
34280 lane_step_count=6;
34281 //if((lane_step_count%2)==0)
34282 {
34283
34284 if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
34285 {
34286 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
34287 }
34288 }
34289 /*
34290 if ((lane_step_count%2) == 1)
34291 {
34292 if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
34293 {
34294 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
34295 }
34296 }
34297 */
34298
34299 }
34300
34301
34302
34303
34304 }
34305 if (test_lcdlr_reach_lcdlr_limited_flag)
34306 {
34307 test_arg_6_step_status=test_arg_6_step_status+1;
34308 num_array[6] = test_arg_6_step_status ;
34309 temp_count=6;
34310 read_write_window_test_parameter(data_source,
34311 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34312 run_command("reset",0);
34313 while (1) ;
34314 }
34315 }
34316
34317 else if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL) //pass 1 error 2
34318 {
34319
34320 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
34321 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
34322 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
34323 {
34324 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
34325 }
34326 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
34327 {
34328 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
34329 }
34330 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
34331 num_array[7] = test_arg_7_lcdlr_offset ;
34332 temp_count=7;
34333 read_write_window_test_parameter(data_source,
34334 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34335
34336
34337
34338 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
34339 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34340 temp_count=5;
34341 read_write_window_test_parameter(data_source,
34342 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34343
34344 test_arg_6_step_status=test_arg_6_step_status+1;
34345 num_array[6] = test_arg_6_step_status ;
34346 temp_count=6;
34347 read_write_window_test_parameter(data_source,
34348 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34349 run_command("reset",0);
34350 while (1) ;
34351 }
34352 }
34353
34354
34355 //(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL)
34356 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
34357 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
34358 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
34359 {
34360 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l+1;
34361 }
34362 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
34363 {
34364 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
34365 }
34366 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
34367 num_array[7] = test_arg_7_lcdlr_offset ;
34368 temp_count=7;
34369 read_write_window_test_parameter(data_source,
34370 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34371
34372 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
34373 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34374 temp_count=5;
34375 read_write_window_test_parameter(data_source,
34376 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34377
34378 ddr_test_watchdog_enable(test_watchdog_time_s); //s
34379 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
34380 ddr_test_watchdog_clear();
34381
34382
34383 {
34384
34385 // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34386 {
34387 lane_step_count=6;
34388 printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
34389 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
34390 {
34391 if ((lane_step_count%2) == 0)
34392 {
34393 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
34394 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
34395 {test_lcdlr_temp_value=0;
34396 }
34397 }
34398 if ((lane_step_count%2) == 1)
34399 {
34400 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
34401 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
34402 {test_lcdlr_temp_value=0;
34403 }
34404 }
34405 }
34406
34407 if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
34408 {
34409 if ((lane_step_count%2) == 0)
34410 {
34411 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
34412 }
34413 if ((lane_step_count%2) == 1)
34414 {
34415 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
34416
34417 }
34418 }
34419
34420
34421 {
34422 //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
34423 //printf("\nstr=%s\n",str);
34424 stick_test_ddr_window_delay_override_value=test_lcdlr_temp_value;
34425 sprintf(str,"g12_d2pll %d 0x%08x 0x%08x",global_ddr_clk,( stick_test_ddr_window_delay_override_index),
34426 stick_test_ddr_window_delay_override_value);
34427 printf("\nstr=%s\n",str);
34428 run_command(str,0);
34429 // run_command("reset",0);
34430 while (1) ;
34431
34432 }
34433 // do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
34434 // (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
34435 }
34436
34437
34438
34439
34440 }
34441
34442 //here will dead
34443 if (test_arg_6_step_status>4)
34444 {
34445 //ddr_test_watchdog_disable(); //s
34446 ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
34447 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
34448 // num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34449 // temp_count=5;
34450 // read_write_window_test_parameter(data_source,
34451 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34452 run_command("run storeboot",0);
34453 while (1) ;
34454 } else
34455 {
34456 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
34457 }
34458
34459 if (temp_test_error)
34460 {
34461 run_command("reset",0);
34462 while (1) ;
34463 }
34464 else
34465 {
34466 ddr_test_watchdog_clear();
34467
34468
34469
34470 {
34471 //write org value
34472 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34473 {
34474 if ((lane_step_count%2) == 0)
34475 {
34476 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
34477 }
34478 if ((lane_step_count%2) == 1)
34479 {
34480 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
34481 }
34482 do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
34483 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
34484 }
34485
34486
34487
34488
34489 }
34490
34491 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
34492 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34493 temp_count=5;
34494 read_write_window_test_parameter(data_source,
34495 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34496 run_command("reset",0);
34497 while (1) ;
34498
34499
34500
34501
34502
34503 }
34504 }
34505
34506
34507 if ((test_arg_6_step_status == 4) || (test_arg_6_step_status == 6))
34508 {
34509 test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_UBOOT_FINISH;
34510 num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
34511 temp_count=4;
34512 read_write_window_test_parameter(data_source,
34513 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34514
34515 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;//DDR_TEST_NULL;
34516 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34517 temp_count=5;
34518 read_write_window_test_parameter(data_source,
34519 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34520
34521 }
34522 if ((test_arg_6_step_status >= 4)) ////kernel find from fail to pass offset from max ->0
34523 {
34524 if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
34525 ||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
34526 )
34527 {
34528 test_arg_6_step_status=test_arg_6_step_status+1;
34529 num_array[6] = test_arg_6_step_status ;
34530 temp_count=6;
34531 read_write_window_test_parameter(data_source,
34532 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34533 }
34534
34535 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
34536 {
34537 if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
34538 {
34539 // test_arg_6_step_status=test_arg_6_step_status+1;
34540
34541 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
34542 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34543 temp_count=5;
34544 read_write_window_test_parameter(data_source,
34545 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34546
34547 if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
34548 {
34549
34550 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34551 {
34552 if ((lane_step_count%2) == 0)
34553 {
34554
34555 if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
34556 {
34557 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
34558 }
34559 }
34560 if ((lane_step_count%2) == 1)
34561 {
34562 if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
34563 {
34564 test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
34565 }
34566 }
34567
34568 }
34569
34570
34571
34572
34573 }
34574 // if(test_lcdlr_reach_lcdlr_limited_flag)
34575 {
34576 test_arg_6_step_status=test_arg_6_step_status+1;
34577 num_array[6] = test_arg_6_step_status ;
34578 temp_count=6;
34579 read_write_window_test_parameter(data_source,
34580 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34581 run_command("reset",0);
34582 while (1) ;
34583 }
34584 }
34585
34586 else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
34587 //||(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL))//pass 2 error 1
34588 )
34589 {
34590
34591 // test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
34592 // test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
34593 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
34594 {
34595 test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
34596 }
34597 else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
34598 {
34599 test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
34600 }
34601 test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
34602 num_array[7] = test_arg_7_lcdlr_offset ;
34603 temp_count=7;
34604 read_write_window_test_parameter(data_source,
34605 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34606
34607
34608
34609 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
34610 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;
34611 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34612 temp_count=5;
34613 read_write_window_test_parameter(data_source,
34614 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34615
34616
34617 }
34618 else if (test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL)//pass 2 error 1
34619 {printf("\nfind drop power,test_arg_5_pass_fail_flag_add_sticky_offset=%d \n",test_arg_5_pass_fail_flag_add_sticky_offset);
34620 }
34621
34622 ddr_test_watchdog_enable(test_watchdog_time_s); //s
34623 printf("\nenable %ds watchdog \n",test_watchdog_time_s);
34624 ddr_test_watchdog_clear();
34625
34626 {
34627
34628 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34629 {
34630 printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
34631 if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
34632 {
34633 if ((lane_step_count%2) == 0)
34634 {
34635 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
34636 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
34637 {test_lcdlr_temp_value=0;
34638 }
34639 }
34640 if ((lane_step_count%2) == 1)
34641 {
34642 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
34643 if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
34644 {test_lcdlr_temp_value=0;
34645 }
34646 }
34647 }
34648
34649 if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
34650 {
34651 if ((lane_step_count%2) == 0)
34652 {
34653 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
34654 }
34655 if ((lane_step_count%2) == 1)
34656 {
34657 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
34658
34659 }
34660 }
34661
34662
34663
34664 do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
34665 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
34666 }
34667
34668
34669
34670
34671 }
34672
34673 //here will dead
34674 if (test_arg_6_step_status>4)
34675 {
34676 //ddr_test_watchdog_disable(); //s
34677 ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
34678 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
34679 // num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34680 // temp_count=5;
34681 // read_write_window_test_parameter(data_source,
34682 // temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34683 run_command("run storeboot",0);
34684 while (1) ;
34685 } else
34686 {
34687 temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
34688 }
34689
34690 if (temp_test_error)
34691 {
34692 run_command("reset",0);
34693 while (1) ;
34694 }
34695 else
34696 {
34697 ddr_test_watchdog_clear();
34698 {
34699 //write org value
34700 for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
34701 {
34702 if ((lane_step_count%2) == 0)
34703 {
34704 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
34705 }
34706 if ((lane_step_count%2) == 1)
34707 {
34708 test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
34709 }
34710 do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
34711 (test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
34712 }
34713
34714 }
34715
34716 test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
34717 num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
34718 temp_count=5;
34719 read_write_window_test_parameter(data_source,
34720 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34721 run_command("reset",0);
34722 while (1) ;
34723
34724 }
34725 }
34726 }
34727 }
34728
34729 if (test_arg_6_step_status >= 8) //finish
34730 {
34731 ddr_test_watchdog_disable(); //s
34732 printf("close watchdog\n");
34733
34734
34735
34736 {
34737 //acmdlr=do_ddr_read_acmdlr();
34738 u_int32_t acmdlr=32;
34739 delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
34740 printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
34741 delay_step_x100/100,delay_step_x100/10,delay_step_x100);
34742
34743
34744 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ,test_arg_7_lcdlr_offset_r=%4d ",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l,test_arg_7_lcdlr_offset_r);
34745 printf("\nlcd_offset=0x%08x,test_arg_7_lcdlr_offset=%4d ps,test_arg_7_lcdlr_offset_r=%4d ps",test_arg_7_lcdlr_offset,test_arg_7_lcdlr_offset_l*delay_step_x100/100,test_arg_7_lcdlr_offset_r*delay_step_x100/100);
34746 printf("\n\n-----------------------------------------------------------------------------\n\n");
34747
34748 test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_KERNEL_FINISH;
34749 num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
34750 temp_count=4;
34751 read_write_window_test_parameter(data_source,
34752 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34753 }
34754 }
34755
34756 test_arg_6_step_status=0xffff;
34757 {
34758 // test_arg_6_step_status=test_arg_6_step_status+1;
34759 num_array[6] = test_arg_6_step_status ;
34760 temp_count=6;
34761 read_write_window_test_parameter(data_source,
34762 temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
34763 }
34764 ddr_test_watchdog_disable(); //s
34765 // test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
34766 run_command("run storeboot",0);
34767 while (1) ;
34768 return 1;
34769}
34770#endif
34771#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
34772
34773int do_ddr_g12_override_data(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
34774{
34775
34776 //ddr_test_cmd 0x25 1 1 10 10 10 10 10 10 10 10 10 10
34777
34778 printf("\12nm phy read write register should closed apd and asr function\n");
34779 writel((0), 0xff638630);
34780 writel((0), 0xff638634);
34781#define G12_DATA_READ_OFFSET_MAX (0X3F)
34782#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32)
34783
34784#if 1
34785 // if(!argc)
34786 // goto DDR_TUNE_DQS_START;
34787 int i=0;
34788 printf("\nargc== 0x%08x\n", argc);
34789 for (i = 0;i<argc;i++)
34790 {
34791 printf("\nargv[%d]=%s\n",i,argv[i]);
34792 }
34793 char *endp;
34794 //rank_index dq_index write_read left/right offset_value
34795 unsigned int test_index=0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq
34796 unsigned int dq_index=0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3
34797 // unsigned int test_dq_mask_1=0; //each bit mask correspond with dq_index
34798 // unsigned int test_dq_mask_2=0; //each bit mask correspond with dq_index
34799 // unsigned int test_dq_mask_3=0; //each bit mask correspond with dq_index
34800 //unsigned int write_read_flag=0;// 2 write ,1 read #define DDR_PARAMETER_READ 1 #define DDR_PARAMETER_WRITE 2
34801 // unsigned int left_right_flag=0;// 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2
34802 unsigned int ovrride_value=0;//
34803
34804 // unsigned int offset_enable=0;//
34805
34806 // unsigned int temp_value=0;//
34807 unsigned int count=0;
34808 // unsigned int count1=0;
34809 // unsigned int count_max=0;
34810 unsigned int lcdlr_max=0;
34811 // unsigned int reg_add=0;
34812 // unsigned int reg_value=0;
34813
34814 if (argc == 1)
34815 { printf("\nplease read help\n");
34816
34817 }
34818 else if (argc >4)
34819 {//offset_enable=1;
34820
34821 {
34822 count=0;
34823 test_index= simple_strtoull_ddr(argv[count+1], &endp, 0);
34824 if (*argv[count+1] == 0 || *endp != 0)
34825 {
34826 test_index = 0;
34827 }
34828
34829 }
34830 {
34831 count++;
34832 dq_index= simple_strtoull_ddr(argv[count+1], &endp, 0);
34833 if (*argv[count+1] == 0 || *endp != 0)
34834 {
34835 dq_index = 0;
34836 }
34837
34838 }
34839
34840
34841
34842 {
34843 count++;
34844 ovrride_value= simple_strtoull_ddr(argv[count+1], &endp, 0);
34845 if (*argv[count+1] == 0 || *endp != 0)
34846 {
34847 ovrride_value = 0;
34848 }
34849
34850 }
34851
34852
34853 }
34854 else {
34855 return 1;
34856 }
34857 printf("lcdlr_max %d,\n",lcdlr_max);
34858
34859 {
34860
34861
34862 {
34863
34864 {
34865 dwc_window_reg_after_training_update(test_index,
34866 dq_index,
34867 ovrride_value);
34868 }
34869
34870 }
34871 }
34872
34873
34874#endif
34875 return 1;
34876}
34877U_BOOT_CMD(
34878 ddr_g12_override_data, 20, 1, do_ddr_g12_override_data,
34879 "ddr_g12_override_data 1 0 0 0 1 3",
34880 "ddr_g12_override_data test_index dq_index ovrride_value \n"
34881);
34882int do_ddr_g12_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
34883{
34884
34885 //ddr_test_cmd 0x25 1 1 10 10 10 10 10 10 10 10 10 10
34886
34887
34888#define G12_DATA_READ_OFFSET_MAX (0X3F)
34889#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32)
34890 printf("\12nm phy read write register should closed apd and asr function\n");
34891 writel((0), 0xff638630);
34892 writel((0), 0xff638634);
34893#if 1
34894 // if(!argc)
34895 // goto DDR_TUNE_DQS_START;
34896 int i=0;
34897 printf("\nargc== 0x%08x\n", argc);
34898 for (i = 0;i<argc;i++)
34899 {
34900 printf("\nargv[%d]=%s\n",i,argv[i]);
34901 }
34902 char *endp;
34903 //rank_index dq_index write_read left/right offset_value
34904 unsigned int test_index=0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq
34905 // unsigned int dq_index=0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3
34906 unsigned int test_dq_mask_1=0; //each bit mask correspond with dq_index
34907 unsigned int test_dq_mask_2=0; //each bit mask correspond with dq_index
34908 unsigned int test_dq_mask_3=0; //each bit mask correspond with dq_index
34909 //unsigned int write_read_flag=0;// 2 write ,1 read #define DDR_PARAMETER_READ 1 #define DDR_PARAMETER_WRITE 2
34910 unsigned int left_right_flag=0;// 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2
34911 unsigned int offset_value=0;//
34912
34913 // unsigned int offset_enable=0;//
34914
34915 // unsigned int temp_value=0;//
34916 unsigned int count=0;
34917 //unsigned int count1=0;
34918 unsigned int count_max=0;
34919 unsigned int lcdlr_max=0;
34920 // unsigned int reg_add=0;
34921 // unsigned int reg_value=0;
34922
34923
34924 bdlr_100step=get_bdlr_100step(global_ddr_clk);
34925 ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32));
34926
34927 if (argc == 1)
34928 { printf("\nplease read help\n");
34929
34930 }
34931 else if (argc >6)
34932 {//offset_enable=1;
34933
34934 {
34935 count=0;
34936 test_index= simple_strtoull_ddr(argv[count+1], &endp, 0);
34937 if (*argv[count+1] == 0 || *endp != 0)
34938 {
34939 test_index = 0;
34940 }
34941
34942 }
34943 {
34944 count++;
34945 test_dq_mask_1= simple_strtoull_ddr(argv[count+1], &endp, 0);
34946 if (*argv[count+1] == 0 || *endp != 0)
34947 {
34948 test_dq_mask_1 = 0;
34949 }
34950
34951 }
34952 {
34953 count++;
34954 test_dq_mask_2= simple_strtoull_ddr(argv[count+1], &endp, 0);
34955 if (*argv[count+1] == 0 || *endp != 0)
34956 {
34957 test_dq_mask_2 = 0;
34958 }
34959
34960 }
34961 {
34962 count++;
34963 test_dq_mask_3= simple_strtoull_ddr(argv[count+1], &endp, 0);
34964 if (*argv[count+1] == 0 || *endp != 0)
34965 {
34966 test_dq_mask_3 = 0;
34967 }
34968
34969 }
34970 {
34971 count++;
34972 left_right_flag= simple_strtoull_ddr(argv[count+1], &endp, 0);
34973 if (*argv[count+1] == 0 || *endp != 0)
34974 {
34975 left_right_flag = 0;
34976 }
34977
34978 }
34979 {
34980 count++;
34981 offset_value= simple_strtoull_ddr(argv[count+1], &endp, 0);
34982 if (*argv[count+1] == 0 || *endp != 0)
34983 {
34984 offset_value = 0;
34985 }
34986
34987 }
34988
34989
34990 }
34991 else {
34992 return 1;
34993 }
34994 printf("lcdlr_max %d,\n",lcdlr_max);
34995 if (left_right_flag == DDR_PARAMETER_RIGHT)
34996 printf("offset right ++ left_right_flag %d,\n",left_right_flag);
34997 if (left_right_flag == DDR_PARAMETER_LEFT)
34998 printf("offset left --left_right_flag %d,\n",left_right_flag);
34999
35000 if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
35001 count_max=10;
35002
35003 lcdlr_max=3*32;//0x3ff;
35004 }
35005
35006 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
35007 count_max=16;
35008
35009 lcdlr_max=16*32;//0x3ff;
35010 }
35011 if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
35012 count_max=16;
35013 lcdlr_max=96;//0x3f;
35014 }
35015 if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
35016 count_max=36*2;
35017 lcdlr_max=8*32;//0x1ff;
35018 }
35019 if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
35020 count_max=36*2;
35021 lcdlr_max=0x3f;
35022 }
35023 if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
35024 count_max=36*1;
35025 lcdlr_max=0x3f;
35026 printf(" soc vref rank0 and rank1 share vref dac\n");
35027 }
35028
35029
35030
35031 count=0;
35032 for (;count<count_max;count++) {
35033 if ((count<32)) {
35034 if (test_dq_mask_1&(1<<(count%32))) {
35035 continue;
35036 }
35037 }
35038 if ((count>31) && (count<63)) {
35039 if (test_dq_mask_2&(1<<(count%32))) {
35040 continue;
35041 }
35042 }
35043 if ((count>63)) {
35044 if (test_dq_mask_3&(1<<(count%32))) {
35045 continue;
35046 }
35047 }
35048
35049 // for (count1=0;count1<offset_value;count1++)
35050 {
35051 if (left_right_flag == DDR_PARAMETER_RIGHT)
35052 {
35053 dwc_window_reg_after_training_update_increas(test_index,
35054 count,
35055 0,offset_value);
35056 }
35057 if (left_right_flag == DDR_PARAMETER_LEFT)
35058 {
35059 dwc_window_reg_after_training_update_increas(test_index,
35060 count,
35061 1,offset_value);
35062 }
35063 }
35064 }
35065
35066
35067#endif
35068 return 1;
35069}
35070
35071
35072U_BOOT_CMD(
35073 ddr_g12_offset_data, 20, 1, do_ddr_g12_offset_data,
35074 "ddr_g12_offset_data 1 0 0 0 1 3",
35075 "ddr_g12_offset_data test_index mask1 mask2 mask3 left/right offset_value \n"
35076);
35077
35078#endif
35079
35080
35081#if 0
35082U_BOOT_CMD(
35083 ddr_g12_offset_data_lcdlr, 10, 1, do_ddr_g12_offset_data_lcdlr,
35084 "ddr_g12_offset_data_lcdlr 0 1 2 2 3",
35085 "ddr_g12_offset_data_lcdlr rank_index dq_index write_read left/right offset_value \n"
35086);
35087#endif
35088int do_ddr_test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
35089{
35090 //ddr_test_watchdog_init(4000);
35091 //printf("\nopen watchdog %dms\n",4000);
35092 printf("\nargc== 0x%08x\n", argc);
35093 int i ;
35094 for (i = 0;i<argc;i++)
35095 printf("\nargv[%d]=%s\n",i,argv[i]);
35096
35097 /* need at least two arguments */
35098 if (argc < 2)
35099 goto usage;
35100 if ((strcmp(argv[1], "h") == 0))
35101 goto usage;
35102
35103#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
35104 printf("\12nm phy read write register should closed apd and asr function\n");
35105 writel((0), 0xff638630);
35106 writel((0), 0xff638634);
35107#else
35108 OPEN_CHANNEL_A_PHY_CLK();
35109 OPEN_CHANNEL_B_PHY_CLK();
35110
35111 unsigned int ddr_pll = rd_reg(AM_DDR_PLL_CNTL0);
35112 unsigned int ddr_clk =0;
35113 //#if( CONFIG_DDR_PHY >=P_DDR_PHY_G12)
35114 //ddr_clk=pll_convert_to_ddr_clk_g12a(ddr_pll);
35115 //#else
35116 ddr_clk=pll_convert_to_ddr_clk(ddr_pll);
35117 //#endif
35118 ///2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
35119
35120 printf("\nddr_clk== %dMHz\n", ddr_clk);
35121 global_ddr_clk=ddr_clk;
35122 unsigned int zq0pr = rd_reg(DDR0_PUB_ZQ0PR);
35123 printf("\nddr_zq0pr== 0x%08x\n", zq0pr);
35124
35125#endif
35126#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
35127 unsigned int ddr_pll = rd_reg(G12_AM_DDR_PLL_CNTL0);
35128 unsigned int ddr_clk =0;
35129 //#if( CONFIG_DDR_PHY >=P_DDR_PHY_G12)
35130 //ddr_clk=pll_convert_to_ddr_clk_g12a(ddr_pll);
35131 //#else
35132 ddr_clk=pll_convert_to_ddr_clk(ddr_pll);
35133 //#endif
35134 ///2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
35135
35136 printf("\nddr_clk== %dMHz\n", ddr_clk);
35137 global_ddr_clk=ddr_clk;
35138 // unsigned int zq0pr = rd_reg(DDR0_PUB_ZQ0PR);
35139 // printf("\nddr_zq0pr== 0x%08x\n", zq0pr);
35140#endif
35141
35142#define DDR_TEST_CMD__NONE 0
35143#define DDR_TEST_CMD__DDR_TEST 1
35144#define DDR_TEST_CMD__DDR_TUNE_ACLCDLR 2
35145#define DDR_TEST_CMD__DDR_TUNE_MAX_CLK 3 //ddr_test_cmd 3 0x8000000 3 1
35146#define DDR_TEST_CMD__DDR_TUNE_ZQ 4
35147#define DDR_TEST_CMD__DDR_TUNE_VREF 5
35148#define DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK 6
35149#define DDR_TEST_CMD__DDR_BANDWIDTH_TEST 7
35150#define DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE 8
35151#define DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK 9
35152#define DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK 0xa
35153
35154#define DDR_TEST_CMD__DDR_SETZQ 0x10
35155#define DDR_TEST_CMD__DDR_TUNE_DQS 0x11
35156#define DDR_TEST_CMD__DDR_SET_TEST_START_ADD 0x12
35157#define DDR_TEST_CMD__DDR_TEST_AC_BIT_SETUP_HOLD_MARGIN 0x13
35158#define DDR_TEST_CMD__DDR_TEST_DATA_BIT_SETUP_HOLD_MARGIN 0x14
35159#define DDR_TEST_CMD__DDR_TEST_AC_LANE_BIT_MARGIN 0x15
35160#define DDR_TEST_CMD__DDR_TEST_EE_VOLTAGE_MDLR_STEP 0x16
35161#define DDR_TEST_CMD__DDR_TEST_D2PLL_CMD 0x17
35162#define DDR_TEST_CMD__DDR_TEST_DATA_LANE_BIT_MARGIN 0x18
35163#define DDR_TEST_CMD__DDR4_TUNE_PHY_VREF 0x19
35164#define DDR_TEST_CMD__DDR4_TUNE_DRAM_VREF 0x1A
35165#define DDR_TEST_CMD__DDR4_TUNE_AC_VREF 0x1b
35166#define DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL 0x1c
35167#define DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY 0x1d
35168#define DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ 0x1e
35169#define DDR_TEST_CMD__DDR_TEST_PWM_CMD 0x1f
35170#define DDR_TEST_CMD__DDR_TEST_EE_SI 0x20
35171#define DDR_TEST_CMD__DDR_TEST_VDDQ_SI 0x21
35172#define DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_ENV 0x22
35173#define DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY_TXL 0x23
35174#define DDR_TEST_CMD__DISPLAY_DDR_INFORMATION 0x24
35175#define DDR_TEST_CMD__OFFSET_LCDLR 0x25
35176#define DDR_TEST_CMD__SET_WATCH_DOG_VALUE 0x26
35177#define DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY 0x27
35178#define DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL_STICKY 0x28
35179#define DDR_TEST_CMD__DDR4_DDR_BIST_TEST_USE_D2PLL_STICKY 0x29
35180#define DDR_TEST_CMD__DDR_SET_BIST_TEST_SIZE_STICKY_6 0x30
35181#define DDR_TEST_CMD__DDR_SET_UBOOT_STORE_WINDOW 0x31
35182#define DDR_TEST_CMD__DDR_SET_UBOOT_STORE_QUICK_WINDOW 0x32
35183#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW 0x33
35184#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW_MULTI 0x34
35185#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_WINDOW_SAME_CHANGE 0x35
35186#define DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD 0x36
35187#define DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION 0x37
35188#define DDR_TEST_CMD__DDR_G12_DMC_TEST 0x38
35189#define DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST 0x39
35190
35191 unsigned int ddr_test_cmd=0;
35192 unsigned int arg[30]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
35193 char *endp;
35194 ddr_test_cmd = simple_strtoull_ddr(argv[1], &endp, 0);
35195 for (i = 2;i<argc;i++)
35196 arg[i-2]=simple_strtoull_ddr(argv[i], &endp, 0);
35197 printf("\nddr_test_cmd== 0x%08x\n", ddr_test_cmd);
35198
35199 for (i = 0;i<(argc-2);i++)
35200 printf("\narg[%08x]=%08x\n",i,arg[i]);
35201 //int argc2_length;
35202 //argc2_length=(argc-2);
35203 //cmd_tbl_t *cmdtp2;
35204 //int flag2;
35205 int argc2;
35206 char* argv2[30];
35207
35208 argc2=argc-1;
35209 for (i = 1;i<(argc);i++)
35210 argv2[i-1]=argv[i];
35211 //argv2=(char *)argv++;
35212 {
35213 run_command("dcache off",0);
35214 run_command("dcache on",0);
35215 printf("\n cache off on");
35216 switch (ddr_test_cmd)
35217 {case(DDR_TEST_CMD__NONE):
35218 {
35219 printf("\n 0x0 help\n");
35220 printf("\n 0x1 ddrtest ddr_test_cmd 0x1 start_add test_size loops ");
35221 printf("\n 0x2 test aclcdlr ddr_test_cmd 0x2 start_add test_size loops ddr_test_cmd 0x2 a 0 0x8000000 1");
35222 printf("\n 0x3 test max_pllclk ddr_test_cmd 0x3 test_size loops add_freq sub_freq ");
35223 printf("\n 0x4 test zq ddr_test_cmd 0x4 test_size loops add_freq sub_freq drv_odt_flag ");
35224 printf("\n 0x5 test vref ddr_test_cmd 0x5 ");
35225 printf("\n 0x6 test gxtvbb_crosstalk ddr_test_cmd 0x6 loops pattern_flag ");
35226 printf("\n 0x7 test bandwidth ddr_test_cmd 0x7 size loops port sub_id timer_ms ");
35227 printf("\n 0x8 test lcdlr_use_env_uart ddr_test_cmd 0x8 input_src wr_adj_per[] rd_adj_per[][] ");
35228 printf("\n 0x9 test_reg_use_mask ddr_test_cmd 0x9 reg_add value mask ");
35229 printf("\n 0xa test ac_clk ddr_test_cmd 0xa start_add test_size loops ddr_test_cmd 0xa a 0 0x8000000 1 ");
35230 printf("\n 0xb ... ");
35231 printf("\n 0xc ... ");
35232 printf("\n 0xd ... ");
35233 printf("\n 0xe ... ");
35234 printf("\n 0xf ... ");
35235 printf("\n 0x10 test set zq ddr_test_cmd 0x10 zq0pr0 zq1pr0 zq2pr0 ");
35236 printf("\n 0x11 test tune dqs ddr_test_cmd 0x11 a 0 test_size ddr_test_cmd 0x11 a 0 0x80000");
35237 printf("\n 0x12 test set start_add ddr_test_cmd 0x12 start_add ");
35238 printf("\n 0x13 test ac_bit_setup_hold time ddr_test_cmd 0x13 a 0 size method pin_id ddr_test_cmd 0x13 a 0 0x8000000 0 0xc");
35239 printf("\n 0x14 test data_bit_setup_hold time ddr_test_cmd 0x14 a 0 size setup/hold pin_id ddr_test_cmd 0x14 a 0 0x80000 0 3 ");
35240 printf("\n 0x15 test ac_lane_setup_hold ddr_test_cmd 0x15 a 0 size ");
35241 printf("\n 0x16 test ee mdlr ddr_test_cmd 0x16 voltage pwm_id loops ");
35242 printf("\n 0x17 d2pll ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n \
35243 example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n \
35244 or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
35245 printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n");
35246 printf("\n 0x18 test data_lane_setup_hold ddr_test_cmd 0x18 a 0 size range start_pin_id end_pin_id ddr_test_cmd 0x18 a 0 0x80000 1 0 96 ");
35247 printf("\n 0x19 test phy vref ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec \
35248 ddr_test_cmd 0x19 a 0 0x1000000 1 63 1 1 0x8 0 1 ");
35249 printf("\n 0x1a test dram vref ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec \
35250 \n env_set ddr_test_ddr4ram_vref ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 1 0 0x8 0 0 0 ; env_set storeboot run ddr_test_ddr4ram_vref ;save;reset ");
35251 printf("\n 0x1b test ac vref ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec");
35252 printf("\n 0x1c sweep dram clk use d2pll_env ddr_test_cmd 0x1c test_size start_freq end_freq test_loops ddr_test_cmd 0x1c 0x8000000 800 1500 1");
35253 printf("\n 0x1d test shift clk ddr_test_cmd 0x1d type delay_ms times");
35254 printf("\n 0x1e test write_read ddr_test_cmd 0x1e write_read pattern_id loop start_add test_size");
35255 printf("\n 0x1f test pwm_cmd ddr_test_cmd 0x1f pwmid pwm_low pwm_high");
35256 printf("\n 0x22 test ddr_window use env ddr_test_cmd 0x22 a 0 test_size watchdog_time \
35257 lane_disable_mask add_test_size env_set bootcmd ddr_test_cmd 0x22 a 0 0x800000 15 0 0x8000000");
35258 printf("\n defenv;save;env_set bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000");
35259 printf("\n env_set env_ddrtest_data_lane 0x22;save;reset");
35260 printf("\n 0x23 test shift ddr frequency ddr_test_cmd 0x23");
35261 printf("\n 0x24 display ddr_information ddr_test_cmd 0x24");
35262 printf("\n 0x25 offset ddr_lcdlr ddr_test_cmd 0x25");
35263 printf("\n 0x26 set watchdog_value ddr_test_cmd 0x26 30");
35264 printf("\n 0x27 test ddr_window use sticky register ddr_test_cmd 0x27 a 0 test_size watchdog_time \
35265 lane_disable_mask add_test_size env_set bootcmd ddr_test_cmd 0x27 a 0 0x800000 15 0 0x8000000");
35266 printf("\n 0x28 sweep dram clk use d2pll_sticky ddr_test_cmd 0x28 test_size start_freq end_freq test_loops ddr_test_cmd 0x28 0x8000000 800 1500 1");
35267
35268 /*
35269 ddr_tune_dqs_step a 0 0x800000 1 2 lane0-7 min
35270 ddr_tune_dqs_step a 0 0x800000 1 1 lane0-7 max
35271
35272 ddr_tune_aclcdlr_step a 0 0x8000000 1 2 lane0-1 min
35273 ddr_tune_aclcdlr_step a 0 0x8000000 1 1 lane0-1 max
35274
35275 env_set bootcmd "ddr_test_cmd 0x22 a 0 0x800000 18 0 0x8000000" watchdog_time ��lane_disable_mask,add_test_size
35276 env_set env_ddrtest_data_lane 0x22 �������ʼ��־
35277 save watchdog_time ��lane_disable_mask,add_test_size
35278 d2pll 1200
35279
35280 env_set ddr_soc_iovref_test_ddr_clk "0x0000000";
35281 env_set ddr_soc_iovref_lef "0x0000000";
35282 env_set ddr_soc_iovref_org "0x0";
35283 env_set ddr_soc_iovref_rig "0x000000 ";
35284 save
35285 d2pll 1104
35286 ddr_test_cmd 0x19 a 0 0x80000 1 70 1 1 0x8 0 1
35287
35288
35289
35290 �ز�Ҫ���磬���ݴ���stick �Ĵ�����
35291 env_set ddr_dram_iovref_test_ddr_clk "0x0000000";
35292 env_set ddr_dram_iovref_lef "0x0000000";
35293 env_set ddr_dram_iovref_org "0x0";
35294 env_set ddr_dram_iovref_rig "0x000000 ";
35295 env_set ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x080000 0 70 0 0 0x08 0 0 1"
35296 env_set bootcmd "run ddr_test_ddr4ram_vref"
35297 save
35298 �����ϵ�
35299 d2pll 1104
35300 */
35301
35302
35303 }
35304 return 1;
35305
35306
35307 case(DDR_TEST_CMD__DDR_TEST):
35308 {
35309 // run_command("ddrtest 0x10000000 0x8000000 3",0);
35310 //ddr_test_cmd 0x1 star_add test_size loops
35311 // do_ddr_test(cmdtp, flag, argc2,argv);
35312 do_ddr_test((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2,(argv2));
35313 break;
35314 }
35315 case(DDR_TEST_CMD__DDR_TUNE_ACLCDLR):
35316 {
35317 // run_command("ddr_tune_ddr_ac_aclcdlr a 0 0x8000000 3",0);
35318 //ddr_test_cmd 0x2 a 0 0x8000000 1
35319 do_ddr_test_ac_windows_aclcdlr((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35320 }
35321 break;
35322 case(DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK):
35323 {
35324 // run_command("ddr_tune_ddr_ac_acbdlr_ck a 0 0x8000000 3",0);
35325 //ddr_test_cmd 0xA a 0 0x8000000 1
35326 do_ddr_test_ac_windows_acbdlr_ck((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35327 }
35328 break;
35329
35330
35331 case(DDR_TEST_CMD__DDR_TUNE_MAX_CLK):
35332 {
35333 // run_command("ddr_test_cmd 3 0x8000000 0",0);
35334 printf("\nTest ddr max frequency should use max timming ,such as 14-14-14\n");
35335
35336 do_ddr_test_ddr_max_freq((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35337 }
35338 break;
35339 case(DDR_TEST_CMD__DDR_TUNE_ZQ):
35340 {
35341 // run_command("ddr_tune_ddr_ac_aclcdlr 0x10000000 0x8000000 3",0);
35342 printf("\nTest zq,should first test max ddr frequency use default zq value\n");
35343
35344 do_ddr_test_ddr_zq((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35345 }
35346 break;
35347 case(DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK):
35348 {
35349 // run_command("ddr_tune_ddr_ac_aclcdlr 0x10000000 0x8000000 3",0);
35350 printf("\nTest GXTVBB cross talk,test only channel 0 --0x10000000 channel 1 --0x10000400 32byte\n");
35351
35352 do_ddr_gxtvbb_crosstalk((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35353 }
35354 break;
35355 case(DDR_TEST_CMD__DDR_BANDWIDTH_TEST):
35356 {
35357 // run_command("ddr_tune_ddr_ac_aclcdlr 0x10000000 0x8000000 3",0);
35358 printf("\nNOTE test DDR bandwidth in uboot limited by cpu speed \n");
35359
35360 do_ddr_test_bandwidth((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35361 }
35362 break;
35363 case(DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE):
35364 {
35365 // run_command("ddr_tune_ddr_ac_aclcdlr 0x10000000 0x8000000 3",0);
35366 printf("\ntune ddr lcdlr use uboot env or uart input \n");
35367
35368 do_ddr_fine_tune_lcdlr_env((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35369 }
35370 break;
35371 case(DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK):
35372 {
35373 // run_command("ddr_tune_ddr_ac_aclcdlr 0x10000000 0x8000000 3",0);
35374 printf("\nmodify ddr reg use mask \n");
35375
35376 do_ddr_modify_reg_use_mask((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35377 }
35378 break;
35379 case(DDR_TEST_CMD__DDR_SETZQ):
35380 {
35381 // run_command("ddr_test_cmd 0x10 0x59 0x5d 0x5b ",0);
35382 printf("\nset ddr zq \n");
35383
35384 do_ddr_set_zq((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35385 }
35386 break;
35387
35388#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
35389#else
35390 case(DDR_TEST_CMD__DDR_TUNE_DQS):
35391 {
35392 // run_command("ddr_test_cmd 0x11 a 0 0x80000 ",0);
35393 printf("\ntest dqs window \n");
35394
35395 do_ddr_test_dqs_window((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35396 }
35397 break;
35398 case(DDR_TEST_CMD__DDR_SET_TEST_START_ADD):
35399 {
35400 // run_command("ddr_test_cmd 12 0x41080000 ",0);
35401
35402
35403 test_start_addr=arg[0];
35404 if (test_start_addr == 0)
35405 test_start_addr=0x1080000;
35406 printf("\nset ddr test test_start_addr==0x%08x \n",test_start_addr);
35407 }
35408 break;
35409 case(DDR_TEST_CMD__DDR_TEST_AC_BIT_SETUP_HOLD_MARGIN):
35410 { //clk seed use for clk too early,clk must delay
35411 // run_command("ddr_test_cmd 0x13 a 0 0x8000000 0 0xc ",0); cs0 setup
35412 // run_command("ddr_test_cmd 0x13 a 0 0x8000000 1 0xc ",0); cs0 hold
35413 // run_command("ddr_test_cmd 0x13 a 0 0x8000000 2 0xc ",0); cs0 hold //some times ddr frequency too high cannot move clk delay.then should only move cmd bdl
35414 //so should test hold time use method 1 and method 2----test hold time take care--20160804-jiaxing
35415 // run_command("ddr_test_cmd 0x13 a 0 0x8000000 0 0xd ",0); cs1 setup
35416 // run_command("ddr_test_cmd 0x13 a 0 0x8000000 1 0xd ",0); cs1 hold
35417 printf("\ntest AC bit window \n");
35418
35419 do_ddr_test_ac_bit_setup_hold_window((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35420 //do_ddr_test_ac_bit_setup_hold_window a 0 0x8000000 0 c
35421 }
35422 break;
35423
35424 case(DDR_TEST_CMD__DDR_TEST_D2PLL_CMD):
35425 {
35426 //printf(" ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n");
35427 //printf("example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n");
35428 //printf("or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
35429 printf("\ntest d2pll cmd ,see ddr_test_cmd 0x17 help \n");
35430
35431 do_ddr2pll_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35432 }
35433 break;
35434 case(DDR_TEST_CMD__DDR_TEST_EE_VOLTAGE_MDLR_STEP):
35435 {
35436 // run_command("ddr_test_cmd 0x16 1000 1 1",0);//test EE 1000mV ddl step pwmb -1 211 212--pwmd--3
35437 //1000 1 1 ---1000mv pwmid loop ,if loop then test all pwm voltage
35438 //ddr_test_cmd 0x16 1000 1 set to 1000mv
35439 printf("\ntest ee voltage ddl step \n");
35440
35441 do_ddr_test_pwm_ddl((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35442 }
35443 break;
35444 case(DDR_TEST_CMD__DDR_TEST_AC_LANE_BIT_MARGIN):
35445 {
35446 // run_command("ddr_test_cmd 0x15 a 0 0x800000 0",0);
35447 printf("\ntest ac lane bit margin not include cs pin \n");
35448
35449 do_ddr_test_ac_bit_margin((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35450 //do_ddr_test_ac_bit_setup_hold_window a 0 0x8000000 0 c
35451 }
35452 break;
35453 case(DDR_TEST_CMD__DDR_TEST_DATA_BIT_SETUP_HOLD_MARGIN):
35454 {
35455 // run_command("ddr_test_cmd 0x14 a 0 0x80000 setup/hold pin_id",0);
35456 // run_command("ddr_test_cmd 0x14 a 0 0x80000 0 3",0);
35457 printf("\ntest data lane bit setup hold \n");
35458
35459 do_ddr_test_data_bit_setup_hold_window((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35460 }
35461 break;
35462 case(DDR_TEST_CMD__DDR_TEST_DATA_LANE_BIT_MARGIN):
35463 {
35464 // run_command("ddr_test_cmd 0x18 a 0 0x80000 0",0);
35465 // run_command("ddr_test_cmd 0x18 a 0 0x80000 1 0 96",0);
35466 printf("\ntest data lane bit margin \n");
35467
35468 do_ddr_test_data_bit_margin((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35469 }
35470 break;
35471
35472 case(DDR_TEST_CMD__DDR4_TUNE_PHY_VREF):
35473 {
35474 // run_command("ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec",0);
35475 //ddr_test_cmd 0x19 a 0 0x1000000 1 0x1a 1 1 0x8 0 0
35476 //ddr_test_cmd 0x19 a 0 0x1000000 1 63 1 1 0x8 0 1
35477 printf("\ntest ddr4 phy vref \n");
35478
35479 do_ddr4_test_phy_vref((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35480 }
35481 break;
35482 case(DDR_TEST_CMD__DDR4_TUNE_DRAM_VREF):
35483 {
35484 // run_command("ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec",0);
35485 //ddr_test_cmd 0x1A a 0 0x1000000 0 0 3 0 0x10
35486 //env_set ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 0 0 0x8 0 0 0"
35487 //env_set storeboot "run ddr_test_ddr4ram_vref"
35488 printf("\ntest ddr4 DRAM vref \n");
35489
35490 do_ddr4_test_dram_vref((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35491 }
35492 break;
35493 case(DDR_TEST_CMD__DDR4_TUNE_AC_VREF):
35494 {
35495 // run_command("ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec",0);
35496 //ddr_test_cmd 0x1B a 0 0x1000000 0 0 1 0 0x10 0
35497 printf("\ntest ddr4 AC or dd3 dram ac_data vref \n");
35498
35499 do_ddr4_test_dram_ac_vref((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35500 }
35501 break;
35502
35503 //DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL
35504 case(DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL):
35505 {
35506 // run_command("ddr_test_cmd 0x1c test_size start_freq end_freq test_loops",0);
35507 //ddr_test_cmd 0x1c 0x8000000 800 1500 3
35508 printf("\ntest ddr4 sweep ddr clk use d2pll \n");
35509
35510 do_ddr4_test_dram_clk((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35511 }
35512 break;
35513 case(DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY):
35514 {
35515 // run_command("ddr_test_cmd 0x1d ",0);
35516 //ddr_test_cmd 0x1d type delay_ms times //ddr_test_cmd 0x1d 0 1000 100000
35517 //times =0xffffffff will auto loop
35518 printf("\ntest ddr shift ddr clk \n");
35519
35520 do_ddr_test_shift_ddr_clk((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35521 }
35522 break;
35523 //DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ
35524
35525 case(DDR_TEST_CMD__DDR_TEST_PWM_CMD):
35526 {
35527 // run_command("ddr_test_cmd 0x1f 0x1 0x2 0x1A ",0);//test EE pwmb --1 211 212--pwmd--3
35528 //1000 1 1 ---pwmid pwm_low pwm_high pwm_low+pwm_high==normal=28
35529 printf("\npwmid pwm_low pwm_high \n");
35530
35531 do_ddr_test_pwm_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35532 }
35533 break;
35534 case(DDR_TEST_CMD__DDR_TEST_EE_SI):
35535 {
35536 // run_command("ddr_test_cmd 0x20 0x1 0x2 0x1A ",0);//test EE pwmb --1 211 212--pwmd--3
35537 //1000 1 1 ---pwmid pwm_low pwm_high pwm_low+pwm_high==normal=28
35538 // do_ddr_test_ee_si((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35539 }
35540 break;
35541#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
35542#else
35543 case(DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_ENV):
35544 {
35545 // run_command("ddr_test_cmd 0x22 a 0 0x80000 ",0);
35546 printf("\ntest dqs window use env \n");
35547
35548 do_ddr_test_dqs_window_env((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35549 }
35550 break;
35551 case(DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY_TXL):
35552 {
35553 // run_command("ddr_test_cmd 0x1d ",0);
35554 //ddr_test_cmd 0x1d type delay_ms times //ddr_test_cmd 0x1d 0 1000 100000
35555 //times =0xffffffff will auto loop
35556 printf("\ntest ddr shift ddr clk \n");
35557
35558 do_ddr_test_shift_ddr_clk_txl((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35559 }
35560 break;
35561#endif
35562 case(DDR_TEST_CMD__DISPLAY_DDR_INFORMATION):
35563 {
35564
35565 printf("\ndisplay ddr_information \n");
35566
35567 do_ddr_display_ddr_information((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35568 }
35569 break;
35570 case(DDR_TEST_CMD__OFFSET_LCDLR):
35571 {
35572
35573 printf("\noffset ddr lcdlr \n");
35574
35575 do_ddr_offset_ddr_lcdlr((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35576 }
35577 break;
35578 case(DDR_TEST_CMD__SET_WATCH_DOG_VALUE):
35579 {
35580 printf("\nset watchdog value \n");
35581 do_ddr_set_watchdog_value ((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35582
35583 }
35584 break;
35585
35586 case(DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL_STICKY):
35587 {
35588 // run_command("ddr_test_cmd 0x28
35589 printf("\ntest ddr frequency use sticky register\n");
35590
35591 do_ddr4_test_dram_clk_use_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35592 }
35593 break;
35594 case(DDR_TEST_CMD__DDR4_DDR_BIST_TEST_USE_D2PLL_STICKY):
35595 {
35596 // run_command("ddr_test_cmd 0x29
35597 printf("\ntest ddr bist test use sticky register\n");
35598
35599 do_ddr4_test_bist_test_use_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35600 }
35601 break;
35602 case(DDR_TEST_CMD__DDR_SET_BIST_TEST_SIZE_STICKY_6):
35603 {
35604 // run_command("ddr_test_cmd 0x30
35605 printf("\nset ddr bist test size use sticky6 register\n");
35606
35607 do_ddr_set_bist_test_size_use_sticky_6((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35608 }
35609 break;
35610 case(DDR_TEST_CMD__DDR_SET_UBOOT_STORE_WINDOW):
35611 {
35612 // run_command("ddr_test_cmd 0x31
35613 printf("\nset do_ddr_uboot_window_use_source\n");
35614
35615 do_ddr_uboot_window_use_source((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35616 }
35617 break;
35618 case(DDR_TEST_CMD__DDR_SET_UBOOT_STORE_QUICK_WINDOW):
35619 {
35620 // run_command("ddr_test_cmd 0x32
35621 printf("\nset do_ddr_uboot_window_use_source_quick_test\n");
35622
35623 do_ddr_uboot_window_use_source_quick_method((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35624 }
35625 break;
35626 case(DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW):
35627 {
35628 // run_command("ddr_test_cmd 0x33
35629 printf("\nset do_ddr_uboot_kernel_window_use_source_quick_method\n");
35630
35631 do_ddr_uboot_kernel_window_use_source_quick_method((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35632 }
35633 break;
35634 case(DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW_MULTI):
35635 {
35636 // run_command("ddr_test_cmd 0x34
35637 printf("\nset do_ddr_uboot_kernel_window_use_source_quick_methods\n");
35638
35639 do_ddr_uboot_kernel_window_use_source_quick_methods((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35640 }
35641 break;
35642 //int do_ddr_uboot_window_use_source_all_same_increase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
35643 case(DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_WINDOW_SAME_CHANGE):
35644 {
35645 // run_command("ddr_test_cmd 0x35
35646 printf("\nset do_ddr_uboot_kernel_window_use_all lcdlr same change \n");
35647
35648 do_ddr_uboot_window_use_source_all_same_increase((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35649 }
35650 break;
35651 #endif
35652 case(DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY):
35653 {
35654 // run_command("ddr_test_cmd 0x27
35655 printf("\ntest dqs window use sticky register\n");
35656
35657 do_ddr_test_dqs_window_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35658 }
35659 break;
35660 case(DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ):
35661 {
35662 // run_command("ddr_test_cmd 0x1e write_read pattern_id loop start_addr test_size delay_us",0);
35663 //ddr_test_cmd 0x1e 1 2 10 0x40000000 0x10000000
35664 //times =0xffffffff will auto loop
35665 printf("\ntest ddr write read \n");
35666
35667 do_ddr_test_write_read((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35668 }
35669 break;
35670 //DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD
35671 case(DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD):
35672 {
35673 // run_command("ddr_test_cmd 0x36
35674 printf("\nset do_ddr_uboot_reconfig cmd\n");
35675
35676 do_ddr_uboot_new_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35677 }
35678 break;
35679
35680 case(DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION):
35681 {
35682 // run_command("ddr_test_cmd 0x37
35683 printf("\nshow g12 ddr information\n");
35684
35685 do_ddr_display_g12_ddr_information((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35686 }
35687 break;
35688
35689 case(DDR_TEST_CMD__DDR_G12_DMC_TEST):
35690 {
35691 // run_command("ddr_test_cmd 0x38
35692 printf("\nUboot dmc test \n");
35693
35694 do_ddr_g12_uboot_dmc_test((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35695 }
35696 break;
35697 case(DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST):
35698 {
35699 // run_command("ddr_test_cmd 0x39
35700 printf("\nUboot BDLR test \n");
35701
35702 do_ddr_test_pwm_bdlr((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
35703 }
35704 break;
35705 }
35706 return 1;//test_start_addr
35707 }
35708
35709usage:
35710 cmd_usage(cmdtp);
35711 return 1;
35712
35713}
35714U_BOOT_CMD(
35715 ddr_test_cmd, 30, 1, do_ddr_test_cmd,
35716 "ddr_test_cmd cmd arg1 arg2 arg3...",
35717 "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
35718 );
35719
35720int do_ddr_auto_test_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
35721{
35722 global_boot_times=rd_reg(PREG_STICKY_G12A_REG0);
35723 printf("\nglobal_boot_times== %d\n", global_boot_times);
35724
35725 printf("\nargc== 0x%08x\n", argc);
35726 printf("\nargc== 0x%08x\n", argc);
35727 int i ;
35728 for (i = 0;i<argc;i++)
35729 {
35730 printf("\nargv[%d]=%s\n",i,argv[i]);
35731 }
35732
35733 char str[1024]="";
35734 unsigned int ddr_test_cmd=0;
35735 unsigned int temp_reg_add=0;
35736 unsigned int num_arry[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
35737
35738 //int argc2;
35739 //char * argv2[30];
35740
35741 temp_reg_add=((DMC_STICKY_G12A_0));
35742 //num_arry = (uint16_t *)(uint64_t )(sticky_reg_base_add);
35743 for (i = 0; i < 32; i++) {
35744 num_arry[i]=ddr_rd_8_16bit_on_32reg(temp_reg_add,8,i);
35745 if ((i == 0) || (i == 16)) {
35746 printf("\n numarry[%d]" ,i);
35747 }
35748 printf(" %d ",num_arry[i]);
35749 }
35750
35751 ddr_test_cmd=num_arry[0];
35752
35753 unsigned int cs0_test_start= 0x1080000;
35754 unsigned int cs0_test_size= DDR_CROSS_TALK_TEST_SIZE;
35755 unsigned int cs1_test_start= 0;
35756 unsigned int cs1_test_size= 0;
35757 unsigned int watchdog_time_s=0;
35758 unsigned int test_index_enable=0;
35759 unsigned int all_tighter_enable=0;
35760 //unsigned int nibble_mask[3]={0,0,0};
35761 cs0_test_start=((num_arry[TEST_ARG_CS0_TEST_START_INDEX])|((num_arry[TEST_ARG_CS0_TEST_START_INDEX+1])<<8)|
35762 ((num_arry[TEST_ARG_CS0_TEST_START_INDEX+2])<<16)|((num_arry[TEST_ARG_CS0_TEST_START_INDEX+3])<<24));
35763 cs0_test_size=((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX])|((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+1])<<8)|
35764 ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+2])<<16)|((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+3])<<24));
35765 cs1_test_start=((num_arry[TEST_ARG_CS1_TEST_START_INDEX])|((num_arry[TEST_ARG_CS1_TEST_START_INDEX+1])<<8)|
35766 ((num_arry[TEST_ARG_CS1_TEST_START_INDEX+2])<<16)|((num_arry[TEST_ARG_CS1_TEST_START_INDEX+3])<<24));
35767 cs1_test_size=((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX])|((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+1])<<8)|
35768 ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+2])<<16)|((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+3])<<24));
35769 watchdog_time_s=((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX])|((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1])<<8));
35770 test_index_enable=((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX])|((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX+1])<<8));
35771 all_tighter_enable=(num_arry[TEST_ARG_3_ALL_TIGHTER]);
35772 switch (ddr_test_cmd)
35773 {
35774 case(DMC_STICKY_UBOOT_WINDOW_MAGIC_1):
35775 if (num_arry[1] == DMC_STICKY_UBOOT_WINDOW_MAGIC_1)
35776 {
35777 //argc2=10;
35778 sprintf(str,"ddr_test_cmd 0x27 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \
35779 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",cs0_test_start,cs0_test_size,cs1_test_start,cs1_test_size,
35780 watchdog_time_s,test_index_enable,0,0,0,0,0,0,all_tighter_enable );
35781 // for (i = 1;i<(argc2);i++)
35782 // {
35783 // argv2[i]=(arg[i]);
35784 // sprintf(str," 0x%08x ",(arg[i]));
35785 // }
35786
35787 printf("\nstr=%s\n",str);
35788
35789 run_command(str,0);
35790 // ddr_test_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2,(argv2));
35791 break;
35792 }
35793 }
35794
35795 return 1;
35796}
35797U_BOOT_CMD(
35798 ddr_auto_test_window, 30, 1, do_ddr_auto_test_window,
35799 "ddr_test_cmd cmd arg1 arg2 arg3...",
35800 "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
35801 );
35802
35803int do_ddr_auto_scan_drv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
35804{
35805 // ddr_type 2 lpddr4 rank_config
35806 #define AUTO_SCAN_DDR3 0
35807 #define AUTO_SCAN_DDR4 1
35808 #define AUTO_SCAN_LPDDR3 2
35809 #define AUTO_SCAN_LPDDR4 3
35810
35811 #define AUTO_SCAN_CONFIG_RANK0 0
35812 #define AUTO_SCAN_CONFIG_RANK01 1
35813
35814 char *string_print_flag= " window-loop \n";
35815 global_boot_times=rd_reg(PREG_STICKY_G12A_REG0);
35816
35817 printf("\nargc== 0x%08x\n", argc);
35818 printf("\nargc== 0x%08x\n", argc);
35819 int i ;
35820 for (i = 0;i<argc;i++)
35821 {
35822 printf("\nargv[%d]=%s\n",i,argv[i]);
35823 }
35824
35825 unsigned int ddr_type=0;
35826 unsigned int ddr_channel_rank_config=0;
35827 unsigned int loop=0;
35828 char *endp;
35829 if (argc>1)
35830 {
35831 ddr_type = simple_strtoull_ddr(argv[1], &endp, 0);
35832 if (*argv[1] == 0 || *endp != 0)
35833 ddr_type=0;
35834 }
35835 if (argc>2)
35836 {
35837 ddr_channel_rank_config = simple_strtoull_ddr(argv[2], &endp, 0);
35838 if (*argv[2] == 0 || *endp != 0)
35839 ddr_channel_rank_config=0;
35840 }
35841 if (argc>3)
35842 {
35843 loop = simple_strtoull_ddr(argv[3], &endp, 0);
35844 if (*argv[3] == 0 || *endp != 0)
35845 loop=0;
35846 }
35847 unsigned int temp_reg_add=0;
35848 {
35849 temp_reg_add=((DMC_STICKY_G12A_0));
35850 }
35851
35852 char str[1024]="";
35853 // unsigned int ddr_test_cmd=0;
35854 // unsigned int temp_reg_add=0;
35855 // unsigned int num_arry[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
35856
35857 unsigned int counter_loop=0;
35858 unsigned int ddr_frequency=0;
35859 unsigned int soc_data_drv_ohm_p=0;//74 //config soc data pin pull up driver strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
35860 unsigned int soc_data_drv_ohm_n=0;//76
35861 unsigned int soc_data_odt_ohm_p=0;//78 //config soc data pin odt pull up strength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
35862 unsigned int soc_data_odt_ohm_n=0;//80
35863 unsigned int dram_data_drv_ohm=0;//82 //config dram data pin pull up pull down driver strength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
35864 unsigned int dram_data_odt_ohm=0;//84 //config dram data pin odt pull up down strength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
35865 unsigned int dram_data_wr_odt_ohm=0; //174 char 1
35866 i=74/2;
35867 soc_data_drv_ohm_p=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35868 i=76/2;
35869 soc_data_drv_ohm_n=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35870 i=78/2;
35871 soc_data_odt_ohm_p=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35872 i=80/2;
35873 soc_data_odt_ohm_n=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35874 i=82/2;
35875 dram_data_drv_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35876 i=84/2;
35877 dram_data_odt_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35878 i=174/1;
35879 dram_data_wr_odt_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,8,i);
35880 i=52/2;
35881 ddr_frequency=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
35882 //ddr_frequency=global_ddr_clk;
35883 if (global_boot_times == 1)
35884 {
35885 printf("\norg_global_boot_times== %d %s", global_boot_times,string_print_flag);
35886 //printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag);
35887 printf("\nsoc_data_drv_ohm_p=%d %s",soc_data_drv_ohm_p,string_print_flag);
35888 printf("\nsoc_data_drv_ohm_n=%d %s",soc_data_drv_ohm_n,string_print_flag);
35889 printf("\nsoc_data_odt_ohm_p=%d %s",soc_data_odt_ohm_p,string_print_flag);
35890 printf("\nsoc_data_odt_ohm_n=%d %s",soc_data_odt_ohm_n,string_print_flag);
35891 printf("\ndram_data_drv_ohm=%d %s",dram_data_drv_ohm,string_print_flag);
35892 printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag);
35893 printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag);
35894 }
35895 unsigned int soc_data_drv_ohm_p_t[]={34,40,48,60};
35896 // unsigned int soc_data_drv_ohm_n_t[]={34,40,48,60};
35897
35898 unsigned int dram_data_odt_ohm_t_ddr3[]={40,60,120}; //ddr3
35899 unsigned int dram_data_odt_ohm_t_ddr4[]={40,48,60,120}; //ddr4
35900 unsigned int dram_data_odt_ohm_t_lpddr4[]={40,48,60,120}; //lpddr4
35901
35902 unsigned int dram_data_drv_ohm_t_ddr3[]={34,40}; //ddr3
35903 unsigned int dram_data_drv_ohm_t_ddr4[]={34,48}; //ddr4
35904 unsigned int dram_data_drv_ohm_t_lpddr4[]={40,48,60}; //lpddr4
35905
35906 unsigned int soc_data_odt_ohm_p_t[]={40,48,60,80,120};
35907 unsigned int soc_data_odt_ohm_n_t[]={40,48,60,80,120};
35908
35909 unsigned int dram_data_wr_odt_ohm_t_ddr3[]={60,120,0}; //ddr3
35910 unsigned int dram_data_wr_odt_ohm_t_ddr4[]={80,120,0}; //ddr4
35911
35912 unsigned int *p_soc_data_drv_ohm_p=NULL;
35913 // unsigned int *p_soc_data_drv_ohm_n=NULL;
35914 unsigned int *p_soc_data_odt_ohm_p=NULL;
35915 unsigned int *p_soc_data_odt_ohm_n=NULL;
35916
35917
35918 unsigned int *p_dram_data_drv_ohm=NULL;
35919 unsigned int *p_dram_data_odt_ohm=NULL;
35920 unsigned int *p_dram_data_wr_odt_ohm=NULL;
35921
35922 p_soc_data_drv_ohm_p=soc_data_drv_ohm_p_t;
35923 // p_soc_data_drv_ohm_n=soc_data_drv_ohm_n_t;
35924 p_soc_data_odt_ohm_p=soc_data_odt_ohm_p_t;
35925 p_soc_data_odt_ohm_n=soc_data_odt_ohm_n_t;
35926
35927
35928 p_dram_data_drv_ohm=dram_data_drv_ohm_t_ddr3;
35929 p_dram_data_odt_ohm=dram_data_odt_ohm_t_ddr3;
35930 p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_ddr3;
35931
35932 unsigned int max_counter_loop_w1=(sizeof(soc_data_drv_ohm_p_t))/(sizeof(soc_data_drv_ohm_p_t[0]));
35933 unsigned int max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_ddr3))/(sizeof(dram_data_odt_ohm_t_ddr3[0]));
35934 unsigned int max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr3))/(sizeof(dram_data_drv_ohm_t_ddr3[0]));
35935 unsigned int max_counter_loop_r2=(sizeof(soc_data_odt_ohm_p_t))/(sizeof(soc_data_odt_ohm_p_t[0]));
35936 unsigned int max_counter_loop_wr1=1;
35937 if (ddr_channel_rank_config)
35938 {
35939 max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr3))/(sizeof(dram_data_wr_odt_ohm_t_ddr3[0]));
35940 }
35941 //ddr_channel_rank_configCONFIG_DDR0_32BIT_RANK01_CH0
35942 if (ddr_type == AUTO_SCAN_DDR4)
35943 {
35944 p_dram_data_drv_ohm=dram_data_drv_ohm_t_ddr4;
35945 p_dram_data_odt_ohm=dram_data_odt_ohm_t_ddr4;
35946 p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_ddr4;
35947 max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_ddr4))/(sizeof(dram_data_odt_ohm_t_ddr4[0]));
35948 max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr4))/(sizeof(dram_data_drv_ohm_t_ddr4[0]));
35949
35950 if (ddr_channel_rank_config)
35951 {
35952 max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr4))/(sizeof(dram_data_wr_odt_ohm_t_ddr4[0]));
35953 }
35954 }
35955 if (ddr_type == AUTO_SCAN_LPDDR4)
35956 {
35957 p_dram_data_drv_ohm=dram_data_drv_ohm_t_lpddr4;
35958 p_dram_data_odt_ohm=dram_data_odt_ohm_t_lpddr4;
35959 // p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_lpddr4;
35960 max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_lpddr4))/(sizeof(dram_data_odt_ohm_t_lpddr4[0]));
35961 max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_lpddr4))/(sizeof(dram_data_drv_ohm_t_lpddr4[0]));
35962 max_counter_loop_r2=(sizeof(soc_data_odt_ohm_n_t))/(sizeof(soc_data_odt_ohm_n_t[0]));
35963
35964 // unsigned int *p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_lpddr4;
35965 if (ddr_channel_rank_config)
35966 {
35967 max_counter_loop_wr1=1;
35968 }
35969 }
35970
35971 unsigned int max_counter_total=(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)*max_counter_loop_wr1;
35972 //add 2 times recover
35973 /*
35974 switch (global_boot_times)
35975 {
35976 case(1):
35977 {
35978 break;
35979 }
35980 }
35981 */
35982 //each array test 2 times ,for maybe 1times will fail,then next time will recovery //jiaxing 20181114
35983 counter_loop=(((global_boot_times-1)/2)%max_counter_total);
35984 dram_data_wr_odt_ohm=0;
35985 if (max_counter_loop_wr1>1)
35986 {
35987 dram_data_wr_odt_ohm=p_dram_data_wr_odt_ohm[(counter_loop/(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))];
35988 }
35989 if ((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2))
35990 {
35991 soc_data_drv_ohm_p=p_soc_data_drv_ohm_p[(((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))%max_counter_loop_w1)];
35992 soc_data_drv_ohm_n=soc_data_drv_ohm_p;
35993 dram_data_odt_ohm=p_dram_data_odt_ohm[ (((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))/max_counter_loop_w1)];
35994 }
35995 else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))==((max_counter_loop_w1*max_counter_loop_w2)+0))
35996 {
35997 ddr_test_watchdog_reset_system();
35998 // sprintf(str,"g12_d2pll 1200 0x11 0x6 0 0x0 0 0 0 0x800000 0 1 "
35999 // printf("\nstr=%s\n",str);
36000 // run_command(str,0);
36001 }
36002 else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2-1))
36003 {
36004 dram_data_drv_ohm=p_dram_data_drv_ohm[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))%max_counter_loop_r1)];
36005 soc_data_odt_ohm_p=p_soc_data_odt_ohm_p[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)];
36006 soc_data_odt_ohm_n=0;
36007 if (ddr_type == CONFIG_DDR_TYPE_LPDDR4)
36008 {
36009 soc_data_odt_ohm_p=0;
36010 soc_data_odt_ohm_n=p_soc_data_odt_ohm_n[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)];
36011 }
36012 }
36013 else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))==(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2-1))
36014 {
36015 ddr_test_watchdog_reset_system();
36016 }
36017 printf("\nglobal_boot_times== %d %s", global_boot_times,string_print_flag);
36018 if (loop)
36019 {
36020 if (((global_boot_times-1)/2)>max_counter_total)
36021 return 1;
36022 }
36023 printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag);
36024 printf("\nsoc_data_drv_ohm_p=%d %s",soc_data_drv_ohm_p,string_print_flag);
36025 printf("\nsoc_data_drv_ohm_n=%d %s",soc_data_drv_ohm_n,string_print_flag);
36026 printf("\nsoc_data_odt_ohm_p=%d %s",soc_data_odt_ohm_p,string_print_flag);
36027 printf("\nsoc_data_odt_ohm_n=%d %s",soc_data_odt_ohm_n,string_print_flag);
36028 printf("\ndram_data_drv_ohm=%d %s",dram_data_drv_ohm,string_print_flag);
36029 printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag);
36030 printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag);
36031{
36032 if (soc_data_drv_ohm_p)
36033 {
36034 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 74 %d 2 0 ",
36035 soc_data_drv_ohm_p);
36036 printf("\nstr=%s\n",str);
36037 run_command(str,0);
36038 }
36039 if (soc_data_drv_ohm_n)
36040 {
36041 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 76 %d 2 0 ",
36042 soc_data_drv_ohm_n);
36043 printf("\nstr=%s\n",str);
36044 run_command(str,0);
36045 }
36046 if (soc_data_odt_ohm_p)
36047 {
36048 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 78 %d 2 0 ",
36049 soc_data_odt_ohm_p);
36050 printf("\nstr=%s\n",str);
36051 run_command(str,0);
36052 }
36053 if (soc_data_odt_ohm_n)
36054 {
36055 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 80 %d 2 0 ",
36056 soc_data_odt_ohm_n);
36057 printf("\nstr=%s\n",str);
36058 run_command(str,0);
36059 }
36060 if (dram_data_drv_ohm)
36061 {
36062 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 82 %d 2 0 ",
36063 dram_data_drv_ohm);
36064 printf("\nstr=%s\n",str);
36065 run_command(str,0);
36066 }
36067 if (dram_data_odt_ohm)
36068 {
36069 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 84 %d 2 0 ",
36070 dram_data_odt_ohm);
36071 printf("\nstr=%s\n",str);
36072 run_command(str,0);
36073 }
36074 //if(dram_data_wr_odt_ohm)
36075 {
36076 sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 174 %d 1 0 ",
36077 dram_data_wr_odt_ohm);
36078 printf("\nstr=%s\n",str);
36079 run_command(str,0);
36080 }
36081
36082 sprintf(str,"g12_d2pll %d 0x12 0x6 0 0x0 0 0 0 0x800000 0 1 ",ddr_frequency);
36083 printf("\nstr=%s\n",str);
36084 run_command(str,0);
36085}
36086
36087return 1;
36088}
36089U_BOOT_CMD(
36090 ddr_auto_scan_drv, 30, 1, do_ddr_auto_scan_drv,
36091 "ddr_test_cmd cmd arg1 arg2 arg3...",
36092 "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
36093 );