Bo Lv | 72d0e90 | 2023-01-02 14:27:34 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef CLK_MESON_H |
| 7 | #define CLK_MESON_H |
| 8 | |
| 9 | /* Gate Structure */ |
| 10 | struct meson_gate { |
| 11 | unsigned int index; |
| 12 | unsigned int reg; |
| 13 | unsigned int bit; |
| 14 | }; |
| 15 | |
| 16 | /* Mux Structure */ |
| 17 | struct meson_mux { |
| 18 | unsigned int index; |
| 19 | unsigned int reg; |
| 20 | unsigned int shift; |
| 21 | unsigned int mask; |
| 22 | unsigned int *table; |
| 23 | unsigned int table_size; |
| 24 | }; |
| 25 | |
| 26 | /* Div Structure */ |
| 27 | struct meson_div { |
| 28 | unsigned int index; |
| 29 | unsigned int reg; |
| 30 | unsigned int shift; |
| 31 | unsigned int width; |
| 32 | unsigned int parent_index; |
| 33 | }; |
| 34 | |
| 35 | /* PLL Parameters */ |
| 36 | struct parm { |
| 37 | u16 reg_off; |
| 38 | u8 shift; |
| 39 | u8 width; |
| 40 | }; |
| 41 | |
| 42 | #define PMASK(width) GENMASK(width - 1, 0) |
| 43 | #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) |
| 44 | #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) |
| 45 | |
| 46 | #define PARM_GET(width, shift, reg) \ |
| 47 | (((reg) & SETPMASK(width, shift)) >> (shift)) |
| 48 | #define PARM_SET(width, shift, reg, val) \ |
| 49 | (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) |
| 50 | |
| 51 | #define CLK81_RATE 166666667 |
| 52 | |
| 53 | struct meson_clk { |
| 54 | void __iomem *addr; |
| 55 | struct clk clkin; |
| 56 | u32 actual_rate; |
| 57 | }; |
| 58 | |
| 59 | /* MPLL Parameters */ |
| 60 | |
| 61 | #define SDM_DEN 16384 |
| 62 | #define N2_MIN 4 |
| 63 | #define N2_MAX 511 |
| 64 | |
| 65 | int meson_set_gate_by_id(struct clk *clk, struct meson_gate *gate_arr, |
| 66 | unsigned int arr_size, bool on); |
| 67 | |
| 68 | int meson_mux_set_parent_by_id(struct clk *clk, struct meson_mux *mux_arr, |
| 69 | unsigned int arr_size, struct clk *parent_clk); |
| 70 | |
| 71 | int meson_clk_get_mux_parent(struct clk *clk, struct meson_mux *mux_arr, |
| 72 | unsigned int arr_size, ulong parent_id); |
| 73 | |
| 74 | int meson_clk_set_div(struct meson_clk *priv, struct meson_div *div, |
| 75 | unsigned int div_val); |
| 76 | |
| 77 | #endif |