blob: f9738bb122844f660f19c5c68cbf1ca269659b7f [file] [log] [blame]
dongqing.li3d3670e2023-10-17 11:15:45 +08001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#ifndef __RAMDUMP_H__
7#define __RAMDUMP_H__
8
9/* PAGE_SHIFT determines the page size */
10#define PAGE_SHIFT 12
11#define PAGE_SIZE ((1) << PAGE_SHIFT)
12
13/* align addr on a size boundary - adjust address up/down if needed */
14#define _ALIGN_UP(addr, size) (((addr) + ((size) - 1)) & (~((typeof(addr))(size) - 1)))
15#define _ALIGN_DOWN(addr, size) ((addr) & (~((typeof(addr))(size) - 1)))
16
17/* align addr on a size boundary - adjust address up if needed */
18#define _ALIGN(addr, size) _ALIGN_UP(addr, size)
19
20/* to align the pointer to the (next) page boundary */
21#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
22
23#define RAMDUMP_STICKY_DATA_MASK (0xFFFF)
24
25extern void check_ramdump(void);
26extern void ramdump_init(void);
27
28extern unsigned long ramdump_base;
29extern unsigned long ramdump_size;
30
31int ramdump_save_compress_data(void);
32
dongqing.li4c9adeb2024-09-14 09:58:20 +000033/* ramdump ddr md5 check */
34#define MD5_BLOCK_SIZE (8 << 20)
35#define MD5_STORE_SIZE (64 << 10)
36#define MD5_PER_ROW_NUM (32)
37#define MD5_BL2E_1_BASE_ADDR (0x00B00000)
38#define MD5_BL2E_2_BASE_ADDR (0x00B10000)
39#define MD5_BL33Z_1_BASE_ADDR (0x00B20000)
40#define MD5_BL33Z_2_BASE_ADDR (0x00B30000)
41#define MD5_BL33X_1_BASE_ADDR (0x00B40000)
42#define MD5_BL33X_2_BASE_ADDR (0x00B50000)
43#define MD5_MAGIC "RAMDUMPMD5"
44
45struct rammd5_info_t {
46 char magic[16];
47 char stage[16];
48 unsigned int block_size;
49 unsigned int ddr_size;
50 unsigned int area1_start;
51 unsigned int area1_end;
52 unsigned int area2_start;
53 unsigned int area2_end;
54};
55
dongqing.li3d3670e2023-10-17 11:15:45 +080056#endif /* __RAMDUMP_H__ */