| Bo Lv | 72d0e90 | 2023-01-02 14:27:34 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __SPICC_H__ |
| 7 | #define __SPICC_H__ |
| 8 | |
| 9 | #define SPICC_DEFAULT_CLK_RATE 166666666 |
| 10 | #define CS_GPIO_MAX 2 |
| 11 | |
| 12 | /* |
| 13 | * @compatible: |
| 14 | * @reg: controller registers address. |
| 15 | * @mem_map: memory_mapped for read operations. |
| 16 | * @clk_rate: |
| 17 | * @clk_set_rate: |
| 18 | * @pinctrl_enable: |
| 19 | * @num_chipselect: |
| 20 | * @cs_gpios: |
| 21 | */ |
| 22 | struct spicc_platdata { |
| 23 | #ifndef CONFIG_OF_CONTROL |
| 24 | char *compatible; |
| 25 | int clk_rate; |
| 26 | int (*clk_set_rate)(int rate); |
| 27 | int (*clk_enable)(bool enable); |
| 28 | int (*pinctrl_enable)(bool enable); |
| 29 | #endif |
| 30 | void __iomem *reg; |
| 31 | const char *cs_gpio_names[CS_GPIO_MAX]; |
| 32 | unsigned int clk_cs_delay; |
| 33 | unsigned int mo_delay; |
| 34 | unsigned int mi_delay; |
| 35 | unsigned int mi_capture_delay; |
| 36 | unsigned int tt_delay; |
| 37 | unsigned int ti_delay; |
| 38 | }; |
| 39 | |
| 40 | #endif /* __SPICC_H__ */ |