blob: a7298e4998c8d29206605d6e5bee1adb35b46203 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Ingo Molnar06fcb0c2006-06-29 02:24:40 -07002#ifndef _LINUX_IRQ_H
3#define _LINUX_IRQ_H
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5/*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/cache.h>
14#include <linux/spinlock.h>
15#include <linux/cpumask.h>
Thomas Gleixner75ffc002014-11-11 21:58:34 +010016#include <linux/irqhandler.h>
Jan Beulich908dcec2006-06-23 02:06:00 -070017#include <linux/irqreturn.h>
Thomas Gleixnerdd3a1db2008-10-16 18:20:58 +020018#include <linux/irqnr.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020019#include <linux/topology.h>
Kevin Cernekee332fd7c2014-11-06 22:44:17 -080020#include <linux/io.h>
Bartosz Golaszewski707188f2017-05-31 18:06:56 +020021#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
23#include <asm/irq.h>
24#include <asm/ptrace.h>
David Howells7d12e782006-10-05 14:55:46 +010025#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Thomas Gleixnerab7798f2011-03-25 16:48:50 +010027struct seq_file;
Paul Gortmakerec53cf22011-09-19 20:33:19 -040028struct module;
Jiang Liu515085e2014-11-06 22:20:17 +080029struct msi_msg;
Dou Liyangbec04032018-12-04 23:51:20 +080030struct irq_affinity_desc;
Marc Zyngier1b7047e2015-03-18 11:01:22 +000031enum irqchip_irq_state;
David Howells57a58a92006-10-05 13:06:34 +010032
Linus Torvalds1da177e2005-04-16 15:20:36 -070033/*
34 * IRQ line status.
Thomas Gleixner6e213612006-07-01 19:29:03 -070035 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010036 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
Thomas Gleixner6e213612006-07-01 19:29:03 -070037 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010038 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000046 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
51 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010052 * IRQ_TYPE_PROBE - Special flag for probing in progress
53 *
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
Geert Uytterhoeven0911f122011-04-10 11:01:51 +020057 * bits are modified via irq_set_irq_type()
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010058 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
62 * request_irq()
Paul Mundt7f1b1242011-04-07 06:01:44 +090063 * IRQ_NOTHREAD - Interrupt cannot be threaded
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010064 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 * request/setup_irq()
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
Mika Westerberg92068d12015-10-01 15:54:52 +030068 * IRQ_NESTED_THREAD - Interrupt nests into another thread
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010069 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010070 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
Thomas Gleixnere9849772015-10-09 23:28:58 +020073 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 */
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010075enum {
76 IRQ_TYPE_NONE = 0x00000000,
77 IRQ_TYPE_EDGE_RISING = 0x00000001,
78 IRQ_TYPE_EDGE_FALLING = 0x00000002,
79 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
80 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
81 IRQ_TYPE_LEVEL_LOW = 0x00000008,
82 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
83 IRQ_TYPE_SENSE_MASK = 0x0000000f,
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000084 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
Thomas Gleixner876dbd42011-02-08 17:28:12 +010085
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010086 IRQ_TYPE_PROBE = 0x00000010,
Thomas Gleixner6e213612006-07-01 19:29:03 -070087
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010088 IRQ_LEVEL = (1 << 8),
89 IRQ_PER_CPU = (1 << 9),
90 IRQ_NOPROBE = (1 << 10),
91 IRQ_NOREQUEST = (1 << 11),
92 IRQ_NOAUTOEN = (1 << 12),
93 IRQ_NO_BALANCING = (1 << 13),
94 IRQ_MOVE_PCNTXT = (1 << 14),
95 IRQ_NESTED_THREAD = (1 << 15),
Paul Mundt7f1b1242011-04-07 06:01:44 +090096 IRQ_NOTHREAD = (1 << 16),
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010097 IRQ_PER_CPU_DEVID = (1 << 17),
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010098 IRQ_IS_POLLED = (1 << 18),
Thomas Gleixnere9849772015-10-09 23:28:58 +020099 IRQ_DISABLE_UNLAZY = (1 << 19),
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +0100100};
Thomas Gleixner950f4422007-02-16 01:27:24 -0800101
Thomas Gleixner44247182010-09-28 10:40:18 +0200102#define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
Thomas Gleixner872434d2011-02-05 16:25:25 +0100104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
Thomas Gleixnere9849772015-10-09 23:28:58 +0200106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
Thomas Gleixner44247182010-09-28 10:40:18 +0200107
Thomas Gleixner8f53f922011-02-08 16:50:00 +0100108#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
109
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100110/*
111 * Return value for chip->irq_set_affinity()
112 *
Jiang Liu9df872f2015-06-03 11:47:50 +0800113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
Jiang Liu2cb62542014-11-06 22:20:18 +0800115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100118 */
119enum {
120 IRQ_SET_MASK_OK = 0,
121 IRQ_SET_MASK_OK_NOCOPY,
Jiang Liu2cb62542014-11-06 22:20:18 +0800122 IRQ_SET_MASK_OK_DONE,
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100123};
124
Eric W. Biederman5b912c12007-01-28 12:52:03 -0700125struct msi_desc;
Grant Likely08a543a2011-07-26 03:19:06 -0600126struct irq_domain;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700127
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700128/**
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800129 * struct irq_common_data - per irq data shared by all irqchips
130 * @state_use_accessors: status information for irq chip functions.
131 * Use accessor functions to deal with it
Jiang Liu449e9ca2015-06-01 16:05:16 +0800132 * @node: node index useful for balancing
Jiang Liuaf7080e2015-06-01 16:05:21 +0800133 * @handler_data: per-IRQ data for the irq_chip methods
Qais Yousef955bfe52015-12-08 13:20:17 +0000134 * @affinity: IRQ affinity on SMP. If this is an IPI
135 * related irq, then this is the mask of the
136 * CPUs to which an IPI can be sent.
Thomas Gleixner0d3f5422017-06-20 01:37:38 +0200137 * @effective_affinity: The effective IRQ affinity on SMP as some irq
138 * chips do not allow multi CPU destinations.
139 * A subset of @affinity.
Jiang Liub2377212015-06-01 16:05:43 +0800140 * @msi_desc: MSI descriptor
Qais Youseff256c9a2015-12-08 13:20:16 +0000141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800142 */
143struct irq_common_data {
Boqun Fengb3542862015-12-29 12:18:48 +0800144 unsigned int __private state_use_accessors;
Jiang Liu449e9ca2015-06-01 16:05:16 +0800145#ifdef CONFIG_NUMA
146 unsigned int node;
147#endif
Jiang Liuaf7080e2015-06-01 16:05:21 +0800148 void *handler_data;
Jiang Liub2377212015-06-01 16:05:43 +0800149 struct msi_desc *msi_desc;
Jiang Liu9df872f2015-06-03 11:47:50 +0800150 cpumask_var_t affinity;
Thomas Gleixner0d3f5422017-06-20 01:37:38 +0200151#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
152 cpumask_var_t effective_affinity;
153#endif
Qais Youseff256c9a2015-12-08 13:20:16 +0000154#ifdef CONFIG_GENERIC_IRQ_IPI
155 unsigned int ipi_offset;
156#endif
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800157};
158
159/**
160 * struct irq_data - per irq chip data passed down to chip functions
Thomas Gleixner966dc732013-05-06 14:30:22 +0000161 * @mask: precomputed bitmask for accessing the chip registers
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000162 * @irq: interrupt number
Grant Likely08a543a2011-07-26 03:19:06 -0600163 * @hwirq: hardware interrupt number, local to the interrupt domain
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800164 * @common: point to data shared by all irqchips
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000165 * @chip: low level interrupt hardware access
Grant Likely08a543a2011-07-26 03:19:06 -0600166 * @domain: Interrupt translation domain; responsible for mapping
167 * between hwirq number and linux irq number.
Jiang Liuf8264e32014-11-06 22:20:14 +0800168 * @parent_data: pointer to parent struct irq_data to support hierarchy
169 * irq_domain
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000170 * @chip_data: platform-specific per-chip private data for the chip
171 * methods, to allow shared chip implementations
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000172 */
173struct irq_data {
Thomas Gleixner966dc732013-05-06 14:30:22 +0000174 u32 mask;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000175 unsigned int irq;
Grant Likely08a543a2011-07-26 03:19:06 -0600176 unsigned long hwirq;
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800177 struct irq_common_data *common;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000178 struct irq_chip *chip;
Grant Likely08a543a2011-07-26 03:19:06 -0600179 struct irq_domain *domain;
Jiang Liuf8264e32014-11-06 22:20:14 +0800180#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
181 struct irq_data *parent_data;
182#endif
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000183 void *chip_data;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000184};
185
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100186/*
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800187 * Bit masks for irq_common_data.state_use_accessors
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100188 *
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
Marc Zyngier08d85f32017-01-17 16:00:48 +0000191 * IRQD_ACTIVATED - Interrupt has already been activated
Thomas Gleixnera0056772011-02-08 17:11:03 +0100192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
193 * IRQD_PER_CPU - Interrupt is per cpu
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100194 * IRQD_AFFINITY_SET - Interrupt affinity was set
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100195 * IRQD_LEVEL - Interrupt is level triggered
Thomas Gleixner7f942262011-02-10 19:46:26 +0100196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
197 * from suspend
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100198 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
199 * context
Thomas Gleixner32f41252011-03-28 14:10:52 +0200200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
201 * IRQD_IRQ_MASKED - Masked state of the interrupt
202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200203 * IRQD_WAKEUP_ARMED - Wakeup mode armed
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
Thomas Gleixner9c255582016-07-04 17:39:23 +0900205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
Thomas Gleixner1bb04012017-06-20 01:37:18 +0200206 * IRQD_IRQ_STARTED - Startup state of the interrupt
Thomas Gleixner54fdf6a2017-06-20 01:37:47 +0200207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
208 * mask. Applies only to affinity managed irqs.
Thomas Gleixnerd52dd442017-06-20 01:37:52 +0200209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
Marc Zyngier4f8413a2017-11-09 14:17:59 +0000210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
Thomas Gleixner69790ba2017-12-29 16:44:34 +0100211 * IRQD_CAN_RESERVE - Can use reservation mode
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100212 */
213enum {
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100214 IRQD_TRIGGER_MASK = 0xf,
Thomas Gleixnera0056772011-02-08 17:11:03 +0100215 IRQD_SETAFFINITY_PENDING = (1 << 8),
Marc Zyngier08d85f32017-01-17 16:00:48 +0000216 IRQD_ACTIVATED = (1 << 9),
Thomas Gleixnera0056772011-02-08 17:11:03 +0100217 IRQD_NO_BALANCING = (1 << 10),
218 IRQD_PER_CPU = (1 << 11),
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100219 IRQD_AFFINITY_SET = (1 << 12),
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100220 IRQD_LEVEL = (1 << 13),
Thomas Gleixner7f942262011-02-10 19:46:26 +0100221 IRQD_WAKEUP_STATE = (1 << 14),
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100222 IRQD_MOVE_PCNTXT = (1 << 15),
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200223 IRQD_IRQ_DISABLED = (1 << 16),
Thomas Gleixner32f41252011-03-28 14:10:52 +0200224 IRQD_IRQ_MASKED = (1 << 17),
225 IRQD_IRQ_INPROGRESS = (1 << 18),
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200226 IRQD_WAKEUP_ARMED = (1 << 19),
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200227 IRQD_FORWARDED_TO_VCPU = (1 << 20),
Thomas Gleixner9c255582016-07-04 17:39:23 +0900228 IRQD_AFFINITY_MANAGED = (1 << 21),
Thomas Gleixner201d7f42017-05-31 11:58:32 +0200229 IRQD_IRQ_STARTED = (1 << 22),
Thomas Gleixner54fdf6a2017-06-20 01:37:47 +0200230 IRQD_MANAGED_SHUTDOWN = (1 << 23),
Thomas Gleixnerd52dd442017-06-20 01:37:52 +0200231 IRQD_SINGLE_TARGET = (1 << 24),
Marc Zyngier4f8413a2017-11-09 14:17:59 +0000232 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
Thomas Gleixner69790ba2017-12-29 16:44:34 +0100233 IRQD_CAN_RESERVE = (1 << 26),
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100234};
235
Boqun Fengb3542862015-12-29 12:18:48 +0800236#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800237
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100238static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
239{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800240 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100241}
242
Thomas Gleixnera0056772011-02-08 17:11:03 +0100243static inline bool irqd_is_per_cpu(struct irq_data *d)
244{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800245 return __irqd_to_state(d) & IRQD_PER_CPU;
Thomas Gleixnera0056772011-02-08 17:11:03 +0100246}
247
248static inline bool irqd_can_balance(struct irq_data *d)
249{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800250 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
Thomas Gleixnera0056772011-02-08 17:11:03 +0100251}
252
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100253static inline bool irqd_affinity_was_set(struct irq_data *d)
254{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800255 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100256}
257
Thomas Gleixneree38c042011-03-28 17:11:13 +0200258static inline void irqd_mark_affinity_was_set(struct irq_data *d)
259{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800260 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
Thomas Gleixneree38c042011-03-28 17:11:13 +0200261}
262
Marc Zyngier4f8413a2017-11-09 14:17:59 +0000263static inline bool irqd_trigger_type_was_set(struct irq_data *d)
264{
265 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
266}
267
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100268static inline u32 irqd_get_trigger_type(struct irq_data *d)
269{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800270 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100271}
272
273/*
Marc Zyngier4f8413a2017-11-09 14:17:59 +0000274 * Must only be called inside irq_chip.irq_set_type() functions or
275 * from the DT/ACPI setup code.
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100276 */
277static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
278{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800279 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
280 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
Marc Zyngier4f8413a2017-11-09 14:17:59 +0000281 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100282}
283
284static inline bool irqd_is_level_type(struct irq_data *d)
285{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800286 return __irqd_to_state(d) & IRQD_LEVEL;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100287}
288
Thomas Gleixnerd52dd442017-06-20 01:37:52 +0200289/*
290 * Must only be called of irqchip.irq_set_affinity() or low level
291 * hieararchy domain allocation functions.
292 */
293static inline void irqd_set_single_target(struct irq_data *d)
294{
295 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
296}
297
298static inline bool irqd_is_single_target(struct irq_data *d)
299{
300 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
301}
302
Thomas Gleixner7f942262011-02-10 19:46:26 +0100303static inline bool irqd_is_wakeup_set(struct irq_data *d)
304{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800305 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
Thomas Gleixner7f942262011-02-10 19:46:26 +0100306}
307
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100308static inline bool irqd_can_move_in_process_context(struct irq_data *d)
309{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800310 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100311}
312
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200313static inline bool irqd_irq_disabled(struct irq_data *d)
314{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800315 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200316}
317
Thomas Gleixner32f41252011-03-28 14:10:52 +0200318static inline bool irqd_irq_masked(struct irq_data *d)
319{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800320 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200321}
322
323static inline bool irqd_irq_inprogress(struct irq_data *d)
324{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800325 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200326}
327
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200328static inline bool irqd_is_wakeup_armed(struct irq_data *d)
329{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800330 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200331}
332
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200333static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
334{
335 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
336}
337
338static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
339{
340 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
341}
342
343static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
344{
345 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
346}
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200347
Thomas Gleixner9c255582016-07-04 17:39:23 +0900348static inline bool irqd_affinity_is_managed(struct irq_data *d)
349{
350 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
351}
352
Marc Zyngier08d85f32017-01-17 16:00:48 +0000353static inline bool irqd_is_activated(struct irq_data *d)
354{
355 return __irqd_to_state(d) & IRQD_ACTIVATED;
356}
357
358static inline void irqd_set_activated(struct irq_data *d)
359{
360 __irqd_to_state(d) |= IRQD_ACTIVATED;
361}
362
363static inline void irqd_clr_activated(struct irq_data *d)
364{
365 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
366}
367
Thomas Gleixner201d7f42017-05-31 11:58:32 +0200368static inline bool irqd_is_started(struct irq_data *d)
369{
370 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
371}
372
Thomas Gleixner761ea382017-06-20 01:37:50 +0200373static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
Thomas Gleixner54fdf6a2017-06-20 01:37:47 +0200374{
375 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
376}
377
Thomas Gleixner69790ba2017-12-29 16:44:34 +0100378static inline void irqd_set_can_reserve(struct irq_data *d)
379{
380 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
381}
382
383static inline void irqd_clr_can_reserve(struct irq_data *d)
384{
385 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
386}
387
388static inline bool irqd_can_reserve(struct irq_data *d)
389{
390 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
391}
392
Boqun Fengb3542862015-12-29 12:18:48 +0800393#undef __irqd_to_state
394
Grant Likelya699e4e2012-04-03 07:11:04 -0600395static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
396{
397 return d->hwirq;
398}
399
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000400/**
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700401 * struct irq_chip - hardware interrupt chip descriptor
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700402 *
Jon Hunterbe45beb2016-06-07 16:12:29 +0100403 * @parent_device: pointer to parent device for irqchip
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700404 * @name: name for /proc/interrupts
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000405 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
406 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
407 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
408 * @irq_disable: disable the interrupt
409 * @irq_ack: start of a new interrupt
410 * @irq_mask: mask an interrupt source
411 * @irq_mask_ack: ack and mask an interrupt source
412 * @irq_unmask: unmask an interrupt source
413 * @irq_eoi: end of interrupt
Thomas Gleixner83979132017-07-27 12:21:11 +0200414 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
415 * argument is true, it tells the driver to
416 * unconditionally apply the affinity setting. Sanity
417 * checks against the supplied affinity mask are not
418 * required. This is used for CPU hotplug where the
419 * target CPU is not yet set in the cpu_online_mask.
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000420 * @irq_retrigger: resend an IRQ to the CPU
421 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
422 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
423 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
424 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
David Daney0fdb4b22011-03-25 12:38:49 -0700425 * @irq_cpu_online: configure an interrupt source for a secondary CPU
426 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700427 * @irq_suspend: function called from core code on suspend once per
428 * chip, when one or more interrupts are installed
429 * @irq_resume: function called from core code on resume once per chip,
430 * when one ore more interrupts are installed
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200431 * @irq_pm_shutdown: function called from core code on shutdown once per chip
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000432 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100433 * @irq_print_chip: optional to print special chip info in show_interrupts
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100434 * @irq_request_resources: optional to request resources before calling
435 * any other callback related to this irq
436 * @irq_release_resources: optional to release resources acquired with
437 * irq_request_resources
Jiang Liu515085e2014-11-06 22:20:17 +0800438 * @irq_compose_msi_msg: optional to compose message content for MSI
Jiang Liu9dde55b2014-11-09 23:10:28 +0800439 * @irq_write_msi_msg: optional to write message content for MSI
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000440 * @irq_get_irqchip_state: return the internal state of an interrupt
441 * @irq_set_irqchip_state: set the internal state of a interrupt
Jiang Liu0a4377d2015-05-19 17:07:14 +0800442 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
Qais Yousef34dc1ae2015-12-08 13:20:21 +0000443 * @ipi_send_single: send a single IPI to destination cpus
444 * @ipi_send_mask: send an IPI to destination cpus in cpumask
Julien Thierryb5259032019-01-31 14:53:58 +0000445 * @irq_nmi_setup: function called from core code before enabling an NMI
446 * @irq_nmi_teardown: function called from core code after disabling an NMI
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100447 * @flags: chip specific flags
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700449struct irq_chip {
Jon Hunterbe45beb2016-06-07 16:12:29 +0100450 struct device *parent_device;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700451 const char *name;
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000452 unsigned int (*irq_startup)(struct irq_data *data);
453 void (*irq_shutdown)(struct irq_data *data);
454 void (*irq_enable)(struct irq_data *data);
455 void (*irq_disable)(struct irq_data *data);
456
457 void (*irq_ack)(struct irq_data *data);
458 void (*irq_mask)(struct irq_data *data);
459 void (*irq_mask_ack)(struct irq_data *data);
460 void (*irq_unmask)(struct irq_data *data);
461 void (*irq_eoi)(struct irq_data *data);
462
463 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
464 int (*irq_retrigger)(struct irq_data *data);
465 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
466 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
467
468 void (*irq_bus_lock)(struct irq_data *data);
469 void (*irq_bus_sync_unlock)(struct irq_data *data);
470
David Daney0fdb4b22011-03-25 12:38:49 -0700471 void (*irq_cpu_online)(struct irq_data *data);
472 void (*irq_cpu_offline)(struct irq_data *data);
473
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200474 void (*irq_suspend)(struct irq_data *data);
475 void (*irq_resume)(struct irq_data *data);
476 void (*irq_pm_shutdown)(struct irq_data *data);
477
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000478 void (*irq_calc_mask)(struct irq_data *data);
479
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100480 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100481 int (*irq_request_resources)(struct irq_data *data);
482 void (*irq_release_resources)(struct irq_data *data);
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100483
Jiang Liu515085e2014-11-06 22:20:17 +0800484 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu9dde55b2014-11-09 23:10:28 +0800485 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu515085e2014-11-06 22:20:17 +0800486
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000487 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
488 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
489
Jiang Liu0a4377d2015-05-19 17:07:14 +0800490 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
491
Qais Yousef34dc1ae2015-12-08 13:20:21 +0000492 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
493 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
494
Julien Thierryb5259032019-01-31 14:53:58 +0000495 int (*irq_nmi_setup)(struct irq_data *data);
496 void (*irq_nmi_teardown)(struct irq_data *data);
497
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100498 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499};
500
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100501/*
502 * irq_chip specific flags
503 *
Thomas Gleixner77694b42011-02-15 10:33:57 +0100504 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
505 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100506 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200507 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
508 * when irq enabled
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530509 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
Thomas Gleixner4f6e4f72014-03-13 15:32:47 +0100510 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
Thomas Gleixner328a4972014-03-13 19:03:51 +0100511 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
Marc Zyngier72a8edc2018-06-22 10:52:48 +0100512 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
Julien Thierryb5259032019-01-31 14:53:58 +0000513 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100514 */
515enum {
516 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
Thomas Gleixner77694b42011-02-15 10:33:57 +0100517 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100518 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200519 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530520 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
Thomas Gleixnerdc9b2292012-07-13 19:29:45 +0200521 IRQCHIP_ONESHOT_SAFE = (1 << 5),
Thomas Gleixner328a4972014-03-13 19:03:51 +0100522 IRQCHIP_EOI_THREADED = (1 << 6),
Marc Zyngier6988e0e2018-05-08 13:14:31 +0100523 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
Julien Thierryb5259032019-01-31 14:53:58 +0000524 IRQCHIP_SUPPORTS_NMI = (1 << 8),
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100525};
526
Thomas Gleixnere1447102010-10-01 16:03:45 +0200527#include <linux/irqdesc.h>
Thomas Gleixnerc6b76742008-10-15 14:31:29 +0200528
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700529/*
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700530 * Pick up the arch-dependent methods:
531 */
532#include <asm/hw_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533
Thomas Gleixnerb683de22010-09-27 20:55:03 +0200534#ifndef NR_IRQS_LEGACY
535# define NR_IRQS_LEGACY 0
536#endif
537
Thomas Gleixner1318a482010-09-27 21:01:37 +0200538#ifndef ARCH_IRQ_INIT_FLAGS
539# define ARCH_IRQ_INIT_FLAGS 0
540#endif
541
Thomas Gleixnerc1594b72011-02-07 22:11:30 +0100542#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
Thomas Gleixner1318a482010-09-27 21:01:37 +0200543
Thomas Gleixnere1447102010-10-01 16:03:45 +0200544struct irqaction;
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700545extern int setup_irq(unsigned int irq, struct irqaction *new);
Magnus Dammcbf94f02009-03-12 21:05:51 +0900546extern void remove_irq(unsigned int irq, struct irqaction *act);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100547extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
548extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549
David Daney0fdb4b22011-03-25 12:38:49 -0700550extern void irq_cpu_online(void);
551extern void irq_cpu_offline(void);
Thomas Gleixner01f8fa42014-04-16 14:36:44 +0000552extern int irq_set_affinity_locked(struct irq_data *data,
553 const struct cpumask *cpumask, bool force);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800554extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
David Daney0fdb4b22011-03-25 12:38:49 -0700555
Thomas Gleixnerc5cb83b2017-06-20 01:37:51 +0200556#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
Yang Yingliangf1e0bb02015-09-24 17:32:13 +0800557extern void irq_migrate_all_off_this_cpu(void);
Thomas Gleixnerc5cb83b2017-06-20 01:37:51 +0200558extern int irq_affinity_online_cpu(unsigned int cpu);
559#else
560# define irq_affinity_online_cpu NULL
561#endif
Yang Yingliangf1e0bb02015-09-24 17:32:13 +0800562
Thomas Gleixner3a3856d02010-10-04 13:47:12 +0200563#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
Thomas Gleixnerd340ebd2018-06-06 14:46:59 +0200564void __irq_move_irq(struct irq_data *data);
565static inline void irq_move_irq(struct irq_data *data)
566{
567 if (unlikely(irqd_is_setaffinity_pending(data)))
568 __irq_move_irq(data);
569}
Thomas Gleixnera4395202011-02-04 18:46:16 +0100570void irq_move_masked_irq(struct irq_data *data);
Thomas Gleixnerf0383c22017-06-20 01:37:29 +0200571void irq_force_complete_move(struct irq_desc *desc);
Thomas Gleixnere1447102010-10-01 16:03:45 +0200572#else
Thomas Gleixnera4395202011-02-04 18:46:16 +0100573static inline void irq_move_irq(struct irq_data *data) { }
574static inline void irq_move_masked_irq(struct irq_data *data) { }
Thomas Gleixnerf0383c22017-06-20 01:37:29 +0200575static inline void irq_force_complete_move(struct irq_desc *desc) { }
Thomas Gleixnere1447102010-10-01 16:03:45 +0200576#endif
Ashok Raj54d5d422005-09-06 15:16:15 -0700577
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578extern int no_irq_affinity;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579
Thomas Gleixner293a7a02012-10-16 15:07:49 -0700580#ifdef CONFIG_HARDIRQS_SW_RESEND
581int irq_set_parent(int irq, int parent_irq);
582#else
583static inline int irq_set_parent(int irq, int parent_irq)
584{
585 return 0;
586}
587#endif
588
Ingo Molnar2e60bbb2006-06-29 02:24:39 -0700589/*
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700590 * Built-in IRQ handlers for various IRQ types,
Krzysztof Halasabebd04c2009-11-15 18:57:24 +0100591 * callable via desc->handle_irq()
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700592 */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200593extern void handle_level_irq(struct irq_desc *desc);
594extern void handle_fasteoi_irq(struct irq_desc *desc);
595extern void handle_edge_irq(struct irq_desc *desc);
596extern void handle_edge_eoi_irq(struct irq_desc *desc);
597extern void handle_simple_irq(struct irq_desc *desc);
Keith Buschedd14cf2016-06-17 16:00:20 -0600598extern void handle_untracked_irq(struct irq_desc *desc);
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200599extern void handle_percpu_irq(struct irq_desc *desc);
600extern void handle_percpu_devid_irq(struct irq_desc *desc);
601extern void handle_bad_irq(struct irq_desc *desc);
Mark Brown31b47cf2009-08-24 20:28:04 +0100602extern void handle_nested_irq(unsigned int irq);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700603
Jiang Liu515085e2014-11-06 22:20:17 +0800604extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
Jon Hunterbe45beb2016-06-07 16:12:29 +0100605extern int irq_chip_pm_get(struct irq_data *data);
606extern int irq_chip_pm_put(struct irq_data *data);
Jiang Liu85f08c12014-11-06 22:20:16 +0800607#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
David Daney7703b082017-08-17 17:53:31 -0700608extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
609extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
Stefan Agner3cfeffc2015-05-16 11:44:14 +0200610extern void irq_chip_enable_parent(struct irq_data *data);
611extern void irq_chip_disable_parent(struct irq_data *data);
Jiang Liu85f08c12014-11-06 22:20:16 +0800612extern void irq_chip_ack_parent(struct irq_data *data);
613extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
Yingjoe Chen56e8aba2014-11-13 23:37:05 +0800614extern void irq_chip_mask_parent(struct irq_data *data);
615extern void irq_chip_unmask_parent(struct irq_data *data);
616extern void irq_chip_eoi_parent(struct irq_data *data);
617extern int irq_chip_set_affinity_parent(struct irq_data *data,
618 const struct cpumask *dest,
619 bool force);
Marc Zyngier08b55e22015-03-11 15:43:43 +0000620extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800621extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
622 void *vcpu_info);
Grygorii Strashkob7560de2015-08-14 15:20:26 +0300623extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
Jiang Liu85f08c12014-11-06 22:20:16 +0800624#endif
625
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700626/* Handling of unhandled and spurious interrupts: */
Jiang Liu0dcdbc92015-06-04 12:13:28 +0800627extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628
Thomas Gleixnera4633adc2006-06-29 02:24:48 -0700629
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700630/* Enable/disable irq debugging output: */
631extern int noirqdebug_setup(char *str);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700633/* Checks whether the interrupt can be requested by request_irq(): */
634extern int can_request_irq(unsigned int irq, unsigned long irqflags);
635
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100636/* Dummy irq-chip implementations: */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700637extern struct irq_chip no_irq_chip;
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100638extern struct irq_chip dummy_irq_chip;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700639
640extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100641irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
Ingo Molnara460e742006-10-17 00:10:03 -0700642 irq_flow_handler_t handle, const char *name);
643
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100644static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
645 irq_flow_handler_t handle)
646{
647 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
648}
649
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100650extern int irq_set_percpu_devid(unsigned int irq);
Marc Zyngier222df542016-04-11 09:57:52 +0100651extern int irq_set_percpu_devid_partition(unsigned int irq,
652 const struct cpumask *affinity);
653extern int irq_get_percpu_devid_partition(unsigned int irq,
654 struct cpumask *affinity);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100655
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700656extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100657__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
Ingo Molnara460e742006-10-17 00:10:03 -0700658 const char *name);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700659
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700660static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100661irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700662{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100663 __irq_set_handler(irq, handle, 0, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700664}
665
666/*
667 * Set a highlevel chained flow handler for a given IRQ.
668 * (a chained handler is automatically enabled and set to
Paul Mundt7f1b1242011-04-07 06:01:44 +0900669 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700670 */
671static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100672irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700673{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100674 __irq_set_handler(irq, handle, 1, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700675}
676
Russell King3b0f95b2015-06-16 23:06:20 +0100677/*
678 * Set a highlevel chained flow handler and its data for a given IRQ.
679 * (a chained handler is automatically enabled and set to
680 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
681 */
682void
683irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
684 void *data);
685
Thomas Gleixner44247182010-09-28 10:40:18 +0200686void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
687
688static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
689{
690 irq_modify_status(irq, 0, set);
691}
692
693static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
694{
695 irq_modify_status(irq, clr, 0);
696}
697
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100698static inline void irq_set_noprobe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200699{
700 irq_modify_status(irq, 0, IRQ_NOPROBE);
701}
702
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100703static inline void irq_set_probe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200704{
705 irq_modify_status(irq, IRQ_NOPROBE, 0);
706}
Ralf Baechle46f4f8f2008-02-08 04:22:01 -0800707
Paul Mundt7f1b1242011-04-07 06:01:44 +0900708static inline void irq_set_nothread(unsigned int irq)
709{
710 irq_modify_status(irq, 0, IRQ_NOTHREAD);
711}
712
713static inline void irq_set_thread(unsigned int irq)
714{
715 irq_modify_status(irq, IRQ_NOTHREAD, 0);
716}
717
Thomas Gleixner6f91a522011-02-14 13:33:16 +0100718static inline void irq_set_nested_thread(unsigned int irq, bool nest)
719{
720 if (nest)
721 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
722 else
723 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
724}
725
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100726static inline void irq_set_percpu_devid_flags(unsigned int irq)
727{
728 irq_set_status_flags(irq,
729 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
730 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
731}
732
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700733/* Set/get chip/data for an IRQ: */
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100734extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
735extern int irq_set_handler_data(unsigned int irq, void *data);
736extern int irq_set_chip_data(unsigned int irq, void *data);
737extern int irq_set_irq_type(unsigned int irq, unsigned int type);
738extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
Alexander Gordeev51906e72012-11-19 16:01:29 +0100739extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
740 struct msi_desc *entry);
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200741extern struct irq_data *irq_get_irq_data(unsigned int irq);
Thomas Gleixnerdd87eb32006-06-29 02:24:53 -0700742
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100743static inline struct irq_chip *irq_get_chip(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200744{
745 struct irq_data *d = irq_get_irq_data(irq);
746 return d ? d->chip : NULL;
747}
748
749static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
750{
751 return d->chip;
752}
753
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100754static inline void *irq_get_chip_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200755{
756 struct irq_data *d = irq_get_irq_data(irq);
757 return d ? d->chip_data : NULL;
758}
759
760static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
761{
762 return d->chip_data;
763}
764
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100765static inline void *irq_get_handler_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200766{
767 struct irq_data *d = irq_get_irq_data(irq);
Jiang Liuaf7080e2015-06-01 16:05:21 +0800768 return d ? d->common->handler_data : NULL;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200769}
770
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100771static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200772{
Jiang Liuaf7080e2015-06-01 16:05:21 +0800773 return d->common->handler_data;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200774}
775
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100776static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200777{
778 struct irq_data *d = irq_get_irq_data(irq);
Jiang Liub2377212015-06-01 16:05:43 +0800779 return d ? d->common->msi_desc : NULL;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200780}
781
Jiang Liuc391f262015-06-01 16:05:41 +0800782static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200783{
Jiang Liub2377212015-06-01 16:05:43 +0800784 return d->common->msi_desc;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200785}
786
Javier Martinez Canillas1f6236b2013-06-14 18:40:43 +0200787static inline u32 irq_get_trigger_type(unsigned int irq)
788{
789 struct irq_data *d = irq_get_irq_data(irq);
790 return d ? irqd_get_trigger_type(d) : 0;
791}
792
Jiang Liu449e9ca2015-06-01 16:05:16 +0800793static inline int irq_common_data_get_node(struct irq_common_data *d)
794{
795#ifdef CONFIG_NUMA
796 return d->node;
797#else
798 return 0;
799#endif
800}
801
Jiang Liu67830112015-06-01 16:05:13 +0800802static inline int irq_data_get_node(struct irq_data *d)
803{
Jiang Liu449e9ca2015-06-01 16:05:16 +0800804 return irq_common_data_get_node(d->common);
Jiang Liu67830112015-06-01 16:05:13 +0800805}
806
Jiang Liuc64301a2015-06-01 16:05:23 +0800807static inline struct cpumask *irq_get_affinity_mask(int irq)
808{
809 struct irq_data *d = irq_get_irq_data(irq);
810
Jiang Liu9df872f2015-06-03 11:47:50 +0800811 return d ? d->common->affinity : NULL;
Jiang Liuc64301a2015-06-01 16:05:23 +0800812}
813
814static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
815{
Jiang Liu9df872f2015-06-03 11:47:50 +0800816 return d->common->affinity;
Jiang Liuc64301a2015-06-01 16:05:23 +0800817}
818
Thomas Gleixner0d3f5422017-06-20 01:37:38 +0200819#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
820static inline
821struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
822{
Thomas Gleixner05519682017-09-21 11:54:44 +0200823 return d->common->effective_affinity;
Thomas Gleixner0d3f5422017-06-20 01:37:38 +0200824}
825static inline void irq_data_update_effective_affinity(struct irq_data *d,
826 const struct cpumask *m)
827{
828 cpumask_copy(d->common->effective_affinity, m);
829}
830#else
831static inline void irq_data_update_effective_affinity(struct irq_data *d,
832 const struct cpumask *m)
833{
834}
835static inline
836struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
837{
838 return d->common->affinity;
839}
840#endif
841
Thomas Gleixner62a08ae2014-04-24 09:50:53 +0200842unsigned int arch_dynirq_lower_bound(unsigned int from);
843
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200844int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
Dou Liyangbec04032018-12-04 23:51:20 +0800845 struct module *owner,
846 const struct irq_affinity_desc *affinity);
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200847
Bartosz Golaszewski2b5e7732017-02-10 13:23:23 +0100848int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
849 unsigned int cnt, int node, struct module *owner,
Dou Liyangbec04032018-12-04 23:51:20 +0800850 const struct irq_affinity_desc *affinity);
Bartosz Golaszewski2b5e7732017-02-10 13:23:23 +0100851
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400852/* use macros to avoid needing export.h for THIS_MODULE */
853#define irq_alloc_descs(irq, from, cnt, node) \
Thomas Gleixner06ee6d52016-07-04 17:39:24 +0900854 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400855
856#define irq_alloc_desc(node) \
857 irq_alloc_descs(-1, 0, 1, node)
858
859#define irq_alloc_desc_at(at, node) \
860 irq_alloc_descs(at, at, 1, node)
861
862#define irq_alloc_desc_from(from, node) \
863 irq_alloc_descs(-1, from, 1, node)
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200864
Alexander Gordeev51906e72012-11-19 16:01:29 +0100865#define irq_alloc_descs_from(from, cnt, node) \
866 irq_alloc_descs(-1, from, cnt, node)
867
Bartosz Golaszewski2b5e7732017-02-10 13:23:23 +0100868#define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
869 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
870
871#define devm_irq_alloc_desc(dev, node) \
872 devm_irq_alloc_descs(dev, -1, 0, 1, node)
873
874#define devm_irq_alloc_desc_at(dev, at, node) \
875 devm_irq_alloc_descs(dev, at, at, 1, node)
876
877#define devm_irq_alloc_desc_from(dev, from, node) \
878 devm_irq_alloc_descs(dev, -1, from, 1, node)
879
880#define devm_irq_alloc_descs_from(dev, from, cnt, node) \
881 devm_irq_alloc_descs(dev, -1, from, cnt, node)
882
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200883void irq_free_descs(unsigned int irq, unsigned int cnt);
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200884static inline void irq_free_desc(unsigned int irq)
885{
886 irq_free_descs(irq, 1);
887}
888
Thomas Gleixner7b6ef122014-05-07 15:44:05 +0000889#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
890unsigned int irq_alloc_hwirqs(int cnt, int node);
891static inline unsigned int irq_alloc_hwirq(int node)
892{
893 return irq_alloc_hwirqs(1, node);
894}
895void irq_free_hwirqs(unsigned int from, int cnt);
896static inline void irq_free_hwirq(unsigned int irq)
897{
898 return irq_free_hwirqs(irq, 1);
899}
900int arch_setup_hwirq(unsigned int irq, int node);
901void arch_teardown_hwirq(unsigned int irq);
902#endif
903
Thomas Gleixnerc940e012014-05-07 15:44:22 +0000904#ifdef CONFIG_GENERIC_IRQ_LEGACY
905void irq_init_desc(unsigned int irq);
906#endif
907
Thomas Gleixner7d828062011-04-03 11:42:53 +0200908/**
909 * struct irq_chip_regs - register offsets for struct irq_gci
910 * @enable: Enable register offset to reg_base
911 * @disable: Disable register offset to reg_base
912 * @mask: Mask register offset to reg_base
913 * @ack: Ack register offset to reg_base
914 * @eoi: Eoi register offset to reg_base
915 * @type: Type configuration register offset to reg_base
916 * @polarity: Polarity configuration register offset to reg_base
917 */
918struct irq_chip_regs {
919 unsigned long enable;
920 unsigned long disable;
921 unsigned long mask;
922 unsigned long ack;
923 unsigned long eoi;
924 unsigned long type;
925 unsigned long polarity;
926};
927
928/**
929 * struct irq_chip_type - Generic interrupt chip instance for a flow type
930 * @chip: The real interrupt chip which provides the callbacks
931 * @regs: Register offsets for this chip
932 * @handler: Flow handler associated with this chip
933 * @type: Chip can handle these flow types
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000934 * @mask_cache_priv: Cached mask register private to the chip type
935 * @mask_cache: Pointer to cached mask register
Thomas Gleixner7d828062011-04-03 11:42:53 +0200936 *
937 * A irq_generic_chip can have several instances of irq_chip_type when
938 * it requires different functions and register offsets for different
939 * flow types.
940 */
941struct irq_chip_type {
942 struct irq_chip chip;
943 struct irq_chip_regs regs;
944 irq_flow_handler_t handler;
945 u32 type;
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000946 u32 mask_cache_priv;
947 u32 *mask_cache;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200948};
949
950/**
951 * struct irq_chip_generic - Generic irq chip data structure
952 * @lock: Lock to protect register and cache data access
953 * @reg_base: Register base address (virtual)
Kevin Cernekee2b280372014-11-06 22:44:18 -0800954 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
955 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700956 * @suspend: Function called from core code on suspend once per
957 * chip; can be useful instead of irq_chip::suspend to
958 * handle chip details even when no interrupts are in use
959 * @resume: Function called from core code on resume once per chip;
960 * can be useful instead of irq_chip::suspend to handle
961 * chip details even when no interrupts are in use
Thomas Gleixner7d828062011-04-03 11:42:53 +0200962 * @irq_base: Interrupt base nr for this chip
963 * @irq_cnt: Number of interrupts handled by this chip
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000964 * @mask_cache: Cached mask register shared between all chip types
Thomas Gleixner7d828062011-04-03 11:42:53 +0200965 * @type_cache: Cached type register
966 * @polarity_cache: Cached polarity register
967 * @wake_enabled: Interrupt can wakeup from suspend
968 * @wake_active: Interrupt is marked as an wakeup from suspend source
969 * @num_ct: Number of available irq_chip_type instances (usually 1)
970 * @private: Private data for non generic chip callbacks
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000971 * @installed: bitfield to denote installed interrupts
Grant Likelye8bd8342013-05-29 03:10:52 +0100972 * @unused: bitfield to denote unused interrupts
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000973 * @domain: irq domain pointer
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200974 * @list: List head for keeping track of instances
Thomas Gleixner7d828062011-04-03 11:42:53 +0200975 * @chip_types: Array of interrupt irq_chip_types
976 *
977 * Note, that irq_chip_generic can have multiple irq_chip_type
978 * implementations which can be associated to a particular irq line of
979 * an irq_chip_generic instance. That allows to share and protect
980 * state in an irq_chip_generic instance when we need to implement
981 * different flow mechanisms (level/edge) for it.
982 */
983struct irq_chip_generic {
984 raw_spinlock_t lock;
985 void __iomem *reg_base;
Kevin Cernekee2b280372014-11-06 22:44:18 -0800986 u32 (*reg_readl)(void __iomem *addr);
987 void (*reg_writel)(u32 val, void __iomem *addr);
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700988 void (*suspend)(struct irq_chip_generic *gc);
989 void (*resume)(struct irq_chip_generic *gc);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200990 unsigned int irq_base;
991 unsigned int irq_cnt;
992 u32 mask_cache;
993 u32 type_cache;
994 u32 polarity_cache;
995 u32 wake_enabled;
996 u32 wake_active;
997 unsigned int num_ct;
998 void *private;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000999 unsigned long installed;
Grant Likelye8bd8342013-05-29 03:10:52 +01001000 unsigned long unused;
Thomas Gleixner088f40b2013-05-06 14:30:27 +00001001 struct irq_domain *domain;
Thomas Gleixnercfefd212011-04-15 22:36:08 +02001002 struct list_head list;
Thomas Gleixner7d828062011-04-03 11:42:53 +02001003 struct irq_chip_type chip_types[0];
1004};
1005
1006/**
1007 * enum irq_gc_flags - Initialization flags for generic irq chips
1008 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1009 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1010 * irq chips which need to call irq_set_wake() on
1011 * the parent irq. Usually GPIO implementations
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +00001012 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
Thomas Gleixner966dc732013-05-06 14:30:22 +00001013 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
Kevin Cernekeeb7905592014-11-06 22:44:19 -08001014 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
Thomas Gleixner7d828062011-04-03 11:42:53 +02001015 */
1016enum irq_gc_flags {
1017 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1018 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +00001019 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
Thomas Gleixner966dc732013-05-06 14:30:22 +00001020 IRQ_GC_NO_MASK = 1 << 3,
Kevin Cernekeeb7905592014-11-06 22:44:19 -08001021 IRQ_GC_BE_IO = 1 << 4,
Thomas Gleixner7d828062011-04-03 11:42:53 +02001022};
1023
Thomas Gleixner088f40b2013-05-06 14:30:27 +00001024/*
1025 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1026 * @irqs_per_chip: Number of interrupts per chip
1027 * @num_chips: Number of chips
1028 * @irq_flags_to_set: IRQ* flags to set on irq setup
1029 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1030 * @gc_flags: Generic chip specific setup flags
1031 * @gc: Array of pointers to generic interrupt chips
1032 */
1033struct irq_domain_chip_generic {
1034 unsigned int irqs_per_chip;
1035 unsigned int num_chips;
1036 unsigned int irq_flags_to_clear;
1037 unsigned int irq_flags_to_set;
1038 enum irq_gc_flags gc_flags;
1039 struct irq_chip_generic *gc[0];
1040};
1041
Thomas Gleixner7d828062011-04-03 11:42:53 +02001042/* Generic chip callback functions */
1043void irq_gc_noop(struct irq_data *d);
1044void irq_gc_mask_disable_reg(struct irq_data *d);
1045void irq_gc_mask_set_bit(struct irq_data *d);
1046void irq_gc_mask_clr_bit(struct irq_data *d);
1047void irq_gc_unmask_enable_reg(struct irq_data *d);
Simon Guinot659fb322011-07-06 12:41:31 -04001048void irq_gc_ack_set_bit(struct irq_data *d);
1049void irq_gc_ack_clr_bit(struct irq_data *d);
Doug Berger20608922017-10-04 14:26:26 +02001050void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
Thomas Gleixner7d828062011-04-03 11:42:53 +02001051void irq_gc_eoi(struct irq_data *d);
1052int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1053
1054/* Setup functions for irq_chip_generic */
Boris BREZILLONa5152c82014-07-10 19:14:16 +02001055int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1056 irq_hw_number_t hw_irq);
Thomas Gleixner7d828062011-04-03 11:42:53 +02001057struct irq_chip_generic *
1058irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1059 void __iomem *reg_base, irq_flow_handler_t handler);
1060void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1061 enum irq_gc_flags flags, unsigned int clr,
1062 unsigned int set);
1063int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
Thomas Gleixnercfefd212011-04-15 22:36:08 +02001064void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1065 unsigned int clr, unsigned int set);
Thomas Gleixner7d828062011-04-03 11:42:53 +02001066
Bartosz Golaszewski1c3e3632017-05-31 18:06:59 +02001067struct irq_chip_generic *
1068devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1069 unsigned int irq_base, void __iomem *reg_base,
1070 irq_flow_handler_t handler);
Bartosz Golaszewski30fd8fc2017-05-31 18:07:00 +02001071int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1072 u32 msk, enum irq_gc_flags flags,
1073 unsigned int clr, unsigned int set);
Bartosz Golaszewski1c3e3632017-05-31 18:06:59 +02001074
Thomas Gleixner088f40b2013-05-06 14:30:27 +00001075struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
Thomas Gleixner088f40b2013-05-06 14:30:27 +00001076
Sebastian Friasf88eecf2016-08-16 16:05:08 +02001077int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1078 int num_ct, const char *name,
1079 irq_flow_handler_t handler,
1080 unsigned int clr, unsigned int set,
1081 enum irq_gc_flags flags);
1082
1083#define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1084 handler, clr, set, flags) \
1085({ \
1086 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1087 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1088 handler, clr, set, flags); \
1089})
Thomas Gleixner088f40b2013-05-06 14:30:27 +00001090
Bartosz Golaszewski707188f2017-05-31 18:06:56 +02001091static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1092{
1093 kfree(gc);
1094}
1095
Bartosz Golaszewski32bb6cb2017-05-31 18:06:57 +02001096static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1097 u32 msk, unsigned int clr,
1098 unsigned int set)
1099{
1100 irq_remove_generic_chip(gc, msk, clr, set);
1101 irq_free_generic_chip(gc);
1102}
1103
Thomas Gleixner7d828062011-04-03 11:42:53 +02001104static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1105{
1106 return container_of(d->chip, struct irq_chip_type, chip);
1107}
1108
1109#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1110
1111#ifdef CONFIG_SMP
1112static inline void irq_gc_lock(struct irq_chip_generic *gc)
1113{
1114 raw_spin_lock(&gc->lock);
1115}
1116
1117static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1118{
1119 raw_spin_unlock(&gc->lock);
1120}
1121#else
1122static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1123static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1124#endif
1125
Boris Brezillonebf9ff72016-09-13 15:58:28 +02001126/*
1127 * The irqsave variants are for usage in non interrupt code. Do not use
1128 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1129 */
1130#define irq_gc_lock_irqsave(gc, flags) \
1131 raw_spin_lock_irqsave(&(gc)->lock, flags)
1132
1133#define irq_gc_unlock_irqrestore(gc, flags) \
1134 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1135
Kevin Cernekee332fd7c2014-11-06 22:44:17 -08001136static inline void irq_reg_writel(struct irq_chip_generic *gc,
1137 u32 val, int reg_offset)
1138{
Kevin Cernekee2b280372014-11-06 22:44:18 -08001139 if (gc->reg_writel)
1140 gc->reg_writel(val, gc->reg_base + reg_offset);
1141 else
1142 writel(val, gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -08001143}
1144
1145static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1146 int reg_offset)
1147{
Kevin Cernekee2b280372014-11-06 22:44:18 -08001148 if (gc->reg_readl)
1149 return gc->reg_readl(gc->reg_base + reg_offset);
1150 else
1151 return readl(gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -08001152}
1153
Thomas Gleixner2f75d9e2017-09-13 23:29:14 +02001154struct irq_matrix;
1155struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1156 unsigned int alloc_start,
1157 unsigned int alloc_end);
1158void irq_matrix_online(struct irq_matrix *m);
1159void irq_matrix_offline(struct irq_matrix *m);
1160void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1161int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1162void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
Dou Liyang76f99ae2018-09-09 01:58:38 +08001163int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1164 unsigned int *mapped_cpu);
Thomas Gleixner2f75d9e2017-09-13 23:29:14 +02001165void irq_matrix_reserve(struct irq_matrix *m);
1166void irq_matrix_remove_reserved(struct irq_matrix *m);
1167int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1168 bool reserved, unsigned int *mapped_cpu);
1169void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1170 unsigned int bit, bool managed);
1171void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1172unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1173unsigned int irq_matrix_allocated(struct irq_matrix *m);
1174unsigned int irq_matrix_reserved(struct irq_matrix *m);
1175void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1176
Qais Yousefd17bf242015-12-08 13:20:19 +00001177/* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1178#define INVALID_HWIRQ (~0UL)
Qais Youseff9bce792015-12-08 13:20:20 +00001179irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
Qais Yousef3b8e29a2015-12-08 13:20:22 +00001180int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1181int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1182int ipi_send_single(unsigned int virq, unsigned int cpu);
1183int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
Qais Yousefd17bf242015-12-08 13:20:19 +00001184
Palmer Dabbeltcaacdbf2018-03-07 15:57:27 -08001185#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1186/*
1187 * Registers a generic IRQ handling function as the top-level IRQ handler in
1188 * the system, which is generally the first C code called from an assembly
1189 * architecture-specific interrupt handler.
1190 *
1191 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1192 * registered.
1193 */
1194int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1195
1196/*
1197 * Allows interrupt handlers to find the irqchip that's been registered as the
1198 * top-level IRQ handler.
1199 */
1200extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1201#endif
1202
Ingo Molnar06fcb0c2006-06-29 02:24:40 -07001203#endif /* _LINUX_IRQ_H */