blob: 219dd674dc92a52c98fc7d5a7b6293ba3befaa34 [file] [log] [blame]
Roland Stigge2944a442012-06-07 12:22:15 +02001/*
2 * NXP LPC32XX NAND SLC driver
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright © 2011 NXP Semiconductors
9 * Copyright © 2012 Roland Stigge
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/delay.h>
31#include <linux/io.h>
32#include <linux/mm.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmaengine.h>
35#include <linux/mtd/nand_ecc.h>
36#include <linux/gpio.h>
37#include <linux/of.h>
38#include <linux/of_mtd.h>
39#include <linux/of_gpio.h>
Roland Stiggede20c222012-08-16 15:15:34 +020040#include <linux/mtd/lpc32xx_slc.h>
Roland Stigge2944a442012-06-07 12:22:15 +020041
42#define LPC32XX_MODNAME "lpc32xx-nand"
43
44/**********************************************************************
45* SLC NAND controller register offsets
46**********************************************************************/
47
48#define SLC_DATA(x) (x + 0x000)
49#define SLC_ADDR(x) (x + 0x004)
50#define SLC_CMD(x) (x + 0x008)
51#define SLC_STOP(x) (x + 0x00C)
52#define SLC_CTRL(x) (x + 0x010)
53#define SLC_CFG(x) (x + 0x014)
54#define SLC_STAT(x) (x + 0x018)
55#define SLC_INT_STAT(x) (x + 0x01C)
56#define SLC_IEN(x) (x + 0x020)
57#define SLC_ISR(x) (x + 0x024)
58#define SLC_ICR(x) (x + 0x028)
59#define SLC_TAC(x) (x + 0x02C)
60#define SLC_TC(x) (x + 0x030)
61#define SLC_ECC(x) (x + 0x034)
62#define SLC_DMA_DATA(x) (x + 0x038)
63
64/**********************************************************************
65* slc_ctrl register definitions
66**********************************************************************/
67#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
68#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
69#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
70
71/**********************************************************************
72* slc_cfg register definitions
73**********************************************************************/
74#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
75#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
76#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
77#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
78#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
79#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
80
81/**********************************************************************
82* slc_stat register definitions
83**********************************************************************/
84#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
85#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
86#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
87
88/**********************************************************************
89* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
90**********************************************************************/
91#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
92#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
93
94/**********************************************************************
95* slc_tac register definitions
96**********************************************************************/
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +030097/* Computation of clock cycles on basis of controller and device clock rates */
Vladimir Zapolskiyd54e8802015-10-01 02:23:37 +030098#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +030099
Roland Stigge2944a442012-06-07 12:22:15 +0200100/* Clock setting for RDY write sample wait time in 2*n clocks */
101#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
102/* Write pulse width in clock cycles, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300103#define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24))
Roland Stigge2944a442012-06-07 12:22:15 +0200104/* Write hold time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300105#define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20))
Roland Stigge2944a442012-06-07 12:22:15 +0200106/* Write setup time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300107#define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16))
Roland Stigge2944a442012-06-07 12:22:15 +0200108/* Clock setting for RDY read sample wait time in 2*n clocks */
109#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
110/* Read pulse width in clock cycles, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300111#define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8))
Roland Stigge2944a442012-06-07 12:22:15 +0200112/* Read hold time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300113#define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4))
Roland Stigge2944a442012-06-07 12:22:15 +0200114/* Read setup time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300115#define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0))
Roland Stigge2944a442012-06-07 12:22:15 +0200116
117/**********************************************************************
118* slc_ecc register definitions
119**********************************************************************/
120/* ECC line party fetch macro */
121#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
122#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
123
124/*
125 * DMA requires storage space for the DMA local buffer and the hardware ECC
126 * storage area. The DMA local buffer is only used if DMA mapping fails
127 * during runtime.
128 */
129#define LPC32XX_DMA_DATA_SIZE 4096
130#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
131
132/* Number of bytes used for ECC stored in NAND per 256 bytes */
133#define LPC32XX_SLC_DEV_ECC_BYTES 3
134
135/*
136 * If the NAND base clock frequency can't be fetched, this frequency will be
137 * used instead as the base. This rate is used to setup the timing registers
138 * used for NAND accesses.
139 */
140#define LPC32XX_DEF_BUS_RATE 133250000
141
142/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
143#define LPC32XX_DMA_TIMEOUT 100
144
145/*
146 * NAND ECC Layout for small page NAND devices
147 * Note: For large and huge page devices, the default layouts are used
148 */
Boris Brezillond50b5232016-02-03 20:02:41 +0100149static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
150 struct mtd_oob_region *oobregion)
151{
152 if (section)
153 return -ERANGE;
154
155 oobregion->length = 6;
156 oobregion->offset = 10;
157
158 return 0;
159}
160
161static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
162 struct mtd_oob_region *oobregion)
163{
164 if (section > 1)
165 return -ERANGE;
166
167 if (!section) {
168 oobregion->offset = 0;
169 oobregion->length = 4;
170 } else {
171 oobregion->offset = 6;
172 oobregion->length = 4;
173 }
174
175 return 0;
176}
177
178static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
179 .ecc = lpc32xx_ooblayout_ecc,
180 .free = lpc32xx_ooblayout_free,
Roland Stigge2944a442012-06-07 12:22:15 +0200181};
182
183static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
184static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
185
186/*
187 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
188 * Note: Large page devices used the default layout
189 */
190static struct nand_bbt_descr bbt_smallpage_main_descr = {
191 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
192 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
193 .offs = 0,
194 .len = 4,
195 .veroffs = 6,
196 .maxblocks = 4,
197 .pattern = bbt_pattern
198};
199
200static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
201 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
202 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
203 .offs = 0,
204 .len = 4,
205 .veroffs = 6,
206 .maxblocks = 4,
207 .pattern = mirror_pattern
208};
209
210/*
211 * NAND platform configuration structure
212 */
213struct lpc32xx_nand_cfg_slc {
214 uint32_t wdr_clks;
215 uint32_t wwidth;
216 uint32_t whold;
217 uint32_t wsetup;
218 uint32_t rdr_clks;
219 uint32_t rwidth;
220 uint32_t rhold;
221 uint32_t rsetup;
222 bool use_bbt;
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200223 int wp_gpio;
Roland Stigge2944a442012-06-07 12:22:15 +0200224 struct mtd_partition *parts;
225 unsigned num_parts;
226};
227
228struct lpc32xx_nand_host {
229 struct nand_chip nand_chip;
Roland Stiggede20c222012-08-16 15:15:34 +0200230 struct lpc32xx_slc_platform_data *pdata;
Roland Stigge2944a442012-06-07 12:22:15 +0200231 struct clk *clk;
Roland Stigge2944a442012-06-07 12:22:15 +0200232 void __iomem *io_base;
233 struct lpc32xx_nand_cfg_slc *ncfg;
234
235 struct completion comp;
236 struct dma_chan *dma_chan;
237 uint32_t dma_buf_len;
238 struct dma_slave_config dma_slave_config;
239 struct scatterlist sgl;
240
241 /*
242 * DMA and CPU addresses of ECC work area and data buffer
243 */
244 uint32_t *ecc_buf;
245 uint8_t *data_buf;
246 dma_addr_t io_base_dma;
247};
248
249static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
250{
251 uint32_t clkrate, tmp;
252
253 /* Reset SLC controller */
254 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
255 udelay(1000);
256
257 /* Basic setup */
258 writel(0, SLC_CFG(host->io_base));
259 writel(0, SLC_IEN(host->io_base));
260 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
261 SLC_ICR(host->io_base));
262
263 /* Get base clock for SLC block */
264 clkrate = clk_get_rate(host->clk);
265 if (clkrate == 0)
266 clkrate = LPC32XX_DEF_BUS_RATE;
267
268 /* Compute clock setup values */
269 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300270 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
271 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
272 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
Roland Stigge2944a442012-06-07 12:22:15 +0200273 SLCTAC_RDR(host->ncfg->rdr_clks) |
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300274 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
275 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
276 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
Roland Stigge2944a442012-06-07 12:22:15 +0200277 writel(tmp, SLC_TAC(host->io_base));
278}
279
280/*
281 * Hardware specific access to control lines
282 */
283static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
284 unsigned int ctrl)
285{
286 uint32_t tmp;
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100287 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100288 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200289
290 /* Does CE state need to be changed? */
291 tmp = readl(SLC_CFG(host->io_base));
292 if (ctrl & NAND_NCE)
293 tmp |= SLCCFG_CE_LOW;
294 else
295 tmp &= ~SLCCFG_CE_LOW;
296 writel(tmp, SLC_CFG(host->io_base));
297
298 if (cmd != NAND_CMD_NONE) {
299 if (ctrl & NAND_CLE)
300 writel(cmd, SLC_CMD(host->io_base));
301 else
302 writel(cmd, SLC_ADDR(host->io_base));
303 }
304}
305
306/*
307 * Read the Device Ready pin
308 */
309static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
310{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100311 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100312 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200313 int rdy = 0;
314
315 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
316 rdy = 1;
317
318 return rdy;
319}
320
321/*
322 * Enable NAND write protect
323 */
324static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
325{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200326 if (gpio_is_valid(host->ncfg->wp_gpio))
327 gpio_set_value(host->ncfg->wp_gpio, 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200328}
329
330/*
331 * Disable NAND write protect
332 */
333static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
334{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200335 if (gpio_is_valid(host->ncfg->wp_gpio))
336 gpio_set_value(host->ncfg->wp_gpio, 1);
Roland Stigge2944a442012-06-07 12:22:15 +0200337}
338
339/*
340 * Prepares SLC for transfers with H/W ECC enabled
341 */
342static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
343{
344 /* Hardware ECC is enabled automatically in hardware as needed */
345}
346
347/*
348 * Calculates the ECC for the data
349 */
350static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
351 const unsigned char *buf,
352 unsigned char *code)
353{
354 /*
355 * ECC is calculated automatically in hardware during syndrome read
356 * and write operations, so it doesn't need to be calculated here.
357 */
358 return 0;
359}
360
361/*
362 * Read a single byte from NAND device
363 */
364static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
365{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100366 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100367 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200368
369 return (uint8_t)readl(SLC_DATA(host->io_base));
370}
371
372/*
373 * Simple device read without ECC
374 */
375static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
376{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100377 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100378 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200379
380 /* Direct device read with no ECC */
381 while (len-- > 0)
382 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
383}
384
385/*
386 * Simple device write without ECC
387 */
388static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
389{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100390 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100391 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200392
393 /* Direct device write with no ECC */
394 while (len-- > 0)
395 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
396}
397
398/*
Roland Stigge2944a442012-06-07 12:22:15 +0200399 * Read the OOB data from the device without ECC using FIFO method
400 */
401static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
402 struct nand_chip *chip, int page)
403{
404 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
405 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
406
407 return 0;
408}
409
410/*
411 * Write the OOB data to the device without ECC using FIFO method
412 */
413static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
414 struct nand_chip *chip, int page)
415{
416 int status;
417
418 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
419 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
420
421 /* Send command to program the OOB data */
422 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
423
424 status = chip->waitfunc(mtd, chip);
425
426 return status & NAND_STATUS_FAIL ? -EIO : 0;
427}
428
429/*
430 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
431 */
432static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
433{
434 int i;
435
436 for (i = 0; i < (count * 3); i += 3) {
437 uint32_t ce = ecc[i / 3];
438 ce = ~(ce << 2) & 0xFFFFFF;
439 spare[i + 2] = (uint8_t)(ce & 0xFF);
440 ce >>= 8;
441 spare[i + 1] = (uint8_t)(ce & 0xFF);
442 ce >>= 8;
443 spare[i] = (uint8_t)(ce & 0xFF);
444 }
445}
446
447static void lpc32xx_dma_complete_func(void *completion)
448{
449 complete(completion);
450}
451
452static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
453 void *mem, int len, enum dma_transfer_direction dir)
454{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100455 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100456 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200457 struct dma_async_tx_descriptor *desc;
458 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
459 int res;
460
461 host->dma_slave_config.direction = dir;
462 host->dma_slave_config.src_addr = dma;
463 host->dma_slave_config.dst_addr = dma;
464 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
465 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
466 host->dma_slave_config.src_maxburst = 4;
467 host->dma_slave_config.dst_maxburst = 4;
468 /* DMA controller does flow control: */
469 host->dma_slave_config.device_fc = false;
470 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
471 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
472 return -ENXIO;
473 }
474
475 sg_init_one(&host->sgl, mem, len);
476
477 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
478 DMA_BIDIRECTIONAL);
479 if (res != 1) {
480 dev_err(mtd->dev.parent, "Failed to map sg list\n");
481 return -ENXIO;
482 }
483 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
484 flags);
485 if (!desc) {
486 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
487 goto out1;
488 }
489
490 init_completion(&host->comp);
491 desc->callback = lpc32xx_dma_complete_func;
492 desc->callback_param = &host->comp;
493
494 dmaengine_submit(desc);
495 dma_async_issue_pending(host->dma_chan);
496
497 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
498
499 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
500 DMA_BIDIRECTIONAL);
501
502 return 0;
503out1:
504 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
505 DMA_BIDIRECTIONAL);
506 return -ENXIO;
507}
508
509/*
510 * DMA read/write transfers with ECC support
511 */
512static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
513 int read)
514{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100515 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100516 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200517 int i, status = 0;
518 unsigned long timeout;
519 int res;
520 enum dma_transfer_direction dir =
521 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
522 uint8_t *dma_buf;
523 bool dma_mapped;
524
525 if ((void *)buf <= high_memory) {
526 dma_buf = buf;
527 dma_mapped = true;
528 } else {
529 dma_buf = host->data_buf;
530 dma_mapped = false;
531 if (!read)
532 memcpy(host->data_buf, buf, mtd->writesize);
533 }
534
535 if (read) {
536 writel(readl(SLC_CFG(host->io_base)) |
537 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
538 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
539 } else {
540 writel((readl(SLC_CFG(host->io_base)) |
541 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
542 ~SLCCFG_DMA_DIR,
543 SLC_CFG(host->io_base));
544 }
545
546 /* Clear initial ECC */
547 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
548
549 /* Transfer size is data area only */
550 writel(mtd->writesize, SLC_TC(host->io_base));
551
552 /* Start transfer in the NAND controller */
553 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
554 SLC_CTRL(host->io_base));
555
556 for (i = 0; i < chip->ecc.steps; i++) {
557 /* Data */
558 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
559 dma_buf + i * chip->ecc.size,
560 mtd->writesize / chip->ecc.steps, dir);
561 if (res)
562 return res;
563
564 /* Always _read_ ECC */
565 if (i == chip->ecc.steps - 1)
566 break;
567 if (!read) /* ECC availability delayed on write */
568 udelay(10);
569 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
570 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
571 if (res)
572 return res;
573 }
574
575 /*
576 * According to NXP, the DMA can be finished here, but the NAND
577 * controller may still have buffered data. After porting to using the
578 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
579 * appears to be always true, according to tests. Keeping the check for
580 * safety reasons for now.
581 */
582 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
583 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
584 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
585 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
586 time_before(jiffies, timeout))
587 cpu_relax();
588 if (!time_before(jiffies, timeout)) {
589 dev_err(mtd->dev.parent, "FIFO held data too long\n");
590 status = -EIO;
591 }
592 }
593
594 /* Read last calculated ECC value */
595 if (!read)
596 udelay(10);
597 host->ecc_buf[chip->ecc.steps - 1] =
598 readl(SLC_ECC(host->io_base));
599
600 /* Flush DMA */
601 dmaengine_terminate_all(host->dma_chan);
602
603 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
604 readl(SLC_TC(host->io_base))) {
605 /* Something is left in the FIFO, something is wrong */
606 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
607 status = -EIO;
608 }
609
610 /* Stop DMA & HW ECC */
611 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
612 SLC_CTRL(host->io_base));
613 writel(readl(SLC_CFG(host->io_base)) &
614 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
615 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
616
617 if (!dma_mapped && read)
618 memcpy(buf, host->data_buf, mtd->writesize);
619
620 return status;
621}
622
623/*
624 * Read the data and OOB data from the device, use ECC correction with the
625 * data, disable ECC for the OOB data
626 */
627static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
628 struct nand_chip *chip, uint8_t *buf,
629 int oob_required, int page)
630{
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100631 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100632 struct mtd_oob_region oobregion = { };
633 int stat, i, status, error;
Roland Stigge2944a442012-06-07 12:22:15 +0200634 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
635
636 /* Issue read command */
637 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
638
639 /* Read data and oob, calculate ECC */
640 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
641
642 /* Get OOB data */
643 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
644
645 /* Convert to stored ECC format */
646 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
647
648 /* Pointer to ECC data retrieved from NAND spare area */
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100649 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
650 if (error)
651 return error;
652
653 oobecc = chip->oob_poi + oobregion.offset;
Roland Stigge2944a442012-06-07 12:22:15 +0200654
655 for (i = 0; i < chip->ecc.steps; i++) {
656 stat = chip->ecc.correct(mtd, buf, oobecc,
657 &tmpecc[i * chip->ecc.bytes]);
658 if (stat < 0)
659 mtd->ecc_stats.failed++;
660 else
661 mtd->ecc_stats.corrected += stat;
662
663 buf += chip->ecc.size;
664 oobecc += chip->ecc.bytes;
665 }
666
667 return status;
668}
669
670/*
671 * Read the data and OOB data from the device, no ECC correction with the
672 * data or OOB data
673 */
674static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
675 struct nand_chip *chip,
676 uint8_t *buf, int oob_required,
677 int page)
678{
679 /* Issue read command */
680 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
681
682 /* Raw reads can just use the FIFO interface */
683 chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
684 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
685
686 return 0;
687}
688
689/*
690 * Write the data and OOB data to the device, use ECC with the data,
691 * disable ECC for the OOB data
692 */
693static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
694 struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200695 const uint8_t *buf,
696 int oob_required, int page)
Roland Stigge2944a442012-06-07 12:22:15 +0200697{
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100698 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100699 struct mtd_oob_region oobregion = { };
700 uint8_t *pb;
Roland Stigge2944a442012-06-07 12:22:15 +0200701 int error;
702
703 /* Write data, calculate ECC on outbound data */
704 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
705 if (error)
706 return error;
707
708 /*
709 * The calculated ECC needs some manual work done to it before
710 * committing it to NAND. Process the calculated ECC and place
711 * the resultant values directly into the OOB buffer. */
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100712 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
713 if (error)
714 return error;
715
716 pb = chip->oob_poi + oobregion.offset;
Roland Stigge2944a442012-06-07 12:22:15 +0200717 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
718
719 /* Write ECC data to device */
720 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
721 return 0;
722}
723
724/*
725 * Write the data and OOB data to the device, no ECC correction with the
726 * data or OOB data
727 */
728static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
729 struct nand_chip *chip,
730 const uint8_t *buf,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200731 int oob_required, int page)
Roland Stigge2944a442012-06-07 12:22:15 +0200732{
733 /* Raw writes can just use the FIFO interface */
734 chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
735 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
736 return 0;
737}
738
Roland Stigge2944a442012-06-07 12:22:15 +0200739static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
740{
Boris BREZILLON0faf8c32015-12-10 09:00:10 +0100741 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200742 dma_cap_mask_t mask;
743
Roland Stiggede20c222012-08-16 15:15:34 +0200744 if (!host->pdata || !host->pdata->dma_filter) {
745 dev_err(mtd->dev.parent, "no DMA platform data\n");
746 return -ENOENT;
747 }
748
Roland Stigge2944a442012-06-07 12:22:15 +0200749 dma_cap_zero(mask);
750 dma_cap_set(DMA_SLAVE, mask);
Roland Stiggede20c222012-08-16 15:15:34 +0200751 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
752 "nand-slc");
Roland Stigge2944a442012-06-07 12:22:15 +0200753 if (!host->dma_chan) {
754 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
755 return -EBUSY;
756 }
757
758 return 0;
759}
760
Roland Stigge2944a442012-06-07 12:22:15 +0200761static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
762{
Roland Stigge10594f62012-08-24 15:06:51 +0200763 struct lpc32xx_nand_cfg_slc *ncfg;
Roland Stigge2944a442012-06-07 12:22:15 +0200764 struct device_node *np = dev->of_node;
765
Roland Stigge10594f62012-08-24 15:06:51 +0200766 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
Jingoo Han8ecb66b2013-12-26 12:18:56 +0900767 if (!ncfg)
Roland Stigge2944a442012-06-07 12:22:15 +0200768 return NULL;
Roland Stigge2944a442012-06-07 12:22:15 +0200769
Roland Stigge10594f62012-08-24 15:06:51 +0200770 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
771 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
772 of_property_read_u32(np, "nxp,whold", &ncfg->whold);
773 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
774 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
775 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
776 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
777 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
Roland Stigge2944a442012-06-07 12:22:15 +0200778
Roland Stigge10594f62012-08-24 15:06:51 +0200779 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
780 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
781 !ncfg->rhold || !ncfg->rsetup) {
Roland Stigge2944a442012-06-07 12:22:15 +0200782 dev_err(dev, "chip parameters not specified correctly\n");
783 return NULL;
784 }
785
Roland Stigge10594f62012-08-24 15:06:51 +0200786 ncfg->use_bbt = of_get_nand_on_flash_bbt(np);
787 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200788
Roland Stigge10594f62012-08-24 15:06:51 +0200789 return ncfg;
Roland Stigge2944a442012-06-07 12:22:15 +0200790}
Roland Stigge2944a442012-06-07 12:22:15 +0200791
792/*
793 * Probe for NAND controller
794 */
Bill Pemberton06f25512012-11-19 13:23:07 -0500795static int lpc32xx_nand_probe(struct platform_device *pdev)
Roland Stigge2944a442012-06-07 12:22:15 +0200796{
797 struct lpc32xx_nand_host *host;
798 struct mtd_info *mtd;
799 struct nand_chip *chip;
800 struct resource *rc;
Roland Stigge2944a442012-06-07 12:22:15 +0200801 int res;
802
803 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804 if (rc == NULL) {
805 dev_err(&pdev->dev, "No memory resource found for device\n");
806 return -EBUSY;
807 }
808
809 /* Allocate memory for the device structure (and zero it) */
810 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
Jingoo Han8ecb66b2013-12-26 12:18:56 +0900811 if (!host)
Roland Stigge2944a442012-06-07 12:22:15 +0200812 return -ENOMEM;
Roland Stigge2944a442012-06-07 12:22:15 +0200813 host->io_base_dma = rc->start;
814
Thierry Redingb0de7742013-01-21 11:09:12 +0100815 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
816 if (IS_ERR(host->io_base))
817 return PTR_ERR(host->io_base);
Roland Stigge2944a442012-06-07 12:22:15 +0200818
819 if (pdev->dev.of_node)
820 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
Roland Stigge2944a442012-06-07 12:22:15 +0200821 if (!host->ncfg) {
Roland Stigge10594f62012-08-24 15:06:51 +0200822 dev_err(&pdev->dev,
823 "Missing or bad NAND config from device tree\n");
Roland Stigge2944a442012-06-07 12:22:15 +0200824 return -ENOENT;
825 }
Roland Stigged5842ab2012-06-27 17:51:15 +0200826 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
827 return -EPROBE_DEFER;
Jingoo Han133432a2013-12-26 10:44:30 +0900828 if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
829 host->ncfg->wp_gpio, "NAND WP")) {
Roland Stigge2944a442012-06-07 12:22:15 +0200830 dev_err(&pdev->dev, "GPIO not available\n");
831 return -EBUSY;
832 }
833 lpc32xx_wp_disable(host);
834
Jingoo Han453810b2013-07-30 17:18:33 +0900835 host->pdata = dev_get_platdata(&pdev->dev);
Roland Stiggede20c222012-08-16 15:15:34 +0200836
Roland Stigge2944a442012-06-07 12:22:15 +0200837 chip = &host->nand_chip;
Boris BREZILLON0faf8c32015-12-10 09:00:10 +0100838 mtd = nand_to_mtd(chip);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100839 nand_set_controller_data(chip, host);
Brian Norrisa61ae812015-10-30 20:33:25 -0700840 nand_set_flash_node(chip, pdev->dev.of_node);
Roland Stigge2944a442012-06-07 12:22:15 +0200841 mtd->owner = THIS_MODULE;
842 mtd->dev.parent = &pdev->dev;
843
844 /* Get NAND clock */
Jingoo Han133432a2013-12-26 10:44:30 +0900845 host->clk = devm_clk_get(&pdev->dev, NULL);
Roland Stigge2944a442012-06-07 12:22:15 +0200846 if (IS_ERR(host->clk)) {
847 dev_err(&pdev->dev, "Clock failure\n");
848 res = -ENOENT;
849 goto err_exit1;
850 }
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300851 clk_prepare_enable(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +0200852
853 /* Set NAND IO addresses and command/ready functions */
854 chip->IO_ADDR_R = SLC_DATA(host->io_base);
855 chip->IO_ADDR_W = SLC_DATA(host->io_base);
856 chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
857 chip->dev_ready = lpc32xx_nand_device_ready;
858 chip->chip_delay = 20; /* 20us command delay time */
859
860 /* Init NAND controller */
861 lpc32xx_nand_setup(host);
862
863 platform_set_drvdata(pdev, host);
864
865 /* NAND callbacks for LPC32xx SLC hardware */
866 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
867 chip->read_byte = lpc32xx_nand_read_byte;
868 chip->read_buf = lpc32xx_nand_read_buf;
869 chip->write_buf = lpc32xx_nand_write_buf;
870 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
871 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
872 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
873 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
874 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
875 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
876 chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
877 chip->ecc.correct = nand_correct_data;
878 chip->ecc.strength = 1;
879 chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
Roland Stigge2944a442012-06-07 12:22:15 +0200880
Roland Stigge2944a442012-06-07 12:22:15 +0200881 /*
882 * Allocate a large enough buffer for a single huge page plus
883 * extra space for the spare area and ECC storage area
884 */
885 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
886 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
887 GFP_KERNEL);
888 if (host->data_buf == NULL) {
Roland Stigge2944a442012-06-07 12:22:15 +0200889 res = -ENOMEM;
890 goto err_exit2;
891 }
892
893 res = lpc32xx_nand_dma_setup(host);
894 if (res) {
895 res = -EIO;
896 goto err_exit2;
897 }
898
899 /* Find NAND device */
900 if (nand_scan_ident(mtd, 1, NULL)) {
901 res = -ENXIO;
902 goto err_exit3;
903 }
904
905 /* OOB and ECC CPU and DMA work areas */
906 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
907
908 /*
909 * Small page FLASH has a unique OOB layout, but large and huge
910 * page FLASH use the standard layout. Small page FLASH uses a
911 * custom BBT marker layout.
912 */
913 if (mtd->writesize <= 512)
Boris Brezillond50b5232016-02-03 20:02:41 +0100914 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
Roland Stigge2944a442012-06-07 12:22:15 +0200915
916 /* These sizes remain the same regardless of page size */
917 chip->ecc.size = 256;
918 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
919 chip->ecc.prepad = chip->ecc.postpad = 0;
920
921 /* Avoid extra scan if using BBT, setup BBT support */
922 if (host->ncfg->use_bbt) {
Roland Stigge2944a442012-06-07 12:22:15 +0200923 chip->bbt_options |= NAND_BBT_USE_FLASH;
924
925 /*
926 * Use a custom BBT marker setup for small page FLASH that
927 * won't interfere with the ECC layout. Large and huge page
928 * FLASH use the standard layout.
929 */
930 if (mtd->writesize <= 512) {
931 chip->bbt_td = &bbt_smallpage_main_descr;
932 chip->bbt_md = &bbt_smallpage_mirror_descr;
933 }
934 }
935
936 /*
937 * Fills out all the uninitialized function pointers with the defaults
938 */
939 if (nand_scan_tail(mtd)) {
940 res = -ENXIO;
941 goto err_exit3;
942 }
943
Roland Stigge2944a442012-06-07 12:22:15 +0200944 mtd->name = "nxp_lpc3220_slc";
Brian Norrisa61ae812015-10-30 20:33:25 -0700945 res = mtd_device_register(mtd, host->ncfg->parts,
946 host->ncfg->num_parts);
Roland Stigge2944a442012-06-07 12:22:15 +0200947 if (!res)
948 return res;
949
950 nand_release(mtd);
951
952err_exit3:
953 dma_release_channel(host->dma_chan);
954err_exit2:
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300955 clk_disable_unprepare(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +0200956err_exit1:
957 lpc32xx_wp_enable(host);
Roland Stigge2944a442012-06-07 12:22:15 +0200958
959 return res;
960}
961
962/*
963 * Remove NAND device.
964 */
Bill Pemberton810b7e02012-11-19 13:26:04 -0500965static int lpc32xx_nand_remove(struct platform_device *pdev)
Roland Stigge2944a442012-06-07 12:22:15 +0200966{
967 uint32_t tmp;
968 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
Boris BREZILLON0faf8c32015-12-10 09:00:10 +0100969 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200970
971 nand_release(mtd);
972 dma_release_channel(host->dma_chan);
973
974 /* Force CE high */
975 tmp = readl(SLC_CTRL(host->io_base));
976 tmp &= ~SLCCFG_CE_LOW;
977 writel(tmp, SLC_CTRL(host->io_base));
978
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300979 clk_disable_unprepare(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +0200980 lpc32xx_wp_enable(host);
Roland Stigge2944a442012-06-07 12:22:15 +0200981
982 return 0;
983}
984
985#ifdef CONFIG_PM
986static int lpc32xx_nand_resume(struct platform_device *pdev)
987{
988 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
989
990 /* Re-enable NAND clock */
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300991 clk_prepare_enable(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +0200992
993 /* Fresh init of NAND controller */
994 lpc32xx_nand_setup(host);
995
996 /* Disable write protect */
997 lpc32xx_wp_disable(host);
998
999 return 0;
1000}
1001
1002static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
1003{
1004 uint32_t tmp;
1005 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1006
1007 /* Force CE high */
1008 tmp = readl(SLC_CTRL(host->io_base));
1009 tmp &= ~SLCCFG_CE_LOW;
1010 writel(tmp, SLC_CTRL(host->io_base));
1011
1012 /* Enable write protect for safety */
1013 lpc32xx_wp_enable(host);
1014
1015 /* Disable clock */
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +03001016 clk_disable_unprepare(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +02001017
1018 return 0;
1019}
1020
1021#else
1022#define lpc32xx_nand_resume NULL
1023#define lpc32xx_nand_suspend NULL
1024#endif
1025
Roland Stigge2944a442012-06-07 12:22:15 +02001026static const struct of_device_id lpc32xx_nand_match[] = {
1027 { .compatible = "nxp,lpc3220-slc" },
1028 { /* sentinel */ },
1029};
1030MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
Roland Stigge2944a442012-06-07 12:22:15 +02001031
1032static struct platform_driver lpc32xx_nand_driver = {
1033 .probe = lpc32xx_nand_probe,
Bill Pemberton5153b882012-11-19 13:21:24 -05001034 .remove = lpc32xx_nand_remove,
Roland Stigge2944a442012-06-07 12:22:15 +02001035 .resume = lpc32xx_nand_resume,
1036 .suspend = lpc32xx_nand_suspend,
1037 .driver = {
1038 .name = LPC32XX_MODNAME,
Sachin Kamatfea7b562013-09-30 15:10:23 +05301039 .of_match_table = lpc32xx_nand_match,
Roland Stigge2944a442012-06-07 12:22:15 +02001040 },
1041};
1042
1043module_platform_driver(lpc32xx_nand_driver);
1044
1045MODULE_LICENSE("GPL");
1046MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1047MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1048MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");