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git.odroid.com / yocto / kernel / common / d65fd3a42e00d322448f2518db6a3f0eb12ce1bd / . / sound / soc / codecs / rt5677.c
blob: 0d24dc45dfe4d4bc6f6f84268461284906c31aea [file] [log] [blame]
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]18#include <linux/of_gpio.h>
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]23#include <linux/firmware.h>
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]24#include <linux/gpio.h>
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]33#include "rl6231.h"
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]34#include "rt5677.h"
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]35#include "rt5677-spi.h"
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64};
65#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
66
67static const struct reg_default rt5677_reg[] = {
68 {RT5677_RESET , 0x0000},
69 {RT5677_LOUT1 , 0xa800},
70 {RT5677_IN1 , 0x0000},
71 {RT5677_MICBIAS , 0x0000},
72 {RT5677_SLIMBUS_PARAM , 0x0000},
73 {RT5677_SLIMBUS_RX , 0x0000},
74 {RT5677_SLIMBUS_CTRL , 0x0000},
75 {RT5677_SIDETONE_CTRL , 0x000b},
76 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
77 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
78 {RT5677_DAC4_DIG_VOL , 0xafaf},
79 {RT5677_DAC3_DIG_VOL , 0xafaf},
80 {RT5677_DAC1_DIG_VOL , 0xafaf},
81 {RT5677_DAC2_DIG_VOL , 0xafaf},
82 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
83 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
84 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_STO1_2_ADC_BST , 0x0000},
86 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_ADC_BST_CTRL2 , 0x0000},
88 {RT5677_STO3_4_ADC_BST , 0x0000},
89 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_MIXER , 0xd4c0},
92 {RT5677_STO3_ADC_MIXER , 0xd4c0},
93 {RT5677_STO2_ADC_MIXER , 0xd4c0},
94 {RT5677_STO1_ADC_MIXER , 0xd4c0},
95 {RT5677_MONO_ADC_MIXER , 0xd4d1},
96 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
97 {RT5677_STO1_DAC_MIXER , 0xaaaa},
98 {RT5677_MONO_DAC_MIXER , 0xaaaa},
99 {RT5677_DD1_MIXER , 0xaaaa},
100 {RT5677_DD2_MIXER , 0xaaaa},
101 {RT5677_IF3_DATA , 0x0000},
102 {RT5677_IF4_DATA , 0x0000},
103 {RT5677_PDM_OUT_CTRL , 0x8888},
104 {RT5677_PDM_DATA_CTRL1 , 0x0000},
105 {RT5677_PDM_DATA_CTRL2 , 0x0000},
106 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
109 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
112 {RT5677_TDM1_CTRL1 , 0x0300},
113 {RT5677_TDM1_CTRL2 , 0x0000},
114 {RT5677_TDM1_CTRL3 , 0x4000},
115 {RT5677_TDM1_CTRL4 , 0x0123},
116 {RT5677_TDM1_CTRL5 , 0x4567},
117 {RT5677_TDM2_CTRL1 , 0x0300},
118 {RT5677_TDM2_CTRL2 , 0x0000},
119 {RT5677_TDM2_CTRL3 , 0x4000},
120 {RT5677_TDM2_CTRL4 , 0x0123},
121 {RT5677_TDM2_CTRL5 , 0x4567},
122 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
123 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
130 {RT5677_DMIC_CTRL1 , 0x1505},
131 {RT5677_DMIC_CTRL2 , 0x0055},
132 {RT5677_HAP_GENE_CTRL1 , 0x0111},
133 {RT5677_HAP_GENE_CTRL2 , 0x0064},
134 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL9 , 0xf000},
141 {RT5677_HAP_GENE_CTRL10 , 0x0000},
142 {RT5677_PWR_DIG1 , 0x0000},
143 {RT5677_PWR_DIG2 , 0x0000},
144 {RT5677_PWR_ANLG1 , 0x0055},
145 {RT5677_PWR_ANLG2 , 0x0000},
146 {RT5677_PWR_DSP1 , 0x0001},
147 {RT5677_PWR_DSP_ST , 0x0000},
148 {RT5677_PWR_DSP2 , 0x0000},
149 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
150 {RT5677_PRIV_INDEX , 0x0000},
151 {RT5677_PRIV_DATA , 0x0000},
152 {RT5677_I2S4_SDP , 0x8000},
153 {RT5677_I2S1_SDP , 0x8000},
154 {RT5677_I2S2_SDP , 0x8000},
155 {RT5677_I2S3_SDP , 0x8000},
156 {RT5677_CLK_TREE_CTRL1 , 0x1111},
157 {RT5677_CLK_TREE_CTRL2 , 0x1111},
158 {RT5677_CLK_TREE_CTRL3 , 0x0000},
159 {RT5677_PLL1_CTRL1 , 0x0000},
160 {RT5677_PLL1_CTRL2 , 0x0000},
161 {RT5677_PLL2_CTRL1 , 0x0c60},
162 {RT5677_PLL2_CTRL2 , 0x2000},
163 {RT5677_GLB_CLK1 , 0x0000},
164 {RT5677_GLB_CLK2 , 0x0000},
165 {RT5677_ASRC_1 , 0x0000},
166 {RT5677_ASRC_2 , 0x0000},
167 {RT5677_ASRC_3 , 0x0000},
168 {RT5677_ASRC_4 , 0x0000},
169 {RT5677_ASRC_5 , 0x0000},
170 {RT5677_ASRC_6 , 0x0000},
171 {RT5677_ASRC_7 , 0x0000},
172 {RT5677_ASRC_8 , 0x0000},
173 {RT5677_ASRC_9 , 0x0000},
174 {RT5677_ASRC_10 , 0x0000},
175 {RT5677_ASRC_11 , 0x0000},
176 {RT5677_ASRC_12 , 0x0008},
177 {RT5677_ASRC_13 , 0x0000},
178 {RT5677_ASRC_14 , 0x0000},
179 {RT5677_ASRC_15 , 0x0000},
180 {RT5677_ASRC_16 , 0x0000},
181 {RT5677_ASRC_17 , 0x0000},
182 {RT5677_ASRC_18 , 0x0000},
183 {RT5677_ASRC_19 , 0x0000},
184 {RT5677_ASRC_20 , 0x0000},
185 {RT5677_ASRC_21 , 0x000c},
186 {RT5677_ASRC_22 , 0x0000},
187 {RT5677_ASRC_23 , 0x0000},
188 {RT5677_VAD_CTRL1 , 0x2184},
189 {RT5677_VAD_CTRL2 , 0x010a},
190 {RT5677_VAD_CTRL3 , 0x0aea},
191 {RT5677_VAD_CTRL4 , 0x000c},
192 {RT5677_VAD_CTRL5 , 0x0000},
193 {RT5677_DSP_INB_CTRL1 , 0x0000},
194 {RT5677_DSP_INB_CTRL2 , 0x0000},
195 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
196 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
197 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
200 {RT5677_ADC_EQ_CTRL1 , 0x6000},
201 {RT5677_ADC_EQ_CTRL2 , 0x0000},
202 {RT5677_EQ_CTRL1 , 0xc000},
203 {RT5677_EQ_CTRL2 , 0x0000},
204 {RT5677_EQ_CTRL3 , 0x0000},
205 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
206 {RT5677_JD_CTRL1 , 0x0000},
207 {RT5677_JD_CTRL2 , 0x0000},
208 {RT5677_JD_CTRL3 , 0x0000},
209 {RT5677_IRQ_CTRL1 , 0x0000},
210 {RT5677_IRQ_CTRL2 , 0x0000},
211 {RT5677_GPIO_ST , 0x0000},
212 {RT5677_GPIO_CTRL1 , 0x0000},
213 {RT5677_GPIO_CTRL2 , 0x0000},
214 {RT5677_GPIO_CTRL3 , 0x0000},
215 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
216 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_MB_DRC_CTRL1 , 0x0f20},
226 {RT5677_DRC1_CTRL1 , 0x001f},
227 {RT5677_DRC1_CTRL2 , 0x020c},
228 {RT5677_DRC1_CTRL3 , 0x1f00},
229 {RT5677_DRC1_CTRL4 , 0x0000},
230 {RT5677_DRC1_CTRL5 , 0x0000},
231 {RT5677_DRC1_CTRL6 , 0x0029},
232 {RT5677_DRC2_CTRL1 , 0x001f},
233 {RT5677_DRC2_CTRL2 , 0x020c},
234 {RT5677_DRC2_CTRL3 , 0x1f00},
235 {RT5677_DRC2_CTRL4 , 0x0000},
236 {RT5677_DRC2_CTRL5 , 0x0000},
237 {RT5677_DRC2_CTRL6 , 0x0029},
238 {RT5677_DRC1_HL_CTRL1 , 0x8000},
239 {RT5677_DRC1_HL_CTRL2 , 0x0200},
240 {RT5677_DRC2_HL_CTRL1 , 0x8000},
241 {RT5677_DRC2_HL_CTRL2 , 0x0200},
242 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
243 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
244 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
246 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
259 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
260 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
262 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
263 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
264 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
265 {RT5677_DIG_MISC , 0x0000},
266 {RT5677_GEN_CTRL1 , 0x0000},
267 {RT5677_GEN_CTRL2 , 0x0000},
268 {RT5677_VENDOR_ID , 0x0000},
269 {RT5677_VENDOR_ID1 , 0x10ec},
270 {RT5677_VENDOR_ID2 , 0x6327},
271};
272
273static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
274{
275 int i;
276
277 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
278 if (reg >= rt5677_ranges[i].range_min &&
279 reg <= rt5677_ranges[i].range_max) {
280 return true;
281 }
282 }
283
284 switch (reg) {
285 case RT5677_RESET:
286 case RT5677_SLIMBUS_PARAM:
287 case RT5677_PDM_DATA_CTRL1:
288 case RT5677_PDM_DATA_CTRL2:
289 case RT5677_PDM1_DATA_CTRL4:
290 case RT5677_PDM2_DATA_CTRL4:
291 case RT5677_I2C_MASTER_CTRL1:
292 case RT5677_I2C_MASTER_CTRL7:
293 case RT5677_I2C_MASTER_CTRL8:
294 case RT5677_HAP_GENE_CTRL2:
295 case RT5677_PWR_DSP_ST:
296 case RT5677_PRIV_DATA:
297 case RT5677_PLL1_CTRL2:
298 case RT5677_PLL2_CTRL2:
299 case RT5677_ASRC_22:
300 case RT5677_ASRC_23:
301 case RT5677_VAD_CTRL5:
302 case RT5677_ADC_EQ_CTRL1:
303 case RT5677_EQ_CTRL1:
304 case RT5677_IRQ_CTRL1:
305 case RT5677_IRQ_CTRL2:
306 case RT5677_GPIO_ST:
307 case RT5677_DSP_INB1_SRC_CTRL4:
308 case RT5677_DSP_INB2_SRC_CTRL4:
309 case RT5677_DSP_INB3_SRC_CTRL4:
310 case RT5677_DSP_OUTB1_SRC_CTRL4:
311 case RT5677_DSP_OUTB2_SRC_CTRL4:
312 case RT5677_VENDOR_ID:
313 case RT5677_VENDOR_ID1:
314 case RT5677_VENDOR_ID2:
315 return true;
316 default:
317 return false;
318 }
319}
320
321static bool rt5677_readable_register(struct device *dev, unsigned int reg)
322{
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
326 if (reg >= rt5677_ranges[i].range_min &&
327 reg <= rt5677_ranges[i].range_max) {
328 return true;
329 }
330 }
331
332 switch (reg) {
333 case RT5677_RESET:
334 case RT5677_LOUT1:
335 case RT5677_IN1:
336 case RT5677_MICBIAS:
337 case RT5677_SLIMBUS_PARAM:
338 case RT5677_SLIMBUS_RX:
339 case RT5677_SLIMBUS_CTRL:
340 case RT5677_SIDETONE_CTRL:
341 case RT5677_ANA_DAC1_2_3_SRC:
342 case RT5677_IF_DSP_DAC3_4_MIXER:
343 case RT5677_DAC4_DIG_VOL:
344 case RT5677_DAC3_DIG_VOL:
345 case RT5677_DAC1_DIG_VOL:
346 case RT5677_DAC2_DIG_VOL:
347 case RT5677_IF_DSP_DAC2_MIXER:
348 case RT5677_STO1_ADC_DIG_VOL:
349 case RT5677_MONO_ADC_DIG_VOL:
350 case RT5677_STO1_2_ADC_BST:
351 case RT5677_STO2_ADC_DIG_VOL:
352 case RT5677_ADC_BST_CTRL2:
353 case RT5677_STO3_4_ADC_BST:
354 case RT5677_STO3_ADC_DIG_VOL:
355 case RT5677_STO4_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_MIXER:
357 case RT5677_STO3_ADC_MIXER:
358 case RT5677_STO2_ADC_MIXER:
359 case RT5677_STO1_ADC_MIXER:
360 case RT5677_MONO_ADC_MIXER:
361 case RT5677_ADC_IF_DSP_DAC1_MIXER:
362 case RT5677_STO1_DAC_MIXER:
363 case RT5677_MONO_DAC_MIXER:
364 case RT5677_DD1_MIXER:
365 case RT5677_DD2_MIXER:
366 case RT5677_IF3_DATA:
367 case RT5677_IF4_DATA:
368 case RT5677_PDM_OUT_CTRL:
369 case RT5677_PDM_DATA_CTRL1:
370 case RT5677_PDM_DATA_CTRL2:
371 case RT5677_PDM1_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL3:
373 case RT5677_PDM1_DATA_CTRL4:
374 case RT5677_PDM2_DATA_CTRL2:
375 case RT5677_PDM2_DATA_CTRL3:
376 case RT5677_PDM2_DATA_CTRL4:
377 case RT5677_TDM1_CTRL1:
378 case RT5677_TDM1_CTRL2:
379 case RT5677_TDM1_CTRL3:
380 case RT5677_TDM1_CTRL4:
381 case RT5677_TDM1_CTRL5:
382 case RT5677_TDM2_CTRL1:
383 case RT5677_TDM2_CTRL2:
384 case RT5677_TDM2_CTRL3:
385 case RT5677_TDM2_CTRL4:
386 case RT5677_TDM2_CTRL5:
387 case RT5677_I2C_MASTER_CTRL1:
388 case RT5677_I2C_MASTER_CTRL2:
389 case RT5677_I2C_MASTER_CTRL3:
390 case RT5677_I2C_MASTER_CTRL4:
391 case RT5677_I2C_MASTER_CTRL5:
392 case RT5677_I2C_MASTER_CTRL6:
393 case RT5677_I2C_MASTER_CTRL7:
394 case RT5677_I2C_MASTER_CTRL8:
395 case RT5677_DMIC_CTRL1:
396 case RT5677_DMIC_CTRL2:
397 case RT5677_HAP_GENE_CTRL1:
398 case RT5677_HAP_GENE_CTRL2:
399 case RT5677_HAP_GENE_CTRL3:
400 case RT5677_HAP_GENE_CTRL4:
401 case RT5677_HAP_GENE_CTRL5:
402 case RT5677_HAP_GENE_CTRL6:
403 case RT5677_HAP_GENE_CTRL7:
404 case RT5677_HAP_GENE_CTRL8:
405 case RT5677_HAP_GENE_CTRL9:
406 case RT5677_HAP_GENE_CTRL10:
407 case RT5677_PWR_DIG1:
408 case RT5677_PWR_DIG2:
409 case RT5677_PWR_ANLG1:
410 case RT5677_PWR_ANLG2:
411 case RT5677_PWR_DSP1:
412 case RT5677_PWR_DSP_ST:
413 case RT5677_PWR_DSP2:
414 case RT5677_ADC_DAC_HPF_CTRL1:
415 case RT5677_PRIV_INDEX:
416 case RT5677_PRIV_DATA:
417 case RT5677_I2S4_SDP:
418 case RT5677_I2S1_SDP:
419 case RT5677_I2S2_SDP:
420 case RT5677_I2S3_SDP:
421 case RT5677_CLK_TREE_CTRL1:
422 case RT5677_CLK_TREE_CTRL2:
423 case RT5677_CLK_TREE_CTRL3:
424 case RT5677_PLL1_CTRL1:
425 case RT5677_PLL1_CTRL2:
426 case RT5677_PLL2_CTRL1:
427 case RT5677_PLL2_CTRL2:
428 case RT5677_GLB_CLK1:
429 case RT5677_GLB_CLK2:
430 case RT5677_ASRC_1:
431 case RT5677_ASRC_2:
432 case RT5677_ASRC_3:
433 case RT5677_ASRC_4:
434 case RT5677_ASRC_5:
435 case RT5677_ASRC_6:
436 case RT5677_ASRC_7:
437 case RT5677_ASRC_8:
438 case RT5677_ASRC_9:
439 case RT5677_ASRC_10:
440 case RT5677_ASRC_11:
441 case RT5677_ASRC_12:
442 case RT5677_ASRC_13:
443 case RT5677_ASRC_14:
444 case RT5677_ASRC_15:
445 case RT5677_ASRC_16:
446 case RT5677_ASRC_17:
447 case RT5677_ASRC_18:
448 case RT5677_ASRC_19:
449 case RT5677_ASRC_20:
450 case RT5677_ASRC_21:
451 case RT5677_ASRC_22:
452 case RT5677_ASRC_23:
453 case RT5677_VAD_CTRL1:
454 case RT5677_VAD_CTRL2:
455 case RT5677_VAD_CTRL3:
456 case RT5677_VAD_CTRL4:
457 case RT5677_VAD_CTRL5:
458 case RT5677_DSP_INB_CTRL1:
459 case RT5677_DSP_INB_CTRL2:
460 case RT5677_DSP_IN_OUTB_CTRL:
461 case RT5677_DSP_OUTB0_1_DIG_VOL:
462 case RT5677_DSP_OUTB2_3_DIG_VOL:
463 case RT5677_DSP_OUTB4_5_DIG_VOL:
464 case RT5677_DSP_OUTB6_7_DIG_VOL:
465 case RT5677_ADC_EQ_CTRL1:
466 case RT5677_ADC_EQ_CTRL2:
467 case RT5677_EQ_CTRL1:
468 case RT5677_EQ_CTRL2:
469 case RT5677_EQ_CTRL3:
470 case RT5677_SOFT_VOL_ZERO_CROSS1:
471 case RT5677_JD_CTRL1:
472 case RT5677_JD_CTRL2:
473 case RT5677_JD_CTRL3:
474 case RT5677_IRQ_CTRL1:
475 case RT5677_IRQ_CTRL2:
476 case RT5677_GPIO_ST:
477 case RT5677_GPIO_CTRL1:
478 case RT5677_GPIO_CTRL2:
479 case RT5677_GPIO_CTRL3:
480 case RT5677_STO1_ADC_HI_FILTER1:
481 case RT5677_STO1_ADC_HI_FILTER2:
482 case RT5677_MONO_ADC_HI_FILTER1:
483 case RT5677_MONO_ADC_HI_FILTER2:
484 case RT5677_STO2_ADC_HI_FILTER1:
485 case RT5677_STO2_ADC_HI_FILTER2:
486 case RT5677_STO3_ADC_HI_FILTER1:
487 case RT5677_STO3_ADC_HI_FILTER2:
488 case RT5677_STO4_ADC_HI_FILTER1:
489 case RT5677_STO4_ADC_HI_FILTER2:
490 case RT5677_MB_DRC_CTRL1:
491 case RT5677_DRC1_CTRL1:
492 case RT5677_DRC1_CTRL2:
493 case RT5677_DRC1_CTRL3:
494 case RT5677_DRC1_CTRL4:
495 case RT5677_DRC1_CTRL5:
496 case RT5677_DRC1_CTRL6:
497 case RT5677_DRC2_CTRL1:
498 case RT5677_DRC2_CTRL2:
499 case RT5677_DRC2_CTRL3:
500 case RT5677_DRC2_CTRL4:
501 case RT5677_DRC2_CTRL5:
502 case RT5677_DRC2_CTRL6:
503 case RT5677_DRC1_HL_CTRL1:
504 case RT5677_DRC1_HL_CTRL2:
505 case RT5677_DRC2_HL_CTRL1:
506 case RT5677_DRC2_HL_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL1:
508 case RT5677_DSP_INB1_SRC_CTRL2:
509 case RT5677_DSP_INB1_SRC_CTRL3:
510 case RT5677_DSP_INB1_SRC_CTRL4:
511 case RT5677_DSP_INB2_SRC_CTRL1:
512 case RT5677_DSP_INB2_SRC_CTRL2:
513 case RT5677_DSP_INB2_SRC_CTRL3:
514 case RT5677_DSP_INB2_SRC_CTRL4:
515 case RT5677_DSP_INB3_SRC_CTRL1:
516 case RT5677_DSP_INB3_SRC_CTRL2:
517 case RT5677_DSP_INB3_SRC_CTRL3:
518 case RT5677_DSP_INB3_SRC_CTRL4:
519 case RT5677_DSP_OUTB1_SRC_CTRL1:
520 case RT5677_DSP_OUTB1_SRC_CTRL2:
521 case RT5677_DSP_OUTB1_SRC_CTRL3:
522 case RT5677_DSP_OUTB1_SRC_CTRL4:
523 case RT5677_DSP_OUTB2_SRC_CTRL1:
524 case RT5677_DSP_OUTB2_SRC_CTRL2:
525 case RT5677_DSP_OUTB2_SRC_CTRL3:
526 case RT5677_DSP_OUTB2_SRC_CTRL4:
527 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
528 case RT5677_DSP_OUTB_45_MIXER_CTRL:
529 case RT5677_DSP_OUTB_67_MIXER_CTRL:
530 case RT5677_DIG_MISC:
531 case RT5677_GEN_CTRL1:
532 case RT5677_GEN_CTRL2:
533 case RT5677_VENDOR_ID:
534 case RT5677_VENDOR_ID1:
535 case RT5677_VENDOR_ID2:
536 return true;
537 default:
538 return false;
539 }
540}
541
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]542/**
543 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
544 * @codec: SoC audio codec device.
545 * @addr: Address index.
546 * @value: Address data.
547 *
548 *
549 * Returns 0 for success or negative error code.
550 */
551static int rt5677_dsp_mode_i2c_write_addr(struct snd_soc_codec *codec,
552 unsigned int addr, unsigned int value, unsigned int opcode)
553{
554 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
555 int ret;
556
557 mutex_lock(&rt5677->dsp_cmd_lock);
558
559 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_MSB, addr >> 16);
560 if (ret < 0) {
561 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
562 goto err;
563 }
564
565 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_LSB,
566 addr & 0xffff);
567 if (ret < 0) {
568 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
569 goto err;
570 }
571
572 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_DATA_MSB,
573 value >> 16);
574 if (ret < 0) {
575 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
576 goto err;
577 }
578
579 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_DATA_LSB,
580 value & 0xffff);
581 if (ret < 0) {
582 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
583 goto err;
584 }
585
586 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_OP_CODE, opcode);
587 if (ret < 0) {
588 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
589 goto err;
590 }
591
592err:
593 mutex_unlock(&rt5677->dsp_cmd_lock);
594
595 return ret;
596}
597
598/**
599 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
600 * @codec: SoC audio codec device.
601 * @addr: Address index.
602 * @value: Address data.
603 *
604 * Returns 0 for success or negative error code.
605 */
606static int rt5677_dsp_mode_i2c_read_addr(
607 struct snd_soc_codec *codec, unsigned int addr, unsigned int *value)
608{
609 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
610 int ret;
611 unsigned int msb, lsb;
612
613 mutex_lock(&rt5677->dsp_cmd_lock);
614
615 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_MSB, addr >> 16);
616 if (ret < 0) {
617 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
618 goto err;
619 }
620
621 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_LSB,
622 addr & 0xffff);
623 if (ret < 0) {
624 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
625 goto err;
626 }
627
628 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_OP_CODE , 0x0002);
629 if (ret < 0) {
630 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
631 goto err;
632 }
633
634 regmap_read(rt5677->regmap, RT5677_DSP_I2C_DATA_MSB, &msb);
635 regmap_read(rt5677->regmap, RT5677_DSP_I2C_DATA_LSB, &lsb);
636 *value = (msb << 16) | lsb;
637
638err:
639 mutex_unlock(&rt5677->dsp_cmd_lock);
640
641 return ret;
642}
643
644/**
645 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
646 * @codec: SoC audio codec device.
647 * @reg: Register index.
648 * @value: Register data.
649 *
650 *
651 * Returns 0 for success or negative error code.
652 */
653static int rt5677_dsp_mode_i2c_write(struct snd_soc_codec *codec,
654 unsigned int reg, unsigned int value)
655{
656 return rt5677_dsp_mode_i2c_write_addr(codec, 0x18020000 + reg * 2,
657 value, 0x0001);
658}
659
660/**
661 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
662 * @codec: SoC audio codec device.
663 * @reg: Register index.
664 *
665 *
666 * Returns Register value.
667 */
668static unsigned int rt5677_dsp_mode_i2c_read(
669 struct snd_soc_codec *codec, unsigned int reg)
670{
671 unsigned int value = 0;
672
673 rt5677_dsp_mode_i2c_read_addr(codec, 0x18020000 + reg * 2, &value);
674
675 return value;
676}
677
678/**
679 * rt5677_dsp_mode_i2c_update_bits - update register on DSP mode.
680 * @codec: audio codec
681 * @reg: register index.
682 * @mask: register mask
683 * @value: new value
684 *
685 *
686 * Returns 1 for change, 0 for no change, or negative error code.
687 */
688static int rt5677_dsp_mode_i2c_update_bits(struct snd_soc_codec *codec,
689 unsigned int reg, unsigned int mask, unsigned int value)
690{
691 unsigned int old, new;
692 int change, ret;
693
694 ret = rt5677_dsp_mode_i2c_read(codec, reg);
695 if (ret < 0) {
696 dev_err(codec->dev, "Failed to read reg: %d\n", ret);
697 goto err;
698 }
699
700 old = ret;
701 new = (old & ~mask) | (value & mask);
702 change = old != new;
703 if (change) {
704 ret = rt5677_dsp_mode_i2c_write(codec, reg, new);
705 if (ret < 0) {
706 dev_err(codec->dev,
707 "Failed to write reg: %d\n", ret);
708 goto err;
709 }
710 }
711 return change;
712
713err:
714 return ret;
715}
716
717static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
718{
719 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
720 static bool activity;
721 int ret;
722
723 if (on && !activity) {
724 activity = true;
725
726 regcache_cache_only(rt5677->regmap, false);
727 regcache_cache_bypass(rt5677->regmap, true);
728
729 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
730 regmap_update_bits(rt5677->regmap,
731 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
732 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
733 RT5677_LDO1_SEL_MASK, 0x0);
734 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
735 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
736 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 0x0080);
737 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
738 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07ff);
739
740 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
741 codec->dev);
742 if (ret == 0) {
743 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
744 release_firmware(rt5677->fw1);
745 }
746
747 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
748 codec->dev);
749 if (ret == 0) {
750 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
751 release_firmware(rt5677->fw2);
752 }
753
754 rt5677_dsp_mode_i2c_update_bits(codec, RT5677_PWR_DSP1, 0x1,
755 0x0);
756
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_cache_only(rt5677->regmap, true);
759 } else if (!on && activity) {
760 activity = false;
761
762 regcache_cache_only(rt5677->regmap, false);
763 regcache_cache_bypass(rt5677->regmap, true);
764
765 rt5677_dsp_mode_i2c_update_bits(codec, RT5677_PWR_DSP1, 0x1,
766 0x1);
767 rt5677_dsp_mode_i2c_write(codec, RT5677_PWR_DSP1, 0x0001);
768
769 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
770
771 regcache_cache_bypass(rt5677->regmap, false);
772 regcache_mark_dirty(rt5677->regmap);
773 regcache_sync(rt5677->regmap);
774 }
775
776 return 0;
777}
778
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]779static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
780static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
781static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
782static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
783static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame]784static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]785
786/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
787static unsigned int bst_tlv[] = {
788 TLV_DB_RANGE_HEAD(7),
789 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
790 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
791 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
792 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
793 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
794 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
795 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
796};
797
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]798static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
800{
801 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
802 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
803
804 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
805
806 return 0;
807}
808
809static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
810 struct snd_ctl_elem_value *ucontrol)
811{
812 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
813 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
814
815 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
816
817 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
818 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
819
820 return 0;
821}
822
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]823static const struct snd_kcontrol_new rt5677_snd_controls[] = {
824 /* OUTPUT Control */
825 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
826 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
827 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
828 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
829 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
831
832 /* DAC Digital Volume */
833 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
834 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
835 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
837 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
839 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
841
842 /* IN1/IN2 Control */
843 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
844 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
845
846 /* ADC Digital Volume Control */
847 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
848 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
849 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
851 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857
858 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
859 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
860 adc_vol_tlv),
861 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
871 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
872 adc_vol_tlv),
873
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame]874 /* Sidetone Control */
875 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
876 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
877
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]878 /* ADC Boost Volume Control */
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]879 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]880 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
881 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]882 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]883 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]885 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]886 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]888 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]889 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]891 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]892 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]894
895 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
896 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]897};
898
899/**
900 * set_dmic_clk - Set parameter of dmic.
901 *
902 * @w: DAPM widget.
903 * @kcontrol: The kcontrol of this widget.
904 * @event: Event id.
905 *
906 * Choose dmic clock between 1MHz and 3MHz.
907 * It is better for clock to approximate 3MHz.
908 */
909static int set_dmic_clk(struct snd_soc_dapm_widget *w,
910 struct snd_kcontrol *kcontrol, int event)
911{
912 struct snd_soc_codec *codec = w->codec;
913 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin9a535812014-06-03 10:58:58 +0800[diff] [blame]914 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]915
916 if (idx < 0)
917 dev_err(codec->dev, "Failed to set DMIC clock\n");
918 else
919 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
920 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
921 return idx;
922}
923
924static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
925 struct snd_soc_dapm_widget *sink)
926{
927 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
928 unsigned int val;
929
930 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
931 val &= RT5677_SCLK_SRC_MASK;
932 if (val == RT5677_SCLK_SRC_PLL1)
933 return 1;
934 else
935 return 0;
936}
937
938/* Digital Mixer */
939static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
940 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
941 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
942 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
943 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
944};
945
946static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
947 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
948 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
949 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
950 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
951};
952
953static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
954 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
955 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
956 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
957 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
958};
959
960static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
961 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
962 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
963 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
964 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
965};
966
967static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
968 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
969 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
970 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
971 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
972};
973
974static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
975 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
976 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
977 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
978 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
979};
980
981static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
982 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
983 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
984 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
985 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
986};
987
988static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
989 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
990 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
991 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
992 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
993};
994
995static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
996 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
997 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
998 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
999 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1000};
1001
1002static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1003 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1004 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1005 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1006 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1007};
1008
1009static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1010 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1011 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1012 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1013 RT5677_M_DAC1_L_SFT, 1, 1),
1014};
1015
1016static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1017 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1018 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1019 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1020 RT5677_M_DAC1_R_SFT, 1, 1),
1021};
1022
1023static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1024 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1025 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1026 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1027 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1028 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1029 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1030 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1031 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1032};
1033
1034static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1035 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1036 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1037 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1038 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1039 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1040 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1042 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1043};
1044
1045static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1046 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1047 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1049 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1050 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1051 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1052 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1053 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1054};
1055
1056static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1057 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1058 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1059 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1060 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1062 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1064 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1065};
1066
1067static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1068 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1069 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1071 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1072 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1073 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1074 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1075 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1076};
1077
1078static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1079 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1080 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1081 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1082 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1083 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1084 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1085 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1086 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1087};
1088
1089static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1090 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1091 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1092 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1093 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1094 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1095 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1097 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1098};
1099
1100static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1101 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1102 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1104 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1106 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1108 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1109};
1110
1111static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1112 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1113 RT5677_DSP_IB_01_H_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1115 RT5677_DSP_IB_23_H_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1117 RT5677_DSP_IB_45_H_SFT, 1, 1),
1118 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1119 RT5677_DSP_IB_6_H_SFT, 1, 1),
1120 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1121 RT5677_DSP_IB_7_H_SFT, 1, 1),
1122 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1123 RT5677_DSP_IB_8_H_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1125 RT5677_DSP_IB_9_H_SFT, 1, 1),
1126};
1127
1128static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1129 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1130 RT5677_DSP_IB_01_L_SFT, 1, 1),
1131 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1132 RT5677_DSP_IB_23_L_SFT, 1, 1),
1133 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1134 RT5677_DSP_IB_45_L_SFT, 1, 1),
1135 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1136 RT5677_DSP_IB_6_L_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1138 RT5677_DSP_IB_7_L_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1140 RT5677_DSP_IB_8_L_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1142 RT5677_DSP_IB_9_L_SFT, 1, 1),
1143};
1144
1145static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1146 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1147 RT5677_DSP_IB_01_H_SFT, 1, 1),
1148 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1149 RT5677_DSP_IB_23_H_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1151 RT5677_DSP_IB_45_H_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1153 RT5677_DSP_IB_6_H_SFT, 1, 1),
1154 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1155 RT5677_DSP_IB_7_H_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1157 RT5677_DSP_IB_8_H_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1159 RT5677_DSP_IB_9_H_SFT, 1, 1),
1160};
1161
1162static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1163 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1164 RT5677_DSP_IB_01_L_SFT, 1, 1),
1165 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1166 RT5677_DSP_IB_23_L_SFT, 1, 1),
1167 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1168 RT5677_DSP_IB_45_L_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1170 RT5677_DSP_IB_6_L_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1172 RT5677_DSP_IB_7_L_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1174 RT5677_DSP_IB_8_L_SFT, 1, 1),
1175 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1176 RT5677_DSP_IB_9_L_SFT, 1, 1),
1177};
1178
1179static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1180 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1181 RT5677_DSP_IB_01_H_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1183 RT5677_DSP_IB_23_H_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1185 RT5677_DSP_IB_45_H_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1187 RT5677_DSP_IB_6_H_SFT, 1, 1),
1188 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1189 RT5677_DSP_IB_7_H_SFT, 1, 1),
1190 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1191 RT5677_DSP_IB_8_H_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1193 RT5677_DSP_IB_9_H_SFT, 1, 1),
1194};
1195
1196static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1197 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1198 RT5677_DSP_IB_01_L_SFT, 1, 1),
1199 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1200 RT5677_DSP_IB_23_L_SFT, 1, 1),
1201 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1202 RT5677_DSP_IB_45_L_SFT, 1, 1),
1203 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1204 RT5677_DSP_IB_6_L_SFT, 1, 1),
1205 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1206 RT5677_DSP_IB_7_L_SFT, 1, 1),
1207 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1208 RT5677_DSP_IB_8_L_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1210 RT5677_DSP_IB_9_L_SFT, 1, 1),
1211};
1212
1213
1214/* Mux */
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1215/* DAC1 L/R Source */ /* MX-29 [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1216static const char * const rt5677_dac1_src[] = {
1217 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1218 "OB 01"
1219};
1220
1221static SOC_ENUM_SINGLE_DECL(
1222 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1223 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1224
1225static const struct snd_kcontrol_new rt5677_dac1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1226 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1227
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1228/* ADDA1 L/R Source */ /* MX-29 [1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1229static const char * const rt5677_adda1_src[] = {
1230 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1231};
1232
1233static SOC_ENUM_SINGLE_DECL(
1234 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1235 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1236
1237static const struct snd_kcontrol_new rt5677_adda1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1238 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1239
1240
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1241/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1242static const char * const rt5677_dac2l_src[] = {
1243 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1244 "OB 2",
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1249 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1250
1251static const struct snd_kcontrol_new rt5677_dac2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1252 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1253
1254static const char * const rt5677_dac2r_src[] = {
1255 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1256 "OB 3", "Haptic Generator", "VAD ADC"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1261 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1262
1263static const struct snd_kcontrol_new rt5677_dac2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1264 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1265
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1266/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1267static const char * const rt5677_dac3l_src[] = {
1268 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1269 "SLB DAC 4", "OB 4"
1270};
1271
1272static SOC_ENUM_SINGLE_DECL(
1273 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1274 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1275
1276static const struct snd_kcontrol_new rt5677_dac3_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1277 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1278
1279static const char * const rt5677_dac3r_src[] = {
1280 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1281 "SLB DAC 5", "OB 5"
1282};
1283
1284static SOC_ENUM_SINGLE_DECL(
1285 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1286 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1287
1288static const struct snd_kcontrol_new rt5677_dac3_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1289 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1290
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1291/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1292static const char * const rt5677_dac4l_src[] = {
1293 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1294 "SLB DAC 6", "OB 6"
1295};
1296
1297static SOC_ENUM_SINGLE_DECL(
1298 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1299 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1300
1301static const struct snd_kcontrol_new rt5677_dac4_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1302 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1303
1304static const char * const rt5677_dac4r_src[] = {
1305 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1306 "SLB DAC 7", "OB 7"
1307};
1308
1309static SOC_ENUM_SINGLE_DECL(
1310 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1311 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1312
1313static const struct snd_kcontrol_new rt5677_dac4_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1314 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1315
1316/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1317static const char * const rt5677_iob_bypass_src[] = {
1318 "Bypass", "Pass SRC"
1319};
1320
1321static SOC_ENUM_SINGLE_DECL(
1322 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1323 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1324
1325static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1326 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1327
1328static SOC_ENUM_SINGLE_DECL(
1329 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1330 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1331
1332static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1333 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1334
1335static SOC_ENUM_SINGLE_DECL(
1336 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1337 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1338
1339static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1340 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1341
1342static SOC_ENUM_SINGLE_DECL(
1343 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1344 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1345
1346static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1347 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1348
1349static SOC_ENUM_SINGLE_DECL(
1350 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1351 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1352
1353static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1354 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1355
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1356/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1357static const char * const rt5677_stereo_adc2_src[] = {
1358 "DD MIX1", "DMIC", "Stereo DAC MIX"
1359};
1360
1361static SOC_ENUM_SINGLE_DECL(
1362 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1363 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1364
1365static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1366 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1367
1368static SOC_ENUM_SINGLE_DECL(
1369 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1370 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1371
1372static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1373 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1374
1375static SOC_ENUM_SINGLE_DECL(
1376 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1377 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1378
1379static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1380 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1381
1382/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1383static const char * const rt5677_dmic_src[] = {
1384 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1385};
1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1389 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1390
1391static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1392 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1393
1394static SOC_ENUM_SINGLE_DECL(
1395 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1396 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1397
1398static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1399 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1400
1401static SOC_ENUM_SINGLE_DECL(
1402 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1403 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1404
1405static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1406 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1407
1408static SOC_ENUM_SINGLE_DECL(
1409 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1410 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1411
1412static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1413 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1414
1415static SOC_ENUM_SINGLE_DECL(
1416 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1417 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1418
1419static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1420 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1421
1422static SOC_ENUM_SINGLE_DECL(
1423 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1424 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1425
1426static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1427 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1428
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1429/* Stereo2 ADC Source */ /* MX-26 [0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1430static const char * const rt5677_stereo2_adc_lr_src[] = {
1431 "L", "LR"
1432};
1433
1434static SOC_ENUM_SINGLE_DECL(
1435 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1436 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1437
1438static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1439 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1440
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1441/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1442static const char * const rt5677_stereo_adc1_src[] = {
1443 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1444};
1445
1446static SOC_ENUM_SINGLE_DECL(
1447 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1448 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1449
1450static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1451 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1452
1453static SOC_ENUM_SINGLE_DECL(
1454 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1455 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1456
1457static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1458 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1459
1460static SOC_ENUM_SINGLE_DECL(
1461 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1462 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1463
1464static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1465 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1466
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1467/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1468static const char * const rt5677_mono_adc2_l_src[] = {
1469 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1470};
1471
1472static SOC_ENUM_SINGLE_DECL(
1473 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1474 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1475
1476static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1477 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1478
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1479/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1480static const char * const rt5677_mono_adc1_l_src[] = {
1481 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1482};
1483
1484static SOC_ENUM_SINGLE_DECL(
1485 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1486 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1487
1488static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1489 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1490
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1491/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1492static const char * const rt5677_mono_adc2_r_src[] = {
1493 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1494};
1495
1496static SOC_ENUM_SINGLE_DECL(
1497 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1498 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1499
1500static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1501 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1502
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1503/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1504static const char * const rt5677_mono_adc1_r_src[] = {
1505 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1506};
1507
1508static SOC_ENUM_SINGLE_DECL(
1509 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1510 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1511
1512static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1513 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1514
1515/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1516static const char * const rt5677_stereo4_adc2_src[] = {
1517 "DD MIX1", "DMIC", "DD MIX2"
1518};
1519
1520static SOC_ENUM_SINGLE_DECL(
1521 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1522 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1523
1524static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1525 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1526
1527
1528/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1529static const char * const rt5677_stereo4_adc1_src[] = {
1530 "DD MIX1", "ADC1/2", "DD MIX2"
1531};
1532
1533static SOC_ENUM_SINGLE_DECL(
1534 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1535 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1536
1537static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1538 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1539
1540/* InBound0/1 Source */ /* MX-A3 [14:12] */
1541static const char * const rt5677_inbound01_src[] = {
1542 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1543 "VAD ADC/DAC1 FS"
1544};
1545
1546static SOC_ENUM_SINGLE_DECL(
1547 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1548 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1549
1550static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1551 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1552
1553/* InBound2/3 Source */ /* MX-A3 [10:8] */
1554static const char * const rt5677_inbound23_src[] = {
1555 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1556 "DAC1 FS", "IF4 DAC"
1557};
1558
1559static SOC_ENUM_SINGLE_DECL(
1560 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1561 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1562
1563static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1564 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1565
1566/* InBound4/5 Source */ /* MX-A3 [6:4] */
1567static const char * const rt5677_inbound45_src[] = {
1568 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1569 "IF3 DAC"
1570};
1571
1572static SOC_ENUM_SINGLE_DECL(
1573 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1574 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1575
1576static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1577 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1578
1579/* InBound6 Source */ /* MX-A3 [2:0] */
1580static const char * const rt5677_inbound6_src[] = {
1581 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1582 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1583};
1584
1585static SOC_ENUM_SINGLE_DECL(
1586 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1587 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1588
1589static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1590 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1591
1592/* InBound7 Source */ /* MX-A4 [14:12] */
1593static const char * const rt5677_inbound7_src[] = {
1594 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1595 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1596};
1597
1598static SOC_ENUM_SINGLE_DECL(
1599 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1600 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1601
1602static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1603 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1604
1605/* InBound8 Source */ /* MX-A4 [10:8] */
1606static const char * const rt5677_inbound8_src[] = {
1607 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1608 "MONO ADC MIX L", "DACL1 FS"
1609};
1610
1611static SOC_ENUM_SINGLE_DECL(
1612 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1613 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1614
1615static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1616 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1617
1618/* InBound9 Source */ /* MX-A4 [6:4] */
1619static const char * const rt5677_inbound9_src[] = {
1620 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1621 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1622};
1623
1624static SOC_ENUM_SINGLE_DECL(
1625 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1626 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1627
1628static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1629 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1630
1631/* VAD Source */ /* MX-9F [6:4] */
1632static const char * const rt5677_vad_src[] = {
1633 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1634 "STO3 ADC MIX L"
1635};
1636
1637static SOC_ENUM_SINGLE_DECL(
1638 rt5677_vad_enum, RT5677_VAD_CTRL4,
1639 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1640
1641static const struct snd_kcontrol_new rt5677_vad_src_mux =
1642 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1643
1644/* Sidetone Source */ /* MX-13 [11:9] */
1645static const char * const rt5677_sidetone_src[] = {
1646 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1647};
1648
1649static SOC_ENUM_SINGLE_DECL(
1650 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1651 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1652
1653static const struct snd_kcontrol_new rt5677_sidetone_mux =
1654 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1655
1656/* DAC1/2 Source */ /* MX-15 [1:0] */
1657static const char * const rt5677_dac12_src[] = {
1658 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1659};
1660
1661static SOC_ENUM_SINGLE_DECL(
1662 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1663 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1664
1665static const struct snd_kcontrol_new rt5677_dac12_mux =
1666 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1667
1668/* DAC3 Source */ /* MX-15 [5:4] */
1669static const char * const rt5677_dac3_src[] = {
1670 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1671};
1672
1673static SOC_ENUM_SINGLE_DECL(
1674 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1675 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1676
1677static const struct snd_kcontrol_new rt5677_dac3_mux =
1678 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1679
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1680/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1681static const char * const rt5677_pdm_src[] = {
1682 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1683};
1684
1685static SOC_ENUM_SINGLE_DECL(
1686 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1687 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1688
1689static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1690 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1691
1692static SOC_ENUM_SINGLE_DECL(
1693 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1694 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1695
1696static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1697 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1698
1699static SOC_ENUM_SINGLE_DECL(
1700 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1701 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1702
1703static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1704 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1705
1706static SOC_ENUM_SINGLE_DECL(
1707 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1708 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1709
1710static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1711 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1712
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1713/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1714static const char * const rt5677_if12_adc1_src[] = {
1715 "STO1 ADC MIX", "OB01", "VAD ADC"
1716};
1717
1718static SOC_ENUM_SINGLE_DECL(
1719 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1720 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1721
1722static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1723 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1724
1725static SOC_ENUM_SINGLE_DECL(
1726 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1727 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1728
1729static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1730 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1731
1732static SOC_ENUM_SINGLE_DECL(
1733 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1734 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1735
1736static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1737 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1738
1739/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1740static const char * const rt5677_if12_adc2_src[] = {
1741 "STO2 ADC MIX", "OB23"
1742};
1743
1744static SOC_ENUM_SINGLE_DECL(
1745 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1746 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1747
1748static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1749 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1750
1751static SOC_ENUM_SINGLE_DECL(
1752 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1753 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1754
1755static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1756 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1757
1758static SOC_ENUM_SINGLE_DECL(
1759 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1760 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1761
1762static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1763 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1764
1765/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1766static const char * const rt5677_if12_adc3_src[] = {
1767 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1768};
1769
1770static SOC_ENUM_SINGLE_DECL(
1771 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1772 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1773
1774static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1775 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1776
1777static SOC_ENUM_SINGLE_DECL(
1778 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1779 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1780
1781static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1782 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1783
1784static SOC_ENUM_SINGLE_DECL(
1785 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1786 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1787
1788static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1789 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1790
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1791/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1792static const char * const rt5677_if12_adc4_src[] = {
1793 "STO4 ADC MIX", "OB67", "OB01"
1794};
1795
1796static SOC_ENUM_SINGLE_DECL(
1797 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1798 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1799
1800static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1801 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1802
1803static SOC_ENUM_SINGLE_DECL(
1804 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1805 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1806
1807static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1808 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1809
1810static SOC_ENUM_SINGLE_DECL(
1811 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1812 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1813
1814static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1815 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1816
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1817/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1818static const char * const rt5677_if34_adc_src[] = {
1819 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1820 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1821};
1822
1823static SOC_ENUM_SINGLE_DECL(
1824 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1825 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1826
1827static const struct snd_kcontrol_new rt5677_if3_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1828 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1829
1830static SOC_ENUM_SINGLE_DECL(
1831 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1832 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1833
1834static const struct snd_kcontrol_new rt5677_if4_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1835 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1836
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]1837/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1838static const char * const rt5677_if12_adc_swap_src[] = {
1839 "L/R", "R/L", "L/L", "R/R"
1840};
1841
1842static SOC_ENUM_SINGLE_DECL(
1843 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1844 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1845
1846static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1847 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1848
1849static SOC_ENUM_SINGLE_DECL(
1850 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1851 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1852
1853static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1854 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1855
1856static SOC_ENUM_SINGLE_DECL(
1857 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1858 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1859
1860static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1861 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1862
1863static SOC_ENUM_SINGLE_DECL(
1864 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1865 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1866
1867static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1868 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1869
1870static SOC_ENUM_SINGLE_DECL(
1871 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1872 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1873
1874static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1875 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1876
1877static SOC_ENUM_SINGLE_DECL(
1878 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1879 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1880
1881static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1882 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1883
1884static SOC_ENUM_SINGLE_DECL(
1885 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1886 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1887
1888static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1889 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1890
1891static SOC_ENUM_SINGLE_DECL(
1892 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1893 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1894
1895static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1896 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1897
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]1898/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]1899static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1900 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1901 "3/1/2/4", "3/4/1/2"
1902};
1903
1904static SOC_ENUM_SINGLE_DECL(
1905 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1906 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1907
1908static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1909 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1910
1911/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1912static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1913 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1914 "2/3/1/4", "3/4/1/2"
1915};
1916
1917static SOC_ENUM_SINGLE_DECL(
1918 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1919 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1920
1921static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
1922 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
1923
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1924static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1925 struct snd_kcontrol *kcontrol, int event)
1926{
1927 struct snd_soc_codec *codec = w->codec;
1928 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1929
1930 switch (event) {
1931 case SND_SOC_DAPM_POST_PMU:
1932 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1933 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1934 break;
1935
1936 case SND_SOC_DAPM_PRE_PMD:
1937 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1938 RT5677_PWR_BST1_P, 0);
1939 break;
1940
1941 default:
1942 return 0;
1943 }
1944
1945 return 0;
1946}
1947
1948static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1949 struct snd_kcontrol *kcontrol, int event)
1950{
1951 struct snd_soc_codec *codec = w->codec;
1952 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1953
1954 switch (event) {
1955 case SND_SOC_DAPM_POST_PMU:
1956 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1957 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1958 break;
1959
1960 case SND_SOC_DAPM_PRE_PMD:
1961 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1962 RT5677_PWR_BST2_P, 0);
1963 break;
1964
1965 default:
1966 return 0;
1967 }
1968
1969 return 0;
1970}
1971
1972static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1973 struct snd_kcontrol *kcontrol, int event)
1974{
1975 struct snd_soc_codec *codec = w->codec;
1976 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1977
1978 switch (event) {
1979 case SND_SOC_DAPM_POST_PMU:
1980 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1981 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1982 break;
1983 default:
1984 return 0;
1985 }
1986
1987 return 0;
1988}
1989
1990static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1991 struct snd_kcontrol *kcontrol, int event)
1992{
1993 struct snd_soc_codec *codec = w->codec;
1994 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1995
1996 switch (event) {
1997 case SND_SOC_DAPM_POST_PMU:
1998 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1999 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2000 break;
2001 default:
2002 return 0;
2003 }
2004
2005 return 0;
2006}
2007
2008static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2009 struct snd_kcontrol *kcontrol, int event)
2010{
2011 struct snd_soc_codec *codec = w->codec;
2012 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2013
2014 switch (event) {
2015 case SND_SOC_DAPM_POST_PMU:
2016 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2017 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2018 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2019 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2020 break;
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]2021
2022 case SND_SOC_DAPM_PRE_PMD:
2023 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2024 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2025 RT5677_PWR_CLK_MB, 0);
2026 break;
2027
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2028 default:
2029 return 0;
2030 }
2031
2032 return 0;
2033}
2034
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2035static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2036 struct snd_kcontrol *kcontrol, int event)
2037{
2038 struct snd_soc_codec *codec = w->codec;
2039 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2040 unsigned int value;
2041
2042 switch (event) {
2043 case SND_SOC_DAPM_PRE_PMU:
2044 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2045 if (value & RT5677_IF1_ADC_CTRL_MASK)
2046 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2047 RT5677_IF1_ADC_MODE_MASK,
2048 RT5677_IF1_ADC_MODE_TDM);
2049 break;
2050
2051 default:
2052 return 0;
2053 }
2054
2055 return 0;
2056}
2057
2058static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2059 struct snd_kcontrol *kcontrol, int event)
2060{
2061 struct snd_soc_codec *codec = w->codec;
2062 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2063 unsigned int value;
2064
2065 switch (event) {
2066 case SND_SOC_DAPM_PRE_PMU:
2067 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2068 if (value & RT5677_IF2_ADC_CTRL_MASK)
2069 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2070 RT5677_IF2_ADC_MODE_MASK,
2071 RT5677_IF2_ADC_MODE_TDM);
2072 break;
2073
2074 default:
2075 return 0;
2076 }
2077
2078 return 0;
2079}
2080
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2081static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2082 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2083 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2084 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2085 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2086
2087 /* Input Side */
2088 /* micbias */
Oder Chiou3d0c03d2014-06-10 14:35:23 +0800[diff] [blame]2089 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]2090 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2091 SND_SOC_DAPM_POST_PMU),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2092
2093 /* Input Lines */
2094 SND_SOC_DAPM_INPUT("DMIC L1"),
2095 SND_SOC_DAPM_INPUT("DMIC R1"),
2096 SND_SOC_DAPM_INPUT("DMIC L2"),
2097 SND_SOC_DAPM_INPUT("DMIC R2"),
2098 SND_SOC_DAPM_INPUT("DMIC L3"),
2099 SND_SOC_DAPM_INPUT("DMIC R3"),
2100 SND_SOC_DAPM_INPUT("DMIC L4"),
2101 SND_SOC_DAPM_INPUT("DMIC R4"),
2102
2103 SND_SOC_DAPM_INPUT("IN1P"),
2104 SND_SOC_DAPM_INPUT("IN1N"),
2105 SND_SOC_DAPM_INPUT("IN2P"),
2106 SND_SOC_DAPM_INPUT("IN2N"),
2107
2108 SND_SOC_DAPM_INPUT("Haptic Generator"),
2109
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2110 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2111 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2112 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2113 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2114
2115 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2116 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2117 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2118 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2119 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2120 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2121 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2122 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2123
2124 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2125 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2126
2127 /* Boost */
2128 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2129 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2130 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2131 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2132 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2133 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2134
2135 /* ADCs */
2136 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2137 0, 0),
2138 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2139 0, 0),
2140 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2141
2142 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2143 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2144 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2145 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2146 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2147 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2148 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2149 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2150
2151 /* ADC Mux */
2152 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2153 &rt5677_sto1_dmic_mux),
2154 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2155 &rt5677_sto1_adc1_mux),
2156 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2157 &rt5677_sto1_adc2_mux),
2158 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2159 &rt5677_sto2_dmic_mux),
2160 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2161 &rt5677_sto2_adc1_mux),
2162 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2163 &rt5677_sto2_adc2_mux),
2164 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2165 &rt5677_sto2_adc_lr_mux),
2166 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2167 &rt5677_sto3_dmic_mux),
2168 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2169 &rt5677_sto3_adc1_mux),
2170 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2171 &rt5677_sto3_adc2_mux),
2172 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2173 &rt5677_sto4_dmic_mux),
2174 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2175 &rt5677_sto4_adc1_mux),
2176 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2177 &rt5677_sto4_adc2_mux),
2178 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2179 &rt5677_mono_dmic_l_mux),
2180 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2181 &rt5677_mono_dmic_r_mux),
2182 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2183 &rt5677_mono_adc2_l_mux),
2184 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2185 &rt5677_mono_adc1_l_mux),
2186 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2187 &rt5677_mono_adc1_r_mux),
2188 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2189 &rt5677_mono_adc2_r_mux),
2190
2191 /* ADC Mixer */
2192 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2193 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2194 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2195 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2196 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2197 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2198 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2199 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2200 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2201 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2202 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2203 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2204 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2205 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2206 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2207 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2208 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2209 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2210 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2211 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2212 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2213 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2214 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2215 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2216 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2217 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2218 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2219 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2220 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2221 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2222 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2223 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2224
2225 /* ADC PGA */
2226 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2227 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2228 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2229 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2230 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2231 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2232 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2233 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2234 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2235 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2236 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2237 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2238 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2239 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2240 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2241 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2242
2243 /* DSP */
2244 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2245 &rt5677_ib9_src_mux),
2246 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2247 &rt5677_ib8_src_mux),
2248 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2249 &rt5677_ib7_src_mux),
2250 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2251 &rt5677_ib6_src_mux),
2252 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2253 &rt5677_ib45_src_mux),
2254 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2255 &rt5677_ib23_src_mux),
2256 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2257 &rt5677_ib01_src_mux),
2258 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2259 &rt5677_ib45_bypass_src_mux),
2260 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2261 &rt5677_ib23_bypass_src_mux),
2262 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2263 &rt5677_ib01_bypass_src_mux),
2264 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2265 &rt5677_ob23_bypass_src_mux),
2266 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2267 &rt5677_ob01_bypass_src_mux),
2268
2269 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2270 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2271
2272 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2273 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2274 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2275 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2276 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2277 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2278
2279 /* Digital Interface */
2280 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2281 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2282 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2283 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2284 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2285 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2286 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2287 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2288 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2289 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2290 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2291 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2292 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2293 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2294 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2295 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2296 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2297 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2298
2299 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2300 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2301 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2302 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2303 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2304 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2305 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2306 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2307 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2308 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2309 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2310 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2311 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2312 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2313 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2314 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2315 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2316 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2317
2318 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2319 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2320 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2321 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2322 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2323 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2324 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2325 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2326
2327 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2328 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2329 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2330 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2331 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2332 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2333 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2334 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2335
2336 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2337 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2338 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2339 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2340 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2341 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2342 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2343 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2344 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2345 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2346 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2347 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2348 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2349 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2350 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2351 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2352 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2353 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2354
2355 /* Digital Interface Select */
2356 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2357 &rt5677_if1_adc1_mux),
2358 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2359 &rt5677_if1_adc2_mux),
2360 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2361 &rt5677_if1_adc3_mux),
2362 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2363 &rt5677_if1_adc4_mux),
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2364 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2365 &rt5677_if1_adc1_swap_mux),
2366 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2367 &rt5677_if1_adc2_swap_mux),
2368 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2369 &rt5677_if1_adc3_swap_mux),
2370 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2371 &rt5677_if1_adc4_swap_mux),
2372 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2373 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2374 SND_SOC_DAPM_PRE_PMU),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2375 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2376 &rt5677_if2_adc1_mux),
2377 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2378 &rt5677_if2_adc2_mux),
2379 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2380 &rt5677_if2_adc3_mux),
2381 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2382 &rt5677_if2_adc4_mux),
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2383 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2384 &rt5677_if2_adc1_swap_mux),
2385 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2386 &rt5677_if2_adc2_swap_mux),
2387 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2388 &rt5677_if2_adc3_swap_mux),
2389 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2390 &rt5677_if2_adc4_swap_mux),
2391 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2392 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2393 SND_SOC_DAPM_PRE_PMU),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2394 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2395 &rt5677_if3_adc_mux),
2396 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2397 &rt5677_if4_adc_mux),
2398 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2399 &rt5677_slb_adc1_mux),
2400 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2401 &rt5677_slb_adc2_mux),
2402 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2403 &rt5677_slb_adc3_mux),
2404 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2405 &rt5677_slb_adc4_mux),
2406
2407 /* Audio Interface */
2408 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2409 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2410 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2411 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2412 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2413 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2414 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2415 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2416 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2417 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2418
2419 /* Sidetone Mux */
2420 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2421 &rt5677_sidetone_mux),
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame]2422 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2423 RT5677_ST_EN_SFT, 0, NULL, 0),
2424
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2425 /* VAD Mux*/
2426 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2427 &rt5677_vad_src_mux),
2428
2429 /* Tensilica DSP */
2430 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2431 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2432 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2433 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2434 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2435 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2436 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2437 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2438 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2439 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2440 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2441 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2442 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2443
2444 /* Output Side */
Oder Chioud65fd3a2014-11-05 13:42:52 +0800[diff] [blame^]2445 /* DAC mixer before sound effect */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2446 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2447 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2448 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2449 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2450 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2451
2452 /* DAC Mux */
2453 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2454 &rt5677_dac1_mux),
2455 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2456 &rt5677_adda1_mux),
2457 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2458 &rt5677_dac12_mux),
2459 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2460 &rt5677_dac3_mux),
2461
2462 /* DAC2 channel Mux */
2463 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2464 &rt5677_dac2_l_mux),
2465 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2466 &rt5677_dac2_r_mux),
2467
2468 /* DAC3 channel Mux */
2469 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2470 &rt5677_dac3_l_mux),
2471 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2472 &rt5677_dac3_r_mux),
2473
2474 /* DAC4 channel Mux */
2475 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2476 &rt5677_dac4_l_mux),
2477 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2478 &rt5677_dac4_r_mux),
2479
2480 /* DAC Mixer */
2481 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2482 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2483 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2484 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2485 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2486 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2487
2488 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2489 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2490 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2491 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2492 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2493 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2494 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2495 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2496 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2497 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2498 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2499 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2500 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2501 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2502 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2503 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2504 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2505 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2506 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2507 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2508
2509 /* DACs */
2510 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2511 RT5677_PWR_DAC1_BIT, 0),
2512 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2513 RT5677_PWR_DAC2_BIT, 0),
2514 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2515 RT5677_PWR_DAC3_BIT, 0),
2516
2517 /* PDM */
2518 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2519 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2520 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2521 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2522
2523 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2524 1, &rt5677_pdm1_l_mux),
2525 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2526 1, &rt5677_pdm1_r_mux),
2527 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2528 1, &rt5677_pdm2_l_mux),
2529 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2530 1, &rt5677_pdm2_r_mux),
2531
2532 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2533 0, NULL, 0),
2534 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2535 0, NULL, 0),
2536 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2537 0, NULL, 0),
2538
2539 /* Output Lines */
2540 SND_SOC_DAPM_OUTPUT("LOUT1"),
2541 SND_SOC_DAPM_OUTPUT("LOUT2"),
2542 SND_SOC_DAPM_OUTPUT("LOUT3"),
2543 SND_SOC_DAPM_OUTPUT("PDM1L"),
2544 SND_SOC_DAPM_OUTPUT("PDM1R"),
2545 SND_SOC_DAPM_OUTPUT("PDM2L"),
2546 SND_SOC_DAPM_OUTPUT("PDM2R"),
2547};
2548
2549static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2550 { "DMIC1", NULL, "DMIC L1" },
2551 { "DMIC1", NULL, "DMIC R1" },
2552 { "DMIC2", NULL, "DMIC L2" },
2553 { "DMIC2", NULL, "DMIC R2" },
2554 { "DMIC3", NULL, "DMIC L3" },
2555 { "DMIC3", NULL, "DMIC R3" },
2556 { "DMIC4", NULL, "DMIC L4" },
2557 { "DMIC4", NULL, "DMIC R4" },
2558
2559 { "DMIC L1", NULL, "DMIC CLK" },
2560 { "DMIC R1", NULL, "DMIC CLK" },
2561 { "DMIC L2", NULL, "DMIC CLK" },
2562 { "DMIC R2", NULL, "DMIC CLK" },
2563 { "DMIC L3", NULL, "DMIC CLK" },
2564 { "DMIC R3", NULL, "DMIC CLK" },
2565 { "DMIC L4", NULL, "DMIC CLK" },
2566 { "DMIC R4", NULL, "DMIC CLK" },
2567
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2568 { "DMIC L1", NULL, "DMIC1 power" },
2569 { "DMIC R1", NULL, "DMIC1 power" },
2570 { "DMIC L3", NULL, "DMIC3 power" },
2571 { "DMIC R3", NULL, "DMIC3 power" },
2572 { "DMIC L4", NULL, "DMIC4 power" },
2573 { "DMIC R4", NULL, "DMIC4 power" },
2574
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2575 { "BST1", NULL, "IN1P" },
2576 { "BST1", NULL, "IN1N" },
2577 { "BST2", NULL, "IN2P" },
2578 { "BST2", NULL, "IN2N" },
2579
Bard Liao22e51342014-08-27 19:50:33 +0800[diff] [blame]2580 { "IN1P", NULL, "MICBIAS1" },
2581 { "IN1N", NULL, "MICBIAS1" },
2582 { "IN2P", NULL, "MICBIAS1" },
2583 { "IN2N", NULL, "MICBIAS1" },
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2584
2585 { "ADC 1", NULL, "BST1" },
2586 { "ADC 1", NULL, "ADC 1 power" },
2587 { "ADC 1", NULL, "ADC1 clock" },
2588 { "ADC 2", NULL, "BST2" },
2589 { "ADC 2", NULL, "ADC 2 power" },
2590 { "ADC 2", NULL, "ADC2 clock" },
2591
2592 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2593 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2594 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2595 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2596
2597 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2598 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2599 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2600 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2601
2602 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2603 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2604 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2605 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2606
2607 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2608 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2609 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2610 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2611
2612 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2613 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2614 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2615 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2616
2617 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2618 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2619 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2620 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2621
2622 { "ADC 1_2", NULL, "ADC 1" },
2623 { "ADC 1_2", NULL, "ADC 2" },
2624
2625 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2626 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2627 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2628
2629 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2630 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2631 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2632
2633 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2634 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2635 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2636
2637 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2638 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2639 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2640
2641 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2642 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2643 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2644
2645 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2646 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2647 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2648
2649 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2650 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2651 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2652
2653 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2654 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2655 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2656
2657 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2658 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2659 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2660
2661 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2662 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2663 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2664
2665 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2666 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2667 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2668
2669 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2670 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2671 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2672
2673 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2674 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2675 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2676 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2677
2678 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2679 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2680 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2681
2682 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2683 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2684 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2685
2686 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2687 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2688
2689 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2690 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2691 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2692 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2693
2694 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2695 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2696
2697 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2698 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2699
2700 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2701 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2702 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2703
2704 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2705 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2706 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2707
2708 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2709 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2710
2711 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2712 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2713 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2714 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2715
2716 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2717 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2718 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2719
2720 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2721 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2722 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2723
2724 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2725 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2726
2727 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2728 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2729 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2730 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2731
2732 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2733 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2734 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2735
2736 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2737 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2738 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2739
2740 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2741 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2742
2743 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2744 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2745 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2746 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2747
2748 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2749 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2750 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2751 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2752
2753 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2754 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2755
2756 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2757 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2758 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2759 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2760 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2761
2762 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2763 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2764 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2765
2766 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2767 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2768
2769 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2770 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2771 { "IF1 ADC3 Mux", "OB45", "OB45" },
2772
2773 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2774 { "IF1 ADC4 Mux", "OB67", "OB67" },
2775 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2776
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2777 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
2778 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
2779 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
2780 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
2781
2782 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
2783 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
2784 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
2785 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
2786
2787 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
2788 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
2789 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
2790 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
2791
2792 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
2793 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
2794 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
2795 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
2796
2797 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
2798 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
2799 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
2800 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
2801
2802 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
2803 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
2804 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
2805 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
2806 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
2807 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
2808 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
2809 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
2810
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2811 { "AIF1TX", NULL, "I2S1" },
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2812 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2813
2814 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2815 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2816 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2817
2818 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2819 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2820
2821 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2822 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2823 { "IF2 ADC3 Mux", "OB45", "OB45" },
2824
2825 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2826 { "IF2 ADC4 Mux", "OB67", "OB67" },
2827 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2828
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2829 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
2830 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
2831 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
2832 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
2833
2834 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
2835 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
2836 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
2837 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
2838
2839 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
2840 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
2841 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
2842 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
2843
2844 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
2845 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
2846 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
2847 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
2848
2849 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
2850 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
2851 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
2852 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
2853
2854 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
2855 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
2856 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
2857 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
2858 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
2859 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
2860 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
2861 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
2862
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2863 { "AIF2TX", NULL, "I2S2" },
Oder Chioue6f6ebc2014-10-22 16:11:39 +0800[diff] [blame]2864 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2865
2866 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2867 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2868 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2869 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2870 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2871 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2872 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2873 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2874
2875 { "AIF3TX", NULL, "I2S3" },
2876 { "AIF3TX", NULL, "IF3 ADC Mux" },
2877
2878 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2879 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2880 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2881 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2882 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2883 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2884 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2885 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2886
2887 { "AIF4TX", NULL, "I2S4" },
2888 { "AIF4TX", NULL, "IF4 ADC Mux" },
2889
2890 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2891 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2892 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2893
2894 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2895 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2896
2897 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2898 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2899 { "SLB ADC3 Mux", "OB45", "OB45" },
2900
2901 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2902 { "SLB ADC4 Mux", "OB67", "OB67" },
2903 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2904
2905 { "SLBTX", NULL, "SLB" },
2906 { "SLBTX", NULL, "SLB ADC1 Mux" },
2907 { "SLBTX", NULL, "SLB ADC2 Mux" },
2908 { "SLBTX", NULL, "SLB ADC3 Mux" },
2909 { "SLBTX", NULL, "SLB ADC4 Mux" },
2910
2911 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2912 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2913 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2914 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2915 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2916
2917 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2918 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2919
2920 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2921 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2922 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2923 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2924 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2925 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2926
2927 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2928 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2929
2930 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2931 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2932 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2933 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2934 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2935
2936 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2937 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2938
2939 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2940 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2941 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2942 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2943 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2944 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2945 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2946 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2947
2948 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2949 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2950 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2951 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2952 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2953 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2954 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2955 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2956
2957 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2958 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2959 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2960 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2961 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2962 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2963
2964 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2965 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2966 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2967 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2968 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2969 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2970 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2971
2972 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2973 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2974 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2975 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2976 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2977 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2978 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2979
2980 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2981 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2982 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2983 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2984 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2985 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2986 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2987
2988 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2989 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2990 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2991 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2992 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2993 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2994 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2995
2996 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2997 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2998 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2999 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3000 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3001 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3002 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3003
3004 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3005 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3006 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3007 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3008 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3009 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3010 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3011
3012 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3013 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3014 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3015 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3016 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3017 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3018 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3019
3020 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3021 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3022 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3023 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3024
3025 { "OutBound2", NULL, "OB23 Bypass Mux" },
3026 { "OutBound3", NULL, "OB23 Bypass Mux" },
3027 { "OutBound4", NULL, "OB4 MIX" },
3028 { "OutBound5", NULL, "OB5 MIX" },
3029 { "OutBound6", NULL, "OB6 MIX" },
3030 { "OutBound7", NULL, "OB7 MIX" },
3031
3032 { "OB45", NULL, "OutBound4" },
3033 { "OB45", NULL, "OutBound5" },
3034 { "OB67", NULL, "OutBound6" },
3035 { "OB67", NULL, "OutBound7" },
3036
3037 { "IF1 DAC0", NULL, "AIF1RX" },
3038 { "IF1 DAC1", NULL, "AIF1RX" },
3039 { "IF1 DAC2", NULL, "AIF1RX" },
3040 { "IF1 DAC3", NULL, "AIF1RX" },
3041 { "IF1 DAC4", NULL, "AIF1RX" },
3042 { "IF1 DAC5", NULL, "AIF1RX" },
3043 { "IF1 DAC6", NULL, "AIF1RX" },
3044 { "IF1 DAC7", NULL, "AIF1RX" },
3045 { "IF1 DAC0", NULL, "I2S1" },
3046 { "IF1 DAC1", NULL, "I2S1" },
3047 { "IF1 DAC2", NULL, "I2S1" },
3048 { "IF1 DAC3", NULL, "I2S1" },
3049 { "IF1 DAC4", NULL, "I2S1" },
3050 { "IF1 DAC5", NULL, "I2S1" },
3051 { "IF1 DAC6", NULL, "I2S1" },
3052 { "IF1 DAC7", NULL, "I2S1" },
3053
3054 { "IF1 DAC01", NULL, "IF1 DAC0" },
3055 { "IF1 DAC01", NULL, "IF1 DAC1" },
3056 { "IF1 DAC23", NULL, "IF1 DAC2" },
3057 { "IF1 DAC23", NULL, "IF1 DAC3" },
3058 { "IF1 DAC45", NULL, "IF1 DAC4" },
3059 { "IF1 DAC45", NULL, "IF1 DAC5" },
3060 { "IF1 DAC67", NULL, "IF1 DAC6" },
3061 { "IF1 DAC67", NULL, "IF1 DAC7" },
3062
3063 { "IF2 DAC0", NULL, "AIF2RX" },
3064 { "IF2 DAC1", NULL, "AIF2RX" },
3065 { "IF2 DAC2", NULL, "AIF2RX" },
3066 { "IF2 DAC3", NULL, "AIF2RX" },
3067 { "IF2 DAC4", NULL, "AIF2RX" },
3068 { "IF2 DAC5", NULL, "AIF2RX" },
3069 { "IF2 DAC6", NULL, "AIF2RX" },
3070 { "IF2 DAC7", NULL, "AIF2RX" },
3071 { "IF2 DAC0", NULL, "I2S2" },
3072 { "IF2 DAC1", NULL, "I2S2" },
3073 { "IF2 DAC2", NULL, "I2S2" },
3074 { "IF2 DAC3", NULL, "I2S2" },
3075 { "IF2 DAC4", NULL, "I2S2" },
3076 { "IF2 DAC5", NULL, "I2S2" },
3077 { "IF2 DAC6", NULL, "I2S2" },
3078 { "IF2 DAC7", NULL, "I2S2" },
3079
3080 { "IF2 DAC01", NULL, "IF2 DAC0" },
3081 { "IF2 DAC01", NULL, "IF2 DAC1" },
3082 { "IF2 DAC23", NULL, "IF2 DAC2" },
3083 { "IF2 DAC23", NULL, "IF2 DAC3" },
3084 { "IF2 DAC45", NULL, "IF2 DAC4" },
3085 { "IF2 DAC45", NULL, "IF2 DAC5" },
3086 { "IF2 DAC67", NULL, "IF2 DAC6" },
3087 { "IF2 DAC67", NULL, "IF2 DAC7" },
3088
3089 { "IF3 DAC", NULL, "AIF3RX" },
3090 { "IF3 DAC", NULL, "I2S3" },
3091
3092 { "IF4 DAC", NULL, "AIF4RX" },
3093 { "IF4 DAC", NULL, "I2S4" },
3094
3095 { "IF3 DAC L", NULL, "IF3 DAC" },
3096 { "IF3 DAC R", NULL, "IF3 DAC" },
3097
3098 { "IF4 DAC L", NULL, "IF4 DAC" },
3099 { "IF4 DAC R", NULL, "IF4 DAC" },
3100
3101 { "SLB DAC0", NULL, "SLBRX" },
3102 { "SLB DAC1", NULL, "SLBRX" },
3103 { "SLB DAC2", NULL, "SLBRX" },
3104 { "SLB DAC3", NULL, "SLBRX" },
3105 { "SLB DAC4", NULL, "SLBRX" },
3106 { "SLB DAC5", NULL, "SLBRX" },
3107 { "SLB DAC6", NULL, "SLBRX" },
3108 { "SLB DAC7", NULL, "SLBRX" },
3109 { "SLB DAC0", NULL, "SLB" },
3110 { "SLB DAC1", NULL, "SLB" },
3111 { "SLB DAC2", NULL, "SLB" },
3112 { "SLB DAC3", NULL, "SLB" },
3113 { "SLB DAC4", NULL, "SLB" },
3114 { "SLB DAC5", NULL, "SLB" },
3115 { "SLB DAC6", NULL, "SLB" },
3116 { "SLB DAC7", NULL, "SLB" },
3117
3118 { "SLB DAC01", NULL, "SLB DAC0" },
3119 { "SLB DAC01", NULL, "SLB DAC1" },
3120 { "SLB DAC23", NULL, "SLB DAC2" },
3121 { "SLB DAC23", NULL, "SLB DAC3" },
3122 { "SLB DAC45", NULL, "SLB DAC4" },
3123 { "SLB DAC45", NULL, "SLB DAC5" },
3124 { "SLB DAC67", NULL, "SLB DAC6" },
3125 { "SLB DAC67", NULL, "SLB DAC7" },
3126
3127 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3128 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3129 { "ADDA1 Mux", "OB 67", "OB67" },
3130
3131 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3132 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3133 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3134 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3135 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3136 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3137
3138 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3139 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3140 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
3141 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3142 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3143 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
3144
3145 { "DAC1 FS", NULL, "DAC1 MIXL" },
3146 { "DAC1 FS", NULL, "DAC1 MIXR" },
3147
3148 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3149 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3150 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3151 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3152 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3153 { "DAC2 L Mux", "OB 2", "OutBound2" },
3154
3155 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3156 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3157 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3158 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3159 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3160 { "DAC2 R Mux", "OB 3", "OutBound3" },
3161 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3162 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3163
3164 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3165 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3166 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3167 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3168 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3169 { "DAC3 L Mux", "OB 4", "OutBound4" },
3170
3171 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3172 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3173 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3174 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3175 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3176 { "DAC3 R Mux", "OB 5", "OutBound5" },
3177
3178 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3179 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3180 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3181 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3182 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3183 { "DAC4 L Mux", "OB 6", "OutBound6" },
3184
3185 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3186 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3187 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3188 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3189 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3190 { "DAC4 R Mux", "OB 7", "OutBound7" },
3191
3192 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3193 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3194 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3195 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3196 { "Sidetone Mux", "ADC1", "ADC 1" },
3197 { "Sidetone Mux", "ADC2", "ADC 2" },
Oder Chiou90bdbb42014-09-18 14:45:59 +0800[diff] [blame]3198 { "Sidetone Mux", NULL, "Sidetone Power" },
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3199
3200 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3201 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3202 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3203 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3204 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3205 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3206 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3207 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3208 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3209 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3210
3211 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3212 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3213 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3214 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3215 { "Mono DAC MIXL", NULL, "dac mono left filter" },
3216 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3217 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3218 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3219 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3220 { "Mono DAC MIXR", NULL, "dac mono right filter" },
3221
3222 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3223 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3224 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3225 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3226 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3227 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3228 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3229 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3230
3231 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3232 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3233 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3234 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3235 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3236 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3237 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3238 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3239
3240 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3241 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3242 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3243 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3244 { "DD1 MIX", NULL, "DD1 MIXL" },
3245 { "DD1 MIX", NULL, "DD1 MIXR" },
3246 { "DD2 MIX", NULL, "DD2 MIXL" },
3247 { "DD2 MIX", NULL, "DD2 MIXR" },
3248
3249 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3250 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3251 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3252 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3253
3254 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3255 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3256 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3257 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3258
3259 { "DAC 1", NULL, "DAC12 SRC Mux" },
3260 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
3261 { "DAC 2", NULL, "DAC12 SRC Mux" },
3262 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
3263 { "DAC 3", NULL, "DAC3 SRC Mux" },
3264 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
3265
3266 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3267 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3268 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3269 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3270 { "PDM1 L Mux", NULL, "PDM1 Power" },
3271 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3272 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3273 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3274 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3275 { "PDM1 R Mux", NULL, "PDM1 Power" },
3276 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3277 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3278 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3279 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3280 { "PDM2 L Mux", NULL, "PDM2 Power" },
3281 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3282 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3283 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3284 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3285 { "PDM2 R Mux", NULL, "PDM2 Power" },
3286
3287 { "LOUT1 amp", NULL, "DAC 1" },
3288 { "LOUT2 amp", NULL, "DAC 2" },
3289 { "LOUT3 amp", NULL, "DAC 3" },
3290
3291 { "LOUT1", NULL, "LOUT1 amp" },
3292 { "LOUT2", NULL, "LOUT2 amp" },
3293 { "LOUT3", NULL, "LOUT3 amp" },
3294
3295 { "PDM1L", NULL, "PDM1 L Mux" },
3296 { "PDM1R", NULL, "PDM1 R Mux" },
3297 { "PDM2L", NULL, "PDM2 L Mux" },
3298 { "PDM2R", NULL, "PDM2 R Mux" },
3299};
3300
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3301static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3302 { "DMIC L2", NULL, "DMIC1 power" },
3303 { "DMIC R2", NULL, "DMIC1 power" },
3304};
3305
3306static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3307 { "DMIC L2", NULL, "DMIC2 power" },
3308 { "DMIC R2", NULL, "DMIC2 power" },
3309};
3310
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3311static int rt5677_hw_params(struct snd_pcm_substream *substream,
3312 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3313{
3314 struct snd_soc_codec *codec = dai->codec;
3315 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3316 unsigned int val_len = 0, val_clk, mask_clk;
3317 int pre_div, bclk_ms, frame_size;
3318
3319 rt5677->lrck[dai->id] = params_rate(params);
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]3320 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3321 if (pre_div < 0) {
Anatol Pomozov8a4bd602014-10-15 13:55:32 -0700[diff] [blame]3322 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3323 rt5677->sysclk, rt5677->lrck[dai->id]);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3324 return -EINVAL;
3325 }
3326 frame_size = snd_soc_params_to_frame_size(params);
3327 if (frame_size < 0) {
3328 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3329 return -EINVAL;
3330 }
3331 bclk_ms = frame_size > 32;
3332 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3333
3334 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3335 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3336 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3337 bclk_ms, pre_div, dai->id);
3338
3339 switch (params_width(params)) {
3340 case 16:
3341 break;
3342 case 20:
3343 val_len |= RT5677_I2S_DL_20;
3344 break;
3345 case 24:
3346 val_len |= RT5677_I2S_DL_24;
3347 break;
3348 case 8:
3349 val_len |= RT5677_I2S_DL_8;
3350 break;
3351 default:
3352 return -EINVAL;
3353 }
3354
3355 switch (dai->id) {
3356 case RT5677_AIF1:
3357 mask_clk = RT5677_I2S_PD1_MASK;
3358 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3359 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3360 RT5677_I2S_DL_MASK, val_len);
3361 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3362 mask_clk, val_clk);
3363 break;
3364 case RT5677_AIF2:
3365 mask_clk = RT5677_I2S_PD2_MASK;
3366 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3367 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3368 RT5677_I2S_DL_MASK, val_len);
3369 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3370 mask_clk, val_clk);
3371 break;
3372 case RT5677_AIF3:
3373 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3374 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3375 pre_div << RT5677_I2S_PD3_SFT;
3376 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3377 RT5677_I2S_DL_MASK, val_len);
3378 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3379 mask_clk, val_clk);
3380 break;
3381 case RT5677_AIF4:
3382 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3383 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3384 pre_div << RT5677_I2S_PD4_SFT;
3385 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3386 RT5677_I2S_DL_MASK, val_len);
3387 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3388 mask_clk, val_clk);
3389 break;
3390 default:
3391 break;
3392 }
3393
3394 return 0;
3395}
3396
3397static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3398{
3399 struct snd_soc_codec *codec = dai->codec;
3400 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3401 unsigned int reg_val = 0;
3402
3403 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3404 case SND_SOC_DAIFMT_CBM_CFM:
3405 rt5677->master[dai->id] = 1;
3406 break;
3407 case SND_SOC_DAIFMT_CBS_CFS:
3408 reg_val |= RT5677_I2S_MS_S;
3409 rt5677->master[dai->id] = 0;
3410 break;
3411 default:
3412 return -EINVAL;
3413 }
3414
3415 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3416 case SND_SOC_DAIFMT_NB_NF:
3417 break;
3418 case SND_SOC_DAIFMT_IB_NF:
3419 reg_val |= RT5677_I2S_BP_INV;
3420 break;
3421 default:
3422 return -EINVAL;
3423 }
3424
3425 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3426 case SND_SOC_DAIFMT_I2S:
3427 break;
3428 case SND_SOC_DAIFMT_LEFT_J:
3429 reg_val |= RT5677_I2S_DF_LEFT;
3430 break;
3431 case SND_SOC_DAIFMT_DSP_A:
3432 reg_val |= RT5677_I2S_DF_PCM_A;
3433 break;
3434 case SND_SOC_DAIFMT_DSP_B:
3435 reg_val |= RT5677_I2S_DF_PCM_B;
3436 break;
3437 default:
3438 return -EINVAL;
3439 }
3440
3441 switch (dai->id) {
3442 case RT5677_AIF1:
3443 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3444 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3445 RT5677_I2S_DF_MASK, reg_val);
3446 break;
3447 case RT5677_AIF2:
3448 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3449 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3450 RT5677_I2S_DF_MASK, reg_val);
3451 break;
3452 case RT5677_AIF3:
3453 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3454 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3455 RT5677_I2S_DF_MASK, reg_val);
3456 break;
3457 case RT5677_AIF4:
3458 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3459 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3460 RT5677_I2S_DF_MASK, reg_val);
3461 break;
3462 default:
3463 break;
3464 }
3465
3466
3467 return 0;
3468}
3469
3470static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3471 int clk_id, unsigned int freq, int dir)
3472{
3473 struct snd_soc_codec *codec = dai->codec;
3474 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3475 unsigned int reg_val = 0;
3476
3477 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3478 return 0;
3479
3480 switch (clk_id) {
3481 case RT5677_SCLK_S_MCLK:
3482 reg_val |= RT5677_SCLK_SRC_MCLK;
3483 break;
3484 case RT5677_SCLK_S_PLL1:
3485 reg_val |= RT5677_SCLK_SRC_PLL1;
3486 break;
3487 case RT5677_SCLK_S_RCCLK:
3488 reg_val |= RT5677_SCLK_SRC_RCCLK;
3489 break;
3490 default:
3491 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3492 return -EINVAL;
3493 }
3494 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3495 RT5677_SCLK_SRC_MASK, reg_val);
3496 rt5677->sysclk = freq;
3497 rt5677->sysclk_src = clk_id;
3498
3499 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3500
3501 return 0;
3502}
3503
3504/**
3505 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3506 * @freq_in: external clock provided to codec.
3507 * @freq_out: target clock which codec works on.
3508 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3509 *
3510 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3511 *
3512 * Returns 0 for success or negative error code.
3513 */
3514static int rt5677_pll_calc(const unsigned int freq_in,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3515 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3516{
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3517 if (RT5677_PLL_INP_MIN > freq_in)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3518 return -EINVAL;
3519
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3520 return rl6231_pll_calc(freq_in, freq_out, pll_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3521}
3522
3523static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3524 unsigned int freq_in, unsigned int freq_out)
3525{
3526 struct snd_soc_codec *codec = dai->codec;
3527 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3528 struct rl6231_pll_code pll_code;
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3529 int ret;
3530
3531 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3532 freq_out == rt5677->pll_out)
3533 return 0;
3534
3535 if (!freq_in || !freq_out) {
3536 dev_dbg(codec->dev, "PLL disabled\n");
3537
3538 rt5677->pll_in = 0;
3539 rt5677->pll_out = 0;
3540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3541 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3542 return 0;
3543 }
3544
3545 switch (source) {
3546 case RT5677_PLL1_S_MCLK:
3547 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3548 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3549 break;
3550 case RT5677_PLL1_S_BCLK1:
3551 case RT5677_PLL1_S_BCLK2:
3552 case RT5677_PLL1_S_BCLK3:
3553 case RT5677_PLL1_S_BCLK4:
3554 switch (dai->id) {
3555 case RT5677_AIF1:
3556 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3557 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3558 break;
3559 case RT5677_AIF2:
3560 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3561 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3562 break;
3563 case RT5677_AIF3:
3564 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3565 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3566 break;
3567 case RT5677_AIF4:
3568 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3569 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3570 break;
3571 default:
3572 break;
3573 }
3574 break;
3575 default:
3576 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3577 return -EINVAL;
3578 }
3579
3580 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3581 if (ret < 0) {
3582 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3583 return ret;
3584 }
3585
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3586 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3587 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3588 pll_code.n_code, pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3589
3590 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3591 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3592 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3593 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3594 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3595
3596 rt5677->pll_in = freq_in;
3597 rt5677->pll_out = freq_out;
3598 rt5677->pll_src = source;
3599
3600 return 0;
3601}
3602
Oder Chiou48561af2014-09-17 15:12:33 +0800[diff] [blame]3603static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3604 unsigned int rx_mask, int slots, int slot_width)
3605{
3606 struct snd_soc_codec *codec = dai->codec;
3607 unsigned int val = 0;
3608
3609 if (rx_mask || tx_mask)
3610 val |= (1 << 12);
3611
3612 switch (slots) {
3613 case 4:
3614 val |= (1 << 10);
3615 break;
3616 case 6:
3617 val |= (2 << 10);
3618 break;
3619 case 8:
3620 val |= (3 << 10);
3621 break;
3622 case 2:
3623 default:
3624 break;
3625 }
3626
3627 switch (slot_width) {
3628 case 20:
3629 val |= (1 << 8);
3630 break;
3631 case 24:
3632 val |= (2 << 8);
3633 break;
3634 case 32:
3635 val |= (3 << 8);
3636 break;
3637 case 16:
3638 default:
3639 break;
3640 }
3641
3642 switch (dai->id) {
3643 case RT5677_AIF1:
3644 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3645 break;
3646 case RT5677_AIF2:
3647 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3648 break;
3649 default:
3650 break;
3651 }
3652
3653 return 0;
3654}
3655
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3656static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3657 enum snd_soc_bias_level level)
3658{
3659 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3660
3661 switch (level) {
3662 case SND_SOC_BIAS_ON:
3663 break;
3664
3665 case SND_SOC_BIAS_PREPARE:
3666 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]3667 rt5677_set_dsp_vad(codec, false);
3668
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3670 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3671 0x0055);
3672 regmap_update_bits(rt5677->regmap,
3673 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3674 0x0f00, 0x0f00);
3675 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3676 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3677 RT5677_PWR_BG | RT5677_PWR_VREF2,
3678 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3679 RT5677_PWR_BG | RT5677_PWR_VREF2);
3680 mdelay(20);
3681 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3682 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3683 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3684 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3685 RT5677_PWR_CORE, RT5677_PWR_CORE);
3686 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3687 0x1, 0x1);
3688 }
3689 break;
3690
3691 case SND_SOC_BIAS_STANDBY:
3692 break;
3693
3694 case SND_SOC_BIAS_OFF:
3695 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3696 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3697 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
Oder Chiouf18803a2014-07-07 15:37:00 +0800[diff] [blame]3698 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3700 regmap_update_bits(rt5677->regmap,
3701 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]3702
3703 if (rt5677->dsp_vad_en)
3704 rt5677_set_dsp_vad(codec, true);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3705 break;
3706
3707 default:
3708 break;
3709 }
3710 codec->dapm.bias_level = level;
3711
3712 return 0;
3713}
3714
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3715#ifdef CONFIG_GPIOLIB
3716static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3717{
3718 return container_of(chip, struct rt5677_priv, gpio_chip);
3719}
3720
3721static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3722{
3723 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3724
3725 switch (offset) {
3726 case RT5677_GPIO1 ... RT5677_GPIO5:
3727 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3728 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3729 break;
3730
3731 case RT5677_GPIO6:
3732 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3733 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3734 break;
3735
3736 default:
3737 break;
3738 }
3739}
3740
3741static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3742 unsigned offset, int value)
3743{
3744 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3745
3746 switch (offset) {
3747 case RT5677_GPIO1 ... RT5677_GPIO5:
3748 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3749 0x3 << (offset * 3 + 1),
3750 (0x2 | !!value) << (offset * 3 + 1));
3751 break;
3752
3753 case RT5677_GPIO6:
3754 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3755 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3756 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3757 break;
3758
3759 default:
3760 break;
3761 }
3762
3763 return 0;
3764}
3765
3766static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3767{
3768 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3769 int value, ret;
3770
3771 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3772 if (ret < 0)
3773 return ret;
3774
3775 return (value & (0x1 << offset)) >> offset;
3776}
3777
3778static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3779{
3780 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3781
3782 switch (offset) {
3783 case RT5677_GPIO1 ... RT5677_GPIO5:
3784 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3785 0x1 << (offset * 3 + 2), 0x0);
3786 break;
3787
3788 case RT5677_GPIO6:
3789 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3790 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3791 break;
3792
3793 default:
3794 break;
3795 }
3796
3797 return 0;
3798}
3799
Anatol Pomozov40eb90a2014-10-10 20:46:36 -0700[diff] [blame]3800/** Configures the gpio as
3801 * 0 - floating
3802 * 1 - pull down
3803 * 2 - pull up
3804 */
3805static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3806 int value)
3807{
3808 int shift;
3809
3810 switch (offset) {
3811 case RT5677_GPIO1 ... RT5677_GPIO2:
3812 shift = 2 * (1 - offset);
3813 regmap_update_bits(rt5677->regmap,
3814 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
3815 0x3 << shift,
3816 (value & 0x3) << shift);
3817 break;
3818
3819 case RT5677_GPIO3 ... RT5677_GPIO6:
3820 shift = 2 * (9 - offset);
3821 regmap_update_bits(rt5677->regmap,
3822 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
3823 0x3 << shift,
3824 (value & 0x3) << shift);
3825 break;
3826
3827 default:
3828 break;
3829 }
3830}
3831
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]3832static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
3833{
3834 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3835 struct regmap_irq_chip_data *data = rt5677->irq_data;
3836 int irq;
3837
3838 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
3839 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
3840 (rt5677->pdata.jd1_gpio == 2 &&
3841 offset == RT5677_GPIO2) ||
3842 (rt5677->pdata.jd1_gpio == 3 &&
3843 offset == RT5677_GPIO3)) {
3844 irq = RT5677_IRQ_JD1;
3845 } else {
3846 return -ENXIO;
3847 }
3848 }
3849
3850 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
3851 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
3852 (rt5677->pdata.jd2_gpio == 2 &&
3853 offset == RT5677_GPIO5) ||
3854 (rt5677->pdata.jd2_gpio == 3 &&
3855 offset == RT5677_GPIO6)) {
3856 irq = RT5677_IRQ_JD2;
3857 } else if ((rt5677->pdata.jd3_gpio == 1 &&
3858 offset == RT5677_GPIO4) ||
3859 (rt5677->pdata.jd3_gpio == 2 &&
3860 offset == RT5677_GPIO5) ||
3861 (rt5677->pdata.jd3_gpio == 3 &&
3862 offset == RT5677_GPIO6)) {
3863 irq = RT5677_IRQ_JD3;
3864 } else {
3865 return -ENXIO;
3866 }
3867 }
3868
3869 return regmap_irq_get_virq(data, irq);
3870}
3871
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3872static struct gpio_chip rt5677_template_chip = {
3873 .label = "rt5677",
3874 .owner = THIS_MODULE,
3875 .direction_output = rt5677_gpio_direction_out,
3876 .set = rt5677_gpio_set,
3877 .direction_input = rt5677_gpio_direction_in,
3878 .get = rt5677_gpio_get,
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]3879 .to_irq = rt5677_to_irq,
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3880 .can_sleep = 1,
3881};
3882
3883static void rt5677_init_gpio(struct i2c_client *i2c)
3884{
3885 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3886 int ret;
3887
3888 rt5677->gpio_chip = rt5677_template_chip;
3889 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3890 rt5677->gpio_chip.dev = &i2c->dev;
3891 rt5677->gpio_chip.base = -1;
3892
3893 ret = gpiochip_add(&rt5677->gpio_chip);
3894 if (ret != 0)
3895 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3896}
3897
3898static void rt5677_free_gpio(struct i2c_client *i2c)
3899{
3900 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3901
Axel Lin5d5e63a2014-09-17 20:58:02 +0800[diff] [blame]3902 gpiochip_remove(&rt5677->gpio_chip);
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3903}
3904#else
Anatol Pomozov45b6e1d2014-10-16 09:40:58 -0700[diff] [blame]3905static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3906 int value)
3907{
3908}
3909
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]3910static void rt5677_init_gpio(struct i2c_client *i2c)
3911{
3912}
3913
3914static void rt5677_free_gpio(struct i2c_client *i2c)
3915{
3916}
3917#endif
3918
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3919static int rt5677_probe(struct snd_soc_codec *codec)
3920{
3921 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Anatol Pomozov40eb90a2014-10-10 20:46:36 -0700[diff] [blame]3922 int i;
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3923
3924 rt5677->codec = codec;
3925
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3926 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3927 snd_soc_dapm_add_routes(&codec->dapm,
3928 rt5677_dmic2_clk_2,
3929 ARRAY_SIZE(rt5677_dmic2_clk_2));
3930 } else { /*use dmic1 clock by default*/
3931 snd_soc_dapm_add_routes(&codec->dapm,
3932 rt5677_dmic2_clk_1,
3933 ARRAY_SIZE(rt5677_dmic2_clk_1));
3934 }
3935
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3936 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3937
3938 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3939 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3940
Anatol Pomozov40eb90a2014-10-10 20:46:36 -0700[diff] [blame]3941 for (i = 0; i < RT5677_GPIO_NUM; i++)
3942 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
3943
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]3944 if (rt5677->irq_data) {
3945 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
3946 0x8000);
3947 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
3948 0x0008);
3949
3950 if (rt5677->pdata.jd1_gpio)
3951 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3952 RT5677_SEL_GPIO_JD1_MASK,
3953 rt5677->pdata.jd1_gpio <<
3954 RT5677_SEL_GPIO_JD1_SFT);
3955
3956 if (rt5677->pdata.jd2_gpio)
3957 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3958 RT5677_SEL_GPIO_JD2_MASK,
3959 rt5677->pdata.jd2_gpio <<
3960 RT5677_SEL_GPIO_JD2_SFT);
3961
3962 if (rt5677->pdata.jd3_gpio)
3963 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3964 RT5677_SEL_GPIO_JD3_MASK,
3965 rt5677->pdata.jd3_gpio <<
3966 RT5677_SEL_GPIO_JD3_SFT);
3967 }
3968
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]3969 mutex_init(&rt5677->dsp_cmd_lock);
3970
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3971 return 0;
3972}
3973
3974static int rt5677_remove(struct snd_soc_codec *codec)
3975{
3976 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3977
3978 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]3979 if (gpio_is_valid(rt5677->pow_ldo2))
3980 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3981
3982 return 0;
3983}
3984
3985#ifdef CONFIG_PM
3986static int rt5677_suspend(struct snd_soc_codec *codec)
3987{
3988 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3989
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]3990 if (!rt5677->dsp_vad_en) {
3991 regcache_cache_only(rt5677->regmap, true);
3992 regcache_mark_dirty(rt5677->regmap);
3993 }
3994
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]3995 if (gpio_is_valid(rt5677->pow_ldo2))
3996 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3997
3998 return 0;
3999}
4000
4001static int rt5677_resume(struct snd_soc_codec *codec)
4002{
4003 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4004
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]4005 if (gpio_is_valid(rt5677->pow_ldo2)) {
4006 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4007 msleep(10);
4008 }
Oder Chiouaf48f1d2014-10-06 16:30:51 +0800[diff] [blame]4009
4010 if (!rt5677->dsp_vad_en) {
4011 regcache_cache_only(rt5677->regmap, false);
4012 regcache_sync(rt5677->regmap);
4013 }
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4014
4015 return 0;
4016}
4017#else
4018#define rt5677_suspend NULL
4019#define rt5677_resume NULL
4020#endif
4021
4022#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4023#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4024 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4025
4026static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4027 .hw_params = rt5677_hw_params,
4028 .set_fmt = rt5677_set_dai_fmt,
4029 .set_sysclk = rt5677_set_dai_sysclk,
4030 .set_pll = rt5677_set_dai_pll,
Oder Chiou48561af2014-09-17 15:12:33 +0800[diff] [blame]4031 .set_tdm_slot = rt5677_set_tdm_slot,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4032};
4033
4034static struct snd_soc_dai_driver rt5677_dai[] = {
4035 {
4036 .name = "rt5677-aif1",
4037 .id = RT5677_AIF1,
4038 .playback = {
4039 .stream_name = "AIF1 Playback",
4040 .channels_min = 1,
4041 .channels_max = 2,
4042 .rates = RT5677_STEREO_RATES,
4043 .formats = RT5677_FORMATS,
4044 },
4045 .capture = {
4046 .stream_name = "AIF1 Capture",
4047 .channels_min = 1,
4048 .channels_max = 2,
4049 .rates = RT5677_STEREO_RATES,
4050 .formats = RT5677_FORMATS,
4051 },
4052 .ops = &rt5677_aif_dai_ops,
4053 },
4054 {
4055 .name = "rt5677-aif2",
4056 .id = RT5677_AIF2,
4057 .playback = {
4058 .stream_name = "AIF2 Playback",
4059 .channels_min = 1,
4060 .channels_max = 2,
4061 .rates = RT5677_STEREO_RATES,
4062 .formats = RT5677_FORMATS,
4063 },
4064 .capture = {
4065 .stream_name = "AIF2 Capture",
4066 .channels_min = 1,
4067 .channels_max = 2,
4068 .rates = RT5677_STEREO_RATES,
4069 .formats = RT5677_FORMATS,
4070 },
4071 .ops = &rt5677_aif_dai_ops,
4072 },
4073 {
4074 .name = "rt5677-aif3",
4075 .id = RT5677_AIF3,
4076 .playback = {
4077 .stream_name = "AIF3 Playback",
4078 .channels_min = 1,
4079 .channels_max = 2,
4080 .rates = RT5677_STEREO_RATES,
4081 .formats = RT5677_FORMATS,
4082 },
4083 .capture = {
4084 .stream_name = "AIF3 Capture",
4085 .channels_min = 1,
4086 .channels_max = 2,
4087 .rates = RT5677_STEREO_RATES,
4088 .formats = RT5677_FORMATS,
4089 },
4090 .ops = &rt5677_aif_dai_ops,
4091 },
4092 {
4093 .name = "rt5677-aif4",
4094 .id = RT5677_AIF4,
4095 .playback = {
4096 .stream_name = "AIF4 Playback",
4097 .channels_min = 1,
4098 .channels_max = 2,
4099 .rates = RT5677_STEREO_RATES,
4100 .formats = RT5677_FORMATS,
4101 },
4102 .capture = {
4103 .stream_name = "AIF4 Capture",
4104 .channels_min = 1,
4105 .channels_max = 2,
4106 .rates = RT5677_STEREO_RATES,
4107 .formats = RT5677_FORMATS,
4108 },
4109 .ops = &rt5677_aif_dai_ops,
4110 },
4111 {
4112 .name = "rt5677-slimbus",
4113 .id = RT5677_AIF5,
4114 .playback = {
4115 .stream_name = "SLIMBus Playback",
4116 .channels_min = 1,
4117 .channels_max = 2,
4118 .rates = RT5677_STEREO_RATES,
4119 .formats = RT5677_FORMATS,
4120 },
4121 .capture = {
4122 .stream_name = "SLIMBus Capture",
4123 .channels_min = 1,
4124 .channels_max = 2,
4125 .rates = RT5677_STEREO_RATES,
4126 .formats = RT5677_FORMATS,
4127 },
4128 .ops = &rt5677_aif_dai_ops,
4129 },
4130};
4131
4132static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4133 .probe = rt5677_probe,
4134 .remove = rt5677_remove,
4135 .suspend = rt5677_suspend,
4136 .resume = rt5677_resume,
4137 .set_bias_level = rt5677_set_bias_level,
4138 .idle_bias_off = true,
4139 .controls = rt5677_snd_controls,
4140 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4141 .dapm_widgets = rt5677_dapm_widgets,
4142 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4143 .dapm_routes = rt5677_dapm_routes,
4144 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4145};
4146
4147static const struct regmap_config rt5677_regmap = {
4148 .reg_bits = 8,
4149 .val_bits = 16,
4150
4151 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4152 RT5677_PR_SPACING),
4153
4154 .volatile_reg = rt5677_volatile_register,
4155 .readable_reg = rt5677_readable_register,
4156
4157 .cache_type = REGCACHE_RBTREE,
4158 .reg_defaults = rt5677_reg,
4159 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4160 .ranges = rt5677_ranges,
4161 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4162};
4163
4164static const struct i2c_device_id rt5677_i2c_id[] = {
4165 { "rt5677", 0 },
4166 { }
4167};
4168MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4169
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]4170static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4171{
Anatol Pomozov6f67c382014-09-26 09:57:27 -0700[diff] [blame]4172 rt5677->pdata.in1_diff = of_property_read_bool(np,
4173 "realtek,in1-differential");
4174 rt5677->pdata.in2_diff = of_property_read_bool(np,
4175 "realtek,in2-differential");
4176 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4177 "realtek,lout1-differential");
4178 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4179 "realtek,lout2-differential");
4180 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4181 "realtek,lout3-differential");
4182
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]4183 rt5677->pow_ldo2 = of_get_named_gpio(np,
4184 "realtek,pow-ldo2-gpio", 0);
4185
4186 /*
4187 * POW_LDO2 is optional (it may be statically tied on the board).
4188 * -ENOENT means that the property doesn't exist, i.e. there is no
4189 * GPIO, so is not an error. Any other error code means the property
4190 * exists, but could not be parsed.
4191 */
4192 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4193 (rt5677->pow_ldo2 != -ENOENT))
4194 return rt5677->pow_ldo2;
4195
Anatol Pomozov40eb90a2014-10-10 20:46:36 -0700[diff] [blame]4196 of_property_read_u8_array(np, "realtek,gpio-config",
4197 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4198
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4199 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4200 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4201 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4202
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]4203 return 0;
4204}
4205
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4206static struct regmap_irq rt5677_irqs[] = {
4207 [RT5677_IRQ_JD1] = {
4208 .reg_offset = 0,
4209 .mask = RT5677_EN_IRQ_GPIO_JD1,
4210 },
4211 [RT5677_IRQ_JD2] = {
4212 .reg_offset = 0,
4213 .mask = RT5677_EN_IRQ_GPIO_JD2,
4214 },
4215 [RT5677_IRQ_JD3] = {
4216 .reg_offset = 0,
4217 .mask = RT5677_EN_IRQ_GPIO_JD3,
4218 },
4219};
4220
4221static struct regmap_irq_chip rt5677_irq_chip = {
4222 .name = "rt5677",
4223 .irqs = rt5677_irqs,
4224 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4225
4226 .num_regs = 1,
4227 .status_base = RT5677_IRQ_CTRL1,
4228 .mask_base = RT5677_IRQ_CTRL1,
4229 .mask_invert = 1,
4230};
4231
kbuild test robot2d27deb2014-10-22 20:04:08 +0800[diff] [blame]4232static int rt5677_irq_init(struct i2c_client *i2c)
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4233{
4234 int ret;
4235 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4236
4237 if (!rt5677->pdata.jd1_gpio &&
4238 !rt5677->pdata.jd2_gpio &&
4239 !rt5677->pdata.jd3_gpio)
4240 return 0;
4241
4242 if (!i2c->irq) {
4243 dev_err(&i2c->dev, "No interrupt specified\n");
4244 return -EINVAL;
4245 }
4246
4247 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4248 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4249 &rt5677_irq_chip, &rt5677->irq_data);
4250
4251 if (ret != 0) {
4252 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4253 return ret;
4254 }
4255
4256 return 0;
4257}
4258
kbuild test robot2d27deb2014-10-22 20:04:08 +0800[diff] [blame]4259static void rt5677_irq_exit(struct i2c_client *i2c)
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4260{
4261 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4262
4263 if (rt5677->irq_data)
4264 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4265}
4266
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4267static int rt5677_i2c_probe(struct i2c_client *i2c,
4268 const struct i2c_device_id *id)
4269{
4270 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4271 struct rt5677_priv *rt5677;
4272 int ret;
4273 unsigned int val;
4274
4275 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4276 GFP_KERNEL);
4277 if (rt5677 == NULL)
4278 return -ENOMEM;
4279
4280 i2c_set_clientdata(i2c, rt5677);
4281
4282 if (pdata)
4283 rt5677->pdata = *pdata;
4284
Anatol Pomozovf9f6a592014-09-17 13:14:20 -0700[diff] [blame]4285 if (i2c->dev.of_node) {
4286 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4287 if (ret) {
4288 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4289 ret);
4290 return ret;
4291 }
4292 } else {
4293 rt5677->pow_ldo2 = -EINVAL;
4294 }
4295
4296 if (gpio_is_valid(rt5677->pow_ldo2)) {
4297 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4298 GPIOF_OUT_INIT_HIGH,
4299 "RT5677 POW_LDO2");
4300 if (ret < 0) {
4301 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4302 rt5677->pow_ldo2, ret);
4303 return ret;
4304 }
4305 /* Wait a while until I2C bus becomes available. The datasheet
4306 * does not specify the exact we should wait but startup
4307 * sequence mentiones at least a few milliseconds.
4308 */
4309 msleep(10);
4310 }
4311
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4312 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
4313 if (IS_ERR(rt5677->regmap)) {
4314 ret = PTR_ERR(rt5677->regmap);
4315 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4316 ret);
4317 return ret;
4318 }
4319
4320 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4321 if (val != RT5677_DEVICE_ID) {
4322 dev_err(&i2c->dev,
4323 "Device with ID register %x is not rt5677\n", val);
4324 return -ENODEV;
4325 }
4326
4327 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4328
4329 ret = regmap_register_patch(rt5677->regmap, init_list,
4330 ARRAY_SIZE(init_list));
4331 if (ret != 0)
4332 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4333
4334 if (rt5677->pdata.in1_diff)
4335 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4336 RT5677_IN_DF1, RT5677_IN_DF1);
4337
4338 if (rt5677->pdata.in2_diff)
4339 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4340 RT5677_IN_DF2, RT5677_IN_DF2);
4341
Anatol Pomozov6f67c382014-09-26 09:57:27 -0700[diff] [blame]4342 if (rt5677->pdata.lout1_diff)
4343 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4344 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4345
4346 if (rt5677->pdata.lout2_diff)
4347 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4348 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4349
4350 if (rt5677->pdata.lout3_diff)
4351 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4352 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4353
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]4354 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4355 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4356 RT5677_GPIO5_FUNC_MASK,
4357 RT5677_GPIO5_FUNC_DMIC);
4358 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4359 RT5677_GPIO5_DIR_MASK,
4360 RT5677_GPIO5_DIR_OUT);
4361 }
4362
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]4363 rt5677_init_gpio(i2c);
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4364 rt5677_irq_init(i2c);
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]4365
Axel Lind0bdcb92014-06-10 11:37:24 +0800[diff] [blame]4366 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4367 rt5677_dai, ARRAY_SIZE(rt5677_dai));
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4368}
4369
4370static int rt5677_i2c_remove(struct i2c_client *i2c)
4371{
Oder Chiou5e3363a2014-10-16 11:24:26 -0700[diff] [blame]4372 rt5677_irq_exit(i2c);
4373
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4374 snd_soc_unregister_codec(&i2c->dev);
Oder Chiou44caf762014-09-16 11:37:39 +0800[diff] [blame]4375 rt5677_free_gpio(i2c);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4376
4377 return 0;
4378}
4379
4380static struct i2c_driver rt5677_i2c_driver = {
4381 .driver = {
4382 .name = "rt5677",
4383 .owner = THIS_MODULE,
4384 },
4385 .probe = rt5677_i2c_probe,
4386 .remove = rt5677_i2c_remove,
4387 .id_table = rt5677_i2c_id,
4388};
Axel Linc8cfbec82014-06-03 10:56:41 +0800[diff] [blame]4389module_i2c_driver(rt5677_i2c_driver);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]4390
4391MODULE_DESCRIPTION("ASoC RT5677 driver");
4392MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4393MODULE_LICENSE("GPL v2");